drivers/media/platform/atmel/atmel-isc-base.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Microchip Image Sensor Controller (ISC) common driver base
   4  *
   5  * Copyright (C) 2016-2019 Microchip Technology, Inc.
   6  *
   7  * Author: Songjun Wu
   8  * Author: Eugen Hristev <eugen.hristev@microchip.com>
   9  *
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/math64.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/videodev2.h>
  25 #include <linux/atmel-isc-media.h>
  26
  27 #include <media/v4l2-ctrls.h>
  28 #include <media/v4l2-device.h>
  29 #include <media/v4l2-event.h>
  30 #include <media/v4l2-image-sizes.h>
  31 #include <media/v4l2-ioctl.h>
  32 #include <media/v4l2-fwnode.h>
  33 #include <media/v4l2-subdev.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "atmel-isc-regs.h"
  37 #include "atmel-isc.h"
  38
  39 static unsigned int debug;
  40 module_param(debug, int, 0644);
  41 MODULE_PARM_DESC(debug, "debug level (0-2)");
  42
  43 static unsigned int sensor_preferred = 1;
  44 module_param(sensor_preferred, uint, 0644);
  45 MODULE_PARM_DESC(sensor_preferred,
  46                  "Sensor is preferred to output the specified format (1-on 0-off), default 1");
  47
  48 /* This is a list of the formats that the ISC can *output* */
  49 const struct isc_format controller_formats[] = {
  50         {
  51                 .fourcc         = V4L2_PIX_FMT_ARGB444,
  52         },
  53         {
  54                 .fourcc         = V4L2_PIX_FMT_ARGB555,
  55         },
  56         {
  57                 .fourcc         = V4L2_PIX_FMT_RGB565,
  58         },
  59         {
  60                 .fourcc         = V4L2_PIX_FMT_ABGR32,
  61         },
  62         {
  63                 .fourcc         = V4L2_PIX_FMT_XBGR32,
  64         },
  65         {
  66                 .fourcc         = V4L2_PIX_FMT_YUV420,
  67         },
  68         {
  69                 .fourcc         = V4L2_PIX_FMT_YUYV,
  70         },
  71         {
  72                 .fourcc         = V4L2_PIX_FMT_YUV422P,
  73         },
  74         {
  75                 .fourcc         = V4L2_PIX_FMT_GREY,
  76         },
  77         {
  78                 .fourcc         = V4L2_PIX_FMT_Y10,
  79         },
  80 };
  81
  82 /* This is a list of formats that the ISC can receive as *input* */
  83 struct isc_format formats_list[] = {
  84         {
  85                 .fourcc         = V4L2_PIX_FMT_SBGGR8,
  86                 .mbus_code      = MEDIA_BUS_FMT_SBGGR8_1X8,
  87                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  88                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
  89         },
  90         {
  91                 .fourcc         = V4L2_PIX_FMT_SGBRG8,
  92                 .mbus_code      = MEDIA_BUS_FMT_SGBRG8_1X8,
  93                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  94                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
  95         },
  96         {
  97                 .fourcc         = V4L2_PIX_FMT_SGRBG8,
  98                 .mbus_code      = MEDIA_BUS_FMT_SGRBG8_1X8,
  99                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 100                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 101         },
 102         {
 103                 .fourcc         = V4L2_PIX_FMT_SRGGB8,
 104                 .mbus_code      = MEDIA_BUS_FMT_SRGGB8_1X8,
 105                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 106                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 107         },
 108         {
 109                 .fourcc         = V4L2_PIX_FMT_SBGGR10,
 110                 .mbus_code      = MEDIA_BUS_FMT_SBGGR10_1X10,
 111                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 112                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 113         },
 114         {
 115                 .fourcc         = V4L2_PIX_FMT_SGBRG10,
 116                 .mbus_code      = MEDIA_BUS_FMT_SGBRG10_1X10,
 117                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 118                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 119         },
 120         {
 121                 .fourcc         = V4L2_PIX_FMT_SGRBG10,
 122                 .mbus_code      = MEDIA_BUS_FMT_SGRBG10_1X10,
 123                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 124                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 125         },
 126         {
 127                 .fourcc         = V4L2_PIX_FMT_SRGGB10,
 128                 .mbus_code      = MEDIA_BUS_FMT_SRGGB10_1X10,
 129                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 130                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 131         },
 132         {
 133                 .fourcc         = V4L2_PIX_FMT_SBGGR12,
 134                 .mbus_code      = MEDIA_BUS_FMT_SBGGR12_1X12,
 135                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 136                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
 137         },
 138         {
 139                 .fourcc         = V4L2_PIX_FMT_SGBRG12,
 140                 .mbus_code      = MEDIA_BUS_FMT_SGBRG12_1X12,
 141                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 142                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 143         },
 144         {
 145                 .fourcc         = V4L2_PIX_FMT_SGRBG12,
 146                 .mbus_code      = MEDIA_BUS_FMT_SGRBG12_1X12,
 147                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 148                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 149         },
 150         {
 151                 .fourcc         = V4L2_PIX_FMT_SRGGB12,
 152                 .mbus_code      = MEDIA_BUS_FMT_SRGGB12_1X12,
 153                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 154                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 155         },
 156         {
 157                 .fourcc         = V4L2_PIX_FMT_GREY,
 158                 .mbus_code      = MEDIA_BUS_FMT_Y8_1X8,
 159                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 160         },
 161         {
 162                 .fourcc         = V4L2_PIX_FMT_YUYV,
 163                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 164                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 165         },
 166         {
 167                 .fourcc         = V4L2_PIX_FMT_RGB565,
 168                 .mbus_code      = MEDIA_BUS_FMT_RGB565_2X8_LE,
 169                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 170         },
 171         {
 172                 .fourcc         = V4L2_PIX_FMT_Y10,
 173                 .mbus_code      = MEDIA_BUS_FMT_Y10_1X10,
 174                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 175         },
 176
 177 };
 178
 179 /* Gamma table with gamma 1/2.2 */
 180 const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = {
 181         /* 0 --> gamma 1/1.8 */
 182         {      0x65,  0x66002F,  0x950025,  0xBB0020,  0xDB001D,  0xF8001A,
 183           0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,
 184           0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,
 185           0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,
 186           0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,
 187           0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,
 188           0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,
 189           0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,
 190           0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,
 191           0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,
 192           0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },
 193
 194         /* 1 --> gamma 1/2 */
 195         {      0x7F,  0x800034,  0xB50028,  0xDE0021, 0x100001E, 0x11E001B,
 196           0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,
 197           0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,
 198           0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,
 199           0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,
 200           0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,
 201           0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,
 202           0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,
 203           0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,
 204           0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,
 205           0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },
 206
 207         /* 2 --> gamma 1/2.2 */
 208         {      0x99,  0x9B0038,  0xD4002A,  0xFF0023, 0x122001F, 0x141001B,
 209           0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,
 210           0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,
 211           0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,
 212           0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,
 213           0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,
 214           0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,
 215           0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,
 216           0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,
 217           0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,
 218           0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },
 219 };
 220
 221 #define ISC_IS_FORMAT_RAW(mbus_code) \
 222         (((mbus_code) & 0xf000) == 0x3000)
 223
 224 #define ISC_IS_FORMAT_GREY(mbus_code) \
 225         (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
 226         (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
 227
 228 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
 229 {
 230         struct isc_ctrls *ctrls = &isc->ctrls;
 231
 232         /* In here we set the v4l2 controls w.r.t. our pipeline config */
 233         v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
 234         v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
 235         v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
 236         v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
 237
 238         v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
 239         v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
 240         v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
 241         v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
 242 }
 243
 244 static inline void isc_update_awb_ctrls(struct isc_device *isc)
 245 {
 246         struct isc_ctrls *ctrls = &isc->ctrls;
 247
 248         /* In here we set our actual hw pipeline config */
 249
 250         regmap_write(isc->regmap, ISC_WB_O_RGR,
 251                      ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
 252                      ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
 253         regmap_write(isc->regmap, ISC_WB_O_BGB,
 254                      ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
 255                      ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
 256         regmap_write(isc->regmap, ISC_WB_G_RGR,
 257                      ctrls->gain[ISC_HIS_CFG_MODE_R] |
 258                      (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
 259         regmap_write(isc->regmap, ISC_WB_G_BGB,
 260                      ctrls->gain[ISC_HIS_CFG_MODE_B] |
 261                      (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
 262 }
 263
 264 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
 265 {
 266         unsigned int c;
 267
 268         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
 269                 /* gains have a fixed point at 9 decimals */
 270                 isc->ctrls.gain[c] = 1 << 9;
 271                 /* offsets are in 2's complements */
 272                 isc->ctrls.offset[c] = 0;
 273         }
 274 }
 275
 276 static int isc_wait_clk_stable(struct clk_hw *hw)
 277 {
 278         struct isc_clk *isc_clk = to_isc_clk(hw);
 279         struct regmap *regmap = isc_clk->regmap;
 280         unsigned long timeout = jiffies + usecs_to_jiffies(1000);
 281         unsigned int status;
 282
 283         while (time_before(jiffies, timeout)) {
 284                 regmap_read(regmap, ISC_CLKSR, &status);
 285                 if (!(status & ISC_CLKSR_SIP))
 286                         return 0;
 287
 288                 usleep_range(10, 250);
 289         }
 290
 291         return -ETIMEDOUT;
 292 }
 293
 294 static int isc_clk_prepare(struct clk_hw *hw)
 295 {
 296         struct isc_clk *isc_clk = to_isc_clk(hw);
 297         int ret;
 298
 299         if (isc_clk->id == ISC_ISPCK) {
 300                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 301                 if (ret < 0)
 302                         return ret;
 303         }
 304
 305         return isc_wait_clk_stable(hw);
 306 }
 307
 308 static void isc_clk_unprepare(struct clk_hw *hw)
 309 {
 310         struct isc_clk *isc_clk = to_isc_clk(hw);
 311
 312         isc_wait_clk_stable(hw);
 313
 314         if (isc_clk->id == ISC_ISPCK)
 315                 pm_runtime_put_sync(isc_clk->dev);
 316 }
 317
 318 static int isc_clk_enable(struct clk_hw *hw)
 319 {
 320         struct isc_clk *isc_clk = to_isc_clk(hw);
 321         u32 id = isc_clk->id;
 322         struct regmap *regmap = isc_clk->regmap;
 323         unsigned long flags;
 324         unsigned int status;
 325
 326         dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n",
 327                 __func__, isc_clk->div, isc_clk->parent_id);
 328
 329         spin_lock_irqsave(&isc_clk->lock, flags);
 330         regmap_update_bits(regmap, ISC_CLKCFG,
 331                            ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
 332                            (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
 333                            (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
 334
 335         regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
 336         spin_unlock_irqrestore(&isc_clk->lock, flags);
 337
 338         regmap_read(regmap, ISC_CLKSR, &status);
 339         if (status & ISC_CLK(id))
 340                 return 0;
 341         else
 342                 return -EINVAL;
 343 }
 344
 345 static void isc_clk_disable(struct clk_hw *hw)
 346 {
 347         struct isc_clk *isc_clk = to_isc_clk(hw);
 348         u32 id = isc_clk->id;
 349         unsigned long flags;
 350
 351         spin_lock_irqsave(&isc_clk->lock, flags);
 352         regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
 353         spin_unlock_irqrestore(&isc_clk->lock, flags);
 354 }
 355
 356 static int isc_clk_is_enabled(struct clk_hw *hw)
 357 {
 358         struct isc_clk *isc_clk = to_isc_clk(hw);
 359         u32 status;
 360         int ret;
 361
 362         if (isc_clk->id == ISC_ISPCK) {
 363                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 364                 if (ret < 0)
 365                         return 0;
 366         }
 367
 368         regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
 369
 370         if (isc_clk->id == ISC_ISPCK)
 371                 pm_runtime_put_sync(isc_clk->dev);
 372
 373         return status & ISC_CLK(isc_clk->id) ? 1 : 0;
 374 }
 375
 376 static unsigned long
 377 isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 378 {
 379         struct isc_clk *isc_clk = to_isc_clk(hw);
 380
 381         return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
 382 }
 383
 384 static int isc_clk_determine_rate(struct clk_hw *hw,
 385                                    struct clk_rate_request *req)
 386 {
 387         struct isc_clk *isc_clk = to_isc_clk(hw);
 388         long best_rate = -EINVAL;
 389         int best_diff = -1;
 390         unsigned int i, div;
 391
 392         for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
 393                 struct clk_hw *parent;
 394                 unsigned long parent_rate;
 395
 396                 parent = clk_hw_get_parent_by_index(hw, i);
 397                 if (!parent)
 398                         continue;
 399
 400                 parent_rate = clk_hw_get_rate(parent);
 401                 if (!parent_rate)
 402                         continue;
 403
 404                 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
 405                         unsigned long rate;
 406                         int diff;
 407
 408                         rate = DIV_ROUND_CLOSEST(parent_rate, div);
 409                         diff = abs(req->rate - rate);
 410
 411                         if (best_diff < 0 || best_diff > diff) {
 412                                 best_rate = rate;
 413                                 best_diff = diff;
 414                                 req->best_parent_rate = parent_rate;
 415                                 req->best_parent_hw = parent;
 416                         }
 417
 418                         if (!best_diff || rate < req->rate)
 419                                 break;
 420                 }
 421
 422                 if (!best_diff)
 423                         break;
 424         }
 425
 426         dev_dbg(isc_clk->dev,
 427                 "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
 428                 __func__, best_rate,
 429                 __clk_get_name((req->best_parent_hw)->clk),
 430                 req->best_parent_rate);
 431
 432         if (best_rate < 0)
 433                 return best_rate;
 434
 435         req->rate = best_rate;
 436
 437         return 0;
 438 }
 439
 440 static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
 441 {
 442         struct isc_clk *isc_clk = to_isc_clk(hw);
 443
 444         if (index >= clk_hw_get_num_parents(hw))
 445                 return -EINVAL;
 446
 447         isc_clk->parent_id = index;
 448
 449         return 0;
 450 }
 451
 452 static u8 isc_clk_get_parent(struct clk_hw *hw)
 453 {
 454         struct isc_clk *isc_clk = to_isc_clk(hw);
 455
 456         return isc_clk->parent_id;
 457 }
 458
 459 static int isc_clk_set_rate(struct clk_hw *hw,
 460                              unsigned long rate,
 461                              unsigned long parent_rate)
 462 {
 463         struct isc_clk *isc_clk = to_isc_clk(hw);
 464         u32 div;
 465
 466         if (!rate)
 467                 return -EINVAL;
 468
 469         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 470         if (div > (ISC_CLK_MAX_DIV + 1) || !div)
 471                 return -EINVAL;
 472
 473         isc_clk->div = div - 1;
 474
 475         return 0;
 476 }
 477
 478 static const struct clk_ops isc_clk_ops = {
 479         .prepare        = isc_clk_prepare,
 480         .unprepare      = isc_clk_unprepare,
 481         .enable         = isc_clk_enable,
 482         .disable        = isc_clk_disable,
 483         .is_enabled     = isc_clk_is_enabled,
 484         .recalc_rate    = isc_clk_recalc_rate,
 485         .determine_rate = isc_clk_determine_rate,
 486         .set_parent     = isc_clk_set_parent,
 487         .get_parent     = isc_clk_get_parent,
 488         .set_rate       = isc_clk_set_rate,
 489 };
 490
 491 static int isc_clk_register(struct isc_device *isc, unsigned int id)
 492 {
 493         struct regmap *regmap = isc->regmap;
 494         struct device_node *np = isc->dev->of_node;
 495         struct isc_clk *isc_clk;
 496         struct clk_init_data init;
 497         const char *clk_name = np->name;
 498         const char *parent_names[3];
 499         int num_parents;
 500
 501         num_parents = of_clk_get_parent_count(np);
 502         if (num_parents < 1 || num_parents > 3)
 503                 return -EINVAL;
 504
 505         if (num_parents > 2 && id == ISC_ISPCK)
 506                 num_parents = 2;
 507
 508         of_clk_parent_fill(np, parent_names, num_parents);
 509
 510         if (id == ISC_MCK)
 511                 of_property_read_string(np, "clock-output-names", &clk_name);
 512         else
 513                 clk_name = "isc-ispck";
 514
 515         init.parent_names       = parent_names;
 516         init.num_parents        = num_parents;
 517         init.name               = clk_name;
 518         init.ops                = &isc_clk_ops;
 519         init.flags              = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
 520
 521         isc_clk = &isc->isc_clks[id];
 522         isc_clk->hw.init        = &init;
 523         isc_clk->regmap         = regmap;
 524         isc_clk->id             = id;
 525         isc_clk->dev            = isc->dev;
 526         spin_lock_init(&isc_clk->lock);
 527
 528         isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
 529         if (IS_ERR(isc_clk->clk)) {
 530                 dev_err(isc->dev, "%s: clock register fail\n", clk_name);
 531                 return PTR_ERR(isc_clk->clk);
 532         } else if (id == ISC_MCK)
 533                 of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
 534
 535         return 0;
 536 }
 537
 538 int isc_clk_init(struct isc_device *isc)
 539 {
 540         unsigned int i;
 541         int ret;
 542
 543         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
 544                 isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
 545
 546         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 547                 ret = isc_clk_register(isc, i);
 548                 if (ret)
 549                         return ret;
 550         }
 551
 552         return 0;
 553 }
 554
 555 void isc_clk_cleanup(struct isc_device *isc)
 556 {
 557         unsigned int i;
 558
 559         of_clk_del_provider(isc->dev->of_node);
 560
 561         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 562                 struct isc_clk *isc_clk = &isc->isc_clks[i];
 563
 564                 if (!IS_ERR(isc_clk->clk))
 565                         clk_unregister(isc_clk->clk);
 566         }
 567 }
 568
 569 static int isc_queue_setup(struct vb2_queue *vq,
 570                             unsigned int *nbuffers, unsigned int *nplanes,
 571                             unsigned int sizes[], struct device *alloc_devs[])
 572 {
 573         struct isc_device *isc = vb2_get_drv_priv(vq);
 574         unsigned int size = isc->fmt.fmt.pix.sizeimage;
 575
 576         if (*nplanes)
 577                 return sizes[0] < size ? -EINVAL : 0;
 578
 579         *nplanes = 1;
 580         sizes[0] = size;
 581
 582         return 0;
 583 }
 584
 585 static int isc_buffer_prepare(struct vb2_buffer *vb)
 586 {
 587         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 588         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 589         unsigned long size = isc->fmt.fmt.pix.sizeimage;
 590
 591         if (vb2_plane_size(vb, 0) < size) {
 592                 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
 593                          vb2_plane_size(vb, 0), size);
 594                 return -EINVAL;
 595         }
 596
 597         vb2_set_plane_payload(vb, 0, size);
 598
 599         vbuf->field = isc->fmt.fmt.pix.field;
 600
 601         return 0;
 602 }
 603
 604 static void isc_start_dma(struct isc_device *isc)
 605 {
 606         struct regmap *regmap = isc->regmap;
 607         u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
 608         u32 dctrl_dview;
 609         dma_addr_t addr0;
 610         u32 h, w;
 611
 612         h = isc->fmt.fmt.pix.height;
 613         w = isc->fmt.fmt.pix.width;
 614
 615         /*
 616          * In case the sensor is not RAW, it will output a pixel (12-16 bits)
 617          * with two samples on the ISC Data bus (which is 8-12)
 618          * ISC will count each sample, so, we need to multiply these values
 619          * by two, to get the real number of samples for the required pixels.
 620          */
 621         if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
 622                 h <<= 1;
 623                 w <<= 1;
 624         }
 625
 626         /*
 627          * We limit the column/row count that the ISC will output according
 628          * to the configured resolution that we want.
 629          * This will avoid the situation where the sensor is misconfigured,
 630          * sending more data, and the ISC will just take it and DMA to memory,
 631          * causing corruption.
 632          */
 633         regmap_write(regmap, ISC_PFE_CFG1,
 634                      (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
 635                      (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
 636
 637         regmap_write(regmap, ISC_PFE_CFG2,
 638                      (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
 639                      (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
 640
 641         regmap_update_bits(regmap, ISC_PFE_CFG0,
 642                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
 643                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 644
 645         addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
 646         regmap_write(regmap, ISC_DAD0, addr0);
 647
 648         switch (isc->config.fourcc) {
 649         case V4L2_PIX_FMT_YUV420:
 650                 regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);
 651                 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);
 652                 break;
 653         case V4L2_PIX_FMT_YUV422P:
 654                 regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);
 655                 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);
 656                 break;
 657         default:
 658                 break;
 659         }
 660
 661         dctrl_dview = isc->config.dctrl_dview;
 662
 663         regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
 664         spin_lock(&isc->awb_lock);
 665         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
 666         spin_unlock(&isc->awb_lock);
 667 }
 668
 669 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
 670 {
 671         struct regmap *regmap = isc->regmap;
 672         struct isc_ctrls *ctrls = &isc->ctrls;
 673         u32 val, bay_cfg;
 674         const u32 *gamma;
 675         unsigned int i;
 676
 677         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
 678         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
 679                 val = pipeline & BIT(i) ? 1 : 0;
 680                 regmap_field_write(isc->pipeline[i], val);
 681         }
 682
 683         if (!pipeline)
 684                 return;
 685
 686         bay_cfg = isc->config.sd_format->cfa_baycfg;
 687
 688         regmap_write(regmap, ISC_WB_CFG, bay_cfg);
 689         isc_update_awb_ctrls(isc);
 690         isc_update_v4l2_ctrls(isc);
 691
 692         regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
 693
 694         gamma = &isc_gamma_table[ctrls->gamma_index][0];
 695         regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
 696         regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 697         regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 698
 699         /* Convert RGB to YUV */
 700         regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
 701         regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
 702         regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
 703         regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
 704         regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
 705         regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
 706
 707         regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
 708         regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
 709 }
 710
 711 static int isc_update_profile(struct isc_device *isc)
 712 {
 713         struct regmap *regmap = isc->regmap;
 714         u32 sr;
 715         int counter = 100;
 716
 717         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
 718
 719         regmap_read(regmap, ISC_CTRLSR, &sr);
 720         while ((sr & ISC_CTRL_UPPRO) && counter--) {
 721                 usleep_range(1000, 2000);
 722                 regmap_read(regmap, ISC_CTRLSR, &sr);
 723         }
 724
 725         if (counter < 0) {
 726                 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
 727                 return -ETIMEDOUT;
 728         }
 729
 730         return 0;
 731 }
 732
 733 static void isc_set_histogram(struct isc_device *isc, bool enable)
 734 {
 735         struct regmap *regmap = isc->regmap;
 736         struct isc_ctrls *ctrls = &isc->ctrls;
 737
 738         if (enable) {
 739                 regmap_write(regmap, ISC_HIS_CFG,
 740                              ISC_HIS_CFG_MODE_GR |
 741                              (isc->config.sd_format->cfa_baycfg
 742                                         << ISC_HIS_CFG_BAYSEL_SHIFT) |
 743                                         ISC_HIS_CFG_RAR);
 744                 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
 745                 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
 746                 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
 747                 isc_update_profile(isc);
 748                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
 749
 750                 ctrls->hist_stat = HIST_ENABLED;
 751         } else {
 752                 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
 753                 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);
 754
 755                 ctrls->hist_stat = HIST_DISABLED;
 756         }
 757 }
 758
 759 static int isc_configure(struct isc_device *isc)
 760 {
 761         struct regmap *regmap = isc->regmap;
 762         u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
 763         struct isc_subdev_entity *subdev = isc->current_subdev;
 764
 765         pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
 766         rlp_mode = isc->config.rlp_cfg_mode;
 767         pipeline = isc->config.bits_pipeline;
 768
 769         dcfg = isc->config.dcfg_imode |
 770                        ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
 771
 772         pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
 773         mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 774                ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
 775                ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
 776                    ISC_PFE_CFG0_CCIR656;
 777
 778         regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 779
 780         regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
 781                            rlp_mode);
 782
 783         regmap_write(regmap, ISC_DCFG, dcfg);
 784
 785         /* Set the pipeline */
 786         isc_set_pipeline(isc, pipeline);
 787
 788         /*
 789          * The current implemented histogram is available for RAW R, B, GB, GR
 790          * channels. We need to check if sensor is outputting RAW BAYER
 791          */
 792         if (isc->ctrls.awb &&
 793             ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 794                 isc_set_histogram(isc, true);
 795         else
 796                 isc_set_histogram(isc, false);
 797
 798         /* Update profile */
 799         return isc_update_profile(isc);
 800 }
 801
 802 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
 803 {
 804         struct isc_device *isc = vb2_get_drv_priv(vq);
 805         struct regmap *regmap = isc->regmap;
 806         struct isc_buffer *buf;
 807         unsigned long flags;
 808         int ret;
 809
 810         /* Enable stream on the sub device */
 811         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
 812         if (ret && ret != -ENOIOCTLCMD) {
 813                 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
 814                          ret);
 815                 goto err_start_stream;
 816         }
 817
 818         ret = pm_runtime_resume_and_get(isc->dev);
 819         if (ret < 0) {
 820                 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
 821                          ret);
 822                 goto err_pm_get;
 823         }
 824
 825         ret = isc_configure(isc);
 826         if (unlikely(ret))
 827                 goto err_configure;
 828
 829         /* Enable DMA interrupt */
 830         regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
 831
 832         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 833
 834         isc->sequence = 0;
 835         isc->stop = false;
 836         reinit_completion(&isc->comp);
 837
 838         isc->cur_frm = list_first_entry(&isc->dma_queue,
 839                                         struct isc_buffer, list);
 840         list_del(&isc->cur_frm->list);
 841
 842         isc_start_dma(isc);
 843
 844         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 845
 846         /* if we streaming from RAW, we can do one-shot white balance adj */
 847         if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 848                 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
 849
 850         return 0;
 851
 852 err_configure:
 853         pm_runtime_put_sync(isc->dev);
 854 err_pm_get:
 855         v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 856
 857 err_start_stream:
 858         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 859         list_for_each_entry(buf, &isc->dma_queue, list)
 860                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
 861         INIT_LIST_HEAD(&isc->dma_queue);
 862         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 863
 864         return ret;
 865 }
 866
 867 static void isc_stop_streaming(struct vb2_queue *vq)
 868 {
 869         struct isc_device *isc = vb2_get_drv_priv(vq);
 870         unsigned long flags;
 871         struct isc_buffer *buf;
 872         int ret;
 873
 874         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
 875
 876         isc->stop = true;
 877
 878         /* Wait until the end of the current frame */
 879         if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
 880                 v4l2_err(&isc->v4l2_dev,
 881                          "Timeout waiting for end of the capture\n");
 882
 883         /* Disable DMA interrupt */
 884         regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
 885
 886         pm_runtime_put_sync(isc->dev);
 887
 888         /* Disable stream on the sub device */
 889         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 890         if (ret && ret != -ENOIOCTLCMD)
 891                 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
 892
 893         /* Release all active buffers */
 894         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 895         if (unlikely(isc->cur_frm)) {
 896                 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
 897                                 VB2_BUF_STATE_ERROR);
 898                 isc->cur_frm = NULL;
 899         }
 900         list_for_each_entry(buf, &isc->dma_queue, list)
 901                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 902         INIT_LIST_HEAD(&isc->dma_queue);
 903         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 904 }
 905
 906 static void isc_buffer_queue(struct vb2_buffer *vb)
 907 {
 908         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 909         struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
 910         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 911         unsigned long flags;
 912
 913         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 914         if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
 915                 vb2_is_streaming(vb->vb2_queue)) {
 916                 isc->cur_frm = buf;
 917                 isc_start_dma(isc);
 918         } else
 919                 list_add_tail(&buf->list, &isc->dma_queue);
 920         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 921 }
 922
 923 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
 924                                                  unsigned int fourcc)
 925 {
 926         unsigned int num_formats = isc->num_user_formats;
 927         struct isc_format *fmt;
 928         unsigned int i;
 929
 930         for (i = 0; i < num_formats; i++) {
 931                 fmt = isc->user_formats[i];
 932                 if (fmt->fourcc == fourcc)
 933                         return fmt;
 934         }
 935
 936         return NULL;
 937 }
 938
 939 static const struct vb2_ops isc_vb2_ops = {
 940         .queue_setup            = isc_queue_setup,
 941         .wait_prepare           = vb2_ops_wait_prepare,
 942         .wait_finish            = vb2_ops_wait_finish,
 943         .buf_prepare            = isc_buffer_prepare,
 944         .start_streaming        = isc_start_streaming,
 945         .stop_streaming         = isc_stop_streaming,
 946         .buf_queue              = isc_buffer_queue,
 947 };
 948
 949 static int isc_querycap(struct file *file, void *priv,
 950                          struct v4l2_capability *cap)
 951 {
 952         struct isc_device *isc = video_drvdata(file);
 953
 954         strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver));
 955         strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
 956         snprintf(cap->bus_info, sizeof(cap->bus_info),
 957                  "platform:%s", isc->v4l2_dev.name);
 958
 959         return 0;
 960 }
 961
 962 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
 963                                  struct v4l2_fmtdesc *f)
 964 {
 965         u32 index = f->index;
 966         u32 i, supported_index;
 967
 968         if (index < ARRAY_SIZE(controller_formats)) {
 969                 f->pixelformat = controller_formats[index].fourcc;
 970                 return 0;
 971         }
 972
 973         index -= ARRAY_SIZE(controller_formats);
 974
 975         i = 0;
 976         supported_index = 0;
 977
 978         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
 979                 if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
 980                     !formats_list[i].sd_support)
 981                         continue;
 982                 if (supported_index == index) {
 983                         f->pixelformat = formats_list[i].fourcc;
 984                         return 0;
 985                 }
 986                 supported_index++;
 987         }
 988
 989         return -EINVAL;
 990 }
 991
 992 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
 993                               struct v4l2_format *fmt)
 994 {
 995         struct isc_device *isc = video_drvdata(file);
 996
 997         *fmt = isc->fmt;
 998
 999         return 0;
1000 }
1001
1002 /*
1003  * Checks the current configured format, if ISC can output it,
1004  * considering which type of format the ISC receives from the sensor
1005  */
1006 static int isc_try_validate_formats(struct isc_device *isc)
1007 {
1008         int ret;
1009         bool bayer = false, yuv = false, rgb = false, grey = false;
1010
1011         /* all formats supported by the RLP module are OK */
1012         switch (isc->try_config.fourcc) {
1013         case V4L2_PIX_FMT_SBGGR8:
1014         case V4L2_PIX_FMT_SGBRG8:
1015         case V4L2_PIX_FMT_SGRBG8:
1016         case V4L2_PIX_FMT_SRGGB8:
1017         case V4L2_PIX_FMT_SBGGR10:
1018         case V4L2_PIX_FMT_SGBRG10:
1019         case V4L2_PIX_FMT_SGRBG10:
1020         case V4L2_PIX_FMT_SRGGB10:
1021         case V4L2_PIX_FMT_SBGGR12:
1022         case V4L2_PIX_FMT_SGBRG12:
1023         case V4L2_PIX_FMT_SGRBG12:
1024         case V4L2_PIX_FMT_SRGGB12:
1025                 ret = 0;
1026                 bayer = true;
1027                 break;
1028
1029         case V4L2_PIX_FMT_YUV420:
1030         case V4L2_PIX_FMT_YUV422P:
1031         case V4L2_PIX_FMT_YUYV:
1032                 ret = 0;
1033                 yuv = true;
1034                 break;
1035
1036         case V4L2_PIX_FMT_RGB565:
1037         case V4L2_PIX_FMT_ABGR32:
1038         case V4L2_PIX_FMT_XBGR32:
1039         case V4L2_PIX_FMT_ARGB444:
1040         case V4L2_PIX_FMT_ARGB555:
1041                 ret = 0;
1042                 rgb = true;
1043                 break;
1044         case V4L2_PIX_FMT_GREY:
1045         case V4L2_PIX_FMT_Y10:
1046                 ret = 0;
1047                 grey = true;
1048                 break;
1049         default:
1050         /* any other different formats are not supported */
1051                 ret = -EINVAL;
1052         }
1053         v4l2_dbg(1, debug, &isc->v4l2_dev,
1054                  "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
1055                  rgb, yuv, grey, bayer);
1056
1057         /* we cannot output RAW if we do not receive RAW */
1058         if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
1059                 return -EINVAL;
1060
1061         /* we cannot output GREY if we do not receive RAW/GREY */
1062         if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
1063             !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
1064                 return -EINVAL;
1065
1066         return ret;
1067 }
1068
1069 /*
1070  * Configures the RLP and DMA modules, depending on the output format
1071  * configured for the ISC.
1072  * If direct_dump == true, just dump raw data 8/16 bits depending on format.
1073  */
1074 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
1075 {
1076         switch (isc->try_config.fourcc) {
1077         case V4L2_PIX_FMT_SBGGR8:
1078         case V4L2_PIX_FMT_SGBRG8:
1079         case V4L2_PIX_FMT_SGRBG8:
1080         case V4L2_PIX_FMT_SRGGB8:
1081                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1082                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1083                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1084                 isc->try_config.bpp = 8;
1085                 break;
1086         case V4L2_PIX_FMT_SBGGR10:
1087         case V4L2_PIX_FMT_SGBRG10:
1088         case V4L2_PIX_FMT_SGRBG10:
1089         case V4L2_PIX_FMT_SRGGB10:
1090                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
1091                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1092                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1093                 isc->try_config.bpp = 16;
1094                 break;
1095         case V4L2_PIX_FMT_SBGGR12:
1096         case V4L2_PIX_FMT_SGBRG12:
1097         case V4L2_PIX_FMT_SGRBG12:
1098         case V4L2_PIX_FMT_SRGGB12:
1099                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
1100                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1101                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1102                 isc->try_config.bpp = 16;
1103                 break;
1104         case V4L2_PIX_FMT_RGB565:
1105                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
1106                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1107                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1108                 isc->try_config.bpp = 16;
1109                 break;
1110         case V4L2_PIX_FMT_ARGB444:
1111                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
1112                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1113                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1114                 isc->try_config.bpp = 16;
1115                 break;
1116         case V4L2_PIX_FMT_ARGB555:
1117                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
1118                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1119                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1120                 isc->try_config.bpp = 16;
1121                 break;
1122         case V4L2_PIX_FMT_ABGR32:
1123         case V4L2_PIX_FMT_XBGR32:
1124                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
1125                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1126                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1127                 isc->try_config.bpp = 32;
1128                 break;
1129         case V4L2_PIX_FMT_YUV420:
1130                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1131                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
1132                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1133                 isc->try_config.bpp = 12;
1134                 break;
1135         case V4L2_PIX_FMT_YUV422P:
1136                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1137                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
1138                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1139                 isc->try_config.bpp = 16;
1140                 break;
1141         case V4L2_PIX_FMT_YUYV:
1142                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1143                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1144                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1145                 isc->try_config.bpp = 16;
1146                 break;
1147         case V4L2_PIX_FMT_GREY:
1148                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
1149                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1150                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1151                 isc->try_config.bpp = 8;
1152                 break;
1153         case V4L2_PIX_FMT_Y10:
1154                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
1155                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1156                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1157                 isc->try_config.bpp = 16;
1158                 break;
1159         default:
1160                 return -EINVAL;
1161         }
1162
1163         if (direct_dump) {
1164                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1165                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1166                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1167                 return 0;
1168         }
1169
1170         return 0;
1171 }
1172
1173 /*
1174  * Configuring pipeline modules, depending on which format the ISC outputs
1175  * and considering which format it has as input from the sensor.
1176  */
1177 static int isc_try_configure_pipeline(struct isc_device *isc)
1178 {
1179         switch (isc->try_config.fourcc) {
1180         case V4L2_PIX_FMT_RGB565:
1181         case V4L2_PIX_FMT_ARGB555:
1182         case V4L2_PIX_FMT_ARGB444:
1183         case V4L2_PIX_FMT_ABGR32:
1184         case V4L2_PIX_FMT_XBGR32:
1185                 /* if sensor format is RAW, we convert inside ISC */
1186                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1187                         isc->try_config.bits_pipeline = CFA_ENABLE |
1188                                 WB_ENABLE | GAM_ENABLES;
1189                 } else {
1190                         isc->try_config.bits_pipeline = 0x0;
1191                 }
1192                 break;
1193         case V4L2_PIX_FMT_YUV420:
1194                 /* if sensor format is RAW, we convert inside ISC */
1195                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1196                         isc->try_config.bits_pipeline = CFA_ENABLE |
1197                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1198                                 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
1199                 } else {
1200                         isc->try_config.bits_pipeline = 0x0;
1201                 }
1202                 break;
1203         case V4L2_PIX_FMT_YUV422P:
1204                 /* if sensor format is RAW, we convert inside ISC */
1205                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1206                         isc->try_config.bits_pipeline = CFA_ENABLE |
1207                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1208                                 SUB422_ENABLE | CBC_ENABLE;
1209                 } else {
1210                         isc->try_config.bits_pipeline = 0x0;
1211                 }
1212                 break;
1213         case V4L2_PIX_FMT_YUYV:
1214                 /* if sensor format is RAW, we convert inside ISC */
1215                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1216                         isc->try_config.bits_pipeline = CFA_ENABLE |
1217                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1218                                 SUB422_ENABLE | CBC_ENABLE;
1219                 } else {
1220                         isc->try_config.bits_pipeline = 0x0;
1221                 }
1222                 break;
1223         case V4L2_PIX_FMT_GREY:
1224                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1225                 /* if sensor format is RAW, we convert inside ISC */
1226                         isc->try_config.bits_pipeline = CFA_ENABLE |
1227                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1228                                 CBC_ENABLE;
1229                 } else {
1230                         isc->try_config.bits_pipeline = 0x0;
1231                 }
1232                 break;
1233         default:
1234                 isc->try_config.bits_pipeline = 0x0;
1235         }
1236         return 0;
1237 }
1238
1239 static void isc_try_fse(struct isc_device *isc,
1240                         struct v4l2_subdev_pad_config *pad_cfg)
1241 {
1242         int ret;
1243         struct v4l2_subdev_frame_size_enum fse = {};
1244
1245         /*
1246          * If we do not know yet which format the subdev is using, we cannot
1247          * do anything.
1248          */
1249         if (!isc->try_config.sd_format)
1250                 return;
1251
1252         fse.code = isc->try_config.sd_format->mbus_code;
1253         fse.which = V4L2_SUBDEV_FORMAT_TRY;
1254
1255         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1256                                pad_cfg, &fse);
1257         /*
1258          * Attempt to obtain format size from subdev. If not available,
1259          * just use the maximum ISC can receive.
1260          */
1261         if (ret) {
1262                 pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH;
1263                 pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT;
1264         } else {
1265                 pad_cfg->try_crop.width = fse.max_width;
1266                 pad_cfg->try_crop.height = fse.max_height;
1267         }
1268 }
1269
1270 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
1271                         u32 *code)
1272 {
1273         int i;
1274         struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
1275         struct v4l2_pix_format *pixfmt = &f->fmt.pix;
1276         struct v4l2_subdev_pad_config pad_cfg = {};
1277         struct v4l2_subdev_format format = {
1278                 .which = V4L2_SUBDEV_FORMAT_TRY,
1279         };
1280         u32 mbus_code;
1281         int ret;
1282         bool rlp_dma_direct_dump = false;
1283
1284         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1285                 return -EINVAL;
1286
1287         /* Step 1: find a RAW format that is supported */
1288         for (i = 0; i < isc->num_user_formats; i++) {
1289                 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
1290                         sd_fmt = isc->user_formats[i];
1291                         break;
1292                 }
1293         }
1294         /* Step 2: We can continue with this RAW format, or we can look
1295          * for better: maybe sensor supports directly what we need.
1296          */
1297         direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
1298
1299         /* Step 3: We have both. We decide given the module parameter which
1300          * one to use.
1301          */
1302         if (direct_fmt && sd_fmt && sensor_preferred)
1303                 sd_fmt = direct_fmt;
1304
1305         /* Step 4: we do not have RAW but we have a direct format. Use it. */
1306         if (direct_fmt && !sd_fmt)
1307                 sd_fmt = direct_fmt;
1308
1309         /* Step 5: if we are using a direct format, we need to package
1310          * everything as 8 bit data and just dump it
1311          */
1312         if (sd_fmt == direct_fmt)
1313                 rlp_dma_direct_dump = true;
1314
1315         /* Step 6: We have no format. This can happen if the userspace
1316          * requests some weird/invalid format.
1317          * In this case, default to whatever we have
1318          */
1319         if (!sd_fmt && !direct_fmt) {
1320                 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
1321                 v4l2_dbg(1, debug, &isc->v4l2_dev,
1322                          "Sensor not supporting %.4s, using %.4s\n",
1323                          (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
1324         }
1325
1326         if (!sd_fmt) {
1327                 ret = -EINVAL;
1328                 goto isc_try_fmt_err;
1329         }
1330
1331         /* Step 7: Print out what we decided for debugging */
1332         v4l2_dbg(1, debug, &isc->v4l2_dev,
1333                  "Preferring to have sensor using format %.4s\n",
1334                  (char *)&sd_fmt->fourcc);
1335
1336         /* Step 8: at this moment we decided which format the subdev will use */
1337         isc->try_config.sd_format = sd_fmt;
1338
1339         /* Limit to Atmel ISC hardware capabilities */
1340         if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
1341                 pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
1342         if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
1343                 pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
1344
1345         /*
1346          * The mbus format is the one the subdev outputs.
1347          * The pixels will be transferred in this format Sensor -> ISC
1348          */
1349         mbus_code = sd_fmt->mbus_code;
1350
1351         /*
1352          * Validate formats. If the required format is not OK, default to raw.
1353          */
1354
1355         isc->try_config.fourcc = pixfmt->pixelformat;
1356
1357         if (isc_try_validate_formats(isc)) {
1358                 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
1359                 /* Re-try to validate the new format */
1360                 ret = isc_try_validate_formats(isc);
1361                 if (ret)
1362                         goto isc_try_fmt_err;
1363         }
1364
1365         ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
1366         if (ret)
1367                 goto isc_try_fmt_err;
1368
1369         ret = isc_try_configure_pipeline(isc);
1370         if (ret)
1371                 goto isc_try_fmt_err;
1372
1373         /* Obtain frame sizes if possible to have crop requirements ready */
1374         isc_try_fse(isc, &pad_cfg);
1375
1376         v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
1377         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
1378                                &pad_cfg, &format);
1379         if (ret < 0)
1380                 goto isc_try_fmt_subdev_err;
1381
1382         v4l2_fill_pix_format(pixfmt, &format.format);
1383
1384         pixfmt->field = V4L2_FIELD_NONE;
1385         pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
1386         pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
1387
1388         if (code)
1389                 *code = mbus_code;
1390
1391         return 0;
1392
1393 isc_try_fmt_err:
1394         v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
1395 isc_try_fmt_subdev_err:
1396         memset(&isc->try_config, 0, sizeof(isc->try_config));
1397
1398         return ret;
1399 }
1400
1401 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
1402 {
1403         struct v4l2_subdev_format format = {
1404                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1405         };
1406         u32 mbus_code = 0;
1407         int ret;
1408
1409         ret = isc_try_fmt(isc, f, &mbus_code);
1410         if (ret)
1411                 return ret;
1412
1413         v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1414         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1415                                set_fmt, NULL, &format);
1416         if (ret < 0)
1417                 return ret;
1418
1419         isc->fmt = *f;
1420
1421         if (isc->try_config.sd_format && isc->config.sd_format &&
1422             isc->try_config.sd_format != isc->config.sd_format) {
1423                 isc->ctrls.hist_stat = HIST_INIT;
1424                 isc_reset_awb_ctrls(isc);
1425                 isc_update_v4l2_ctrls(isc);
1426         }
1427         /* make the try configuration active */
1428         isc->config = isc->try_config;
1429
1430         v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1431
1432         return 0;
1433 }
1434
1435 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1436                               struct v4l2_format *f)
1437 {
1438         struct isc_device *isc = video_drvdata(file);
1439
1440         if (vb2_is_streaming(&isc->vb2_vidq))
1441                 return -EBUSY;
1442
1443         return isc_set_fmt(isc, f);
1444 }
1445
1446 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1447                                 struct v4l2_format *f)
1448 {
1449         struct isc_device *isc = video_drvdata(file);
1450
1451         return isc_try_fmt(isc, f, NULL);
1452 }
1453
1454 static int isc_enum_input(struct file *file, void *priv,
1455                            struct v4l2_input *inp)
1456 {
1457         if (inp->index != 0)
1458                 return -EINVAL;
1459
1460         inp->type = V4L2_INPUT_TYPE_CAMERA;
1461         inp->std = 0;
1462         strscpy(inp->name, "Camera", sizeof(inp->name));
1463
1464         return 0;
1465 }
1466
1467 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1468 {
1469         *i = 0;
1470
1471         return 0;
1472 }
1473
1474 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1475 {
1476         if (i > 0)
1477                 return -EINVAL;
1478
1479         return 0;
1480 }
1481
1482 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1483 {
1484         struct isc_device *isc = video_drvdata(file);
1485
1486         return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1487 }
1488
1489 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1490 {
1491         struct isc_device *isc = video_drvdata(file);
1492
1493         return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1494 }
1495
1496 static int isc_enum_framesizes(struct file *file, void *fh,
1497                                struct v4l2_frmsizeenum *fsize)
1498 {
1499         struct isc_device *isc = video_drvdata(file);
1500         struct v4l2_subdev_frame_size_enum fse = {
1501                 .code = isc->config.sd_format->mbus_code,
1502                 .index = fsize->index,
1503                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1504         };
1505         int ret = -EINVAL;
1506         int i;
1507
1508         for (i = 0; i < isc->num_user_formats; i++)
1509                 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1510                         ret = 0;
1511
1512         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1513                 if (controller_formats[i].fourcc == fsize->pixel_format)
1514                         ret = 0;
1515
1516         if (ret)
1517                 return ret;
1518
1519         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1520                                NULL, &fse);
1521         if (ret)
1522                 return ret;
1523
1524         fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1525         fsize->discrete.width = fse.max_width;
1526         fsize->discrete.height = fse.max_height;
1527
1528         return 0;
1529 }
1530
1531 static int isc_enum_frameintervals(struct file *file, void *fh,
1532                                     struct v4l2_frmivalenum *fival)
1533 {
1534         struct isc_device *isc = video_drvdata(file);
1535         struct v4l2_subdev_frame_interval_enum fie = {
1536                 .code = isc->config.sd_format->mbus_code,
1537                 .index = fival->index,
1538                 .width = fival->width,
1539                 .height = fival->height,
1540                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1541         };
1542         int ret = -EINVAL;
1543         unsigned int i;
1544
1545         for (i = 0; i < isc->num_user_formats; i++)
1546                 if (isc->user_formats[i]->fourcc == fival->pixel_format)
1547                         ret = 0;
1548
1549         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1550                 if (controller_formats[i].fourcc == fival->pixel_format)
1551                         ret = 0;
1552
1553         if (ret)
1554                 return ret;
1555
1556         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1557                                enum_frame_interval, NULL, &fie);
1558         if (ret)
1559                 return ret;
1560
1561         fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1562         fival->discrete = fie.interval;
1563
1564         return 0;
1565 }
1566
1567 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1568         .vidioc_querycap                = isc_querycap,
1569         .vidioc_enum_fmt_vid_cap        = isc_enum_fmt_vid_cap,
1570         .vidioc_g_fmt_vid_cap           = isc_g_fmt_vid_cap,
1571         .vidioc_s_fmt_vid_cap           = isc_s_fmt_vid_cap,
1572         .vidioc_try_fmt_vid_cap         = isc_try_fmt_vid_cap,
1573
1574         .vidioc_enum_input              = isc_enum_input,
1575         .vidioc_g_input                 = isc_g_input,
1576         .vidioc_s_input                 = isc_s_input,
1577
1578         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1579         .vidioc_querybuf                = vb2_ioctl_querybuf,
1580         .vidioc_qbuf                    = vb2_ioctl_qbuf,
1581         .vidioc_expbuf                  = vb2_ioctl_expbuf,
1582         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1583         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1584         .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1585         .vidioc_streamon                = vb2_ioctl_streamon,
1586         .vidioc_streamoff               = vb2_ioctl_streamoff,
1587
1588         .vidioc_g_parm                  = isc_g_parm,
1589         .vidioc_s_parm                  = isc_s_parm,
1590         .vidioc_enum_framesizes         = isc_enum_framesizes,
1591         .vidioc_enum_frameintervals     = isc_enum_frameintervals,
1592
1593         .vidioc_log_status              = v4l2_ctrl_log_status,
1594         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
1595         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1596 };
1597
1598 static int isc_open(struct file *file)
1599 {
1600         struct isc_device *isc = video_drvdata(file);
1601         struct v4l2_subdev *sd = isc->current_subdev->sd;
1602         int ret;
1603
1604         if (mutex_lock_interruptible(&isc->lock))
1605                 return -ERESTARTSYS;
1606
1607         ret = v4l2_fh_open(file);
1608         if (ret < 0)
1609                 goto unlock;
1610
1611         if (!v4l2_fh_is_singular_file(file))
1612                 goto unlock;
1613
1614         ret = v4l2_subdev_call(sd, core, s_power, 1);
1615         if (ret < 0 && ret != -ENOIOCTLCMD) {
1616                 v4l2_fh_release(file);
1617                 goto unlock;
1618         }
1619
1620         ret = isc_set_fmt(isc, &isc->fmt);
1621         if (ret) {
1622                 v4l2_subdev_call(sd, core, s_power, 0);
1623                 v4l2_fh_release(file);
1624         }
1625
1626 unlock:
1627         mutex_unlock(&isc->lock);
1628         return ret;
1629 }
1630
1631 static int isc_release(struct file *file)
1632 {
1633         struct isc_device *isc = video_drvdata(file);
1634         struct v4l2_subdev *sd = isc->current_subdev->sd;
1635         bool fh_singular;
1636         int ret;
1637
1638         mutex_lock(&isc->lock);
1639
1640         fh_singular = v4l2_fh_is_singular_file(file);
1641
1642         ret = _vb2_fop_release(file, NULL);
1643
1644         if (fh_singular)
1645                 v4l2_subdev_call(sd, core, s_power, 0);
1646
1647         mutex_unlock(&isc->lock);
1648
1649         return ret;
1650 }
1651
1652 static const struct v4l2_file_operations isc_fops = {
1653         .owner          = THIS_MODULE,
1654         .open           = isc_open,
1655         .release        = isc_release,
1656         .unlocked_ioctl = video_ioctl2,
1657         .read           = vb2_fop_read,
1658         .mmap           = vb2_fop_mmap,
1659         .poll           = vb2_fop_poll,
1660 };
1661
1662 irqreturn_t isc_interrupt(int irq, void *dev_id)
1663 {
1664         struct isc_device *isc = (struct isc_device *)dev_id;
1665         struct regmap *regmap = isc->regmap;
1666         u32 isc_intsr, isc_intmask, pending;
1667         irqreturn_t ret = IRQ_NONE;
1668
1669         regmap_read(regmap, ISC_INTSR, &isc_intsr);
1670         regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1671
1672         pending = isc_intsr & isc_intmask;
1673
1674         if (likely(pending & ISC_INT_DDONE)) {
1675                 spin_lock(&isc->dma_queue_lock);
1676                 if (isc->cur_frm) {
1677                         struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1678                         struct vb2_buffer *vb = &vbuf->vb2_buf;
1679
1680                         vb->timestamp = ktime_get_ns();
1681                         vbuf->sequence = isc->sequence++;
1682                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1683                         isc->cur_frm = NULL;
1684                 }
1685
1686                 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1687                         isc->cur_frm = list_first_entry(&isc->dma_queue,
1688                                                      struct isc_buffer, list);
1689                         list_del(&isc->cur_frm->list);
1690
1691                         isc_start_dma(isc);
1692                 }
1693
1694                 if (isc->stop)
1695                         complete(&isc->comp);
1696
1697                 ret = IRQ_HANDLED;
1698                 spin_unlock(&isc->dma_queue_lock);
1699         }
1700
1701         if (pending & ISC_INT_HISDONE) {
1702                 schedule_work(&isc->awb_work);
1703                 ret = IRQ_HANDLED;
1704         }
1705
1706         return ret;
1707 }
1708
1709 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1710 {
1711         struct regmap *regmap = isc->regmap;
1712         struct isc_ctrls *ctrls = &isc->ctrls;
1713         u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1714         u32 *hist_entry = &ctrls->hist_entry[0];
1715         u32 i;
1716
1717         *min = 0;
1718         *max = HIST_ENTRIES;
1719
1720         regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);
1721
1722         *hist_count = 0;
1723         /*
1724          * we deliberately ignore the end of the histogram,
1725          * the most white pixels
1726          */
1727         for (i = 1; i < HIST_ENTRIES; i++) {
1728                 if (*hist_entry && !*min)
1729                         *min = i;
1730                 if (*hist_entry)
1731                         *max = i;
1732                 *hist_count += i * (*hist_entry++);
1733         }
1734
1735         if (!*min)
1736                 *min = 1;
1737 }
1738
1739 static void isc_wb_update(struct isc_ctrls *ctrls)
1740 {
1741         u32 *hist_count = &ctrls->hist_count[0];
1742         u32 c, offset[4];
1743         u64 avg = 0;
1744         /* We compute two gains, stretch gain and grey world gain */
1745         u32 s_gain[4], gw_gain[4];
1746
1747         /*
1748          * According to Grey World, we need to set gains for R/B to normalize
1749          * them towards the green channel.
1750          * Thus we want to keep Green as fixed and adjust only Red/Blue
1751          * Compute the average of the both green channels first
1752          */
1753         avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1754                 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1755         avg >>= 1;
1756
1757         /* Green histogram is null, nothing to do */
1758         if (!avg)
1759                 return;
1760
1761         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1762                 /*
1763                  * the color offset is the minimum value of the histogram.
1764                  * we stretch this color to the full range by substracting
1765                  * this value from the color component.
1766                  */
1767                 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1768                 /*
1769                  * The offset is always at least 1. If the offset is 1, we do
1770                  * not need to adjust it, so our result must be zero.
1771                  * the offset is computed in a histogram on 9 bits (0..512)
1772                  * but the offset in register is based on
1773                  * 12 bits pipeline (0..4096).
1774                  * we need to shift with the 3 bits that the histogram is
1775                  * ignoring
1776                  */
1777                 ctrls->offset[c] = (offset[c] - 1) << 3;
1778
1779                 /*
1780                  * the offset is then taken and converted to 2's complements,
1781                  * and must be negative, as we subtract this value from the
1782                  * color components
1783                  */
1784                 ctrls->offset[c] = -ctrls->offset[c];
1785
1786                 /*
1787                  * the stretch gain is the total number of histogram bins
1788                  * divided by the actual range of color component (Max - Min)
1789                  * If we compute gain like this, the actual color component
1790                  * will be stretched to the full histogram.
1791                  * We need to shift 9 bits for precision, we have 9 bits for
1792                  * decimals
1793                  */
1794                 s_gain[c] = (HIST_ENTRIES << 9) /
1795                         (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1796                         ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1797
1798                 /*
1799                  * Now we have to compute the gain w.r.t. the average.
1800                  * Add/lose gain to the component towards the average.
1801                  * If it happens that the component is zero, use the
1802                  * fixed point value : 1.0 gain.
1803                  */
1804                 if (hist_count[c])
1805                         gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1806                 else
1807                         gw_gain[c] = 1 << 9;
1808
1809                 /* multiply both gains and adjust for decimals */
1810                 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1811                 ctrls->gain[c] >>= 9;
1812         }
1813 }
1814
1815 static void isc_awb_work(struct work_struct *w)
1816 {
1817         struct isc_device *isc =
1818                 container_of(w, struct isc_device, awb_work);
1819         struct regmap *regmap = isc->regmap;
1820         struct isc_ctrls *ctrls = &isc->ctrls;
1821         u32 hist_id = ctrls->hist_id;
1822         u32 baysel;
1823         unsigned long flags;
1824         u32 min, max;
1825         int ret;
1826
1827         /* streaming is not active anymore */
1828         if (isc->stop)
1829                 return;
1830
1831         if (ctrls->hist_stat != HIST_ENABLED)
1832                 return;
1833
1834         isc_hist_count(isc, &min, &max);
1835         ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1836         ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1837
1838         if (hist_id != ISC_HIS_CFG_MODE_B) {
1839                 hist_id++;
1840         } else {
1841                 isc_wb_update(ctrls);
1842                 hist_id = ISC_HIS_CFG_MODE_GR;
1843         }
1844
1845         ctrls->hist_id = hist_id;
1846         baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1847
1848         ret = pm_runtime_resume_and_get(isc->dev);
1849         if (ret < 0)
1850                 return;
1851
1852         /*
1853          * only update if we have all the required histograms and controls
1854          * if awb has been disabled, we need to reset registers as well.
1855          */
1856         if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1857                 /*
1858                  * It may happen that DMA Done IRQ will trigger while we are
1859                  * updating white balance registers here.
1860                  * In that case, only parts of the controls have been updated.
1861                  * We can avoid that by locking the section.
1862                  */
1863                 spin_lock_irqsave(&isc->awb_lock, flags);
1864                 isc_update_awb_ctrls(isc);
1865                 spin_unlock_irqrestore(&isc->awb_lock, flags);
1866
1867                 /*
1868                  * if we are doing just the one time white balance adjustment,
1869                  * we are basically done.
1870                  */
1871                 if (ctrls->awb == ISC_WB_ONETIME) {
1872                         v4l2_info(&isc->v4l2_dev,
1873                                   "Completed one time white-balance adjustment.\n");
1874                         /* update the v4l2 controls values */
1875                         isc_update_v4l2_ctrls(isc);
1876                         ctrls->awb = ISC_WB_NONE;
1877                 }
1878         }
1879         regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);
1880         isc_update_profile(isc);
1881         /* if awb has been disabled, we don't need to start another histogram */
1882         if (ctrls->awb)
1883                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1884
1885         pm_runtime_put_sync(isc->dev);
1886 }
1887
1888 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1889 {
1890         struct isc_device *isc = container_of(ctrl->handler,
1891                                              struct isc_device, ctrls.handler);
1892         struct isc_ctrls *ctrls = &isc->ctrls;
1893
1894         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1895                 return 0;
1896
1897         switch (ctrl->id) {
1898         case V4L2_CID_BRIGHTNESS:
1899                 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1900                 break;
1901         case V4L2_CID_CONTRAST:
1902                 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1903                 break;
1904         case V4L2_CID_GAMMA:
1905                 ctrls->gamma_index = ctrl->val;
1906                 break;
1907         default:
1908                 return -EINVAL;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1915         .s_ctrl = isc_s_ctrl,
1916 };
1917
1918 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1919 {
1920         struct isc_device *isc = container_of(ctrl->handler,
1921                                              struct isc_device, ctrls.handler);
1922         struct isc_ctrls *ctrls = &isc->ctrls;
1923
1924         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1925                 return 0;
1926
1927         switch (ctrl->id) {
1928         case V4L2_CID_AUTO_WHITE_BALANCE:
1929                 if (ctrl->val == 1)
1930                         ctrls->awb = ISC_WB_AUTO;
1931                 else
1932                         ctrls->awb = ISC_WB_NONE;
1933
1934                 /* we did not configure ISC yet */
1935                 if (!isc->config.sd_format)
1936                         break;
1937
1938                 /* configure the controls with new values from v4l2 */
1939                 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1940                         ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1941                 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1942                         ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1943                 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1944                         ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1945                 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1946                         ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1947
1948                 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1949                         ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1950                 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1951                         ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1952                 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1953                         ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1954                 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1955                         ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1956
1957                 isc_update_awb_ctrls(isc);
1958
1959                 if (vb2_is_streaming(&isc->vb2_vidq)) {
1960                         /*
1961                          * If we are streaming, we can update profile to
1962                          * have the new settings in place.
1963                          */
1964                         isc_update_profile(isc);
1965                 } else {
1966                         /*
1967                          * The auto cluster will activate automatically this
1968                          * control. This has to be deactivated when not
1969                          * streaming.
1970                          */
1971                         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1972                 }
1973
1974                 /* if we have autowhitebalance on, start histogram procedure */
1975                 if (ctrls->awb == ISC_WB_AUTO &&
1976                     vb2_is_streaming(&isc->vb2_vidq) &&
1977                     ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1978                         isc_set_histogram(isc, true);
1979
1980                 /*
1981                  * for one time whitebalance adjustment, check the button,
1982                  * if it's pressed, perform the one time operation.
1983                  */
1984                 if (ctrls->awb == ISC_WB_NONE &&
1985                     ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1986                     !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1987                     V4L2_CTRL_FLAG_INACTIVE)) {
1988                         ctrls->awb = ISC_WB_ONETIME;
1989                         isc_set_histogram(isc, true);
1990                         v4l2_dbg(1, debug, &isc->v4l2_dev,
1991                                  "One time white-balance started.\n");
1992                 }
1993                 return 0;
1994         }
1995         return 0;
1996 }
1997
1998 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1999 {
2000         struct isc_device *isc = container_of(ctrl->handler,
2001                                              struct isc_device, ctrls.handler);
2002         struct isc_ctrls *ctrls = &isc->ctrls;
2003
2004         switch (ctrl->id) {
2005         /* being a cluster, this id will be called for every control */
2006         case V4L2_CID_AUTO_WHITE_BALANCE:
2007                 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
2008                                         ctrls->gain[ISC_HIS_CFG_MODE_R];
2009                 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
2010                                         ctrls->gain[ISC_HIS_CFG_MODE_B];
2011                 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
2012                                         ctrls->gain[ISC_HIS_CFG_MODE_GR];
2013                 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
2014                                         ctrls->gain[ISC_HIS_CFG_MODE_GB];
2015
2016                 ctrl->cluster[ISC_CTRL_R_OFF]->val =
2017                         ctrls->offset[ISC_HIS_CFG_MODE_R];
2018                 ctrl->cluster[ISC_CTRL_B_OFF]->val =
2019                         ctrls->offset[ISC_HIS_CFG_MODE_B];
2020                 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
2021                         ctrls->offset[ISC_HIS_CFG_MODE_GR];
2022                 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
2023                         ctrls->offset[ISC_HIS_CFG_MODE_GB];
2024                 break;
2025         }
2026         return 0;
2027 }
2028
2029 static const struct v4l2_ctrl_ops isc_awb_ops = {
2030         .s_ctrl = isc_s_awb_ctrl,
2031         .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
2032 };
2033
2034 #define ISC_CTRL_OFF(_name, _id, _name_str) \
2035         static const struct v4l2_ctrl_config _name = { \
2036                 .ops = &isc_awb_ops, \
2037                 .id = _id, \
2038                 .name = _name_str, \
2039                 .type = V4L2_CTRL_TYPE_INTEGER, \
2040                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2041                 .min = -4095, \
2042                 .max = 4095, \
2043                 .step = 1, \
2044                 .def = 0, \
2045         }
2046
2047 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
2048 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
2049 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
2050 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
2051
2052 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
2053         static const struct v4l2_ctrl_config _name = { \
2054                 .ops = &isc_awb_ops, \
2055                 .id = _id, \
2056                 .name = _name_str, \
2057                 .type = V4L2_CTRL_TYPE_INTEGER, \
2058                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2059                 .min = 0, \
2060                 .max = 8191, \
2061                 .step = 1, \
2062                 .def = 512, \
2063         }
2064
2065 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
2066 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
2067 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
2068 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
2069
2070 static int isc_ctrl_init(struct isc_device *isc)
2071 {
2072         const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
2073         struct isc_ctrls *ctrls = &isc->ctrls;
2074         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
2075         int ret;
2076
2077         ctrls->hist_stat = HIST_INIT;
2078         isc_reset_awb_ctrls(isc);
2079
2080         ret = v4l2_ctrl_handler_init(hdl, 13);
2081         if (ret < 0)
2082                 return ret;
2083
2084         ctrls->brightness = 0;
2085         ctrls->contrast = 256;
2086
2087         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
2088         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
2089         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2);
2090         isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2091                                           V4L2_CID_AUTO_WHITE_BALANCE,
2092                                           0, 1, 1, 1);
2093
2094         /* do_white_balance is a button, so min,max,step,default are ignored */
2095         isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2096                                             V4L2_CID_DO_WHITE_BALANCE,
2097                                             0, 0, 0, 0);
2098
2099         if (!isc->do_wb_ctrl) {
2100                 ret = hdl->error;
2101                 v4l2_ctrl_handler_free(hdl);
2102                 return ret;
2103         }
2104
2105         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
2106
2107         isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
2108         isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
2109         isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
2110         isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
2111         isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
2112         isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
2113         isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
2114         isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
2115
2116         /*
2117          * The cluster is in auto mode with autowhitebalance enabled
2118          * and manual mode otherwise.
2119          */
2120         v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
2121
2122         v4l2_ctrl_handler_setup(hdl);
2123
2124         return 0;
2125 }
2126
2127 static int isc_async_bound(struct v4l2_async_notifier *notifier,
2128                             struct v4l2_subdev *subdev,
2129                             struct v4l2_async_subdev *asd)
2130 {
2131         struct isc_device *isc = container_of(notifier->v4l2_dev,
2132                                               struct isc_device, v4l2_dev);
2133         struct isc_subdev_entity *subdev_entity =
2134                 container_of(notifier, struct isc_subdev_entity, notifier);
2135
2136         if (video_is_registered(&isc->video_dev)) {
2137                 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
2138                 return -EBUSY;
2139         }
2140
2141         subdev_entity->sd = subdev;
2142
2143         return 0;
2144 }
2145
2146 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
2147                               struct v4l2_subdev *subdev,
2148                               struct v4l2_async_subdev *asd)
2149 {
2150         struct isc_device *isc = container_of(notifier->v4l2_dev,
2151                                               struct isc_device, v4l2_dev);
2152         cancel_work_sync(&isc->awb_work);
2153         video_unregister_device(&isc->video_dev);
2154         v4l2_ctrl_handler_free(&isc->ctrls.handler);
2155 }
2156
2157 static struct isc_format *find_format_by_code(unsigned int code, int *index)
2158 {
2159         struct isc_format *fmt = &formats_list[0];
2160         unsigned int i;
2161
2162         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
2163                 if (fmt->mbus_code == code) {
2164                         *index = i;
2165                         return fmt;
2166                 }
2167
2168                 fmt++;
2169         }
2170
2171         return NULL;
2172 }
2173
2174 static int isc_formats_init(struct isc_device *isc)
2175 {
2176         struct isc_format *fmt;
2177         struct v4l2_subdev *subdev = isc->current_subdev->sd;
2178         unsigned int num_fmts, i, j;
2179         u32 list_size = ARRAY_SIZE(formats_list);
2180         struct v4l2_subdev_mbus_code_enum mbus_code = {
2181                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2182         };
2183
2184         num_fmts = 0;
2185         while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
2186                NULL, &mbus_code)) {
2187                 mbus_code.index++;
2188
2189                 fmt = find_format_by_code(mbus_code.code, &i);
2190                 if (!fmt) {
2191                         v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
2192                                   mbus_code.code);
2193                         continue;
2194                 }
2195
2196                 fmt->sd_support = true;
2197                 num_fmts++;
2198         }
2199
2200         if (!num_fmts)
2201                 return -ENXIO;
2202
2203         isc->num_user_formats = num_fmts;
2204         isc->user_formats = devm_kcalloc(isc->dev,
2205                                          num_fmts, sizeof(*isc->user_formats),
2206                                          GFP_KERNEL);
2207         if (!isc->user_formats)
2208                 return -ENOMEM;
2209
2210         fmt = &formats_list[0];
2211         for (i = 0, j = 0; i < list_size; i++) {
2212                 if (fmt->sd_support)
2213                         isc->user_formats[j++] = fmt;
2214                 fmt++;
2215         }
2216
2217         return 0;
2218 }
2219
2220 static int isc_set_default_fmt(struct isc_device *isc)
2221 {
2222         struct v4l2_format f = {
2223                 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
2224                 .fmt.pix = {
2225                         .width          = VGA_WIDTH,
2226                         .height         = VGA_HEIGHT,
2227                         .field          = V4L2_FIELD_NONE,
2228                         .pixelformat    = isc->user_formats[0]->fourcc,
2229                 },
2230         };
2231         int ret;
2232
2233         ret = isc_try_fmt(isc, &f, NULL);
2234         if (ret)
2235                 return ret;
2236
2237         isc->fmt = f;
2238         return 0;
2239 }
2240
2241 static int isc_async_complete(struct v4l2_async_notifier *notifier)
2242 {
2243         struct isc_device *isc = container_of(notifier->v4l2_dev,
2244                                               struct isc_device, v4l2_dev);
2245         struct video_device *vdev = &isc->video_dev;
2246         struct vb2_queue *q = &isc->vb2_vidq;
2247         int ret = 0;
2248
2249         INIT_WORK(&isc->awb_work, isc_awb_work);
2250
2251         ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
2252         if (ret < 0) {
2253                 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
2254                 return ret;
2255         }
2256
2257         isc->current_subdev = container_of(notifier,
2258                                            struct isc_subdev_entity, notifier);
2259         mutex_init(&isc->lock);
2260         init_completion(&isc->comp);
2261
2262         /* Initialize videobuf2 queue */
2263         q->type                 = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2264         q->io_modes             = VB2_MMAP | VB2_DMABUF | VB2_READ;
2265         q->drv_priv             = isc;
2266         q->buf_struct_size      = sizeof(struct isc_buffer);
2267         q->ops                  = &isc_vb2_ops;
2268         q->mem_ops              = &vb2_dma_contig_memops;
2269         q->timestamp_flags      = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2270         q->lock                 = &isc->lock;
2271         q->min_buffers_needed   = 1;
2272         q->dev                  = isc->dev;
2273
2274         ret = vb2_queue_init(q);
2275         if (ret < 0) {
2276                 v4l2_err(&isc->v4l2_dev,
2277                          "vb2_queue_init() failed: %d\n", ret);
2278                 goto isc_async_complete_err;
2279         }
2280
2281         /* Init video dma queues */
2282         INIT_LIST_HEAD(&isc->dma_queue);
2283         spin_lock_init(&isc->dma_queue_lock);
2284         spin_lock_init(&isc->awb_lock);
2285
2286         ret = isc_formats_init(isc);
2287         if (ret < 0) {
2288                 v4l2_err(&isc->v4l2_dev,
2289                          "Init format failed: %d\n", ret);
2290                 goto isc_async_complete_err;
2291         }
2292
2293         ret = isc_set_default_fmt(isc);
2294         if (ret) {
2295                 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
2296                 goto isc_async_complete_err;
2297         }
2298
2299         ret = isc_ctrl_init(isc);
2300         if (ret) {
2301                 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
2302                 goto isc_async_complete_err;
2303         }
2304
2305         /* Register video device */
2306         strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name));
2307         vdev->release           = video_device_release_empty;
2308         vdev->fops              = &isc_fops;
2309         vdev->ioctl_ops         = &isc_ioctl_ops;
2310         vdev->v4l2_dev          = &isc->v4l2_dev;
2311         vdev->vfl_dir           = VFL_DIR_RX;
2312         vdev->queue             = q;
2313         vdev->lock              = &isc->lock;
2314         vdev->ctrl_handler      = &isc->ctrls.handler;
2315         vdev->device_caps       = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
2316         video_set_drvdata(vdev, isc);
2317
2318         ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2319         if (ret < 0) {
2320                 v4l2_err(&isc->v4l2_dev,
2321                          "video_register_device failed: %d\n", ret);
2322                 goto isc_async_complete_err;
2323         }
2324
2325         return 0;
2326
2327 isc_async_complete_err:
2328         mutex_destroy(&isc->lock);
2329         return ret;
2330 }
2331
2332 const struct v4l2_async_notifier_operations isc_async_ops = {
2333         .bound = isc_async_bound,
2334         .unbind = isc_async_unbind,
2335         .complete = isc_async_complete,
2336 };
2337
2338 void isc_subdev_cleanup(struct isc_device *isc)
2339 {
2340         struct isc_subdev_entity *subdev_entity;
2341
2342         list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
2343                 v4l2_async_notifier_unregister(&subdev_entity->notifier);
2344                 v4l2_async_notifier_cleanup(&subdev_entity->notifier);
2345         }
2346
2347         INIT_LIST_HEAD(&isc->subdev_entities);
2348 }
2349
2350 int isc_pipeline_init(struct isc_device *isc)
2351 {
2352         struct device *dev = isc->dev;
2353         struct regmap *regmap = isc->regmap;
2354         struct regmap_field *regs;
2355         unsigned int i;
2356
2357         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
2358         const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
2359                 REG_FIELD(ISC_WB_CTRL, 0, 0),
2360                 REG_FIELD(ISC_CFA_CTRL, 0, 0),
2361                 REG_FIELD(ISC_CC_CTRL, 0, 0),
2362                 REG_FIELD(ISC_GAM_CTRL, 0, 0),
2363                 REG_FIELD(ISC_GAM_CTRL, 1, 1),
2364                 REG_FIELD(ISC_GAM_CTRL, 2, 2),
2365                 REG_FIELD(ISC_GAM_CTRL, 3, 3),
2366                 REG_FIELD(ISC_CSC_CTRL, 0, 0),
2367                 REG_FIELD(ISC_CBC_CTRL, 0, 0),
2368                 REG_FIELD(ISC_SUB422_CTRL, 0, 0),
2369                 REG_FIELD(ISC_SUB420_CTRL, 0, 0),
2370         };
2371
2372         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
2373                 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
2374                 if (IS_ERR(regs))
2375                         return PTR_ERR(regs);
2376
2377                 isc->pipeline[i] =  regs;
2378         }
2379
2380         return 0;
2381 }
2382
2383 /* regmap configuration */
2384 #define ATMEL_ISC_REG_MAX    0xbfc
2385 const struct regmap_config isc_regmap_config = {
2386         .reg_bits       = 32,
2387         .reg_stride     = 4,
2388         .val_bits       = 32,
2389         .max_register   = ATMEL_ISC_REG_MAX,
2390 };
2391