drivers/media/platform/atmel/atmel-isc-base.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Microchip Image Sensor Controller (ISC) common driver base
   4  *
   5  * Copyright (C) 2016-2019 Microchip Technology, Inc.
   6  *
   7  * Author: Songjun Wu
   8  * Author: Eugen Hristev <eugen.hristev@microchip.com>
   9  *
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/math64.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/videodev2.h>
  25 #include <linux/atmel-isc-media.h>
  26
  27 #include <media/v4l2-ctrls.h>
  28 #include <media/v4l2-device.h>
  29 #include <media/v4l2-event.h>
  30 #include <media/v4l2-image-sizes.h>
  31 #include <media/v4l2-ioctl.h>
  32 #include <media/v4l2-fwnode.h>
  33 #include <media/v4l2-subdev.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "atmel-isc-regs.h"
  37 #include "atmel-isc.h"
  38
  39 static unsigned int debug;
  40 module_param(debug, int, 0644);
  41 MODULE_PARM_DESC(debug, "debug level (0-2)");
  42
  43 static unsigned int sensor_preferred = 1;
  44 module_param(sensor_preferred, uint, 0644);
  45 MODULE_PARM_DESC(sensor_preferred,
  46                  "Sensor is preferred to output the specified format (1-on 0-off), default 1");
  47
  48 /* This is a list of the formats that the ISC can *output* */
  49 const struct isc_format controller_formats[] = {
  50         {
  51                 .fourcc         = V4L2_PIX_FMT_ARGB444,
  52         },
  53         {
  54                 .fourcc         = V4L2_PIX_FMT_ARGB555,
  55         },
  56         {
  57                 .fourcc         = V4L2_PIX_FMT_RGB565,
  58         },
  59         {
  60                 .fourcc         = V4L2_PIX_FMT_ABGR32,
  61         },
  62         {
  63                 .fourcc         = V4L2_PIX_FMT_XBGR32,
  64         },
  65         {
  66                 .fourcc         = V4L2_PIX_FMT_YUV420,
  67         },
  68         {
  69                 .fourcc         = V4L2_PIX_FMT_YUYV,
  70         },
  71         {
  72                 .fourcc         = V4L2_PIX_FMT_YUV422P,
  73         },
  74         {
  75                 .fourcc         = V4L2_PIX_FMT_GREY,
  76         },
  77         {
  78                 .fourcc         = V4L2_PIX_FMT_Y10,
  79         },
  80 };
  81
  82 /* This is a list of formats that the ISC can receive as *input* */
  83 struct isc_format formats_list[] = {
  84         {
  85                 .fourcc         = V4L2_PIX_FMT_SBGGR8,
  86                 .mbus_code      = MEDIA_BUS_FMT_SBGGR8_1X8,
  87                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  88                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
  89         },
  90         {
  91                 .fourcc         = V4L2_PIX_FMT_SGBRG8,
  92                 .mbus_code      = MEDIA_BUS_FMT_SGBRG8_1X8,
  93                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  94                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
  95         },
  96         {
  97                 .fourcc         = V4L2_PIX_FMT_SGRBG8,
  98                 .mbus_code      = MEDIA_BUS_FMT_SGRBG8_1X8,
  99                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 100                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 101         },
 102         {
 103                 .fourcc         = V4L2_PIX_FMT_SRGGB8,
 104                 .mbus_code      = MEDIA_BUS_FMT_SRGGB8_1X8,
 105                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 106                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 107         },
 108         {
 109                 .fourcc         = V4L2_PIX_FMT_SBGGR10,
 110                 .mbus_code      = MEDIA_BUS_FMT_SBGGR10_1X10,
 111                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 112                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 113         },
 114         {
 115                 .fourcc         = V4L2_PIX_FMT_SGBRG10,
 116                 .mbus_code      = MEDIA_BUS_FMT_SGBRG10_1X10,
 117                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 118                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 119         },
 120         {
 121                 .fourcc         = V4L2_PIX_FMT_SGRBG10,
 122                 .mbus_code      = MEDIA_BUS_FMT_SGRBG10_1X10,
 123                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 124                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 125         },
 126         {
 127                 .fourcc         = V4L2_PIX_FMT_SRGGB10,
 128                 .mbus_code      = MEDIA_BUS_FMT_SRGGB10_1X10,
 129                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 130                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 131         },
 132         {
 133                 .fourcc         = V4L2_PIX_FMT_SBGGR12,
 134                 .mbus_code      = MEDIA_BUS_FMT_SBGGR12_1X12,
 135                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 136                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
 137         },
 138         {
 139                 .fourcc         = V4L2_PIX_FMT_SGBRG12,
 140                 .mbus_code      = MEDIA_BUS_FMT_SGBRG12_1X12,
 141                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 142                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 143         },
 144         {
 145                 .fourcc         = V4L2_PIX_FMT_SGRBG12,
 146                 .mbus_code      = MEDIA_BUS_FMT_SGRBG12_1X12,
 147                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 148                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 149         },
 150         {
 151                 .fourcc         = V4L2_PIX_FMT_SRGGB12,
 152                 .mbus_code      = MEDIA_BUS_FMT_SRGGB12_1X12,
 153                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 154                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 155         },
 156         {
 157                 .fourcc         = V4L2_PIX_FMT_GREY,
 158                 .mbus_code      = MEDIA_BUS_FMT_Y8_1X8,
 159                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 160         },
 161         {
 162                 .fourcc         = V4L2_PIX_FMT_YUYV,
 163                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 164                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 165         },
 166         {
 167                 .fourcc         = V4L2_PIX_FMT_RGB565,
 168                 .mbus_code      = MEDIA_BUS_FMT_RGB565_2X8_LE,
 169                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 170         },
 171         {
 172                 .fourcc         = V4L2_PIX_FMT_Y10,
 173                 .mbus_code      = MEDIA_BUS_FMT_Y10_1X10,
 174                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 175         },
 176
 177 };
 178
 179 #define ISC_IS_FORMAT_RAW(mbus_code) \
 180         (((mbus_code) & 0xf000) == 0x3000)
 181
 182 #define ISC_IS_FORMAT_GREY(mbus_code) \
 183         (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
 184         (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
 185
 186 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
 187 {
 188         struct isc_ctrls *ctrls = &isc->ctrls;
 189
 190         /* In here we set the v4l2 controls w.r.t. our pipeline config */
 191         v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
 192         v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
 193         v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
 194         v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
 195
 196         v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
 197         v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
 198         v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
 199         v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
 200 }
 201
 202 static inline void isc_update_awb_ctrls(struct isc_device *isc)
 203 {
 204         struct isc_ctrls *ctrls = &isc->ctrls;
 205
 206         /* In here we set our actual hw pipeline config */
 207
 208         regmap_write(isc->regmap, ISC_WB_O_RGR,
 209                      ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
 210                      ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
 211         regmap_write(isc->regmap, ISC_WB_O_BGB,
 212                      ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
 213                      ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
 214         regmap_write(isc->regmap, ISC_WB_G_RGR,
 215                      ctrls->gain[ISC_HIS_CFG_MODE_R] |
 216                      (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
 217         regmap_write(isc->regmap, ISC_WB_G_BGB,
 218                      ctrls->gain[ISC_HIS_CFG_MODE_B] |
 219                      (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
 220 }
 221
 222 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
 223 {
 224         unsigned int c;
 225
 226         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
 227                 /* gains have a fixed point at 9 decimals */
 228                 isc->ctrls.gain[c] = 1 << 9;
 229                 /* offsets are in 2's complements */
 230                 isc->ctrls.offset[c] = 0;
 231         }
 232 }
 233
 234 static int isc_wait_clk_stable(struct clk_hw *hw)
 235 {
 236         struct isc_clk *isc_clk = to_isc_clk(hw);
 237         struct regmap *regmap = isc_clk->regmap;
 238         unsigned long timeout = jiffies + usecs_to_jiffies(1000);
 239         unsigned int status;
 240
 241         while (time_before(jiffies, timeout)) {
 242                 regmap_read(regmap, ISC_CLKSR, &status);
 243                 if (!(status & ISC_CLKSR_SIP))
 244                         return 0;
 245
 246                 usleep_range(10, 250);
 247         }
 248
 249         return -ETIMEDOUT;
 250 }
 251
 252 static int isc_clk_prepare(struct clk_hw *hw)
 253 {
 254         struct isc_clk *isc_clk = to_isc_clk(hw);
 255         int ret;
 256
 257         if (isc_clk->id == ISC_ISPCK) {
 258                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 259                 if (ret < 0)
 260                         return ret;
 261         }
 262
 263         return isc_wait_clk_stable(hw);
 264 }
 265
 266 static void isc_clk_unprepare(struct clk_hw *hw)
 267 {
 268         struct isc_clk *isc_clk = to_isc_clk(hw);
 269
 270         isc_wait_clk_stable(hw);
 271
 272         if (isc_clk->id == ISC_ISPCK)
 273                 pm_runtime_put_sync(isc_clk->dev);
 274 }
 275
 276 static int isc_clk_enable(struct clk_hw *hw)
 277 {
 278         struct isc_clk *isc_clk = to_isc_clk(hw);
 279         u32 id = isc_clk->id;
 280         struct regmap *regmap = isc_clk->regmap;
 281         unsigned long flags;
 282         unsigned int status;
 283
 284         dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n",
 285                 __func__, id, isc_clk->div, isc_clk->parent_id);
 286
 287         spin_lock_irqsave(&isc_clk->lock, flags);
 288         regmap_update_bits(regmap, ISC_CLKCFG,
 289                            ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
 290                            (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
 291                            (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
 292
 293         regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
 294         spin_unlock_irqrestore(&isc_clk->lock, flags);
 295
 296         regmap_read(regmap, ISC_CLKSR, &status);
 297         if (status & ISC_CLK(id))
 298                 return 0;
 299         else
 300                 return -EINVAL;
 301 }
 302
 303 static void isc_clk_disable(struct clk_hw *hw)
 304 {
 305         struct isc_clk *isc_clk = to_isc_clk(hw);
 306         u32 id = isc_clk->id;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&isc_clk->lock, flags);
 310         regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
 311         spin_unlock_irqrestore(&isc_clk->lock, flags);
 312 }
 313
 314 static int isc_clk_is_enabled(struct clk_hw *hw)
 315 {
 316         struct isc_clk *isc_clk = to_isc_clk(hw);
 317         u32 status;
 318         int ret;
 319
 320         if (isc_clk->id == ISC_ISPCK) {
 321                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 322                 if (ret < 0)
 323                         return 0;
 324         }
 325
 326         regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
 327
 328         if (isc_clk->id == ISC_ISPCK)
 329                 pm_runtime_put_sync(isc_clk->dev);
 330
 331         return status & ISC_CLK(isc_clk->id) ? 1 : 0;
 332 }
 333
 334 static unsigned long
 335 isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 336 {
 337         struct isc_clk *isc_clk = to_isc_clk(hw);
 338
 339         return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
 340 }
 341
 342 static int isc_clk_determine_rate(struct clk_hw *hw,
 343                                    struct clk_rate_request *req)
 344 {
 345         struct isc_clk *isc_clk = to_isc_clk(hw);
 346         long best_rate = -EINVAL;
 347         int best_diff = -1;
 348         unsigned int i, div;
 349
 350         for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
 351                 struct clk_hw *parent;
 352                 unsigned long parent_rate;
 353
 354                 parent = clk_hw_get_parent_by_index(hw, i);
 355                 if (!parent)
 356                         continue;
 357
 358                 parent_rate = clk_hw_get_rate(parent);
 359                 if (!parent_rate)
 360                         continue;
 361
 362                 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
 363                         unsigned long rate;
 364                         int diff;
 365
 366                         rate = DIV_ROUND_CLOSEST(parent_rate, div);
 367                         diff = abs(req->rate - rate);
 368
 369                         if (best_diff < 0 || best_diff > diff) {
 370                                 best_rate = rate;
 371                                 best_diff = diff;
 372                                 req->best_parent_rate = parent_rate;
 373                                 req->best_parent_hw = parent;
 374                         }
 375
 376                         if (!best_diff || rate < req->rate)
 377                                 break;
 378                 }
 379
 380                 if (!best_diff)
 381                         break;
 382         }
 383
 384         dev_dbg(isc_clk->dev,
 385                 "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
 386                 __func__, best_rate,
 387                 __clk_get_name((req->best_parent_hw)->clk),
 388                 req->best_parent_rate);
 389
 390         if (best_rate < 0)
 391                 return best_rate;
 392
 393         req->rate = best_rate;
 394
 395         return 0;
 396 }
 397
 398 static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
 399 {
 400         struct isc_clk *isc_clk = to_isc_clk(hw);
 401
 402         if (index >= clk_hw_get_num_parents(hw))
 403                 return -EINVAL;
 404
 405         isc_clk->parent_id = index;
 406
 407         return 0;
 408 }
 409
 410 static u8 isc_clk_get_parent(struct clk_hw *hw)
 411 {
 412         struct isc_clk *isc_clk = to_isc_clk(hw);
 413
 414         return isc_clk->parent_id;
 415 }
 416
 417 static int isc_clk_set_rate(struct clk_hw *hw,
 418                              unsigned long rate,
 419                              unsigned long parent_rate)
 420 {
 421         struct isc_clk *isc_clk = to_isc_clk(hw);
 422         u32 div;
 423
 424         if (!rate)
 425                 return -EINVAL;
 426
 427         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 428         if (div > (ISC_CLK_MAX_DIV + 1) || !div)
 429                 return -EINVAL;
 430
 431         isc_clk->div = div - 1;
 432
 433         return 0;
 434 }
 435
 436 static const struct clk_ops isc_clk_ops = {
 437         .prepare        = isc_clk_prepare,
 438         .unprepare      = isc_clk_unprepare,
 439         .enable         = isc_clk_enable,
 440         .disable        = isc_clk_disable,
 441         .is_enabled     = isc_clk_is_enabled,
 442         .recalc_rate    = isc_clk_recalc_rate,
 443         .determine_rate = isc_clk_determine_rate,
 444         .set_parent     = isc_clk_set_parent,
 445         .get_parent     = isc_clk_get_parent,
 446         .set_rate       = isc_clk_set_rate,
 447 };
 448
 449 static int isc_clk_register(struct isc_device *isc, unsigned int id)
 450 {
 451         struct regmap *regmap = isc->regmap;
 452         struct device_node *np = isc->dev->of_node;
 453         struct isc_clk *isc_clk;
 454         struct clk_init_data init;
 455         const char *clk_name = np->name;
 456         const char *parent_names[3];
 457         int num_parents;
 458
 459         num_parents = of_clk_get_parent_count(np);
 460         if (num_parents < 1 || num_parents > 3)
 461                 return -EINVAL;
 462
 463         if (num_parents > 2 && id == ISC_ISPCK)
 464                 num_parents = 2;
 465
 466         of_clk_parent_fill(np, parent_names, num_parents);
 467
 468         if (id == ISC_MCK)
 469                 of_property_read_string(np, "clock-output-names", &clk_name);
 470         else
 471                 clk_name = "isc-ispck";
 472
 473         init.parent_names       = parent_names;
 474         init.num_parents        = num_parents;
 475         init.name               = clk_name;
 476         init.ops                = &isc_clk_ops;
 477         init.flags              = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
 478
 479         isc_clk = &isc->isc_clks[id];
 480         isc_clk->hw.init        = &init;
 481         isc_clk->regmap         = regmap;
 482         isc_clk->id             = id;
 483         isc_clk->dev            = isc->dev;
 484         spin_lock_init(&isc_clk->lock);
 485
 486         isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
 487         if (IS_ERR(isc_clk->clk)) {
 488                 dev_err(isc->dev, "%s: clock register fail\n", clk_name);
 489                 return PTR_ERR(isc_clk->clk);
 490         } else if (id == ISC_MCK)
 491                 of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
 492
 493         return 0;
 494 }
 495
 496 int isc_clk_init(struct isc_device *isc)
 497 {
 498         unsigned int i;
 499         int ret;
 500
 501         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
 502                 isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
 503
 504         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 505                 ret = isc_clk_register(isc, i);
 506                 if (ret)
 507                         return ret;
 508         }
 509
 510         return 0;
 511 }
 512
 513 void isc_clk_cleanup(struct isc_device *isc)
 514 {
 515         unsigned int i;
 516
 517         of_clk_del_provider(isc->dev->of_node);
 518
 519         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 520                 struct isc_clk *isc_clk = &isc->isc_clks[i];
 521
 522                 if (!IS_ERR(isc_clk->clk))
 523                         clk_unregister(isc_clk->clk);
 524         }
 525 }
 526
 527 static int isc_queue_setup(struct vb2_queue *vq,
 528                             unsigned int *nbuffers, unsigned int *nplanes,
 529                             unsigned int sizes[], struct device *alloc_devs[])
 530 {
 531         struct isc_device *isc = vb2_get_drv_priv(vq);
 532         unsigned int size = isc->fmt.fmt.pix.sizeimage;
 533
 534         if (*nplanes)
 535                 return sizes[0] < size ? -EINVAL : 0;
 536
 537         *nplanes = 1;
 538         sizes[0] = size;
 539
 540         return 0;
 541 }
 542
 543 static int isc_buffer_prepare(struct vb2_buffer *vb)
 544 {
 545         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 546         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 547         unsigned long size = isc->fmt.fmt.pix.sizeimage;
 548
 549         if (vb2_plane_size(vb, 0) < size) {
 550                 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
 551                          vb2_plane_size(vb, 0), size);
 552                 return -EINVAL;
 553         }
 554
 555         vb2_set_plane_payload(vb, 0, size);
 556
 557         vbuf->field = isc->fmt.fmt.pix.field;
 558
 559         return 0;
 560 }
 561
 562 static void isc_start_dma(struct isc_device *isc)
 563 {
 564         struct regmap *regmap = isc->regmap;
 565         u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
 566         u32 dctrl_dview;
 567         dma_addr_t addr0;
 568         u32 h, w;
 569
 570         h = isc->fmt.fmt.pix.height;
 571         w = isc->fmt.fmt.pix.width;
 572
 573         /*
 574          * In case the sensor is not RAW, it will output a pixel (12-16 bits)
 575          * with two samples on the ISC Data bus (which is 8-12)
 576          * ISC will count each sample, so, we need to multiply these values
 577          * by two, to get the real number of samples for the required pixels.
 578          */
 579         if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
 580                 h <<= 1;
 581                 w <<= 1;
 582         }
 583
 584         /*
 585          * We limit the column/row count that the ISC will output according
 586          * to the configured resolution that we want.
 587          * This will avoid the situation where the sensor is misconfigured,
 588          * sending more data, and the ISC will just take it and DMA to memory,
 589          * causing corruption.
 590          */
 591         regmap_write(regmap, ISC_PFE_CFG1,
 592                      (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
 593                      (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
 594
 595         regmap_write(regmap, ISC_PFE_CFG2,
 596                      (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
 597                      (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
 598
 599         regmap_update_bits(regmap, ISC_PFE_CFG0,
 600                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
 601                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 602
 603         addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
 604         regmap_write(regmap, ISC_DAD0, addr0);
 605
 606         switch (isc->config.fourcc) {
 607         case V4L2_PIX_FMT_YUV420:
 608                 regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);
 609                 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);
 610                 break;
 611         case V4L2_PIX_FMT_YUV422P:
 612                 regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);
 613                 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);
 614                 break;
 615         default:
 616                 break;
 617         }
 618
 619         dctrl_dview = isc->config.dctrl_dview;
 620
 621         regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
 622         spin_lock(&isc->awb_lock);
 623         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
 624         spin_unlock(&isc->awb_lock);
 625 }
 626
 627 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
 628 {
 629         struct regmap *regmap = isc->regmap;
 630         struct isc_ctrls *ctrls = &isc->ctrls;
 631         u32 val, bay_cfg;
 632         const u32 *gamma;
 633         unsigned int i;
 634
 635         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
 636         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
 637                 val = pipeline & BIT(i) ? 1 : 0;
 638                 regmap_field_write(isc->pipeline[i], val);
 639         }
 640
 641         if (!pipeline)
 642                 return;
 643
 644         bay_cfg = isc->config.sd_format->cfa_baycfg;
 645
 646         regmap_write(regmap, ISC_WB_CFG, bay_cfg);
 647         isc_update_awb_ctrls(isc);
 648         isc_update_v4l2_ctrls(isc);
 649
 650         regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
 651
 652         gamma = &isc->gamma_table[ctrls->gamma_index][0];
 653         regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
 654         regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 655         regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 656
 657         isc->config_csc(isc);
 658         isc->config_cbc(isc);
 659 }
 660
 661 static int isc_update_profile(struct isc_device *isc)
 662 {
 663         struct regmap *regmap = isc->regmap;
 664         u32 sr;
 665         int counter = 100;
 666
 667         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
 668
 669         regmap_read(regmap, ISC_CTRLSR, &sr);
 670         while ((sr & ISC_CTRL_UPPRO) && counter--) {
 671                 usleep_range(1000, 2000);
 672                 regmap_read(regmap, ISC_CTRLSR, &sr);
 673         }
 674
 675         if (counter < 0) {
 676                 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
 677                 return -ETIMEDOUT;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static void isc_set_histogram(struct isc_device *isc, bool enable)
 684 {
 685         struct regmap *regmap = isc->regmap;
 686         struct isc_ctrls *ctrls = &isc->ctrls;
 687
 688         if (enable) {
 689                 regmap_write(regmap, ISC_HIS_CFG,
 690                              ISC_HIS_CFG_MODE_GR |
 691                              (isc->config.sd_format->cfa_baycfg
 692                                         << ISC_HIS_CFG_BAYSEL_SHIFT) |
 693                                         ISC_HIS_CFG_RAR);
 694                 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
 695                 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
 696                 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
 697                 isc_update_profile(isc);
 698                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
 699
 700                 ctrls->hist_stat = HIST_ENABLED;
 701         } else {
 702                 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
 703                 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);
 704
 705                 ctrls->hist_stat = HIST_DISABLED;
 706         }
 707 }
 708
 709 static int isc_configure(struct isc_device *isc)
 710 {
 711         struct regmap *regmap = isc->regmap;
 712         u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
 713         struct isc_subdev_entity *subdev = isc->current_subdev;
 714
 715         pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
 716         rlp_mode = isc->config.rlp_cfg_mode;
 717         pipeline = isc->config.bits_pipeline;
 718
 719         dcfg = isc->config.dcfg_imode | isc->dcfg;
 720
 721         pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
 722         mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 723                ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
 724                ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
 725                    ISC_PFE_CFG0_CCIR656;
 726
 727         regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 728
 729         regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
 730                            rlp_mode);
 731
 732         regmap_write(regmap, ISC_DCFG, dcfg);
 733
 734         /* Set the pipeline */
 735         isc_set_pipeline(isc, pipeline);
 736
 737         /*
 738          * The current implemented histogram is available for RAW R, B, GB, GR
 739          * channels. We need to check if sensor is outputting RAW BAYER
 740          */
 741         if (isc->ctrls.awb &&
 742             ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 743                 isc_set_histogram(isc, true);
 744         else
 745                 isc_set_histogram(isc, false);
 746
 747         /* Update profile */
 748         return isc_update_profile(isc);
 749 }
 750
 751 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
 752 {
 753         struct isc_device *isc = vb2_get_drv_priv(vq);
 754         struct regmap *regmap = isc->regmap;
 755         struct isc_buffer *buf;
 756         unsigned long flags;
 757         int ret;
 758
 759         /* Enable stream on the sub device */
 760         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
 761         if (ret && ret != -ENOIOCTLCMD) {
 762                 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
 763                          ret);
 764                 goto err_start_stream;
 765         }
 766
 767         ret = pm_runtime_resume_and_get(isc->dev);
 768         if (ret < 0) {
 769                 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
 770                          ret);
 771                 goto err_pm_get;
 772         }
 773
 774         ret = isc_configure(isc);
 775         if (unlikely(ret))
 776                 goto err_configure;
 777
 778         /* Enable DMA interrupt */
 779         regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
 780
 781         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 782
 783         isc->sequence = 0;
 784         isc->stop = false;
 785         reinit_completion(&isc->comp);
 786
 787         isc->cur_frm = list_first_entry(&isc->dma_queue,
 788                                         struct isc_buffer, list);
 789         list_del(&isc->cur_frm->list);
 790
 791         isc_start_dma(isc);
 792
 793         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 794
 795         /* if we streaming from RAW, we can do one-shot white balance adj */
 796         if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 797                 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
 798
 799         return 0;
 800
 801 err_configure:
 802         pm_runtime_put_sync(isc->dev);
 803 err_pm_get:
 804         v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 805
 806 err_start_stream:
 807         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 808         list_for_each_entry(buf, &isc->dma_queue, list)
 809                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
 810         INIT_LIST_HEAD(&isc->dma_queue);
 811         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 812
 813         return ret;
 814 }
 815
 816 static void isc_stop_streaming(struct vb2_queue *vq)
 817 {
 818         struct isc_device *isc = vb2_get_drv_priv(vq);
 819         unsigned long flags;
 820         struct isc_buffer *buf;
 821         int ret;
 822
 823         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
 824
 825         isc->stop = true;
 826
 827         /* Wait until the end of the current frame */
 828         if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
 829                 v4l2_err(&isc->v4l2_dev,
 830                          "Timeout waiting for end of the capture\n");
 831
 832         /* Disable DMA interrupt */
 833         regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
 834
 835         pm_runtime_put_sync(isc->dev);
 836
 837         /* Disable stream on the sub device */
 838         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 839         if (ret && ret != -ENOIOCTLCMD)
 840                 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
 841
 842         /* Release all active buffers */
 843         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 844         if (unlikely(isc->cur_frm)) {
 845                 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
 846                                 VB2_BUF_STATE_ERROR);
 847                 isc->cur_frm = NULL;
 848         }
 849         list_for_each_entry(buf, &isc->dma_queue, list)
 850                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 851         INIT_LIST_HEAD(&isc->dma_queue);
 852         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 853 }
 854
 855 static void isc_buffer_queue(struct vb2_buffer *vb)
 856 {
 857         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 858         struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
 859         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 860         unsigned long flags;
 861
 862         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 863         if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
 864                 vb2_is_streaming(vb->vb2_queue)) {
 865                 isc->cur_frm = buf;
 866                 isc_start_dma(isc);
 867         } else
 868                 list_add_tail(&buf->list, &isc->dma_queue);
 869         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 870 }
 871
 872 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
 873                                                  unsigned int fourcc)
 874 {
 875         unsigned int num_formats = isc->num_user_formats;
 876         struct isc_format *fmt;
 877         unsigned int i;
 878
 879         for (i = 0; i < num_formats; i++) {
 880                 fmt = isc->user_formats[i];
 881                 if (fmt->fourcc == fourcc)
 882                         return fmt;
 883         }
 884
 885         return NULL;
 886 }
 887
 888 static const struct vb2_ops isc_vb2_ops = {
 889         .queue_setup            = isc_queue_setup,
 890         .wait_prepare           = vb2_ops_wait_prepare,
 891         .wait_finish            = vb2_ops_wait_finish,
 892         .buf_prepare            = isc_buffer_prepare,
 893         .start_streaming        = isc_start_streaming,
 894         .stop_streaming         = isc_stop_streaming,
 895         .buf_queue              = isc_buffer_queue,
 896 };
 897
 898 static int isc_querycap(struct file *file, void *priv,
 899                          struct v4l2_capability *cap)
 900 {
 901         struct isc_device *isc = video_drvdata(file);
 902
 903         strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
 904         strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
 905         snprintf(cap->bus_info, sizeof(cap->bus_info),
 906                  "platform:%s", isc->v4l2_dev.name);
 907
 908         return 0;
 909 }
 910
 911 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
 912                                  struct v4l2_fmtdesc *f)
 913 {
 914         u32 index = f->index;
 915         u32 i, supported_index;
 916
 917         if (index < ARRAY_SIZE(controller_formats)) {
 918                 f->pixelformat = controller_formats[index].fourcc;
 919                 return 0;
 920         }
 921
 922         index -= ARRAY_SIZE(controller_formats);
 923
 924         supported_index = 0;
 925
 926         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
 927                 if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
 928                     !formats_list[i].sd_support)
 929                         continue;
 930                 if (supported_index == index) {
 931                         f->pixelformat = formats_list[i].fourcc;
 932                         return 0;
 933                 }
 934                 supported_index++;
 935         }
 936
 937         return -EINVAL;
 938 }
 939
 940 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
 941                               struct v4l2_format *fmt)
 942 {
 943         struct isc_device *isc = video_drvdata(file);
 944
 945         *fmt = isc->fmt;
 946
 947         return 0;
 948 }
 949
 950 /*
 951  * Checks the current configured format, if ISC can output it,
 952  * considering which type of format the ISC receives from the sensor
 953  */
 954 static int isc_try_validate_formats(struct isc_device *isc)
 955 {
 956         int ret;
 957         bool bayer = false, yuv = false, rgb = false, grey = false;
 958
 959         /* all formats supported by the RLP module are OK */
 960         switch (isc->try_config.fourcc) {
 961         case V4L2_PIX_FMT_SBGGR8:
 962         case V4L2_PIX_FMT_SGBRG8:
 963         case V4L2_PIX_FMT_SGRBG8:
 964         case V4L2_PIX_FMT_SRGGB8:
 965         case V4L2_PIX_FMT_SBGGR10:
 966         case V4L2_PIX_FMT_SGBRG10:
 967         case V4L2_PIX_FMT_SGRBG10:
 968         case V4L2_PIX_FMT_SRGGB10:
 969         case V4L2_PIX_FMT_SBGGR12:
 970         case V4L2_PIX_FMT_SGBRG12:
 971         case V4L2_PIX_FMT_SGRBG12:
 972         case V4L2_PIX_FMT_SRGGB12:
 973                 ret = 0;
 974                 bayer = true;
 975                 break;
 976
 977         case V4L2_PIX_FMT_YUV420:
 978         case V4L2_PIX_FMT_YUV422P:
 979         case V4L2_PIX_FMT_YUYV:
 980                 ret = 0;
 981                 yuv = true;
 982                 break;
 983
 984         case V4L2_PIX_FMT_RGB565:
 985         case V4L2_PIX_FMT_ABGR32:
 986         case V4L2_PIX_FMT_XBGR32:
 987         case V4L2_PIX_FMT_ARGB444:
 988         case V4L2_PIX_FMT_ARGB555:
 989                 ret = 0;
 990                 rgb = true;
 991                 break;
 992         case V4L2_PIX_FMT_GREY:
 993         case V4L2_PIX_FMT_Y10:
 994                 ret = 0;
 995                 grey = true;
 996                 break;
 997         default:
 998         /* any other different formats are not supported */
 999                 ret = -EINVAL;
1000         }
1001         v4l2_dbg(1, debug, &isc->v4l2_dev,
1002                  "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
1003                  rgb, yuv, grey, bayer);
1004
1005         /* we cannot output RAW if we do not receive RAW */
1006         if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
1007                 return -EINVAL;
1008
1009         /* we cannot output GREY if we do not receive RAW/GREY */
1010         if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
1011             !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
1012                 return -EINVAL;
1013
1014         return ret;
1015 }
1016
1017 /*
1018  * Configures the RLP and DMA modules, depending on the output format
1019  * configured for the ISC.
1020  * If direct_dump == true, just dump raw data 8/16 bits depending on format.
1021  */
1022 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
1023 {
1024         switch (isc->try_config.fourcc) {
1025         case V4L2_PIX_FMT_SBGGR8:
1026         case V4L2_PIX_FMT_SGBRG8:
1027         case V4L2_PIX_FMT_SGRBG8:
1028         case V4L2_PIX_FMT_SRGGB8:
1029                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1030                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1031                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1032                 isc->try_config.bpp = 8;
1033                 break;
1034         case V4L2_PIX_FMT_SBGGR10:
1035         case V4L2_PIX_FMT_SGBRG10:
1036         case V4L2_PIX_FMT_SGRBG10:
1037         case V4L2_PIX_FMT_SRGGB10:
1038                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
1039                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1040                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1041                 isc->try_config.bpp = 16;
1042                 break;
1043         case V4L2_PIX_FMT_SBGGR12:
1044         case V4L2_PIX_FMT_SGBRG12:
1045         case V4L2_PIX_FMT_SGRBG12:
1046         case V4L2_PIX_FMT_SRGGB12:
1047                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
1048                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1049                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1050                 isc->try_config.bpp = 16;
1051                 break;
1052         case V4L2_PIX_FMT_RGB565:
1053                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
1054                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1055                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1056                 isc->try_config.bpp = 16;
1057                 break;
1058         case V4L2_PIX_FMT_ARGB444:
1059                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
1060                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1061                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1062                 isc->try_config.bpp = 16;
1063                 break;
1064         case V4L2_PIX_FMT_ARGB555:
1065                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
1066                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1067                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1068                 isc->try_config.bpp = 16;
1069                 break;
1070         case V4L2_PIX_FMT_ABGR32:
1071         case V4L2_PIX_FMT_XBGR32:
1072                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
1073                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1074                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1075                 isc->try_config.bpp = 32;
1076                 break;
1077         case V4L2_PIX_FMT_YUV420:
1078                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1079                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
1080                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1081                 isc->try_config.bpp = 12;
1082                 break;
1083         case V4L2_PIX_FMT_YUV422P:
1084                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1085                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
1086                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1087                 isc->try_config.bpp = 16;
1088                 break;
1089         case V4L2_PIX_FMT_YUYV:
1090                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1091                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1092                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1093                 isc->try_config.bpp = 16;
1094                 break;
1095         case V4L2_PIX_FMT_GREY:
1096                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
1097                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1098                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1099                 isc->try_config.bpp = 8;
1100                 break;
1101         case V4L2_PIX_FMT_Y10:
1102                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
1103                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1104                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1105                 isc->try_config.bpp = 16;
1106                 break;
1107         default:
1108                 return -EINVAL;
1109         }
1110
1111         if (direct_dump) {
1112                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1113                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1114                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1115                 return 0;
1116         }
1117
1118         return 0;
1119 }
1120
1121 /*
1122  * Configuring pipeline modules, depending on which format the ISC outputs
1123  * and considering which format it has as input from the sensor.
1124  */
1125 static int isc_try_configure_pipeline(struct isc_device *isc)
1126 {
1127         switch (isc->try_config.fourcc) {
1128         case V4L2_PIX_FMT_RGB565:
1129         case V4L2_PIX_FMT_ARGB555:
1130         case V4L2_PIX_FMT_ARGB444:
1131         case V4L2_PIX_FMT_ABGR32:
1132         case V4L2_PIX_FMT_XBGR32:
1133                 /* if sensor format is RAW, we convert inside ISC */
1134                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1135                         isc->try_config.bits_pipeline = CFA_ENABLE |
1136                                 WB_ENABLE | GAM_ENABLES;
1137                 } else {
1138                         isc->try_config.bits_pipeline = 0x0;
1139                 }
1140                 break;
1141         case V4L2_PIX_FMT_YUV420:
1142                 /* if sensor format is RAW, we convert inside ISC */
1143                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1144                         isc->try_config.bits_pipeline = CFA_ENABLE |
1145                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1146                                 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
1147                 } else {
1148                         isc->try_config.bits_pipeline = 0x0;
1149                 }
1150                 break;
1151         case V4L2_PIX_FMT_YUV422P:
1152                 /* if sensor format is RAW, we convert inside ISC */
1153                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1154                         isc->try_config.bits_pipeline = CFA_ENABLE |
1155                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1156                                 SUB422_ENABLE | CBC_ENABLE;
1157                 } else {
1158                         isc->try_config.bits_pipeline = 0x0;
1159                 }
1160                 break;
1161         case V4L2_PIX_FMT_YUYV:
1162                 /* if sensor format is RAW, we convert inside ISC */
1163                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1164                         isc->try_config.bits_pipeline = CFA_ENABLE |
1165                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1166                                 SUB422_ENABLE | CBC_ENABLE;
1167                 } else {
1168                         isc->try_config.bits_pipeline = 0x0;
1169                 }
1170                 break;
1171         case V4L2_PIX_FMT_GREY:
1172                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1173                 /* if sensor format is RAW, we convert inside ISC */
1174                         isc->try_config.bits_pipeline = CFA_ENABLE |
1175                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1176                                 CBC_ENABLE;
1177                 } else {
1178                         isc->try_config.bits_pipeline = 0x0;
1179                 }
1180                 break;
1181         default:
1182                 isc->try_config.bits_pipeline = 0x0;
1183         }
1184         return 0;
1185 }
1186
1187 static void isc_try_fse(struct isc_device *isc,
1188                         struct v4l2_subdev_pad_config *pad_cfg)
1189 {
1190         int ret;
1191         struct v4l2_subdev_frame_size_enum fse = {};
1192
1193         /*
1194          * If we do not know yet which format the subdev is using, we cannot
1195          * do anything.
1196          */
1197         if (!isc->try_config.sd_format)
1198                 return;
1199
1200         fse.code = isc->try_config.sd_format->mbus_code;
1201         fse.which = V4L2_SUBDEV_FORMAT_TRY;
1202
1203         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1204                                pad_cfg, &fse);
1205         /*
1206          * Attempt to obtain format size from subdev. If not available,
1207          * just use the maximum ISC can receive.
1208          */
1209         if (ret) {
1210                 pad_cfg->try_crop.width = isc->max_width;
1211                 pad_cfg->try_crop.height = isc->max_height;
1212         } else {
1213                 pad_cfg->try_crop.width = fse.max_width;
1214                 pad_cfg->try_crop.height = fse.max_height;
1215         }
1216 }
1217
1218 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
1219                         u32 *code)
1220 {
1221         int i;
1222         struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
1223         struct v4l2_pix_format *pixfmt = &f->fmt.pix;
1224         struct v4l2_subdev_pad_config pad_cfg = {};
1225         struct v4l2_subdev_format format = {
1226                 .which = V4L2_SUBDEV_FORMAT_TRY,
1227         };
1228         u32 mbus_code;
1229         int ret;
1230         bool rlp_dma_direct_dump = false;
1231
1232         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1233                 return -EINVAL;
1234
1235         /* Step 1: find a RAW format that is supported */
1236         for (i = 0; i < isc->num_user_formats; i++) {
1237                 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
1238                         sd_fmt = isc->user_formats[i];
1239                         break;
1240                 }
1241         }
1242         /* Step 2: We can continue with this RAW format, or we can look
1243          * for better: maybe sensor supports directly what we need.
1244          */
1245         direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
1246
1247         /* Step 3: We have both. We decide given the module parameter which
1248          * one to use.
1249          */
1250         if (direct_fmt && sd_fmt && sensor_preferred)
1251                 sd_fmt = direct_fmt;
1252
1253         /* Step 4: we do not have RAW but we have a direct format. Use it. */
1254         if (direct_fmt && !sd_fmt)
1255                 sd_fmt = direct_fmt;
1256
1257         /* Step 5: if we are using a direct format, we need to package
1258          * everything as 8 bit data and just dump it
1259          */
1260         if (sd_fmt == direct_fmt)
1261                 rlp_dma_direct_dump = true;
1262
1263         /* Step 6: We have no format. This can happen if the userspace
1264          * requests some weird/invalid format.
1265          * In this case, default to whatever we have
1266          */
1267         if (!sd_fmt && !direct_fmt) {
1268                 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
1269                 v4l2_dbg(1, debug, &isc->v4l2_dev,
1270                          "Sensor not supporting %.4s, using %.4s\n",
1271                          (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
1272         }
1273
1274         if (!sd_fmt) {
1275                 ret = -EINVAL;
1276                 goto isc_try_fmt_err;
1277         }
1278
1279         /* Step 7: Print out what we decided for debugging */
1280         v4l2_dbg(1, debug, &isc->v4l2_dev,
1281                  "Preferring to have sensor using format %.4s\n",
1282                  (char *)&sd_fmt->fourcc);
1283
1284         /* Step 8: at this moment we decided which format the subdev will use */
1285         isc->try_config.sd_format = sd_fmt;
1286
1287         /* Limit to Atmel ISC hardware capabilities */
1288         if (pixfmt->width > isc->max_width)
1289                 pixfmt->width = isc->max_width;
1290         if (pixfmt->height > isc->max_height)
1291                 pixfmt->height = isc->max_height;
1292
1293         /*
1294          * The mbus format is the one the subdev outputs.
1295          * The pixels will be transferred in this format Sensor -> ISC
1296          */
1297         mbus_code = sd_fmt->mbus_code;
1298
1299         /*
1300          * Validate formats. If the required format is not OK, default to raw.
1301          */
1302
1303         isc->try_config.fourcc = pixfmt->pixelformat;
1304
1305         if (isc_try_validate_formats(isc)) {
1306                 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
1307                 /* Re-try to validate the new format */
1308                 ret = isc_try_validate_formats(isc);
1309                 if (ret)
1310                         goto isc_try_fmt_err;
1311         }
1312
1313         ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
1314         if (ret)
1315                 goto isc_try_fmt_err;
1316
1317         ret = isc_try_configure_pipeline(isc);
1318         if (ret)
1319                 goto isc_try_fmt_err;
1320
1321         /* Obtain frame sizes if possible to have crop requirements ready */
1322         isc_try_fse(isc, &pad_cfg);
1323
1324         v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
1325         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
1326                                &pad_cfg, &format);
1327         if (ret < 0)
1328                 goto isc_try_fmt_subdev_err;
1329
1330         v4l2_fill_pix_format(pixfmt, &format.format);
1331
1332         /* Limit to Atmel ISC hardware capabilities */
1333         if (pixfmt->width > isc->max_width)
1334                 pixfmt->width = isc->max_width;
1335         if (pixfmt->height > isc->max_height)
1336                 pixfmt->height = isc->max_height;
1337
1338         pixfmt->field = V4L2_FIELD_NONE;
1339         pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
1340         pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
1341
1342         if (code)
1343                 *code = mbus_code;
1344
1345         return 0;
1346
1347 isc_try_fmt_err:
1348         v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
1349 isc_try_fmt_subdev_err:
1350         memset(&isc->try_config, 0, sizeof(isc->try_config));
1351
1352         return ret;
1353 }
1354
1355 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
1356 {
1357         struct v4l2_subdev_format format = {
1358                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1359         };
1360         u32 mbus_code = 0;
1361         int ret;
1362
1363         ret = isc_try_fmt(isc, f, &mbus_code);
1364         if (ret)
1365                 return ret;
1366
1367         v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1368         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1369                                set_fmt, NULL, &format);
1370         if (ret < 0)
1371                 return ret;
1372
1373         /* Limit to Atmel ISC hardware capabilities */
1374         if (f->fmt.pix.width > isc->max_width)
1375                 f->fmt.pix.width = isc->max_width;
1376         if (f->fmt.pix.height > isc->max_height)
1377                 f->fmt.pix.height = isc->max_height;
1378
1379         isc->fmt = *f;
1380
1381         if (isc->try_config.sd_format && isc->config.sd_format &&
1382             isc->try_config.sd_format != isc->config.sd_format) {
1383                 isc->ctrls.hist_stat = HIST_INIT;
1384                 isc_reset_awb_ctrls(isc);
1385                 isc_update_v4l2_ctrls(isc);
1386         }
1387         /* make the try configuration active */
1388         isc->config = isc->try_config;
1389
1390         v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1391
1392         return 0;
1393 }
1394
1395 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1396                               struct v4l2_format *f)
1397 {
1398         struct isc_device *isc = video_drvdata(file);
1399
1400         if (vb2_is_streaming(&isc->vb2_vidq))
1401                 return -EBUSY;
1402
1403         return isc_set_fmt(isc, f);
1404 }
1405
1406 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1407                                 struct v4l2_format *f)
1408 {
1409         struct isc_device *isc = video_drvdata(file);
1410
1411         return isc_try_fmt(isc, f, NULL);
1412 }
1413
1414 static int isc_enum_input(struct file *file, void *priv,
1415                            struct v4l2_input *inp)
1416 {
1417         if (inp->index != 0)
1418                 return -EINVAL;
1419
1420         inp->type = V4L2_INPUT_TYPE_CAMERA;
1421         inp->std = 0;
1422         strscpy(inp->name, "Camera", sizeof(inp->name));
1423
1424         return 0;
1425 }
1426
1427 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1428 {
1429         *i = 0;
1430
1431         return 0;
1432 }
1433
1434 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1435 {
1436         if (i > 0)
1437                 return -EINVAL;
1438
1439         return 0;
1440 }
1441
1442 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1443 {
1444         struct isc_device *isc = video_drvdata(file);
1445
1446         return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1447 }
1448
1449 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1450 {
1451         struct isc_device *isc = video_drvdata(file);
1452
1453         return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1454 }
1455
1456 static int isc_enum_framesizes(struct file *file, void *fh,
1457                                struct v4l2_frmsizeenum *fsize)
1458 {
1459         struct isc_device *isc = video_drvdata(file);
1460         struct v4l2_subdev_frame_size_enum fse = {
1461                 .code = isc->config.sd_format->mbus_code,
1462                 .index = fsize->index,
1463                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1464         };
1465         int ret = -EINVAL;
1466         int i;
1467
1468         for (i = 0; i < isc->num_user_formats; i++)
1469                 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1470                         ret = 0;
1471
1472         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1473                 if (controller_formats[i].fourcc == fsize->pixel_format)
1474                         ret = 0;
1475
1476         if (ret)
1477                 return ret;
1478
1479         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1480                                NULL, &fse);
1481         if (ret)
1482                 return ret;
1483
1484         fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1485         fsize->discrete.width = fse.max_width;
1486         fsize->discrete.height = fse.max_height;
1487
1488         return 0;
1489 }
1490
1491 static int isc_enum_frameintervals(struct file *file, void *fh,
1492                                     struct v4l2_frmivalenum *fival)
1493 {
1494         struct isc_device *isc = video_drvdata(file);
1495         struct v4l2_subdev_frame_interval_enum fie = {
1496                 .code = isc->config.sd_format->mbus_code,
1497                 .index = fival->index,
1498                 .width = fival->width,
1499                 .height = fival->height,
1500                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1501         };
1502         int ret = -EINVAL;
1503         unsigned int i;
1504
1505         for (i = 0; i < isc->num_user_formats; i++)
1506                 if (isc->user_formats[i]->fourcc == fival->pixel_format)
1507                         ret = 0;
1508
1509         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1510                 if (controller_formats[i].fourcc == fival->pixel_format)
1511                         ret = 0;
1512
1513         if (ret)
1514                 return ret;
1515
1516         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1517                                enum_frame_interval, NULL, &fie);
1518         if (ret)
1519                 return ret;
1520
1521         fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1522         fival->discrete = fie.interval;
1523
1524         return 0;
1525 }
1526
1527 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1528         .vidioc_querycap                = isc_querycap,
1529         .vidioc_enum_fmt_vid_cap        = isc_enum_fmt_vid_cap,
1530         .vidioc_g_fmt_vid_cap           = isc_g_fmt_vid_cap,
1531         .vidioc_s_fmt_vid_cap           = isc_s_fmt_vid_cap,
1532         .vidioc_try_fmt_vid_cap         = isc_try_fmt_vid_cap,
1533
1534         .vidioc_enum_input              = isc_enum_input,
1535         .vidioc_g_input                 = isc_g_input,
1536         .vidioc_s_input                 = isc_s_input,
1537
1538         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1539         .vidioc_querybuf                = vb2_ioctl_querybuf,
1540         .vidioc_qbuf                    = vb2_ioctl_qbuf,
1541         .vidioc_expbuf                  = vb2_ioctl_expbuf,
1542         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1543         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1544         .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1545         .vidioc_streamon                = vb2_ioctl_streamon,
1546         .vidioc_streamoff               = vb2_ioctl_streamoff,
1547
1548         .vidioc_g_parm                  = isc_g_parm,
1549         .vidioc_s_parm                  = isc_s_parm,
1550         .vidioc_enum_framesizes         = isc_enum_framesizes,
1551         .vidioc_enum_frameintervals     = isc_enum_frameintervals,
1552
1553         .vidioc_log_status              = v4l2_ctrl_log_status,
1554         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
1555         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1556 };
1557
1558 static int isc_open(struct file *file)
1559 {
1560         struct isc_device *isc = video_drvdata(file);
1561         struct v4l2_subdev *sd = isc->current_subdev->sd;
1562         int ret;
1563
1564         if (mutex_lock_interruptible(&isc->lock))
1565                 return -ERESTARTSYS;
1566
1567         ret = v4l2_fh_open(file);
1568         if (ret < 0)
1569                 goto unlock;
1570
1571         if (!v4l2_fh_is_singular_file(file))
1572                 goto unlock;
1573
1574         ret = v4l2_subdev_call(sd, core, s_power, 1);
1575         if (ret < 0 && ret != -ENOIOCTLCMD) {
1576                 v4l2_fh_release(file);
1577                 goto unlock;
1578         }
1579
1580         ret = isc_set_fmt(isc, &isc->fmt);
1581         if (ret) {
1582                 v4l2_subdev_call(sd, core, s_power, 0);
1583                 v4l2_fh_release(file);
1584         }
1585
1586 unlock:
1587         mutex_unlock(&isc->lock);
1588         return ret;
1589 }
1590
1591 static int isc_release(struct file *file)
1592 {
1593         struct isc_device *isc = video_drvdata(file);
1594         struct v4l2_subdev *sd = isc->current_subdev->sd;
1595         bool fh_singular;
1596         int ret;
1597
1598         mutex_lock(&isc->lock);
1599
1600         fh_singular = v4l2_fh_is_singular_file(file);
1601
1602         ret = _vb2_fop_release(file, NULL);
1603
1604         if (fh_singular)
1605                 v4l2_subdev_call(sd, core, s_power, 0);
1606
1607         mutex_unlock(&isc->lock);
1608
1609         return ret;
1610 }
1611
1612 static const struct v4l2_file_operations isc_fops = {
1613         .owner          = THIS_MODULE,
1614         .open           = isc_open,
1615         .release        = isc_release,
1616         .unlocked_ioctl = video_ioctl2,
1617         .read           = vb2_fop_read,
1618         .mmap           = vb2_fop_mmap,
1619         .poll           = vb2_fop_poll,
1620 };
1621
1622 irqreturn_t isc_interrupt(int irq, void *dev_id)
1623 {
1624         struct isc_device *isc = (struct isc_device *)dev_id;
1625         struct regmap *regmap = isc->regmap;
1626         u32 isc_intsr, isc_intmask, pending;
1627         irqreturn_t ret = IRQ_NONE;
1628
1629         regmap_read(regmap, ISC_INTSR, &isc_intsr);
1630         regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1631
1632         pending = isc_intsr & isc_intmask;
1633
1634         if (likely(pending & ISC_INT_DDONE)) {
1635                 spin_lock(&isc->dma_queue_lock);
1636                 if (isc->cur_frm) {
1637                         struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1638                         struct vb2_buffer *vb = &vbuf->vb2_buf;
1639
1640                         vb->timestamp = ktime_get_ns();
1641                         vbuf->sequence = isc->sequence++;
1642                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1643                         isc->cur_frm = NULL;
1644                 }
1645
1646                 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1647                         isc->cur_frm = list_first_entry(&isc->dma_queue,
1648                                                      struct isc_buffer, list);
1649                         list_del(&isc->cur_frm->list);
1650
1651                         isc_start_dma(isc);
1652                 }
1653
1654                 if (isc->stop)
1655                         complete(&isc->comp);
1656
1657                 ret = IRQ_HANDLED;
1658                 spin_unlock(&isc->dma_queue_lock);
1659         }
1660
1661         if (pending & ISC_INT_HISDONE) {
1662                 schedule_work(&isc->awb_work);
1663                 ret = IRQ_HANDLED;
1664         }
1665
1666         return ret;
1667 }
1668
1669 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1670 {
1671         struct regmap *regmap = isc->regmap;
1672         struct isc_ctrls *ctrls = &isc->ctrls;
1673         u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1674         u32 *hist_entry = &ctrls->hist_entry[0];
1675         u32 i;
1676
1677         *min = 0;
1678         *max = HIST_ENTRIES;
1679
1680         regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);
1681
1682         *hist_count = 0;
1683         /*
1684          * we deliberately ignore the end of the histogram,
1685          * the most white pixels
1686          */
1687         for (i = 1; i < HIST_ENTRIES; i++) {
1688                 if (*hist_entry && !*min)
1689                         *min = i;
1690                 if (*hist_entry)
1691                         *max = i;
1692                 *hist_count += i * (*hist_entry++);
1693         }
1694
1695         if (!*min)
1696                 *min = 1;
1697 }
1698
1699 static void isc_wb_update(struct isc_ctrls *ctrls)
1700 {
1701         u32 *hist_count = &ctrls->hist_count[0];
1702         u32 c, offset[4];
1703         u64 avg = 0;
1704         /* We compute two gains, stretch gain and grey world gain */
1705         u32 s_gain[4], gw_gain[4];
1706
1707         /*
1708          * According to Grey World, we need to set gains for R/B to normalize
1709          * them towards the green channel.
1710          * Thus we want to keep Green as fixed and adjust only Red/Blue
1711          * Compute the average of the both green channels first
1712          */
1713         avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1714                 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1715         avg >>= 1;
1716
1717         /* Green histogram is null, nothing to do */
1718         if (!avg)
1719                 return;
1720
1721         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1722                 /*
1723                  * the color offset is the minimum value of the histogram.
1724                  * we stretch this color to the full range by substracting
1725                  * this value from the color component.
1726                  */
1727                 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1728                 /*
1729                  * The offset is always at least 1. If the offset is 1, we do
1730                  * not need to adjust it, so our result must be zero.
1731                  * the offset is computed in a histogram on 9 bits (0..512)
1732                  * but the offset in register is based on
1733                  * 12 bits pipeline (0..4096).
1734                  * we need to shift with the 3 bits that the histogram is
1735                  * ignoring
1736                  */
1737                 ctrls->offset[c] = (offset[c] - 1) << 3;
1738
1739                 /*
1740                  * the offset is then taken and converted to 2's complements,
1741                  * and must be negative, as we subtract this value from the
1742                  * color components
1743                  */
1744                 ctrls->offset[c] = -ctrls->offset[c];
1745
1746                 /*
1747                  * the stretch gain is the total number of histogram bins
1748                  * divided by the actual range of color component (Max - Min)
1749                  * If we compute gain like this, the actual color component
1750                  * will be stretched to the full histogram.
1751                  * We need to shift 9 bits for precision, we have 9 bits for
1752                  * decimals
1753                  */
1754                 s_gain[c] = (HIST_ENTRIES << 9) /
1755                         (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1756                         ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1757
1758                 /*
1759                  * Now we have to compute the gain w.r.t. the average.
1760                  * Add/lose gain to the component towards the average.
1761                  * If it happens that the component is zero, use the
1762                  * fixed point value : 1.0 gain.
1763                  */
1764                 if (hist_count[c])
1765                         gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1766                 else
1767                         gw_gain[c] = 1 << 9;
1768
1769                 /* multiply both gains and adjust for decimals */
1770                 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1771                 ctrls->gain[c] >>= 9;
1772         }
1773 }
1774
1775 static void isc_awb_work(struct work_struct *w)
1776 {
1777         struct isc_device *isc =
1778                 container_of(w, struct isc_device, awb_work);
1779         struct regmap *regmap = isc->regmap;
1780         struct isc_ctrls *ctrls = &isc->ctrls;
1781         u32 hist_id = ctrls->hist_id;
1782         u32 baysel;
1783         unsigned long flags;
1784         u32 min, max;
1785         int ret;
1786
1787         /* streaming is not active anymore */
1788         if (isc->stop)
1789                 return;
1790
1791         if (ctrls->hist_stat != HIST_ENABLED)
1792                 return;
1793
1794         isc_hist_count(isc, &min, &max);
1795         ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1796         ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1797
1798         if (hist_id != ISC_HIS_CFG_MODE_B) {
1799                 hist_id++;
1800         } else {
1801                 isc_wb_update(ctrls);
1802                 hist_id = ISC_HIS_CFG_MODE_GR;
1803         }
1804
1805         ctrls->hist_id = hist_id;
1806         baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1807
1808         ret = pm_runtime_resume_and_get(isc->dev);
1809         if (ret < 0)
1810                 return;
1811
1812         /*
1813          * only update if we have all the required histograms and controls
1814          * if awb has been disabled, we need to reset registers as well.
1815          */
1816         if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1817                 /*
1818                  * It may happen that DMA Done IRQ will trigger while we are
1819                  * updating white balance registers here.
1820                  * In that case, only parts of the controls have been updated.
1821                  * We can avoid that by locking the section.
1822                  */
1823                 spin_lock_irqsave(&isc->awb_lock, flags);
1824                 isc_update_awb_ctrls(isc);
1825                 spin_unlock_irqrestore(&isc->awb_lock, flags);
1826
1827                 /*
1828                  * if we are doing just the one time white balance adjustment,
1829                  * we are basically done.
1830                  */
1831                 if (ctrls->awb == ISC_WB_ONETIME) {
1832                         v4l2_info(&isc->v4l2_dev,
1833                                   "Completed one time white-balance adjustment.\n");
1834                         /* update the v4l2 controls values */
1835                         isc_update_v4l2_ctrls(isc);
1836                         ctrls->awb = ISC_WB_NONE;
1837                 }
1838         }
1839         regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);
1840         isc_update_profile(isc);
1841         /* if awb has been disabled, we don't need to start another histogram */
1842         if (ctrls->awb)
1843                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1844
1845         pm_runtime_put_sync(isc->dev);
1846 }
1847
1848 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1849 {
1850         struct isc_device *isc = container_of(ctrl->handler,
1851                                              struct isc_device, ctrls.handler);
1852         struct isc_ctrls *ctrls = &isc->ctrls;
1853
1854         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1855                 return 0;
1856
1857         switch (ctrl->id) {
1858         case V4L2_CID_BRIGHTNESS:
1859                 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1860                 break;
1861         case V4L2_CID_CONTRAST:
1862                 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1863                 break;
1864         case V4L2_CID_GAMMA:
1865                 ctrls->gamma_index = ctrl->val;
1866                 break;
1867         default:
1868                 return -EINVAL;
1869         }
1870
1871         return 0;
1872 }
1873
1874 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1875         .s_ctrl = isc_s_ctrl,
1876 };
1877
1878 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1879 {
1880         struct isc_device *isc = container_of(ctrl->handler,
1881                                              struct isc_device, ctrls.handler);
1882         struct isc_ctrls *ctrls = &isc->ctrls;
1883
1884         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1885                 return 0;
1886
1887         switch (ctrl->id) {
1888         case V4L2_CID_AUTO_WHITE_BALANCE:
1889                 if (ctrl->val == 1)
1890                         ctrls->awb = ISC_WB_AUTO;
1891                 else
1892                         ctrls->awb = ISC_WB_NONE;
1893
1894                 /* we did not configure ISC yet */
1895                 if (!isc->config.sd_format)
1896                         break;
1897
1898                 /* configure the controls with new values from v4l2 */
1899                 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1900                         ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1901                 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1902                         ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1903                 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1904                         ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1905                 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1906                         ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1907
1908                 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1909                         ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1910                 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1911                         ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1912                 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1913                         ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1914                 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1915                         ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1916
1917                 isc_update_awb_ctrls(isc);
1918
1919                 if (vb2_is_streaming(&isc->vb2_vidq)) {
1920                         /*
1921                          * If we are streaming, we can update profile to
1922                          * have the new settings in place.
1923                          */
1924                         isc_update_profile(isc);
1925                 } else {
1926                         /*
1927                          * The auto cluster will activate automatically this
1928                          * control. This has to be deactivated when not
1929                          * streaming.
1930                          */
1931                         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1932                 }
1933
1934                 /* if we have autowhitebalance on, start histogram procedure */
1935                 if (ctrls->awb == ISC_WB_AUTO &&
1936                     vb2_is_streaming(&isc->vb2_vidq) &&
1937                     ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1938                         isc_set_histogram(isc, true);
1939
1940                 /*
1941                  * for one time whitebalance adjustment, check the button,
1942                  * if it's pressed, perform the one time operation.
1943                  */
1944                 if (ctrls->awb == ISC_WB_NONE &&
1945                     ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1946                     !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1947                     V4L2_CTRL_FLAG_INACTIVE)) {
1948                         ctrls->awb = ISC_WB_ONETIME;
1949                         isc_set_histogram(isc, true);
1950                         v4l2_dbg(1, debug, &isc->v4l2_dev,
1951                                  "One time white-balance started.\n");
1952                 }
1953                 return 0;
1954         }
1955         return 0;
1956 }
1957
1958 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1959 {
1960         struct isc_device *isc = container_of(ctrl->handler,
1961                                              struct isc_device, ctrls.handler);
1962         struct isc_ctrls *ctrls = &isc->ctrls;
1963
1964         switch (ctrl->id) {
1965         /* being a cluster, this id will be called for every control */
1966         case V4L2_CID_AUTO_WHITE_BALANCE:
1967                 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1968                                         ctrls->gain[ISC_HIS_CFG_MODE_R];
1969                 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1970                                         ctrls->gain[ISC_HIS_CFG_MODE_B];
1971                 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1972                                         ctrls->gain[ISC_HIS_CFG_MODE_GR];
1973                 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1974                                         ctrls->gain[ISC_HIS_CFG_MODE_GB];
1975
1976                 ctrl->cluster[ISC_CTRL_R_OFF]->val =
1977                         ctrls->offset[ISC_HIS_CFG_MODE_R];
1978                 ctrl->cluster[ISC_CTRL_B_OFF]->val =
1979                         ctrls->offset[ISC_HIS_CFG_MODE_B];
1980                 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1981                         ctrls->offset[ISC_HIS_CFG_MODE_GR];
1982                 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1983                         ctrls->offset[ISC_HIS_CFG_MODE_GB];
1984                 break;
1985         }
1986         return 0;
1987 }
1988
1989 static const struct v4l2_ctrl_ops isc_awb_ops = {
1990         .s_ctrl = isc_s_awb_ctrl,
1991         .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
1992 };
1993
1994 #define ISC_CTRL_OFF(_name, _id, _name_str) \
1995         static const struct v4l2_ctrl_config _name = { \
1996                 .ops = &isc_awb_ops, \
1997                 .id = _id, \
1998                 .name = _name_str, \
1999                 .type = V4L2_CTRL_TYPE_INTEGER, \
2000                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2001                 .min = -4095, \
2002                 .max = 4095, \
2003                 .step = 1, \
2004                 .def = 0, \
2005         }
2006
2007 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
2008 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
2009 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
2010 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
2011
2012 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
2013         static const struct v4l2_ctrl_config _name = { \
2014                 .ops = &isc_awb_ops, \
2015                 .id = _id, \
2016                 .name = _name_str, \
2017                 .type = V4L2_CTRL_TYPE_INTEGER, \
2018                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2019                 .min = 0, \
2020                 .max = 8191, \
2021                 .step = 1, \
2022                 .def = 512, \
2023         }
2024
2025 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
2026 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
2027 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
2028 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
2029
2030 static int isc_ctrl_init(struct isc_device *isc)
2031 {
2032         const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
2033         struct isc_ctrls *ctrls = &isc->ctrls;
2034         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
2035         int ret;
2036
2037         ctrls->hist_stat = HIST_INIT;
2038         isc_reset_awb_ctrls(isc);
2039
2040         ret = v4l2_ctrl_handler_init(hdl, 13);
2041         if (ret < 0)
2042                 return ret;
2043
2044         ctrls->brightness = 0;
2045         ctrls->contrast = 256;
2046
2047         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
2048         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
2049         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
2050                           isc->gamma_max);
2051         isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2052                                           V4L2_CID_AUTO_WHITE_BALANCE,
2053                                           0, 1, 1, 1);
2054
2055         /* do_white_balance is a button, so min,max,step,default are ignored */
2056         isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2057                                             V4L2_CID_DO_WHITE_BALANCE,
2058                                             0, 0, 0, 0);
2059
2060         if (!isc->do_wb_ctrl) {
2061                 ret = hdl->error;
2062                 v4l2_ctrl_handler_free(hdl);
2063                 return ret;
2064         }
2065
2066         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
2067
2068         isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
2069         isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
2070         isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
2071         isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
2072         isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
2073         isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
2074         isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
2075         isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
2076
2077         /*
2078          * The cluster is in auto mode with autowhitebalance enabled
2079          * and manual mode otherwise.
2080          */
2081         v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
2082
2083         v4l2_ctrl_handler_setup(hdl);
2084
2085         return 0;
2086 }
2087
2088 static int isc_async_bound(struct v4l2_async_notifier *notifier,
2089                             struct v4l2_subdev *subdev,
2090                             struct v4l2_async_subdev *asd)
2091 {
2092         struct isc_device *isc = container_of(notifier->v4l2_dev,
2093                                               struct isc_device, v4l2_dev);
2094         struct isc_subdev_entity *subdev_entity =
2095                 container_of(notifier, struct isc_subdev_entity, notifier);
2096
2097         if (video_is_registered(&isc->video_dev)) {
2098                 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
2099                 return -EBUSY;
2100         }
2101
2102         subdev_entity->sd = subdev;
2103
2104         return 0;
2105 }
2106
2107 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
2108                               struct v4l2_subdev *subdev,
2109                               struct v4l2_async_subdev *asd)
2110 {
2111         struct isc_device *isc = container_of(notifier->v4l2_dev,
2112                                               struct isc_device, v4l2_dev);
2113         cancel_work_sync(&isc->awb_work);
2114         video_unregister_device(&isc->video_dev);
2115         v4l2_ctrl_handler_free(&isc->ctrls.handler);
2116 }
2117
2118 static struct isc_format *find_format_by_code(unsigned int code, int *index)
2119 {
2120         struct isc_format *fmt = &formats_list[0];
2121         unsigned int i;
2122
2123         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
2124                 if (fmt->mbus_code == code) {
2125                         *index = i;
2126                         return fmt;
2127                 }
2128
2129                 fmt++;
2130         }
2131
2132         return NULL;
2133 }
2134
2135 static int isc_formats_init(struct isc_device *isc)
2136 {
2137         struct isc_format *fmt;
2138         struct v4l2_subdev *subdev = isc->current_subdev->sd;
2139         unsigned int num_fmts, i, j;
2140         u32 list_size = ARRAY_SIZE(formats_list);
2141         struct v4l2_subdev_mbus_code_enum mbus_code = {
2142                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2143         };
2144
2145         num_fmts = 0;
2146         while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
2147                NULL, &mbus_code)) {
2148                 mbus_code.index++;
2149
2150                 fmt = find_format_by_code(mbus_code.code, &i);
2151                 if (!fmt) {
2152                         v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
2153                                   mbus_code.code);
2154                         continue;
2155                 }
2156
2157                 fmt->sd_support = true;
2158                 num_fmts++;
2159         }
2160
2161         if (!num_fmts)
2162                 return -ENXIO;
2163
2164         isc->num_user_formats = num_fmts;
2165         isc->user_formats = devm_kcalloc(isc->dev,
2166                                          num_fmts, sizeof(*isc->user_formats),
2167                                          GFP_KERNEL);
2168         if (!isc->user_formats)
2169                 return -ENOMEM;
2170
2171         fmt = &formats_list[0];
2172         for (i = 0, j = 0; i < list_size; i++) {
2173                 if (fmt->sd_support)
2174                         isc->user_formats[j++] = fmt;
2175                 fmt++;
2176         }
2177
2178         return 0;
2179 }
2180
2181 static int isc_set_default_fmt(struct isc_device *isc)
2182 {
2183         struct v4l2_format f = {
2184                 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
2185                 .fmt.pix = {
2186                         .width          = VGA_WIDTH,
2187                         .height         = VGA_HEIGHT,
2188                         .field          = V4L2_FIELD_NONE,
2189                         .pixelformat    = isc->user_formats[0]->fourcc,
2190                 },
2191         };
2192         int ret;
2193
2194         ret = isc_try_fmt(isc, &f, NULL);
2195         if (ret)
2196                 return ret;
2197
2198         isc->fmt = f;
2199         return 0;
2200 }
2201
2202 static int isc_async_complete(struct v4l2_async_notifier *notifier)
2203 {
2204         struct isc_device *isc = container_of(notifier->v4l2_dev,
2205                                               struct isc_device, v4l2_dev);
2206         struct video_device *vdev = &isc->video_dev;
2207         struct vb2_queue *q = &isc->vb2_vidq;
2208         int ret = 0;
2209
2210         INIT_WORK(&isc->awb_work, isc_awb_work);
2211
2212         ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
2213         if (ret < 0) {
2214                 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
2215                 return ret;
2216         }
2217
2218         isc->current_subdev = container_of(notifier,
2219                                            struct isc_subdev_entity, notifier);
2220         mutex_init(&isc->lock);
2221         init_completion(&isc->comp);
2222
2223         /* Initialize videobuf2 queue */
2224         q->type                 = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2225         q->io_modes             = VB2_MMAP | VB2_DMABUF | VB2_READ;
2226         q->drv_priv             = isc;
2227         q->buf_struct_size      = sizeof(struct isc_buffer);
2228         q->ops                  = &isc_vb2_ops;
2229         q->mem_ops              = &vb2_dma_contig_memops;
2230         q->timestamp_flags      = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2231         q->lock                 = &isc->lock;
2232         q->min_buffers_needed   = 1;
2233         q->dev                  = isc->dev;
2234
2235         ret = vb2_queue_init(q);
2236         if (ret < 0) {
2237                 v4l2_err(&isc->v4l2_dev,
2238                          "vb2_queue_init() failed: %d\n", ret);
2239                 goto isc_async_complete_err;
2240         }
2241
2242         /* Init video dma queues */
2243         INIT_LIST_HEAD(&isc->dma_queue);
2244         spin_lock_init(&isc->dma_queue_lock);
2245         spin_lock_init(&isc->awb_lock);
2246
2247         ret = isc_formats_init(isc);
2248         if (ret < 0) {
2249                 v4l2_err(&isc->v4l2_dev,
2250                          "Init format failed: %d\n", ret);
2251                 goto isc_async_complete_err;
2252         }
2253
2254         ret = isc_set_default_fmt(isc);
2255         if (ret) {
2256                 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
2257                 goto isc_async_complete_err;
2258         }
2259
2260         ret = isc_ctrl_init(isc);
2261         if (ret) {
2262                 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
2263                 goto isc_async_complete_err;
2264         }
2265
2266         /* Register video device */
2267         strscpy(vdev->name, "microchip-isc", sizeof(vdev->name));
2268         vdev->release           = video_device_release_empty;
2269         vdev->fops              = &isc_fops;
2270         vdev->ioctl_ops         = &isc_ioctl_ops;
2271         vdev->v4l2_dev          = &isc->v4l2_dev;
2272         vdev->vfl_dir           = VFL_DIR_RX;
2273         vdev->queue             = q;
2274         vdev->lock              = &isc->lock;
2275         vdev->ctrl_handler      = &isc->ctrls.handler;
2276         vdev->device_caps       = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
2277         video_set_drvdata(vdev, isc);
2278
2279         ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2280         if (ret < 0) {
2281                 v4l2_err(&isc->v4l2_dev,
2282                          "video_register_device failed: %d\n", ret);
2283                 goto isc_async_complete_err;
2284         }
2285
2286         return 0;
2287
2288 isc_async_complete_err:
2289         mutex_destroy(&isc->lock);
2290         return ret;
2291 }
2292
2293 const struct v4l2_async_notifier_operations isc_async_ops = {
2294         .bound = isc_async_bound,
2295         .unbind = isc_async_unbind,
2296         .complete = isc_async_complete,
2297 };
2298
2299 void isc_subdev_cleanup(struct isc_device *isc)
2300 {
2301         struct isc_subdev_entity *subdev_entity;
2302
2303         list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
2304                 v4l2_async_notifier_unregister(&subdev_entity->notifier);
2305                 v4l2_async_notifier_cleanup(&subdev_entity->notifier);
2306         }
2307
2308         INIT_LIST_HEAD(&isc->subdev_entities);
2309 }
2310
2311 int isc_pipeline_init(struct isc_device *isc)
2312 {
2313         struct device *dev = isc->dev;
2314         struct regmap *regmap = isc->regmap;
2315         struct regmap_field *regs;
2316         unsigned int i;
2317
2318         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
2319         const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
2320                 REG_FIELD(ISC_WB_CTRL, 0, 0),
2321                 REG_FIELD(ISC_CFA_CTRL, 0, 0),
2322                 REG_FIELD(ISC_CC_CTRL, 0, 0),
2323                 REG_FIELD(ISC_GAM_CTRL, 0, 0),
2324                 REG_FIELD(ISC_GAM_CTRL, 1, 1),
2325                 REG_FIELD(ISC_GAM_CTRL, 2, 2),
2326                 REG_FIELD(ISC_GAM_CTRL, 3, 3),
2327                 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
2328                 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
2329                 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
2330                 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
2331         };
2332
2333         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
2334                 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
2335                 if (IS_ERR(regs))
2336                         return PTR_ERR(regs);
2337
2338                 isc->pipeline[i] =  regs;
2339         }
2340
2341         return 0;
2342 }
2343
2344 /* regmap configuration */
2345 #define ATMEL_ISC_REG_MAX    0xbfc
2346 const struct regmap_config isc_regmap_config = {
2347         .reg_bits       = 32,
2348         .reg_stride     = 4,
2349         .val_bits       = 32,
2350         .max_register   = ATMEL_ISC_REG_MAX,
2351 };
2352