drivers/media/platform/atmel/atmel-isc-base.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Microchip Image Sensor Controller (ISC) common driver base
   4  *
   5  * Copyright (C) 2016-2019 Microchip Technology, Inc.
   6  *
   7  * Author: Songjun Wu
   8  * Author: Eugen Hristev <eugen.hristev@microchip.com>
   9  *
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/math64.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/videodev2.h>
  25 #include <linux/atmel-isc-media.h>
  26
  27 #include <media/v4l2-ctrls.h>
  28 #include <media/v4l2-device.h>
  29 #include <media/v4l2-event.h>
  30 #include <media/v4l2-image-sizes.h>
  31 #include <media/v4l2-ioctl.h>
  32 #include <media/v4l2-fwnode.h>
  33 #include <media/v4l2-subdev.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "atmel-isc-regs.h"
  37 #include "atmel-isc.h"
  38
  39 static unsigned int debug;
  40 module_param(debug, int, 0644);
  41 MODULE_PARM_DESC(debug, "debug level (0-2)");
  42
  43 static unsigned int sensor_preferred = 1;
  44 module_param(sensor_preferred, uint, 0644);
  45 MODULE_PARM_DESC(sensor_preferred,
  46                  "Sensor is preferred to output the specified format (1-on 0-off), default 1");
  47
  48 /* This is a list of the formats that the ISC can *output* */
  49 const struct isc_format controller_formats[] = {
  50         {
  51                 .fourcc         = V4L2_PIX_FMT_ARGB444,
  52         },
  53         {
  54                 .fourcc         = V4L2_PIX_FMT_ARGB555,
  55         },
  56         {
  57                 .fourcc         = V4L2_PIX_FMT_RGB565,
  58         },
  59         {
  60                 .fourcc         = V4L2_PIX_FMT_ABGR32,
  61         },
  62         {
  63                 .fourcc         = V4L2_PIX_FMT_XBGR32,
  64         },
  65         {
  66                 .fourcc         = V4L2_PIX_FMT_YUV420,
  67         },
  68         {
  69                 .fourcc         = V4L2_PIX_FMT_YUYV,
  70         },
  71         {
  72                 .fourcc         = V4L2_PIX_FMT_YUV422P,
  73         },
  74         {
  75                 .fourcc         = V4L2_PIX_FMT_GREY,
  76         },
  77         {
  78                 .fourcc         = V4L2_PIX_FMT_Y10,
  79         },
  80 };
  81
  82 /* This is a list of formats that the ISC can receive as *input* */
  83 struct isc_format formats_list[] = {
  84         {
  85                 .fourcc         = V4L2_PIX_FMT_SBGGR8,
  86                 .mbus_code      = MEDIA_BUS_FMT_SBGGR8_1X8,
  87                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  88                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
  89         },
  90         {
  91                 .fourcc         = V4L2_PIX_FMT_SGBRG8,
  92                 .mbus_code      = MEDIA_BUS_FMT_SGBRG8_1X8,
  93                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
  94                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
  95         },
  96         {
  97                 .fourcc         = V4L2_PIX_FMT_SGRBG8,
  98                 .mbus_code      = MEDIA_BUS_FMT_SGRBG8_1X8,
  99                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 100                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 101         },
 102         {
 103                 .fourcc         = V4L2_PIX_FMT_SRGGB8,
 104                 .mbus_code      = MEDIA_BUS_FMT_SRGGB8_1X8,
 105                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 106                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 107         },
 108         {
 109                 .fourcc         = V4L2_PIX_FMT_SBGGR10,
 110                 .mbus_code      = MEDIA_BUS_FMT_SBGGR10_1X10,
 111                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 112                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 113         },
 114         {
 115                 .fourcc         = V4L2_PIX_FMT_SGBRG10,
 116                 .mbus_code      = MEDIA_BUS_FMT_SGBRG10_1X10,
 117                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 118                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 119         },
 120         {
 121                 .fourcc         = V4L2_PIX_FMT_SGRBG10,
 122                 .mbus_code      = MEDIA_BUS_FMT_SGRBG10_1X10,
 123                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 124                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 125         },
 126         {
 127                 .fourcc         = V4L2_PIX_FMT_SRGGB10,
 128                 .mbus_code      = MEDIA_BUS_FMT_SRGGB10_1X10,
 129                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 130                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 131         },
 132         {
 133                 .fourcc         = V4L2_PIX_FMT_SBGGR12,
 134                 .mbus_code      = MEDIA_BUS_FMT_SBGGR12_1X12,
 135                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 136                 .cfa_baycfg     = ISC_BAY_CFG_BGBG,
 137         },
 138         {
 139                 .fourcc         = V4L2_PIX_FMT_SGBRG12,
 140                 .mbus_code      = MEDIA_BUS_FMT_SGBRG12_1X12,
 141                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 142                 .cfa_baycfg     = ISC_BAY_CFG_GBGB,
 143         },
 144         {
 145                 .fourcc         = V4L2_PIX_FMT_SGRBG12,
 146                 .mbus_code      = MEDIA_BUS_FMT_SGRBG12_1X12,
 147                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 148                 .cfa_baycfg     = ISC_BAY_CFG_GRGR,
 149         },
 150         {
 151                 .fourcc         = V4L2_PIX_FMT_SRGGB12,
 152                 .mbus_code      = MEDIA_BUS_FMT_SRGGB12_1X12,
 153                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TWELVE,
 154                 .cfa_baycfg     = ISC_BAY_CFG_RGRG,
 155         },
 156         {
 157                 .fourcc         = V4L2_PIX_FMT_GREY,
 158                 .mbus_code      = MEDIA_BUS_FMT_Y8_1X8,
 159                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 160         },
 161         {
 162                 .fourcc         = V4L2_PIX_FMT_YUYV,
 163                 .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 164                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 165         },
 166         {
 167                 .fourcc         = V4L2_PIX_FMT_RGB565,
 168                 .mbus_code      = MEDIA_BUS_FMT_RGB565_2X8_LE,
 169                 .pfe_cfg0_bps   = ISC_PFE_CFG0_BPS_EIGHT,
 170         },
 171         {
 172                 .fourcc         = V4L2_PIX_FMT_Y10,
 173                 .mbus_code      = MEDIA_BUS_FMT_Y10_1X10,
 174                 .pfe_cfg0_bps   = ISC_PFG_CFG0_BPS_TEN,
 175         },
 176
 177 };
 178
 179 #define ISC_IS_FORMAT_RAW(mbus_code) \
 180         (((mbus_code) & 0xf000) == 0x3000)
 181
 182 #define ISC_IS_FORMAT_GREY(mbus_code) \
 183         (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
 184         (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
 185
 186 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
 187 {
 188         struct isc_ctrls *ctrls = &isc->ctrls;
 189
 190         /* In here we set the v4l2 controls w.r.t. our pipeline config */
 191         v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
 192         v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
 193         v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
 194         v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
 195
 196         v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
 197         v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
 198         v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
 199         v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
 200 }
 201
 202 static inline void isc_update_awb_ctrls(struct isc_device *isc)
 203 {
 204         struct isc_ctrls *ctrls = &isc->ctrls;
 205
 206         /* In here we set our actual hw pipeline config */
 207
 208         regmap_write(isc->regmap, ISC_WB_O_RGR,
 209                      ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
 210                      ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
 211         regmap_write(isc->regmap, ISC_WB_O_BGB,
 212                      ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
 213                      ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
 214         regmap_write(isc->regmap, ISC_WB_G_RGR,
 215                      ctrls->gain[ISC_HIS_CFG_MODE_R] |
 216                      (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
 217         regmap_write(isc->regmap, ISC_WB_G_BGB,
 218                      ctrls->gain[ISC_HIS_CFG_MODE_B] |
 219                      (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
 220 }
 221
 222 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
 223 {
 224         unsigned int c;
 225
 226         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
 227                 /* gains have a fixed point at 9 decimals */
 228                 isc->ctrls.gain[c] = 1 << 9;
 229                 /* offsets are in 2's complements */
 230                 isc->ctrls.offset[c] = 0;
 231         }
 232 }
 233
 234 static int isc_wait_clk_stable(struct clk_hw *hw)
 235 {
 236         struct isc_clk *isc_clk = to_isc_clk(hw);
 237         struct regmap *regmap = isc_clk->regmap;
 238         unsigned long timeout = jiffies + usecs_to_jiffies(1000);
 239         unsigned int status;
 240
 241         while (time_before(jiffies, timeout)) {
 242                 regmap_read(regmap, ISC_CLKSR, &status);
 243                 if (!(status & ISC_CLKSR_SIP))
 244                         return 0;
 245
 246                 usleep_range(10, 250);
 247         }
 248
 249         return -ETIMEDOUT;
 250 }
 251
 252 static int isc_clk_prepare(struct clk_hw *hw)
 253 {
 254         struct isc_clk *isc_clk = to_isc_clk(hw);
 255         int ret;
 256
 257         if (isc_clk->id == ISC_ISPCK) {
 258                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 259                 if (ret < 0)
 260                         return ret;
 261         }
 262
 263         return isc_wait_clk_stable(hw);
 264 }
 265
 266 static void isc_clk_unprepare(struct clk_hw *hw)
 267 {
 268         struct isc_clk *isc_clk = to_isc_clk(hw);
 269
 270         isc_wait_clk_stable(hw);
 271
 272         if (isc_clk->id == ISC_ISPCK)
 273                 pm_runtime_put_sync(isc_clk->dev);
 274 }
 275
 276 static int isc_clk_enable(struct clk_hw *hw)
 277 {
 278         struct isc_clk *isc_clk = to_isc_clk(hw);
 279         u32 id = isc_clk->id;
 280         struct regmap *regmap = isc_clk->regmap;
 281         unsigned long flags;
 282         unsigned int status;
 283
 284         dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n",
 285                 __func__, id, isc_clk->div, isc_clk->parent_id);
 286
 287         spin_lock_irqsave(&isc_clk->lock, flags);
 288         regmap_update_bits(regmap, ISC_CLKCFG,
 289                            ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
 290                            (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
 291                            (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
 292
 293         regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
 294         spin_unlock_irqrestore(&isc_clk->lock, flags);
 295
 296         regmap_read(regmap, ISC_CLKSR, &status);
 297         if (status & ISC_CLK(id))
 298                 return 0;
 299         else
 300                 return -EINVAL;
 301 }
 302
 303 static void isc_clk_disable(struct clk_hw *hw)
 304 {
 305         struct isc_clk *isc_clk = to_isc_clk(hw);
 306         u32 id = isc_clk->id;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&isc_clk->lock, flags);
 310         regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
 311         spin_unlock_irqrestore(&isc_clk->lock, flags);
 312 }
 313
 314 static int isc_clk_is_enabled(struct clk_hw *hw)
 315 {
 316         struct isc_clk *isc_clk = to_isc_clk(hw);
 317         u32 status;
 318         int ret;
 319
 320         if (isc_clk->id == ISC_ISPCK) {
 321                 ret = pm_runtime_resume_and_get(isc_clk->dev);
 322                 if (ret < 0)
 323                         return 0;
 324         }
 325
 326         regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
 327
 328         if (isc_clk->id == ISC_ISPCK)
 329                 pm_runtime_put_sync(isc_clk->dev);
 330
 331         return status & ISC_CLK(isc_clk->id) ? 1 : 0;
 332 }
 333
 334 static unsigned long
 335 isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 336 {
 337         struct isc_clk *isc_clk = to_isc_clk(hw);
 338
 339         return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
 340 }
 341
 342 static int isc_clk_determine_rate(struct clk_hw *hw,
 343                                    struct clk_rate_request *req)
 344 {
 345         struct isc_clk *isc_clk = to_isc_clk(hw);
 346         long best_rate = -EINVAL;
 347         int best_diff = -1;
 348         unsigned int i, div;
 349
 350         for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
 351                 struct clk_hw *parent;
 352                 unsigned long parent_rate;
 353
 354                 parent = clk_hw_get_parent_by_index(hw, i);
 355                 if (!parent)
 356                         continue;
 357
 358                 parent_rate = clk_hw_get_rate(parent);
 359                 if (!parent_rate)
 360                         continue;
 361
 362                 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
 363                         unsigned long rate;
 364                         int diff;
 365
 366                         rate = DIV_ROUND_CLOSEST(parent_rate, div);
 367                         diff = abs(req->rate - rate);
 368
 369                         if (best_diff < 0 || best_diff > diff) {
 370                                 best_rate = rate;
 371                                 best_diff = diff;
 372                                 req->best_parent_rate = parent_rate;
 373                                 req->best_parent_hw = parent;
 374                         }
 375
 376                         if (!best_diff || rate < req->rate)
 377                                 break;
 378                 }
 379
 380                 if (!best_diff)
 381                         break;
 382         }
 383
 384         dev_dbg(isc_clk->dev,
 385                 "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
 386                 __func__, best_rate,
 387                 __clk_get_name((req->best_parent_hw)->clk),
 388                 req->best_parent_rate);
 389
 390         if (best_rate < 0)
 391                 return best_rate;
 392
 393         req->rate = best_rate;
 394
 395         return 0;
 396 }
 397
 398 static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
 399 {
 400         struct isc_clk *isc_clk = to_isc_clk(hw);
 401
 402         if (index >= clk_hw_get_num_parents(hw))
 403                 return -EINVAL;
 404
 405         isc_clk->parent_id = index;
 406
 407         return 0;
 408 }
 409
 410 static u8 isc_clk_get_parent(struct clk_hw *hw)
 411 {
 412         struct isc_clk *isc_clk = to_isc_clk(hw);
 413
 414         return isc_clk->parent_id;
 415 }
 416
 417 static int isc_clk_set_rate(struct clk_hw *hw,
 418                              unsigned long rate,
 419                              unsigned long parent_rate)
 420 {
 421         struct isc_clk *isc_clk = to_isc_clk(hw);
 422         u32 div;
 423
 424         if (!rate)
 425                 return -EINVAL;
 426
 427         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 428         if (div > (ISC_CLK_MAX_DIV + 1) || !div)
 429                 return -EINVAL;
 430
 431         isc_clk->div = div - 1;
 432
 433         return 0;
 434 }
 435
 436 static const struct clk_ops isc_clk_ops = {
 437         .prepare        = isc_clk_prepare,
 438         .unprepare      = isc_clk_unprepare,
 439         .enable         = isc_clk_enable,
 440         .disable        = isc_clk_disable,
 441         .is_enabled     = isc_clk_is_enabled,
 442         .recalc_rate    = isc_clk_recalc_rate,
 443         .determine_rate = isc_clk_determine_rate,
 444         .set_parent     = isc_clk_set_parent,
 445         .get_parent     = isc_clk_get_parent,
 446         .set_rate       = isc_clk_set_rate,
 447 };
 448
 449 static int isc_clk_register(struct isc_device *isc, unsigned int id)
 450 {
 451         struct regmap *regmap = isc->regmap;
 452         struct device_node *np = isc->dev->of_node;
 453         struct isc_clk *isc_clk;
 454         struct clk_init_data init;
 455         const char *clk_name = np->name;
 456         const char *parent_names[3];
 457         int num_parents;
 458
 459         num_parents = of_clk_get_parent_count(np);
 460         if (num_parents < 1 || num_parents > 3)
 461                 return -EINVAL;
 462
 463         if (num_parents > 2 && id == ISC_ISPCK)
 464                 num_parents = 2;
 465
 466         of_clk_parent_fill(np, parent_names, num_parents);
 467
 468         if (id == ISC_MCK)
 469                 of_property_read_string(np, "clock-output-names", &clk_name);
 470         else
 471                 clk_name = "isc-ispck";
 472
 473         init.parent_names       = parent_names;
 474         init.num_parents        = num_parents;
 475         init.name               = clk_name;
 476         init.ops                = &isc_clk_ops;
 477         init.flags              = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
 478
 479         isc_clk = &isc->isc_clks[id];
 480         isc_clk->hw.init        = &init;
 481         isc_clk->regmap         = regmap;
 482         isc_clk->id             = id;
 483         isc_clk->dev            = isc->dev;
 484         spin_lock_init(&isc_clk->lock);
 485
 486         isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
 487         if (IS_ERR(isc_clk->clk)) {
 488                 dev_err(isc->dev, "%s: clock register fail\n", clk_name);
 489                 return PTR_ERR(isc_clk->clk);
 490         } else if (id == ISC_MCK)
 491                 of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
 492
 493         return 0;
 494 }
 495
 496 int isc_clk_init(struct isc_device *isc)
 497 {
 498         unsigned int i;
 499         int ret;
 500
 501         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
 502                 isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
 503
 504         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 505                 ret = isc_clk_register(isc, i);
 506                 if (ret)
 507                         return ret;
 508         }
 509
 510         return 0;
 511 }
 512
 513 void isc_clk_cleanup(struct isc_device *isc)
 514 {
 515         unsigned int i;
 516
 517         of_clk_del_provider(isc->dev->of_node);
 518
 519         for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
 520                 struct isc_clk *isc_clk = &isc->isc_clks[i];
 521
 522                 if (!IS_ERR(isc_clk->clk))
 523                         clk_unregister(isc_clk->clk);
 524         }
 525 }
 526
 527 static int isc_queue_setup(struct vb2_queue *vq,
 528                             unsigned int *nbuffers, unsigned int *nplanes,
 529                             unsigned int sizes[], struct device *alloc_devs[])
 530 {
 531         struct isc_device *isc = vb2_get_drv_priv(vq);
 532         unsigned int size = isc->fmt.fmt.pix.sizeimage;
 533
 534         if (*nplanes)
 535                 return sizes[0] < size ? -EINVAL : 0;
 536
 537         *nplanes = 1;
 538         sizes[0] = size;
 539
 540         return 0;
 541 }
 542
 543 static int isc_buffer_prepare(struct vb2_buffer *vb)
 544 {
 545         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 546         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 547         unsigned long size = isc->fmt.fmt.pix.sizeimage;
 548
 549         if (vb2_plane_size(vb, 0) < size) {
 550                 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
 551                          vb2_plane_size(vb, 0), size);
 552                 return -EINVAL;
 553         }
 554
 555         vb2_set_plane_payload(vb, 0, size);
 556
 557         vbuf->field = isc->fmt.fmt.pix.field;
 558
 559         return 0;
 560 }
 561
 562 static void isc_start_dma(struct isc_device *isc)
 563 {
 564         struct regmap *regmap = isc->regmap;
 565         u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
 566         u32 dctrl_dview;
 567         dma_addr_t addr0;
 568         u32 h, w;
 569
 570         h = isc->fmt.fmt.pix.height;
 571         w = isc->fmt.fmt.pix.width;
 572
 573         /*
 574          * In case the sensor is not RAW, it will output a pixel (12-16 bits)
 575          * with two samples on the ISC Data bus (which is 8-12)
 576          * ISC will count each sample, so, we need to multiply these values
 577          * by two, to get the real number of samples for the required pixels.
 578          */
 579         if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
 580                 h <<= 1;
 581                 w <<= 1;
 582         }
 583
 584         /*
 585          * We limit the column/row count that the ISC will output according
 586          * to the configured resolution that we want.
 587          * This will avoid the situation where the sensor is misconfigured,
 588          * sending more data, and the ISC will just take it and DMA to memory,
 589          * causing corruption.
 590          */
 591         regmap_write(regmap, ISC_PFE_CFG1,
 592                      (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
 593                      (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
 594
 595         regmap_write(regmap, ISC_PFE_CFG2,
 596                      (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
 597                      (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
 598
 599         regmap_update_bits(regmap, ISC_PFE_CFG0,
 600                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
 601                            ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 602
 603         addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
 604         regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
 605
 606         switch (isc->config.fourcc) {
 607         case V4L2_PIX_FMT_YUV420:
 608                 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 609                              addr0 + (sizeimage * 2) / 3);
 610                 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 611                              addr0 + (sizeimage * 5) / 6);
 612                 break;
 613         case V4L2_PIX_FMT_YUV422P:
 614                 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 615                              addr0 + sizeimage / 2);
 616                 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 617                              addr0 + (sizeimage * 3) / 4);
 618                 break;
 619         default:
 620                 break;
 621         }
 622
 623         dctrl_dview = isc->config.dctrl_dview;
 624
 625         regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
 626                      dctrl_dview | ISC_DCTRL_IE_IS);
 627         spin_lock(&isc->awb_lock);
 628         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
 629         spin_unlock(&isc->awb_lock);
 630 }
 631
 632 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
 633 {
 634         struct regmap *regmap = isc->regmap;
 635         struct isc_ctrls *ctrls = &isc->ctrls;
 636         u32 val, bay_cfg;
 637         const u32 *gamma;
 638         unsigned int i;
 639
 640         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
 641         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
 642                 val = pipeline & BIT(i) ? 1 : 0;
 643                 regmap_field_write(isc->pipeline[i], val);
 644         }
 645
 646         if (!pipeline)
 647                 return;
 648
 649         bay_cfg = isc->config.sd_format->cfa_baycfg;
 650
 651         regmap_write(regmap, ISC_WB_CFG, bay_cfg);
 652         isc_update_awb_ctrls(isc);
 653         isc_update_v4l2_ctrls(isc);
 654
 655         regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
 656
 657         gamma = &isc->gamma_table[ctrls->gamma_index][0];
 658         regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
 659         regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 660         regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 661
 662         isc->config_csc(isc);
 663         isc->config_cbc(isc);
 664 }
 665
 666 static int isc_update_profile(struct isc_device *isc)
 667 {
 668         struct regmap *regmap = isc->regmap;
 669         u32 sr;
 670         int counter = 100;
 671
 672         regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
 673
 674         regmap_read(regmap, ISC_CTRLSR, &sr);
 675         while ((sr & ISC_CTRL_UPPRO) && counter--) {
 676                 usleep_range(1000, 2000);
 677                 regmap_read(regmap, ISC_CTRLSR, &sr);
 678         }
 679
 680         if (counter < 0) {
 681                 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
 682                 return -ETIMEDOUT;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void isc_set_histogram(struct isc_device *isc, bool enable)
 689 {
 690         struct regmap *regmap = isc->regmap;
 691         struct isc_ctrls *ctrls = &isc->ctrls;
 692
 693         if (enable) {
 694                 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
 695                              ISC_HIS_CFG_MODE_GR |
 696                              (isc->config.sd_format->cfa_baycfg
 697                                         << ISC_HIS_CFG_BAYSEL_SHIFT) |
 698                                         ISC_HIS_CFG_RAR);
 699                 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 700                              ISC_HIS_CTRL_EN);
 701                 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
 702                 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
 703                 isc_update_profile(isc);
 704                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
 705
 706                 ctrls->hist_stat = HIST_ENABLED;
 707         } else {
 708                 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
 709                 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 710                              ISC_HIS_CTRL_DIS);
 711
 712                 ctrls->hist_stat = HIST_DISABLED;
 713         }
 714 }
 715
 716 static int isc_configure(struct isc_device *isc)
 717 {
 718         struct regmap *regmap = isc->regmap;
 719         u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
 720         struct isc_subdev_entity *subdev = isc->current_subdev;
 721
 722         pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
 723         rlp_mode = isc->config.rlp_cfg_mode;
 724         pipeline = isc->config.bits_pipeline;
 725
 726         dcfg = isc->config.dcfg_imode | isc->dcfg;
 727
 728         pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
 729         mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 730                ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
 731                ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
 732                    ISC_PFE_CFG0_CCIR656;
 733
 734         regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 735
 736         regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
 737                            ISC_RLP_CFG_MODE_MASK, rlp_mode);
 738
 739         regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
 740
 741         /* Set the pipeline */
 742         isc_set_pipeline(isc, pipeline);
 743
 744         /*
 745          * The current implemented histogram is available for RAW R, B, GB, GR
 746          * channels. We need to check if sensor is outputting RAW BAYER
 747          */
 748         if (isc->ctrls.awb &&
 749             ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 750                 isc_set_histogram(isc, true);
 751         else
 752                 isc_set_histogram(isc, false);
 753
 754         /* Update profile */
 755         return isc_update_profile(isc);
 756 }
 757
 758 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
 759 {
 760         struct isc_device *isc = vb2_get_drv_priv(vq);
 761         struct regmap *regmap = isc->regmap;
 762         struct isc_buffer *buf;
 763         unsigned long flags;
 764         int ret;
 765
 766         /* Enable stream on the sub device */
 767         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
 768         if (ret && ret != -ENOIOCTLCMD) {
 769                 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
 770                          ret);
 771                 goto err_start_stream;
 772         }
 773
 774         ret = pm_runtime_resume_and_get(isc->dev);
 775         if (ret < 0) {
 776                 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
 777                          ret);
 778                 goto err_pm_get;
 779         }
 780
 781         ret = isc_configure(isc);
 782         if (unlikely(ret))
 783                 goto err_configure;
 784
 785         /* Enable DMA interrupt */
 786         regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
 787
 788         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 789
 790         isc->sequence = 0;
 791         isc->stop = false;
 792         reinit_completion(&isc->comp);
 793
 794         isc->cur_frm = list_first_entry(&isc->dma_queue,
 795                                         struct isc_buffer, list);
 796         list_del(&isc->cur_frm->list);
 797
 798         isc_start_dma(isc);
 799
 800         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 801
 802         /* if we streaming from RAW, we can do one-shot white balance adj */
 803         if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 804                 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
 805
 806         return 0;
 807
 808 err_configure:
 809         pm_runtime_put_sync(isc->dev);
 810 err_pm_get:
 811         v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 812
 813 err_start_stream:
 814         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 815         list_for_each_entry(buf, &isc->dma_queue, list)
 816                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
 817         INIT_LIST_HEAD(&isc->dma_queue);
 818         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 819
 820         return ret;
 821 }
 822
 823 static void isc_stop_streaming(struct vb2_queue *vq)
 824 {
 825         struct isc_device *isc = vb2_get_drv_priv(vq);
 826         unsigned long flags;
 827         struct isc_buffer *buf;
 828         int ret;
 829
 830         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
 831
 832         isc->stop = true;
 833
 834         /* Wait until the end of the current frame */
 835         if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
 836                 v4l2_err(&isc->v4l2_dev,
 837                          "Timeout waiting for end of the capture\n");
 838
 839         /* Disable DMA interrupt */
 840         regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
 841
 842         pm_runtime_put_sync(isc->dev);
 843
 844         /* Disable stream on the sub device */
 845         ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 846         if (ret && ret != -ENOIOCTLCMD)
 847                 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
 848
 849         /* Release all active buffers */
 850         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 851         if (unlikely(isc->cur_frm)) {
 852                 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
 853                                 VB2_BUF_STATE_ERROR);
 854                 isc->cur_frm = NULL;
 855         }
 856         list_for_each_entry(buf, &isc->dma_queue, list)
 857                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 858         INIT_LIST_HEAD(&isc->dma_queue);
 859         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 860 }
 861
 862 static void isc_buffer_queue(struct vb2_buffer *vb)
 863 {
 864         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 865         struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
 866         struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 867         unsigned long flags;
 868
 869         spin_lock_irqsave(&isc->dma_queue_lock, flags);
 870         if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
 871                 vb2_is_streaming(vb->vb2_queue)) {
 872                 isc->cur_frm = buf;
 873                 isc_start_dma(isc);
 874         } else
 875                 list_add_tail(&buf->list, &isc->dma_queue);
 876         spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 877 }
 878
 879 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
 880                                                  unsigned int fourcc)
 881 {
 882         unsigned int num_formats = isc->num_user_formats;
 883         struct isc_format *fmt;
 884         unsigned int i;
 885
 886         for (i = 0; i < num_formats; i++) {
 887                 fmt = isc->user_formats[i];
 888                 if (fmt->fourcc == fourcc)
 889                         return fmt;
 890         }
 891
 892         return NULL;
 893 }
 894
 895 static const struct vb2_ops isc_vb2_ops = {
 896         .queue_setup            = isc_queue_setup,
 897         .wait_prepare           = vb2_ops_wait_prepare,
 898         .wait_finish            = vb2_ops_wait_finish,
 899         .buf_prepare            = isc_buffer_prepare,
 900         .start_streaming        = isc_start_streaming,
 901         .stop_streaming         = isc_stop_streaming,
 902         .buf_queue              = isc_buffer_queue,
 903 };
 904
 905 static int isc_querycap(struct file *file, void *priv,
 906                          struct v4l2_capability *cap)
 907 {
 908         struct isc_device *isc = video_drvdata(file);
 909
 910         strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
 911         strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
 912         snprintf(cap->bus_info, sizeof(cap->bus_info),
 913                  "platform:%s", isc->v4l2_dev.name);
 914
 915         return 0;
 916 }
 917
 918 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
 919                                  struct v4l2_fmtdesc *f)
 920 {
 921         u32 index = f->index;
 922         u32 i, supported_index;
 923
 924         if (index < ARRAY_SIZE(controller_formats)) {
 925                 f->pixelformat = controller_formats[index].fourcc;
 926                 return 0;
 927         }
 928
 929         index -= ARRAY_SIZE(controller_formats);
 930
 931         supported_index = 0;
 932
 933         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
 934                 if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
 935                     !formats_list[i].sd_support)
 936                         continue;
 937                 if (supported_index == index) {
 938                         f->pixelformat = formats_list[i].fourcc;
 939                         return 0;
 940                 }
 941                 supported_index++;
 942         }
 943
 944         return -EINVAL;
 945 }
 946
 947 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
 948                               struct v4l2_format *fmt)
 949 {
 950         struct isc_device *isc = video_drvdata(file);
 951
 952         *fmt = isc->fmt;
 953
 954         return 0;
 955 }
 956
 957 /*
 958  * Checks the current configured format, if ISC can output it,
 959  * considering which type of format the ISC receives from the sensor
 960  */
 961 static int isc_try_validate_formats(struct isc_device *isc)
 962 {
 963         int ret;
 964         bool bayer = false, yuv = false, rgb = false, grey = false;
 965
 966         /* all formats supported by the RLP module are OK */
 967         switch (isc->try_config.fourcc) {
 968         case V4L2_PIX_FMT_SBGGR8:
 969         case V4L2_PIX_FMT_SGBRG8:
 970         case V4L2_PIX_FMT_SGRBG8:
 971         case V4L2_PIX_FMT_SRGGB8:
 972         case V4L2_PIX_FMT_SBGGR10:
 973         case V4L2_PIX_FMT_SGBRG10:
 974         case V4L2_PIX_FMT_SGRBG10:
 975         case V4L2_PIX_FMT_SRGGB10:
 976         case V4L2_PIX_FMT_SBGGR12:
 977         case V4L2_PIX_FMT_SGBRG12:
 978         case V4L2_PIX_FMT_SGRBG12:
 979         case V4L2_PIX_FMT_SRGGB12:
 980                 ret = 0;
 981                 bayer = true;
 982                 break;
 983
 984         case V4L2_PIX_FMT_YUV420:
 985         case V4L2_PIX_FMT_YUV422P:
 986         case V4L2_PIX_FMT_YUYV:
 987                 ret = 0;
 988                 yuv = true;
 989                 break;
 990
 991         case V4L2_PIX_FMT_RGB565:
 992         case V4L2_PIX_FMT_ABGR32:
 993         case V4L2_PIX_FMT_XBGR32:
 994         case V4L2_PIX_FMT_ARGB444:
 995         case V4L2_PIX_FMT_ARGB555:
 996                 ret = 0;
 997                 rgb = true;
 998                 break;
 999         case V4L2_PIX_FMT_GREY:
1000         case V4L2_PIX_FMT_Y10:
1001                 ret = 0;
1002                 grey = true;
1003                 break;
1004         default:
1005         /* any other different formats are not supported */
1006                 ret = -EINVAL;
1007         }
1008         v4l2_dbg(1, debug, &isc->v4l2_dev,
1009                  "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
1010                  rgb, yuv, grey, bayer);
1011
1012         /* we cannot output RAW if we do not receive RAW */
1013         if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
1014                 return -EINVAL;
1015
1016         /* we cannot output GREY if we do not receive RAW/GREY */
1017         if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
1018             !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
1019                 return -EINVAL;
1020
1021         return ret;
1022 }
1023
1024 /*
1025  * Configures the RLP and DMA modules, depending on the output format
1026  * configured for the ISC.
1027  * If direct_dump == true, just dump raw data 8/16 bits depending on format.
1028  */
1029 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
1030 {
1031         switch (isc->try_config.fourcc) {
1032         case V4L2_PIX_FMT_SBGGR8:
1033         case V4L2_PIX_FMT_SGBRG8:
1034         case V4L2_PIX_FMT_SGRBG8:
1035         case V4L2_PIX_FMT_SRGGB8:
1036                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1037                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1038                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1039                 isc->try_config.bpp = 8;
1040                 break;
1041         case V4L2_PIX_FMT_SBGGR10:
1042         case V4L2_PIX_FMT_SGBRG10:
1043         case V4L2_PIX_FMT_SGRBG10:
1044         case V4L2_PIX_FMT_SRGGB10:
1045                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
1046                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1047                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1048                 isc->try_config.bpp = 16;
1049                 break;
1050         case V4L2_PIX_FMT_SBGGR12:
1051         case V4L2_PIX_FMT_SGBRG12:
1052         case V4L2_PIX_FMT_SGRBG12:
1053         case V4L2_PIX_FMT_SRGGB12:
1054                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
1055                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1056                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1057                 isc->try_config.bpp = 16;
1058                 break;
1059         case V4L2_PIX_FMT_RGB565:
1060                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
1061                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1062                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1063                 isc->try_config.bpp = 16;
1064                 break;
1065         case V4L2_PIX_FMT_ARGB444:
1066                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
1067                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1068                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1069                 isc->try_config.bpp = 16;
1070                 break;
1071         case V4L2_PIX_FMT_ARGB555:
1072                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
1073                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1074                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1075                 isc->try_config.bpp = 16;
1076                 break;
1077         case V4L2_PIX_FMT_ABGR32:
1078         case V4L2_PIX_FMT_XBGR32:
1079                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
1080                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1081                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1082                 isc->try_config.bpp = 32;
1083                 break;
1084         case V4L2_PIX_FMT_YUV420:
1085                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1086                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
1087                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1088                 isc->try_config.bpp = 12;
1089                 break;
1090         case V4L2_PIX_FMT_YUV422P:
1091                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1092                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
1093                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1094                 isc->try_config.bpp = 16;
1095                 break;
1096         case V4L2_PIX_FMT_YUYV:
1097                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1098                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1099                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1100                 isc->try_config.bpp = 16;
1101                 break;
1102         case V4L2_PIX_FMT_GREY:
1103                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
1104                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1105                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1106                 isc->try_config.bpp = 8;
1107                 break;
1108         case V4L2_PIX_FMT_Y10:
1109                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
1110                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1111                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1112                 isc->try_config.bpp = 16;
1113                 break;
1114         default:
1115                 return -EINVAL;
1116         }
1117
1118         if (direct_dump) {
1119                 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1120                 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1121                 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1122                 return 0;
1123         }
1124
1125         return 0;
1126 }
1127
1128 /*
1129  * Configuring pipeline modules, depending on which format the ISC outputs
1130  * and considering which format it has as input from the sensor.
1131  */
1132 static int isc_try_configure_pipeline(struct isc_device *isc)
1133 {
1134         switch (isc->try_config.fourcc) {
1135         case V4L2_PIX_FMT_RGB565:
1136         case V4L2_PIX_FMT_ARGB555:
1137         case V4L2_PIX_FMT_ARGB444:
1138         case V4L2_PIX_FMT_ABGR32:
1139         case V4L2_PIX_FMT_XBGR32:
1140                 /* if sensor format is RAW, we convert inside ISC */
1141                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1142                         isc->try_config.bits_pipeline = CFA_ENABLE |
1143                                 WB_ENABLE | GAM_ENABLES;
1144                 } else {
1145                         isc->try_config.bits_pipeline = 0x0;
1146                 }
1147                 break;
1148         case V4L2_PIX_FMT_YUV420:
1149                 /* if sensor format is RAW, we convert inside ISC */
1150                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1151                         isc->try_config.bits_pipeline = CFA_ENABLE |
1152                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1153                                 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
1154                 } else {
1155                         isc->try_config.bits_pipeline = 0x0;
1156                 }
1157                 break;
1158         case V4L2_PIX_FMT_YUV422P:
1159                 /* if sensor format is RAW, we convert inside ISC */
1160                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1161                         isc->try_config.bits_pipeline = CFA_ENABLE |
1162                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1163                                 SUB422_ENABLE | CBC_ENABLE;
1164                 } else {
1165                         isc->try_config.bits_pipeline = 0x0;
1166                 }
1167                 break;
1168         case V4L2_PIX_FMT_YUYV:
1169                 /* if sensor format is RAW, we convert inside ISC */
1170                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1171                         isc->try_config.bits_pipeline = CFA_ENABLE |
1172                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1173                                 SUB422_ENABLE | CBC_ENABLE;
1174                 } else {
1175                         isc->try_config.bits_pipeline = 0x0;
1176                 }
1177                 break;
1178         case V4L2_PIX_FMT_GREY:
1179                 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1180                 /* if sensor format is RAW, we convert inside ISC */
1181                         isc->try_config.bits_pipeline = CFA_ENABLE |
1182                                 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1183                                 CBC_ENABLE;
1184                 } else {
1185                         isc->try_config.bits_pipeline = 0x0;
1186                 }
1187                 break;
1188         default:
1189                 isc->try_config.bits_pipeline = 0x0;
1190         }
1191         return 0;
1192 }
1193
1194 static void isc_try_fse(struct isc_device *isc,
1195                         struct v4l2_subdev_pad_config *pad_cfg)
1196 {
1197         int ret;
1198         struct v4l2_subdev_frame_size_enum fse = {};
1199
1200         /*
1201          * If we do not know yet which format the subdev is using, we cannot
1202          * do anything.
1203          */
1204         if (!isc->try_config.sd_format)
1205                 return;
1206
1207         fse.code = isc->try_config.sd_format->mbus_code;
1208         fse.which = V4L2_SUBDEV_FORMAT_TRY;
1209
1210         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1211                                pad_cfg, &fse);
1212         /*
1213          * Attempt to obtain format size from subdev. If not available,
1214          * just use the maximum ISC can receive.
1215          */
1216         if (ret) {
1217                 pad_cfg->try_crop.width = isc->max_width;
1218                 pad_cfg->try_crop.height = isc->max_height;
1219         } else {
1220                 pad_cfg->try_crop.width = fse.max_width;
1221                 pad_cfg->try_crop.height = fse.max_height;
1222         }
1223 }
1224
1225 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
1226                         u32 *code)
1227 {
1228         int i;
1229         struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
1230         struct v4l2_pix_format *pixfmt = &f->fmt.pix;
1231         struct v4l2_subdev_pad_config pad_cfg = {};
1232         struct v4l2_subdev_format format = {
1233                 .which = V4L2_SUBDEV_FORMAT_TRY,
1234         };
1235         u32 mbus_code;
1236         int ret;
1237         bool rlp_dma_direct_dump = false;
1238
1239         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1240                 return -EINVAL;
1241
1242         /* Step 1: find a RAW format that is supported */
1243         for (i = 0; i < isc->num_user_formats; i++) {
1244                 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
1245                         sd_fmt = isc->user_formats[i];
1246                         break;
1247                 }
1248         }
1249         /* Step 2: We can continue with this RAW format, or we can look
1250          * for better: maybe sensor supports directly what we need.
1251          */
1252         direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
1253
1254         /* Step 3: We have both. We decide given the module parameter which
1255          * one to use.
1256          */
1257         if (direct_fmt && sd_fmt && sensor_preferred)
1258                 sd_fmt = direct_fmt;
1259
1260         /* Step 4: we do not have RAW but we have a direct format. Use it. */
1261         if (direct_fmt && !sd_fmt)
1262                 sd_fmt = direct_fmt;
1263
1264         /* Step 5: if we are using a direct format, we need to package
1265          * everything as 8 bit data and just dump it
1266          */
1267         if (sd_fmt == direct_fmt)
1268                 rlp_dma_direct_dump = true;
1269
1270         /* Step 6: We have no format. This can happen if the userspace
1271          * requests some weird/invalid format.
1272          * In this case, default to whatever we have
1273          */
1274         if (!sd_fmt && !direct_fmt) {
1275                 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
1276                 v4l2_dbg(1, debug, &isc->v4l2_dev,
1277                          "Sensor not supporting %.4s, using %.4s\n",
1278                          (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
1279         }
1280
1281         if (!sd_fmt) {
1282                 ret = -EINVAL;
1283                 goto isc_try_fmt_err;
1284         }
1285
1286         /* Step 7: Print out what we decided for debugging */
1287         v4l2_dbg(1, debug, &isc->v4l2_dev,
1288                  "Preferring to have sensor using format %.4s\n",
1289                  (char *)&sd_fmt->fourcc);
1290
1291         /* Step 8: at this moment we decided which format the subdev will use */
1292         isc->try_config.sd_format = sd_fmt;
1293
1294         /* Limit to Atmel ISC hardware capabilities */
1295         if (pixfmt->width > isc->max_width)
1296                 pixfmt->width = isc->max_width;
1297         if (pixfmt->height > isc->max_height)
1298                 pixfmt->height = isc->max_height;
1299
1300         /*
1301          * The mbus format is the one the subdev outputs.
1302          * The pixels will be transferred in this format Sensor -> ISC
1303          */
1304         mbus_code = sd_fmt->mbus_code;
1305
1306         /*
1307          * Validate formats. If the required format is not OK, default to raw.
1308          */
1309
1310         isc->try_config.fourcc = pixfmt->pixelformat;
1311
1312         if (isc_try_validate_formats(isc)) {
1313                 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
1314                 /* Re-try to validate the new format */
1315                 ret = isc_try_validate_formats(isc);
1316                 if (ret)
1317                         goto isc_try_fmt_err;
1318         }
1319
1320         ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
1321         if (ret)
1322                 goto isc_try_fmt_err;
1323
1324         ret = isc_try_configure_pipeline(isc);
1325         if (ret)
1326                 goto isc_try_fmt_err;
1327
1328         /* Obtain frame sizes if possible to have crop requirements ready */
1329         isc_try_fse(isc, &pad_cfg);
1330
1331         v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
1332         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
1333                                &pad_cfg, &format);
1334         if (ret < 0)
1335                 goto isc_try_fmt_subdev_err;
1336
1337         v4l2_fill_pix_format(pixfmt, &format.format);
1338
1339         /* Limit to Atmel ISC hardware capabilities */
1340         if (pixfmt->width > isc->max_width)
1341                 pixfmt->width = isc->max_width;
1342         if (pixfmt->height > isc->max_height)
1343                 pixfmt->height = isc->max_height;
1344
1345         pixfmt->field = V4L2_FIELD_NONE;
1346         pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
1347         pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
1348
1349         if (code)
1350                 *code = mbus_code;
1351
1352         return 0;
1353
1354 isc_try_fmt_err:
1355         v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
1356 isc_try_fmt_subdev_err:
1357         memset(&isc->try_config, 0, sizeof(isc->try_config));
1358
1359         return ret;
1360 }
1361
1362 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
1363 {
1364         struct v4l2_subdev_format format = {
1365                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1366         };
1367         u32 mbus_code = 0;
1368         int ret;
1369
1370         ret = isc_try_fmt(isc, f, &mbus_code);
1371         if (ret)
1372                 return ret;
1373
1374         v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1375         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1376                                set_fmt, NULL, &format);
1377         if (ret < 0)
1378                 return ret;
1379
1380         /* Limit to Atmel ISC hardware capabilities */
1381         if (f->fmt.pix.width > isc->max_width)
1382                 f->fmt.pix.width = isc->max_width;
1383         if (f->fmt.pix.height > isc->max_height)
1384                 f->fmt.pix.height = isc->max_height;
1385
1386         isc->fmt = *f;
1387
1388         if (isc->try_config.sd_format && isc->config.sd_format &&
1389             isc->try_config.sd_format != isc->config.sd_format) {
1390                 isc->ctrls.hist_stat = HIST_INIT;
1391                 isc_reset_awb_ctrls(isc);
1392                 isc_update_v4l2_ctrls(isc);
1393         }
1394         /* make the try configuration active */
1395         isc->config = isc->try_config;
1396
1397         v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1398
1399         return 0;
1400 }
1401
1402 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1403                               struct v4l2_format *f)
1404 {
1405         struct isc_device *isc = video_drvdata(file);
1406
1407         if (vb2_is_streaming(&isc->vb2_vidq))
1408                 return -EBUSY;
1409
1410         return isc_set_fmt(isc, f);
1411 }
1412
1413 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1414                                 struct v4l2_format *f)
1415 {
1416         struct isc_device *isc = video_drvdata(file);
1417
1418         return isc_try_fmt(isc, f, NULL);
1419 }
1420
1421 static int isc_enum_input(struct file *file, void *priv,
1422                            struct v4l2_input *inp)
1423 {
1424         if (inp->index != 0)
1425                 return -EINVAL;
1426
1427         inp->type = V4L2_INPUT_TYPE_CAMERA;
1428         inp->std = 0;
1429         strscpy(inp->name, "Camera", sizeof(inp->name));
1430
1431         return 0;
1432 }
1433
1434 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1435 {
1436         *i = 0;
1437
1438         return 0;
1439 }
1440
1441 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1442 {
1443         if (i > 0)
1444                 return -EINVAL;
1445
1446         return 0;
1447 }
1448
1449 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1450 {
1451         struct isc_device *isc = video_drvdata(file);
1452
1453         return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1454 }
1455
1456 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1457 {
1458         struct isc_device *isc = video_drvdata(file);
1459
1460         return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1461 }
1462
1463 static int isc_enum_framesizes(struct file *file, void *fh,
1464                                struct v4l2_frmsizeenum *fsize)
1465 {
1466         struct isc_device *isc = video_drvdata(file);
1467         struct v4l2_subdev_frame_size_enum fse = {
1468                 .code = isc->config.sd_format->mbus_code,
1469                 .index = fsize->index,
1470                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1471         };
1472         int ret = -EINVAL;
1473         int i;
1474
1475         for (i = 0; i < isc->num_user_formats; i++)
1476                 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1477                         ret = 0;
1478
1479         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1480                 if (controller_formats[i].fourcc == fsize->pixel_format)
1481                         ret = 0;
1482
1483         if (ret)
1484                 return ret;
1485
1486         ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1487                                NULL, &fse);
1488         if (ret)
1489                 return ret;
1490
1491         fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1492         fsize->discrete.width = fse.max_width;
1493         fsize->discrete.height = fse.max_height;
1494
1495         return 0;
1496 }
1497
1498 static int isc_enum_frameintervals(struct file *file, void *fh,
1499                                     struct v4l2_frmivalenum *fival)
1500 {
1501         struct isc_device *isc = video_drvdata(file);
1502         struct v4l2_subdev_frame_interval_enum fie = {
1503                 .code = isc->config.sd_format->mbus_code,
1504                 .index = fival->index,
1505                 .width = fival->width,
1506                 .height = fival->height,
1507                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1508         };
1509         int ret = -EINVAL;
1510         unsigned int i;
1511
1512         for (i = 0; i < isc->num_user_formats; i++)
1513                 if (isc->user_formats[i]->fourcc == fival->pixel_format)
1514                         ret = 0;
1515
1516         for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1517                 if (controller_formats[i].fourcc == fival->pixel_format)
1518                         ret = 0;
1519
1520         if (ret)
1521                 return ret;
1522
1523         ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1524                                enum_frame_interval, NULL, &fie);
1525         if (ret)
1526                 return ret;
1527
1528         fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1529         fival->discrete = fie.interval;
1530
1531         return 0;
1532 }
1533
1534 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1535         .vidioc_querycap                = isc_querycap,
1536         .vidioc_enum_fmt_vid_cap        = isc_enum_fmt_vid_cap,
1537         .vidioc_g_fmt_vid_cap           = isc_g_fmt_vid_cap,
1538         .vidioc_s_fmt_vid_cap           = isc_s_fmt_vid_cap,
1539         .vidioc_try_fmt_vid_cap         = isc_try_fmt_vid_cap,
1540
1541         .vidioc_enum_input              = isc_enum_input,
1542         .vidioc_g_input                 = isc_g_input,
1543         .vidioc_s_input                 = isc_s_input,
1544
1545         .vidioc_reqbufs                 = vb2_ioctl_reqbufs,
1546         .vidioc_querybuf                = vb2_ioctl_querybuf,
1547         .vidioc_qbuf                    = vb2_ioctl_qbuf,
1548         .vidioc_expbuf                  = vb2_ioctl_expbuf,
1549         .vidioc_dqbuf                   = vb2_ioctl_dqbuf,
1550         .vidioc_create_bufs             = vb2_ioctl_create_bufs,
1551         .vidioc_prepare_buf             = vb2_ioctl_prepare_buf,
1552         .vidioc_streamon                = vb2_ioctl_streamon,
1553         .vidioc_streamoff               = vb2_ioctl_streamoff,
1554
1555         .vidioc_g_parm                  = isc_g_parm,
1556         .vidioc_s_parm                  = isc_s_parm,
1557         .vidioc_enum_framesizes         = isc_enum_framesizes,
1558         .vidioc_enum_frameintervals     = isc_enum_frameintervals,
1559
1560         .vidioc_log_status              = v4l2_ctrl_log_status,
1561         .vidioc_subscribe_event         = v4l2_ctrl_subscribe_event,
1562         .vidioc_unsubscribe_event       = v4l2_event_unsubscribe,
1563 };
1564
1565 static int isc_open(struct file *file)
1566 {
1567         struct isc_device *isc = video_drvdata(file);
1568         struct v4l2_subdev *sd = isc->current_subdev->sd;
1569         int ret;
1570
1571         if (mutex_lock_interruptible(&isc->lock))
1572                 return -ERESTARTSYS;
1573
1574         ret = v4l2_fh_open(file);
1575         if (ret < 0)
1576                 goto unlock;
1577
1578         if (!v4l2_fh_is_singular_file(file))
1579                 goto unlock;
1580
1581         ret = v4l2_subdev_call(sd, core, s_power, 1);
1582         if (ret < 0 && ret != -ENOIOCTLCMD) {
1583                 v4l2_fh_release(file);
1584                 goto unlock;
1585         }
1586
1587         ret = isc_set_fmt(isc, &isc->fmt);
1588         if (ret) {
1589                 v4l2_subdev_call(sd, core, s_power, 0);
1590                 v4l2_fh_release(file);
1591         }
1592
1593 unlock:
1594         mutex_unlock(&isc->lock);
1595         return ret;
1596 }
1597
1598 static int isc_release(struct file *file)
1599 {
1600         struct isc_device *isc = video_drvdata(file);
1601         struct v4l2_subdev *sd = isc->current_subdev->sd;
1602         bool fh_singular;
1603         int ret;
1604
1605         mutex_lock(&isc->lock);
1606
1607         fh_singular = v4l2_fh_is_singular_file(file);
1608
1609         ret = _vb2_fop_release(file, NULL);
1610
1611         if (fh_singular)
1612                 v4l2_subdev_call(sd, core, s_power, 0);
1613
1614         mutex_unlock(&isc->lock);
1615
1616         return ret;
1617 }
1618
1619 static const struct v4l2_file_operations isc_fops = {
1620         .owner          = THIS_MODULE,
1621         .open           = isc_open,
1622         .release        = isc_release,
1623         .unlocked_ioctl = video_ioctl2,
1624         .read           = vb2_fop_read,
1625         .mmap           = vb2_fop_mmap,
1626         .poll           = vb2_fop_poll,
1627 };
1628
1629 irqreturn_t isc_interrupt(int irq, void *dev_id)
1630 {
1631         struct isc_device *isc = (struct isc_device *)dev_id;
1632         struct regmap *regmap = isc->regmap;
1633         u32 isc_intsr, isc_intmask, pending;
1634         irqreturn_t ret = IRQ_NONE;
1635
1636         regmap_read(regmap, ISC_INTSR, &isc_intsr);
1637         regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1638
1639         pending = isc_intsr & isc_intmask;
1640
1641         if (likely(pending & ISC_INT_DDONE)) {
1642                 spin_lock(&isc->dma_queue_lock);
1643                 if (isc->cur_frm) {
1644                         struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1645                         struct vb2_buffer *vb = &vbuf->vb2_buf;
1646
1647                         vb->timestamp = ktime_get_ns();
1648                         vbuf->sequence = isc->sequence++;
1649                         vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1650                         isc->cur_frm = NULL;
1651                 }
1652
1653                 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1654                         isc->cur_frm = list_first_entry(&isc->dma_queue,
1655                                                      struct isc_buffer, list);
1656                         list_del(&isc->cur_frm->list);
1657
1658                         isc_start_dma(isc);
1659                 }
1660
1661                 if (isc->stop)
1662                         complete(&isc->comp);
1663
1664                 ret = IRQ_HANDLED;
1665                 spin_unlock(&isc->dma_queue_lock);
1666         }
1667
1668         if (pending & ISC_INT_HISDONE) {
1669                 schedule_work(&isc->awb_work);
1670                 ret = IRQ_HANDLED;
1671         }
1672
1673         return ret;
1674 }
1675
1676 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1677 {
1678         struct regmap *regmap = isc->regmap;
1679         struct isc_ctrls *ctrls = &isc->ctrls;
1680         u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1681         u32 *hist_entry = &ctrls->hist_entry[0];
1682         u32 i;
1683
1684         *min = 0;
1685         *max = HIST_ENTRIES;
1686
1687         regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1688                          hist_entry, HIST_ENTRIES);
1689
1690         *hist_count = 0;
1691         /*
1692          * we deliberately ignore the end of the histogram,
1693          * the most white pixels
1694          */
1695         for (i = 1; i < HIST_ENTRIES; i++) {
1696                 if (*hist_entry && !*min)
1697                         *min = i;
1698                 if (*hist_entry)
1699                         *max = i;
1700                 *hist_count += i * (*hist_entry++);
1701         }
1702
1703         if (!*min)
1704                 *min = 1;
1705 }
1706
1707 static void isc_wb_update(struct isc_ctrls *ctrls)
1708 {
1709         u32 *hist_count = &ctrls->hist_count[0];
1710         u32 c, offset[4];
1711         u64 avg = 0;
1712         /* We compute two gains, stretch gain and grey world gain */
1713         u32 s_gain[4], gw_gain[4];
1714
1715         /*
1716          * According to Grey World, we need to set gains for R/B to normalize
1717          * them towards the green channel.
1718          * Thus we want to keep Green as fixed and adjust only Red/Blue
1719          * Compute the average of the both green channels first
1720          */
1721         avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1722                 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1723         avg >>= 1;
1724
1725         /* Green histogram is null, nothing to do */
1726         if (!avg)
1727                 return;
1728
1729         for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1730                 /*
1731                  * the color offset is the minimum value of the histogram.
1732                  * we stretch this color to the full range by substracting
1733                  * this value from the color component.
1734                  */
1735                 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1736                 /*
1737                  * The offset is always at least 1. If the offset is 1, we do
1738                  * not need to adjust it, so our result must be zero.
1739                  * the offset is computed in a histogram on 9 bits (0..512)
1740                  * but the offset in register is based on
1741                  * 12 bits pipeline (0..4096).
1742                  * we need to shift with the 3 bits that the histogram is
1743                  * ignoring
1744                  */
1745                 ctrls->offset[c] = (offset[c] - 1) << 3;
1746
1747                 /*
1748                  * the offset is then taken and converted to 2's complements,
1749                  * and must be negative, as we subtract this value from the
1750                  * color components
1751                  */
1752                 ctrls->offset[c] = -ctrls->offset[c];
1753
1754                 /*
1755                  * the stretch gain is the total number of histogram bins
1756                  * divided by the actual range of color component (Max - Min)
1757                  * If we compute gain like this, the actual color component
1758                  * will be stretched to the full histogram.
1759                  * We need to shift 9 bits for precision, we have 9 bits for
1760                  * decimals
1761                  */
1762                 s_gain[c] = (HIST_ENTRIES << 9) /
1763                         (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1764                         ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1765
1766                 /*
1767                  * Now we have to compute the gain w.r.t. the average.
1768                  * Add/lose gain to the component towards the average.
1769                  * If it happens that the component is zero, use the
1770                  * fixed point value : 1.0 gain.
1771                  */
1772                 if (hist_count[c])
1773                         gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1774                 else
1775                         gw_gain[c] = 1 << 9;
1776
1777                 /* multiply both gains and adjust for decimals */
1778                 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1779                 ctrls->gain[c] >>= 9;
1780         }
1781 }
1782
1783 static void isc_awb_work(struct work_struct *w)
1784 {
1785         struct isc_device *isc =
1786                 container_of(w, struct isc_device, awb_work);
1787         struct regmap *regmap = isc->regmap;
1788         struct isc_ctrls *ctrls = &isc->ctrls;
1789         u32 hist_id = ctrls->hist_id;
1790         u32 baysel;
1791         unsigned long flags;
1792         u32 min, max;
1793         int ret;
1794
1795         /* streaming is not active anymore */
1796         if (isc->stop)
1797                 return;
1798
1799         if (ctrls->hist_stat != HIST_ENABLED)
1800                 return;
1801
1802         isc_hist_count(isc, &min, &max);
1803         ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1804         ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1805
1806         if (hist_id != ISC_HIS_CFG_MODE_B) {
1807                 hist_id++;
1808         } else {
1809                 isc_wb_update(ctrls);
1810                 hist_id = ISC_HIS_CFG_MODE_GR;
1811         }
1812
1813         ctrls->hist_id = hist_id;
1814         baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1815
1816         ret = pm_runtime_resume_and_get(isc->dev);
1817         if (ret < 0)
1818                 return;
1819
1820         /*
1821          * only update if we have all the required histograms and controls
1822          * if awb has been disabled, we need to reset registers as well.
1823          */
1824         if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1825                 /*
1826                  * It may happen that DMA Done IRQ will trigger while we are
1827                  * updating white balance registers here.
1828                  * In that case, only parts of the controls have been updated.
1829                  * We can avoid that by locking the section.
1830                  */
1831                 spin_lock_irqsave(&isc->awb_lock, flags);
1832                 isc_update_awb_ctrls(isc);
1833                 spin_unlock_irqrestore(&isc->awb_lock, flags);
1834
1835                 /*
1836                  * if we are doing just the one time white balance adjustment,
1837                  * we are basically done.
1838                  */
1839                 if (ctrls->awb == ISC_WB_ONETIME) {
1840                         v4l2_info(&isc->v4l2_dev,
1841                                   "Completed one time white-balance adjustment.\n");
1842                         /* update the v4l2 controls values */
1843                         isc_update_v4l2_ctrls(isc);
1844                         ctrls->awb = ISC_WB_NONE;
1845                 }
1846         }
1847         regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1848                      hist_id | baysel | ISC_HIS_CFG_RAR);
1849         isc_update_profile(isc);
1850         /* if awb has been disabled, we don't need to start another histogram */
1851         if (ctrls->awb)
1852                 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1853
1854         pm_runtime_put_sync(isc->dev);
1855 }
1856
1857 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1858 {
1859         struct isc_device *isc = container_of(ctrl->handler,
1860                                              struct isc_device, ctrls.handler);
1861         struct isc_ctrls *ctrls = &isc->ctrls;
1862
1863         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1864                 return 0;
1865
1866         switch (ctrl->id) {
1867         case V4L2_CID_BRIGHTNESS:
1868                 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1869                 break;
1870         case V4L2_CID_CONTRAST:
1871                 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1872                 break;
1873         case V4L2_CID_GAMMA:
1874                 ctrls->gamma_index = ctrl->val;
1875                 break;
1876         default:
1877                 return -EINVAL;
1878         }
1879
1880         return 0;
1881 }
1882
1883 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1884         .s_ctrl = isc_s_ctrl,
1885 };
1886
1887 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1888 {
1889         struct isc_device *isc = container_of(ctrl->handler,
1890                                              struct isc_device, ctrls.handler);
1891         struct isc_ctrls *ctrls = &isc->ctrls;
1892
1893         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1894                 return 0;
1895
1896         switch (ctrl->id) {
1897         case V4L2_CID_AUTO_WHITE_BALANCE:
1898                 if (ctrl->val == 1)
1899                         ctrls->awb = ISC_WB_AUTO;
1900                 else
1901                         ctrls->awb = ISC_WB_NONE;
1902
1903                 /* we did not configure ISC yet */
1904                 if (!isc->config.sd_format)
1905                         break;
1906
1907                 /* configure the controls with new values from v4l2 */
1908                 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1909                         ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1910                 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1911                         ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1912                 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1913                         ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1914                 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1915                         ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1916
1917                 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1918                         ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1919                 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1920                         ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1921                 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1922                         ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1923                 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1924                         ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1925
1926                 isc_update_awb_ctrls(isc);
1927
1928                 if (vb2_is_streaming(&isc->vb2_vidq)) {
1929                         /*
1930                          * If we are streaming, we can update profile to
1931                          * have the new settings in place.
1932                          */
1933                         isc_update_profile(isc);
1934                 } else {
1935                         /*
1936                          * The auto cluster will activate automatically this
1937                          * control. This has to be deactivated when not
1938                          * streaming.
1939                          */
1940                         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1941                 }
1942
1943                 /* if we have autowhitebalance on, start histogram procedure */
1944                 if (ctrls->awb == ISC_WB_AUTO &&
1945                     vb2_is_streaming(&isc->vb2_vidq) &&
1946                     ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1947                         isc_set_histogram(isc, true);
1948
1949                 /*
1950                  * for one time whitebalance adjustment, check the button,
1951                  * if it's pressed, perform the one time operation.
1952                  */
1953                 if (ctrls->awb == ISC_WB_NONE &&
1954                     ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1955                     !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1956                     V4L2_CTRL_FLAG_INACTIVE)) {
1957                         ctrls->awb = ISC_WB_ONETIME;
1958                         isc_set_histogram(isc, true);
1959                         v4l2_dbg(1, debug, &isc->v4l2_dev,
1960                                  "One time white-balance started.\n");
1961                 }
1962                 return 0;
1963         }
1964         return 0;
1965 }
1966
1967 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1968 {
1969         struct isc_device *isc = container_of(ctrl->handler,
1970                                              struct isc_device, ctrls.handler);
1971         struct isc_ctrls *ctrls = &isc->ctrls;
1972
1973         switch (ctrl->id) {
1974         /* being a cluster, this id will be called for every control */
1975         case V4L2_CID_AUTO_WHITE_BALANCE:
1976                 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1977                                         ctrls->gain[ISC_HIS_CFG_MODE_R];
1978                 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1979                                         ctrls->gain[ISC_HIS_CFG_MODE_B];
1980                 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1981                                         ctrls->gain[ISC_HIS_CFG_MODE_GR];
1982                 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1983                                         ctrls->gain[ISC_HIS_CFG_MODE_GB];
1984
1985                 ctrl->cluster[ISC_CTRL_R_OFF]->val =
1986                         ctrls->offset[ISC_HIS_CFG_MODE_R];
1987                 ctrl->cluster[ISC_CTRL_B_OFF]->val =
1988                         ctrls->offset[ISC_HIS_CFG_MODE_B];
1989                 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1990                         ctrls->offset[ISC_HIS_CFG_MODE_GR];
1991                 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1992                         ctrls->offset[ISC_HIS_CFG_MODE_GB];
1993                 break;
1994         }
1995         return 0;
1996 }
1997
1998 static const struct v4l2_ctrl_ops isc_awb_ops = {
1999         .s_ctrl = isc_s_awb_ctrl,
2000         .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
2001 };
2002
2003 #define ISC_CTRL_OFF(_name, _id, _name_str) \
2004         static const struct v4l2_ctrl_config _name = { \
2005                 .ops = &isc_awb_ops, \
2006                 .id = _id, \
2007                 .name = _name_str, \
2008                 .type = V4L2_CTRL_TYPE_INTEGER, \
2009                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2010                 .min = -4095, \
2011                 .max = 4095, \
2012                 .step = 1, \
2013                 .def = 0, \
2014         }
2015
2016 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
2017 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
2018 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
2019 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
2020
2021 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
2022         static const struct v4l2_ctrl_config _name = { \
2023                 .ops = &isc_awb_ops, \
2024                 .id = _id, \
2025                 .name = _name_str, \
2026                 .type = V4L2_CTRL_TYPE_INTEGER, \
2027                 .flags = V4L2_CTRL_FLAG_SLIDER, \
2028                 .min = 0, \
2029                 .max = 8191, \
2030                 .step = 1, \
2031                 .def = 512, \
2032         }
2033
2034 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
2035 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
2036 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
2037 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
2038
2039 static int isc_ctrl_init(struct isc_device *isc)
2040 {
2041         const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
2042         struct isc_ctrls *ctrls = &isc->ctrls;
2043         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
2044         int ret;
2045
2046         ctrls->hist_stat = HIST_INIT;
2047         isc_reset_awb_ctrls(isc);
2048
2049         ret = v4l2_ctrl_handler_init(hdl, 13);
2050         if (ret < 0)
2051                 return ret;
2052
2053         ctrls->brightness = 0;
2054         ctrls->contrast = 256;
2055
2056         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
2057         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
2058         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
2059                           isc->gamma_max);
2060         isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2061                                           V4L2_CID_AUTO_WHITE_BALANCE,
2062                                           0, 1, 1, 1);
2063
2064         /* do_white_balance is a button, so min,max,step,default are ignored */
2065         isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
2066                                             V4L2_CID_DO_WHITE_BALANCE,
2067                                             0, 0, 0, 0);
2068
2069         if (!isc->do_wb_ctrl) {
2070                 ret = hdl->error;
2071                 v4l2_ctrl_handler_free(hdl);
2072                 return ret;
2073         }
2074
2075         v4l2_ctrl_activate(isc->do_wb_ctrl, false);
2076
2077         isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
2078         isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
2079         isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
2080         isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
2081         isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
2082         isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
2083         isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
2084         isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
2085
2086         /*
2087          * The cluster is in auto mode with autowhitebalance enabled
2088          * and manual mode otherwise.
2089          */
2090         v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
2091
2092         v4l2_ctrl_handler_setup(hdl);
2093
2094         return 0;
2095 }
2096
2097 static int isc_async_bound(struct v4l2_async_notifier *notifier,
2098                             struct v4l2_subdev *subdev,
2099                             struct v4l2_async_subdev *asd)
2100 {
2101         struct isc_device *isc = container_of(notifier->v4l2_dev,
2102                                               struct isc_device, v4l2_dev);
2103         struct isc_subdev_entity *subdev_entity =
2104                 container_of(notifier, struct isc_subdev_entity, notifier);
2105
2106         if (video_is_registered(&isc->video_dev)) {
2107                 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
2108                 return -EBUSY;
2109         }
2110
2111         subdev_entity->sd = subdev;
2112
2113         return 0;
2114 }
2115
2116 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
2117                               struct v4l2_subdev *subdev,
2118                               struct v4l2_async_subdev *asd)
2119 {
2120         struct isc_device *isc = container_of(notifier->v4l2_dev,
2121                                               struct isc_device, v4l2_dev);
2122         cancel_work_sync(&isc->awb_work);
2123         video_unregister_device(&isc->video_dev);
2124         v4l2_ctrl_handler_free(&isc->ctrls.handler);
2125 }
2126
2127 static struct isc_format *find_format_by_code(unsigned int code, int *index)
2128 {
2129         struct isc_format *fmt = &formats_list[0];
2130         unsigned int i;
2131
2132         for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
2133                 if (fmt->mbus_code == code) {
2134                         *index = i;
2135                         return fmt;
2136                 }
2137
2138                 fmt++;
2139         }
2140
2141         return NULL;
2142 }
2143
2144 static int isc_formats_init(struct isc_device *isc)
2145 {
2146         struct isc_format *fmt;
2147         struct v4l2_subdev *subdev = isc->current_subdev->sd;
2148         unsigned int num_fmts, i, j;
2149         u32 list_size = ARRAY_SIZE(formats_list);
2150         struct v4l2_subdev_mbus_code_enum mbus_code = {
2151                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2152         };
2153
2154         num_fmts = 0;
2155         while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
2156                NULL, &mbus_code)) {
2157                 mbus_code.index++;
2158
2159                 fmt = find_format_by_code(mbus_code.code, &i);
2160                 if (!fmt) {
2161                         v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
2162                                   mbus_code.code);
2163                         continue;
2164                 }
2165
2166                 fmt->sd_support = true;
2167                 num_fmts++;
2168         }
2169
2170         if (!num_fmts)
2171                 return -ENXIO;
2172
2173         isc->num_user_formats = num_fmts;
2174         isc->user_formats = devm_kcalloc(isc->dev,
2175                                          num_fmts, sizeof(*isc->user_formats),
2176                                          GFP_KERNEL);
2177         if (!isc->user_formats)
2178                 return -ENOMEM;
2179
2180         fmt = &formats_list[0];
2181         for (i = 0, j = 0; i < list_size; i++) {
2182                 if (fmt->sd_support)
2183                         isc->user_formats[j++] = fmt;
2184                 fmt++;
2185         }
2186
2187         return 0;
2188 }
2189
2190 static int isc_set_default_fmt(struct isc_device *isc)
2191 {
2192         struct v4l2_format f = {
2193                 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
2194                 .fmt.pix = {
2195                         .width          = VGA_WIDTH,
2196                         .height         = VGA_HEIGHT,
2197                         .field          = V4L2_FIELD_NONE,
2198                         .pixelformat    = isc->user_formats[0]->fourcc,
2199                 },
2200         };
2201         int ret;
2202
2203         ret = isc_try_fmt(isc, &f, NULL);
2204         if (ret)
2205                 return ret;
2206
2207         isc->fmt = f;
2208         return 0;
2209 }
2210
2211 static int isc_async_complete(struct v4l2_async_notifier *notifier)
2212 {
2213         struct isc_device *isc = container_of(notifier->v4l2_dev,
2214                                               struct isc_device, v4l2_dev);
2215         struct video_device *vdev = &isc->video_dev;
2216         struct vb2_queue *q = &isc->vb2_vidq;
2217         int ret = 0;
2218
2219         INIT_WORK(&isc->awb_work, isc_awb_work);
2220
2221         ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
2222         if (ret < 0) {
2223                 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
2224                 return ret;
2225         }
2226
2227         isc->current_subdev = container_of(notifier,
2228                                            struct isc_subdev_entity, notifier);
2229         mutex_init(&isc->lock);
2230         init_completion(&isc->comp);
2231
2232         /* Initialize videobuf2 queue */
2233         q->type                 = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2234         q->io_modes             = VB2_MMAP | VB2_DMABUF | VB2_READ;
2235         q->drv_priv             = isc;
2236         q->buf_struct_size      = sizeof(struct isc_buffer);
2237         q->ops                  = &isc_vb2_ops;
2238         q->mem_ops              = &vb2_dma_contig_memops;
2239         q->timestamp_flags      = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2240         q->lock                 = &isc->lock;
2241         q->min_buffers_needed   = 1;
2242         q->dev                  = isc->dev;
2243
2244         ret = vb2_queue_init(q);
2245         if (ret < 0) {
2246                 v4l2_err(&isc->v4l2_dev,
2247                          "vb2_queue_init() failed: %d\n", ret);
2248                 goto isc_async_complete_err;
2249         }
2250
2251         /* Init video dma queues */
2252         INIT_LIST_HEAD(&isc->dma_queue);
2253         spin_lock_init(&isc->dma_queue_lock);
2254         spin_lock_init(&isc->awb_lock);
2255
2256         ret = isc_formats_init(isc);
2257         if (ret < 0) {
2258                 v4l2_err(&isc->v4l2_dev,
2259                          "Init format failed: %d\n", ret);
2260                 goto isc_async_complete_err;
2261         }
2262
2263         ret = isc_set_default_fmt(isc);
2264         if (ret) {
2265                 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
2266                 goto isc_async_complete_err;
2267         }
2268
2269         ret = isc_ctrl_init(isc);
2270         if (ret) {
2271                 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
2272                 goto isc_async_complete_err;
2273         }
2274
2275         /* Register video device */
2276         strscpy(vdev->name, "microchip-isc", sizeof(vdev->name));
2277         vdev->release           = video_device_release_empty;
2278         vdev->fops              = &isc_fops;
2279         vdev->ioctl_ops         = &isc_ioctl_ops;
2280         vdev->v4l2_dev          = &isc->v4l2_dev;
2281         vdev->vfl_dir           = VFL_DIR_RX;
2282         vdev->queue             = q;
2283         vdev->lock              = &isc->lock;
2284         vdev->ctrl_handler      = &isc->ctrls.handler;
2285         vdev->device_caps       = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
2286         video_set_drvdata(vdev, isc);
2287
2288         ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2289         if (ret < 0) {
2290                 v4l2_err(&isc->v4l2_dev,
2291                          "video_register_device failed: %d\n", ret);
2292                 goto isc_async_complete_err;
2293         }
2294
2295         return 0;
2296
2297 isc_async_complete_err:
2298         mutex_destroy(&isc->lock);
2299         return ret;
2300 }
2301
2302 const struct v4l2_async_notifier_operations isc_async_ops = {
2303         .bound = isc_async_bound,
2304         .unbind = isc_async_unbind,
2305         .complete = isc_async_complete,
2306 };
2307
2308 void isc_subdev_cleanup(struct isc_device *isc)
2309 {
2310         struct isc_subdev_entity *subdev_entity;
2311
2312         list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
2313                 v4l2_async_notifier_unregister(&subdev_entity->notifier);
2314                 v4l2_async_notifier_cleanup(&subdev_entity->notifier);
2315         }
2316
2317         INIT_LIST_HEAD(&isc->subdev_entities);
2318 }
2319
2320 int isc_pipeline_init(struct isc_device *isc)
2321 {
2322         struct device *dev = isc->dev;
2323         struct regmap *regmap = isc->regmap;
2324         struct regmap_field *regs;
2325         unsigned int i;
2326
2327         /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
2328         const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
2329                 REG_FIELD(ISC_WB_CTRL, 0, 0),
2330                 REG_FIELD(ISC_CFA_CTRL, 0, 0),
2331                 REG_FIELD(ISC_CC_CTRL, 0, 0),
2332                 REG_FIELD(ISC_GAM_CTRL, 0, 0),
2333                 REG_FIELD(ISC_GAM_CTRL, 1, 1),
2334                 REG_FIELD(ISC_GAM_CTRL, 2, 2),
2335                 REG_FIELD(ISC_GAM_CTRL, 3, 3),
2336                 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
2337                 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
2338                 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
2339                 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
2340         };
2341
2342         for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
2343                 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
2344                 if (IS_ERR(regs))
2345                         return PTR_ERR(regs);
2346
2347                 isc->pipeline[i] =  regs;
2348         }
2349
2350         return 0;
2351 }
2352
2353 /* regmap configuration */
2354 #define ATMEL_ISC_REG_MAX    0xbfc
2355 const struct regmap_config isc_regmap_config = {
2356         .reg_bits       = 32,
2357         .reg_stride     = 4,
2358         .val_bits       = 32,
2359         .max_register   = ATMEL_ISC_REG_MAX,
2360 };
2361