drivers/media/i2c/tc358743.c

   1 /*
   2  * tc358743 - Toshiba HDMI to CSI-2 bridge
   3  *
   4  * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
   5  * reserved.
   6  *
   7  * This program is free software; you may redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  12  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  13  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  15  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  16  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  17  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  18  * SOFTWARE.
  19  *
  20  */
  21
  22 /*
  23  * References (c = chapter, p = page):
  24  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
  25  * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/slab.h>
  31 #include <linux/i2c.h>
  32 #include <linux/clk.h>
  33 #include <linux/delay.h>
  34 #include <linux/gpio/consumer.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/timer.h>
  37 #include <linux/of_graph.h>
  38 #include <linux/videodev2.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/v4l2-dv-timings.h>
  41 #include <linux/hdmi.h>
  42 #include <media/cec.h>
  43 #include <media/v4l2-dv-timings.h>
  44 #include <media/v4l2-device.h>
  45 #include <media/v4l2-ctrls.h>
  46 #include <media/v4l2-event.h>
  47 #include <media/v4l2-fwnode.h>
  48 #include <media/i2c/tc358743.h>
  49
  50 #include "tc358743_regs.h"
  51
  52 static int debug;
  53 module_param(debug, int, 0644);
  54 MODULE_PARM_DESC(debug, "debug level (0-3)");
  55
  56 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
  57 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
  58 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
  59 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
  60 MODULE_LICENSE("GPL");
  61
  62 #define EDID_NUM_BLOCKS_MAX 8
  63 #define EDID_BLOCK_SIZE 128
  64
  65 #define I2C_MAX_XFER_SIZE  (EDID_BLOCK_SIZE + 2)
  66
  67 #define POLL_INTERVAL_CEC_MS    10
  68 #define POLL_INTERVAL_MS        1000
  69
  70 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
  71         .type = V4L2_DV_BT_656_1120,
  72         /* keep this initialization for compatibility with GCC < 4.4.6 */
  73         .reserved = { 0 },
  74         /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
  75         V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
  76                         V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  77                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
  78                         V4L2_DV_BT_CAP_PROGRESSIVE |
  79                         V4L2_DV_BT_CAP_REDUCED_BLANKING |
  80                         V4L2_DV_BT_CAP_CUSTOM)
  81 };
  82
  83 struct tc358743_state {
  84         struct tc358743_platform_data pdata;
  85         struct v4l2_fwnode_bus_mipi_csi2 bus;
  86         struct v4l2_subdev sd;
  87         struct media_pad pad;
  88         struct v4l2_ctrl_handler hdl;
  89         struct i2c_client *i2c_client;
  90         /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
  91         struct mutex confctl_mutex;
  92
  93         /* controls */
  94         struct v4l2_ctrl *detect_tx_5v_ctrl;
  95         struct v4l2_ctrl *audio_sampling_rate_ctrl;
  96         struct v4l2_ctrl *audio_present_ctrl;
  97
  98         struct delayed_work delayed_work_enable_hotplug;
  99
 100         struct timer_list timer;
 101         struct work_struct work_i2c_poll;
 102
 103         /* edid  */
 104         u8 edid_blocks_written;
 105
 106         struct v4l2_dv_timings timings;
 107         u32 mbus_fmt_code;
 108         u8 csi_lanes_in_use;
 109
 110         struct gpio_desc *reset_gpio;
 111
 112         struct cec_adapter *cec_adap;
 113 };
 114
 115 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
 116                 bool cable_connected);
 117 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
 118
 119 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
 120 {
 121         return container_of(sd, struct tc358743_state, sd);
 122 }
 123
 124 /* --------------- I2C --------------- */
 125
 126 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 127 {
 128         struct tc358743_state *state = to_state(sd);
 129         struct i2c_client *client = state->i2c_client;
 130         int err;
 131         u8 buf[2] = { reg >> 8, reg & 0xff };
 132         struct i2c_msg msgs[] = {
 133                 {
 134                         .addr = client->addr,
 135                         .flags = 0,
 136                         .len = 2,
 137                         .buf = buf,
 138                 },
 139                 {
 140                         .addr = client->addr,
 141                         .flags = I2C_M_RD,
 142                         .len = n,
 143                         .buf = values,
 144                 },
 145         };
 146
 147         err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 148         if (err != ARRAY_SIZE(msgs)) {
 149                 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
 150                                 __func__, reg, client->addr);
 151         }
 152 }
 153
 154 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 155 {
 156         struct tc358743_state *state = to_state(sd);
 157         struct i2c_client *client = state->i2c_client;
 158         int err, i;
 159         struct i2c_msg msg;
 160         u8 data[I2C_MAX_XFER_SIZE];
 161
 162         if ((2 + n) > I2C_MAX_XFER_SIZE) {
 163                 n = I2C_MAX_XFER_SIZE - 2;
 164                 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
 165                           reg, 2 + n);
 166         }
 167
 168         msg.addr = client->addr;
 169         msg.buf = data;
 170         msg.len = 2 + n;
 171         msg.flags = 0;
 172
 173         data[0] = reg >> 8;
 174         data[1] = reg & 0xff;
 175
 176         for (i = 0; i < n; i++)
 177                 data[2 + i] = values[i];
 178
 179         err = i2c_transfer(client->adapter, &msg, 1);
 180         if (err != 1) {
 181                 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
 182                                 __func__, reg, client->addr);
 183                 return;
 184         }
 185
 186         if (debug < 3)
 187                 return;
 188
 189         switch (n) {
 190         case 1:
 191                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
 192                                 reg, data[2]);
 193                 break;
 194         case 2:
 195                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
 196                                 reg, data[3], data[2]);
 197                 break;
 198         case 4:
 199                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
 200                                 reg, data[5], data[4], data[3], data[2]);
 201                 break;
 202         default:
 203                 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
 204                                 n, reg);
 205         }
 206 }
 207
 208 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
 209 {
 210         __le32 val = 0;
 211
 212         i2c_rd(sd, reg, (u8 __force *)&val, n);
 213
 214         return le32_to_cpu(val);
 215 }
 216
 217 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
 218 {
 219         __le32 raw = cpu_to_le32(val);
 220
 221         i2c_wr(sd, reg, (u8 __force *)&raw, n);
 222 }
 223
 224 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
 225 {
 226         return i2c_rdreg(sd, reg, 1);
 227 }
 228
 229 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
 230 {
 231         i2c_wrreg(sd, reg, val, 1);
 232 }
 233
 234 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
 235                 u8 mask, u8 val)
 236 {
 237         i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
 238 }
 239
 240 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
 241 {
 242         return i2c_rdreg(sd, reg, 2);
 243 }
 244
 245 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
 246 {
 247         i2c_wrreg(sd, reg, val, 2);
 248 }
 249
 250 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
 251 {
 252         i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
 253 }
 254
 255 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
 256 {
 257         return i2c_rdreg(sd, reg, 4);
 258 }
 259
 260 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
 261 {
 262         i2c_wrreg(sd, reg, val, 4);
 263 }
 264
 265 /* --------------- STATUS --------------- */
 266
 267 static inline bool is_hdmi(struct v4l2_subdev *sd)
 268 {
 269         return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
 270 }
 271
 272 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
 273 {
 274         return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
 275 }
 276
 277 static inline bool no_signal(struct v4l2_subdev *sd)
 278 {
 279         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
 280 }
 281
 282 static inline bool no_sync(struct v4l2_subdev *sd)
 283 {
 284         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
 285 }
 286
 287 static inline bool audio_present(struct v4l2_subdev *sd)
 288 {
 289         return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
 290 }
 291
 292 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
 293 {
 294         static const int code_to_rate[] = {
 295                 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
 296                 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
 297         };
 298
 299         /* Register FS_SET is not cleared when the cable is disconnected */
 300         if (no_signal(sd))
 301                 return 0;
 302
 303         return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
 304 }
 305
 306 /* --------------- TIMINGS --------------- */
 307
 308 static inline unsigned fps(const struct v4l2_bt_timings *t)
 309 {
 310         if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
 311                 return 0;
 312
 313         return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
 314                         V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
 315 }
 316
 317 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
 318                                      struct v4l2_dv_timings *timings)
 319 {
 320         struct v4l2_bt_timings *bt = &timings->bt;
 321         unsigned width, height, frame_width, frame_height, frame_interval, fps;
 322
 323         memset(timings, 0, sizeof(struct v4l2_dv_timings));
 324
 325         if (no_signal(sd)) {
 326                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
 327                 return -ENOLINK;
 328         }
 329         if (no_sync(sd)) {
 330                 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
 331                 return -ENOLCK;
 332         }
 333
 334         timings->type = V4L2_DV_BT_656_1120;
 335         bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
 336                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
 337
 338         width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
 339                 i2c_rd8(sd, DE_WIDTH_H_LO);
 340         height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
 341                 i2c_rd8(sd, DE_WIDTH_V_LO);
 342         frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
 343                 i2c_rd8(sd, H_SIZE_LO);
 344         frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
 345                 i2c_rd8(sd, V_SIZE_LO)) / 2;
 346         /* frame interval in milliseconds * 10
 347          * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
 348         frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
 349                 i2c_rd8(sd, FV_CNT_LO);
 350         fps = (frame_interval > 0) ?
 351                 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
 352
 353         bt->width = width;
 354         bt->height = height;
 355         bt->vsync = frame_height - height;
 356         bt->hsync = frame_width - width;
 357         bt->pixelclock = frame_width * frame_height * fps;
 358         if (bt->interlaced == V4L2_DV_INTERLACED) {
 359                 bt->height *= 2;
 360                 bt->il_vsync = bt->vsync + 1;
 361                 bt->pixelclock /= 2;
 362         }
 363
 364         return 0;
 365 }
 366
 367 /* --------------- HOTPLUG / HDCP / EDID --------------- */
 368
 369 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
 370 {
 371         struct delayed_work *dwork = to_delayed_work(work);
 372         struct tc358743_state *state = container_of(dwork,
 373                         struct tc358743_state, delayed_work_enable_hotplug);
 374         struct v4l2_subdev *sd = &state->sd;
 375
 376         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 377
 378         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
 379 }
 380
 381 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
 382 {
 383         v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
 384                                 "enable" : "disable");
 385
 386         if (enable) {
 387                 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
 388
 389                 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
 390
 391                 i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
 392                                 MASK_AUTH_UNAUTH_SEL_16_FRAMES |
 393                                 MASK_AUTH_UNAUTH_AUTO);
 394
 395                 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
 396                                 SET_AUTO_P3_RESET_FRAMES(0x0f));
 397         } else {
 398                 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
 399                                 MASK_MANUAL_AUTHENTICATION);
 400         }
 401 }
 402
 403 static void tc358743_disable_edid(struct v4l2_subdev *sd)
 404 {
 405         struct tc358743_state *state = to_state(sd);
 406
 407         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 408
 409         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
 410
 411         /* DDC access to EDID is also disabled when hotplug is disabled. See
 412          * register DDC_CTL */
 413         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
 414 }
 415
 416 static void tc358743_enable_edid(struct v4l2_subdev *sd)
 417 {
 418         struct tc358743_state *state = to_state(sd);
 419
 420         if (state->edid_blocks_written == 0) {
 421                 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
 422                 tc358743_s_ctrl_detect_tx_5v(sd);
 423                 return;
 424         }
 425
 426         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 427
 428         /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
 429          * hotplug is enabled. See register DDC_CTL */
 430         schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
 431
 432         tc358743_enable_interrupts(sd, true);
 433         tc358743_s_ctrl_detect_tx_5v(sd);
 434 }
 435
 436 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
 437 {
 438         int i;
 439
 440         for (i = 0; i < 5; i++)
 441                 i2c_wr8(sd, BKSV + i, 0);
 442 }
 443
 444 /* --------------- AVI infoframe --------------- */
 445
 446 static void print_avi_infoframe(struct v4l2_subdev *sd)
 447 {
 448         struct i2c_client *client = v4l2_get_subdevdata(sd);
 449         struct device *dev = &client->dev;
 450         union hdmi_infoframe frame;
 451         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 452
 453         if (!is_hdmi(sd)) {
 454                 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
 455                 return;
 456         }
 457
 458         i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
 459
 460         if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
 461                 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
 462                 return;
 463         }
 464
 465         hdmi_infoframe_log(KERN_INFO, dev, &frame);
 466 }
 467
 468 /* --------------- CTRLS --------------- */
 469
 470 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
 471 {
 472         struct tc358743_state *state = to_state(sd);
 473
 474         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 475                         tx_5v_power_present(sd));
 476 }
 477
 478 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
 479 {
 480         struct tc358743_state *state = to_state(sd);
 481
 482         return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
 483                         get_audio_sampling_rate(sd));
 484 }
 485
 486 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
 487 {
 488         struct tc358743_state *state = to_state(sd);
 489
 490         return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
 491                         audio_present(sd));
 492 }
 493
 494 static int tc358743_update_controls(struct v4l2_subdev *sd)
 495 {
 496         int ret = 0;
 497
 498         ret |= tc358743_s_ctrl_detect_tx_5v(sd);
 499         ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
 500         ret |= tc358743_s_ctrl_audio_present(sd);
 501
 502         return ret;
 503 }
 504
 505 /* --------------- INIT --------------- */
 506
 507 static void tc358743_reset_phy(struct v4l2_subdev *sd)
 508 {
 509         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 510
 511         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
 512         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
 513 }
 514
 515 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
 516 {
 517         u16 sysctl = i2c_rd16(sd, SYSCTL);
 518
 519         i2c_wr16(sd, SYSCTL, sysctl | mask);
 520         i2c_wr16(sd, SYSCTL, sysctl & ~mask);
 521 }
 522
 523 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
 524 {
 525         i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
 526                         enable ? MASK_SLEEP : 0);
 527 }
 528
 529 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
 530 {
 531         struct tc358743_state *state = to_state(sd);
 532
 533         v4l2_dbg(3, debug, sd, "%s: %sable\n",
 534                         __func__, enable ? "en" : "dis");
 535
 536         if (enable) {
 537                 /* It is critical for CSI receiver to see lane transition
 538                  * LP11->HS. Set to non-continuous mode to enable clock lane
 539                  * LP11 state. */
 540                 i2c_wr32(sd, TXOPTIONCNTRL, 0);
 541                 /* Set to continuous mode to trigger LP11->HS transition */
 542                 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
 543                 /* Unmute video */
 544                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
 545         } else {
 546                 /* Mute video so that all data lanes go to LSP11 state.
 547                  * No data is output to CSI Tx block. */
 548                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
 549         }
 550
 551         mutex_lock(&state->confctl_mutex);
 552         i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
 553                         enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
 554         mutex_unlock(&state->confctl_mutex);
 555 }
 556
 557 static void tc358743_set_pll(struct v4l2_subdev *sd)
 558 {
 559         struct tc358743_state *state = to_state(sd);
 560         struct tc358743_platform_data *pdata = &state->pdata;
 561         u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
 562         u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
 563         u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
 564                 SET_PLL_FBD(pdata->pll_fbd);
 565         u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 566
 567         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 568
 569         /* Only rewrite when needed (new value or disabled), since rewriting
 570          * triggers another format change event. */
 571         if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
 572                 u16 pll_frs;
 573
 574                 if (hsck > 500000000)
 575                         pll_frs = 0x0;
 576                 else if (hsck > 250000000)
 577                         pll_frs = 0x1;
 578                 else if (hsck > 125000000)
 579                         pll_frs = 0x2;
 580                 else
 581                         pll_frs = 0x3;
 582
 583                 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
 584                 tc358743_sleep_mode(sd, true);
 585                 i2c_wr16(sd, PLLCTL0, pllctl0_new);
 586                 i2c_wr16_and_or(sd, PLLCTL1,
 587                                 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
 588                                 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
 589                                  MASK_PLL_EN));
 590                 udelay(10); /* REF_02, Sheet "Source HDMI" */
 591                 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
 592                 tc358743_sleep_mode(sd, false);
 593         }
 594 }
 595
 596 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
 597 {
 598         struct tc358743_state *state = to_state(sd);
 599         struct tc358743_platform_data *pdata = &state->pdata;
 600         u32 sys_freq;
 601         u32 lockdet_ref;
 602         u32 cec_freq;
 603         u16 fh_min;
 604         u16 fh_max;
 605
 606         BUG_ON(!(pdata->refclk_hz == 26000000 ||
 607                  pdata->refclk_hz == 27000000 ||
 608                  pdata->refclk_hz == 42000000));
 609
 610         sys_freq = pdata->refclk_hz / 10000;
 611         i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
 612         i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
 613
 614         i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
 615                         (pdata->refclk_hz == 42000000) ?
 616                         MASK_PHY_SYSCLK_IND : 0x0);
 617
 618         fh_min = pdata->refclk_hz / 100000;
 619         i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
 620         i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
 621
 622         fh_max = (fh_min * 66) / 10;
 623         i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
 624         i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
 625
 626         lockdet_ref = pdata->refclk_hz / 100;
 627         i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
 628         i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
 629         i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
 630
 631         i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
 632                         (pdata->refclk_hz == 27000000) ?
 633                         MASK_NCO_F0_MOD_27MHZ : 0x0);
 634
 635         /*
 636          * Trial and error suggests that the default register value
 637          * of 656 is for a 42 MHz reference clock. Use that to derive
 638          * a new value based on the actual reference clock.
 639          */
 640         cec_freq = (656 * sys_freq) / 4200;
 641         i2c_wr16(sd, CECHCLK, cec_freq);
 642         i2c_wr16(sd, CECLCLK, cec_freq);
 643 }
 644
 645 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
 646 {
 647         struct tc358743_state *state = to_state(sd);
 648
 649         switch (state->mbus_fmt_code) {
 650         case MEDIA_BUS_FMT_UYVY8_1X16:
 651                 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
 652                 i2c_wr8_and_or(sd, VOUT_SET2,
 653                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 654                                 MASK_SEL422 | MASK_VOUT_422FIL_100);
 655                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 656                                 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
 657                 mutex_lock(&state->confctl_mutex);
 658                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
 659                                 MASK_YCBCRFMT_422_8_BIT);
 660                 mutex_unlock(&state->confctl_mutex);
 661                 break;
 662         case MEDIA_BUS_FMT_RGB888_1X24:
 663                 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
 664                 i2c_wr8_and_or(sd, VOUT_SET2,
 665                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 666                                 0x00);
 667                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 668                                 MASK_VOUT_COLOR_RGB_FULL);
 669                 mutex_lock(&state->confctl_mutex);
 670                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
 671                 mutex_unlock(&state->confctl_mutex);
 672                 break;
 673         default:
 674                 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
 675                                 __func__, state->mbus_fmt_code);
 676         }
 677 }
 678
 679 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
 680 {
 681         struct tc358743_state *state = to_state(sd);
 682         struct v4l2_bt_timings *bt = &state->timings.bt;
 683         struct tc358743_platform_data *pdata = &state->pdata;
 684         u32 bits_pr_pixel =
 685                 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ?  16 : 24;
 686         u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
 687         u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 688
 689         return DIV_ROUND_UP(bps, bps_pr_lane);
 690 }
 691
 692 static void tc358743_set_csi(struct v4l2_subdev *sd)
 693 {
 694         struct tc358743_state *state = to_state(sd);
 695         struct tc358743_platform_data *pdata = &state->pdata;
 696         unsigned lanes = tc358743_num_csi_lanes_needed(sd);
 697
 698         v4l2_dbg(3, debug, sd, "%s:\n", __func__);
 699
 700         state->csi_lanes_in_use = lanes;
 701
 702         tc358743_reset(sd, MASK_CTXRST);
 703
 704         if (lanes < 1)
 705                 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
 706         if (lanes < 1)
 707                 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
 708         if (lanes < 2)
 709                 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
 710         if (lanes < 3)
 711                 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
 712         if (lanes < 4)
 713                 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
 714
 715         i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
 716         i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
 717         i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
 718         i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
 719         i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
 720         i2c_wr32(sd, TWAKEUP, pdata->twakeup);
 721         i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
 722         i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
 723         i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
 724
 725         i2c_wr32(sd, HSTXVREGEN,
 726                         ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
 727                         ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
 728                         ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
 729                         ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
 730                         ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
 731
 732         i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
 733                  V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
 734         i2c_wr32(sd, STARTCNTRL, MASK_START);
 735         i2c_wr32(sd, CSI_START, MASK_STRT);
 736
 737         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 738                         MASK_ADDRESS_CSI_CONTROL |
 739                         MASK_CSI_MODE |
 740                         MASK_TXHSMD |
 741                         ((lanes == 4) ? MASK_NOL_4 :
 742                          (lanes == 3) ? MASK_NOL_3 :
 743                          (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
 744
 745         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 746                         MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
 747                         MASK_WCER | MASK_INER);
 748
 749         i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
 750                         MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
 751
 752         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 753                         MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
 754 }
 755
 756 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
 757 {
 758         struct tc358743_state *state = to_state(sd);
 759         struct tc358743_platform_data *pdata = &state->pdata;
 760
 761         /* Default settings from REF_02, sheet "Source HDMI"
 762          * and custom settings as platform data */
 763         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
 764         i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
 765                         SET_FREQ_RANGE_MODE_CYCLES(1));
 766         i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
 767                         (pdata->hdmi_phy_auto_reset_tmds_detected ?
 768                          MASK_PHY_AUTO_RST2 : 0) |
 769                         (pdata->hdmi_phy_auto_reset_tmds_in_range ?
 770                          MASK_PHY_AUTO_RST3 : 0) |
 771                         (pdata->hdmi_phy_auto_reset_tmds_valid ?
 772                          MASK_PHY_AUTO_RST4 : 0));
 773         i2c_wr8(sd, PHY_BIAS, 0x40);
 774         i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
 775         i2c_wr8(sd, AVM_CTL, 45);
 776         i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
 777                         pdata->hdmi_detection_delay << 4);
 778         i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
 779                         (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
 780                          MASK_H_PI_RST : 0) |
 781                         (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
 782                          MASK_V_PI_RST : 0));
 783         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
 784 }
 785
 786 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
 787 {
 788         struct tc358743_state *state = to_state(sd);
 789
 790         /* Default settings from REF_02, sheet "Source HDMI" */
 791         i2c_wr8(sd, FORCE_MUTE, 0x00);
 792         i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
 793                         MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
 794                         MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
 795         i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
 796         i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
 797         i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
 798         i2c_wr8(sd, FS_MUTE, 0x00);
 799         i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
 800         i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
 801         i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
 802         i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
 803         i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
 804         i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
 805
 806         mutex_lock(&state->confctl_mutex);
 807         i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
 808                         MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
 809         mutex_unlock(&state->confctl_mutex);
 810 }
 811
 812 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
 813 {
 814         /* Default settings from REF_02, sheet "Source HDMI" */
 815         i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
 816                         MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
 817                         MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
 818                         MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
 819         i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
 820         i2c_wr8(sd, NO_PKT_CLR, 0x53);
 821         i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
 822         i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
 823         i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
 824 }
 825
 826 static void tc358743_initial_setup(struct v4l2_subdev *sd)
 827 {
 828         struct tc358743_state *state = to_state(sd);
 829         struct tc358743_platform_data *pdata = &state->pdata;
 830
 831         /*
 832          * IR is not supported by this driver.
 833          * CEC is only enabled if needed.
 834          */
 835         i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
 836                                      (MASK_IRRST | MASK_CECRST));
 837
 838         tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
 839 #ifdef CONFIG_VIDEO_TC358743_CEC
 840         tc358743_reset(sd, MASK_CECRST);
 841 #endif
 842         tc358743_sleep_mode(sd, false);
 843
 844         i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
 845
 846         tc358743_set_ref_clk(sd);
 847
 848         i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
 849                         pdata->ddc5v_delay & MASK_DDC5V_MODE);
 850         i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
 851
 852         tc358743_set_hdmi_phy(sd);
 853         tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
 854         tc358743_set_hdmi_audio(sd);
 855         tc358743_set_hdmi_info_frame_mode(sd);
 856
 857         /* All CE and IT formats are detected as RGB full range in DVI mode */
 858         i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
 859
 860         i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
 861                         MASK_VOUTCOLORMODE_AUTO);
 862         i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
 863 }
 864
 865 /* --------------- CEC --------------- */
 866
 867 #ifdef CONFIG_VIDEO_TC358743_CEC
 868 static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable)
 869 {
 870         struct tc358743_state *state = adap->priv;
 871         struct v4l2_subdev *sd = &state->sd;
 872
 873         i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
 874         i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
 875         i2c_wr32(sd, CECEN, enable);
 876         if (enable)
 877                 i2c_wr32(sd, CECREN, MASK_CECREN);
 878         return 0;
 879 }
 880
 881 static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap,
 882                                                 bool enable)
 883 {
 884         struct tc358743_state *state = adap->priv;
 885         struct v4l2_subdev *sd = &state->sd;
 886         u32 reg;
 887
 888         reg = i2c_rd32(sd, CECRCTL1);
 889         if (enable)
 890                 reg |= MASK_CECOTH;
 891         else
 892                 reg &= ~MASK_CECOTH;
 893         i2c_wr32(sd, CECRCTL1, reg);
 894         return 0;
 895 }
 896
 897 static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
 898 {
 899         struct tc358743_state *state = adap->priv;
 900         struct v4l2_subdev *sd = &state->sd;
 901         unsigned int la = 0;
 902
 903         if (log_addr != CEC_LOG_ADDR_INVALID) {
 904                 la = i2c_rd32(sd, CECADD);
 905                 la |= 1 << log_addr;
 906         }
 907         i2c_wr32(sd, CECADD, la);
 908         return 0;
 909 }
 910
 911 static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
 912                                    u32 signal_free_time, struct cec_msg *msg)
 913 {
 914         struct tc358743_state *state = adap->priv;
 915         struct v4l2_subdev *sd = &state->sd;
 916         unsigned int i;
 917
 918         i2c_wr32(sd, CECTCTL,
 919                  (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) |
 920                  (signal_free_time - 1));
 921         for (i = 0; i < msg->len; i++)
 922                 i2c_wr32(sd, CECTBUF1 + i * 4,
 923                         msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0));
 924         i2c_wr32(sd, CECTEN, MASK_CECTEN);
 925         return 0;
 926 }
 927
 928 static const struct cec_adap_ops tc358743_cec_adap_ops = {
 929         .adap_enable = tc358743_cec_adap_enable,
 930         .adap_log_addr = tc358743_cec_adap_log_addr,
 931         .adap_transmit = tc358743_cec_adap_transmit,
 932         .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable,
 933 };
 934
 935 static void tc358743_cec_isr(struct v4l2_subdev *sd, u16 intstatus,
 936                              bool *handled)
 937 {
 938         struct tc358743_state *state = to_state(sd);
 939         unsigned int cec_rxint, cec_txint;
 940         unsigned int clr = 0;
 941
 942         cec_rxint = i2c_rd32(sd, CECRSTAT);
 943         cec_txint = i2c_rd32(sd, CECTSTAT);
 944
 945         if (intstatus & MASK_CEC_RINT)
 946                 clr |= MASK_CECRICLR;
 947         if (intstatus & MASK_CEC_TINT)
 948                 clr |= MASK_CECTICLR;
 949         i2c_wr32(sd, CECICLR, clr);
 950
 951         if ((intstatus & MASK_CEC_TINT) && cec_txint) {
 952                 if (cec_txint & MASK_CECTIEND)
 953                         cec_transmit_attempt_done(state->cec_adap,
 954                                                   CEC_TX_STATUS_OK);
 955                 else if (cec_txint & MASK_CECTIAL)
 956                         cec_transmit_attempt_done(state->cec_adap,
 957                                                   CEC_TX_STATUS_ARB_LOST);
 958                 else if (cec_txint & MASK_CECTIACK)
 959                         cec_transmit_attempt_done(state->cec_adap,
 960                                                   CEC_TX_STATUS_NACK);
 961                 else if (cec_txint & MASK_CECTIUR) {
 962                         /*
 963                          * Not sure when this bit is set. Treat
 964                          * it as an error for now.
 965                          */
 966                         cec_transmit_attempt_done(state->cec_adap,
 967                                                   CEC_TX_STATUS_ERROR);
 968                 }
 969                 *handled = true;
 970         }
 971         if ((intstatus & MASK_CEC_RINT) &&
 972             (cec_rxint & MASK_CECRIEND)) {
 973                 struct cec_msg msg = {};
 974                 unsigned int i;
 975                 unsigned int v;
 976
 977                 v = i2c_rd32(sd, CECRCTR);
 978                 msg.len = v & 0x1f;
 979                 for (i = 0; i < msg.len; i++) {
 980                         v = i2c_rd32(sd, CECRBUF1 + i * 4);
 981                         msg.msg[i] = v & 0xff;
 982                 }
 983                 cec_received_msg(state->cec_adap, &msg);
 984                 *handled = true;
 985         }
 986         i2c_wr16(sd, INTSTATUS,
 987                  intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
 988 }
 989
 990 #endif
 991
 992 /* --------------- IRQ --------------- */
 993
 994 static void tc358743_format_change(struct v4l2_subdev *sd)
 995 {
 996         struct tc358743_state *state = to_state(sd);
 997         struct v4l2_dv_timings timings;
 998         const struct v4l2_event tc358743_ev_fmt = {
 999                 .type = V4L2_EVENT_SOURCE_CHANGE,
1000                 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1001         };
1002
1003         if (tc358743_get_detected_timings(sd, &timings)) {
1004                 enable_stream(sd, false);
1005
1006                 v4l2_dbg(1, debug, sd, "%s: No signal\n",
1007                                 __func__);
1008         } else {
1009                 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
1010                         enable_stream(sd, false);
1011
1012                 if (debug)
1013                         v4l2_print_dv_timings(sd->name,
1014                                         "tc358743_format_change: New format: ",
1015                                         &timings, false);
1016         }
1017
1018         if (sd->devnode)
1019                 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
1020 }
1021
1022 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
1023 {
1024         u16 i;
1025
1026         /* clear interrupt status registers */
1027         for (i = SYS_INT; i <= KEY_INT; i++)
1028                 i2c_wr8(sd, i, 0xff);
1029
1030         i2c_wr16(sd, INTSTATUS, 0xffff);
1031 }
1032
1033 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
1034                 bool cable_connected)
1035 {
1036         v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1037                         cable_connected);
1038
1039         if (cable_connected) {
1040                 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
1041                                         MASK_M_HDMI_DET) & 0xff);
1042                 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
1043                 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
1044                                         MASK_M_AF_UNLOCK) & 0xff);
1045                 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
1046                 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
1047         } else {
1048                 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
1049                 i2c_wr8(sd, CLK_INTM, 0xff);
1050                 i2c_wr8(sd, CBIT_INTM, 0xff);
1051                 i2c_wr8(sd, AUDIO_INTM, 0xff);
1052                 i2c_wr8(sd, MISC_INTM, 0xff);
1053         }
1054 }
1055
1056 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1057                 bool *handled)
1058 {
1059         u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1060         u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1061
1062         i2c_wr8(sd, AUDIO_INT, audio_int);
1063
1064         v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1065
1066         tc358743_s_ctrl_audio_sampling_rate(sd);
1067         tc358743_s_ctrl_audio_present(sd);
1068 }
1069
1070 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
1071 {
1072         v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
1073
1074         i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
1075 }
1076
1077 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1078                 bool *handled)
1079 {
1080         u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1081         u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1082
1083         i2c_wr8(sd, MISC_INT, misc_int);
1084
1085         v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1086
1087         if (misc_int & MASK_I_SYNC_CHG) {
1088                 /* Reset the HDMI PHY to try to trigger proper lock on the
1089                  * incoming video format. Erase BKSV to prevent that old keys
1090                  * are used when a new source is connected. */
1091                 if (no_sync(sd) || no_signal(sd)) {
1092                         tc358743_reset_phy(sd);
1093                         tc358743_erase_bksv(sd);
1094                 }
1095
1096                 tc358743_format_change(sd);
1097
1098                 misc_int &= ~MASK_I_SYNC_CHG;
1099                 if (handled)
1100                         *handled = true;
1101         }
1102
1103         if (misc_int) {
1104                 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1105                                 __func__, misc_int);
1106         }
1107 }
1108
1109 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1110                 bool *handled)
1111 {
1112         u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1113         u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1114
1115         i2c_wr8(sd, CBIT_INT, cbit_int);
1116
1117         v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1118
1119         if (cbit_int & MASK_I_CBIT_FS) {
1120
1121                 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1122                                 __func__);
1123                 tc358743_s_ctrl_audio_sampling_rate(sd);
1124
1125                 cbit_int &= ~MASK_I_CBIT_FS;
1126                 if (handled)
1127                         *handled = true;
1128         }
1129
1130         if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
1131
1132                 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1133                                 __func__);
1134                 tc358743_s_ctrl_audio_present(sd);
1135
1136                 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
1137                 if (handled)
1138                         *handled = true;
1139         }
1140
1141         if (cbit_int) {
1142                 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1143                                 __func__, cbit_int);
1144         }
1145 }
1146
1147 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1148 {
1149         u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1150         u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1151
1152         /* Bit 7 and bit 6 are set even when they are masked */
1153         i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1154
1155         v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1156
1157         if (clk_int & (MASK_I_IN_DE_CHG)) {
1158
1159                 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1160                                 __func__);
1161
1162                 /* If the source switch to a new resolution with the same pixel
1163                  * frequency as the existing (e.g. 1080p25 -> 720p50), the
1164                  * I_SYNC_CHG interrupt is not always triggered, while the
1165                  * I_IN_DE_CHG interrupt seems to work fine. Format change
1166                  * notifications are only sent when the signal is stable to
1167                  * reduce the number of notifications. */
1168                 if (!no_signal(sd) && !no_sync(sd))
1169                         tc358743_format_change(sd);
1170
1171                 clk_int &= ~(MASK_I_IN_DE_CHG);
1172                 if (handled)
1173                         *handled = true;
1174         }
1175
1176         if (clk_int) {
1177                 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1178                                 __func__, clk_int);
1179         }
1180 }
1181
1182 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1183 {
1184         struct tc358743_state *state = to_state(sd);
1185         u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1186         u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1187
1188         i2c_wr8(sd, SYS_INT, sys_int);
1189
1190         v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1191
1192         if (sys_int & MASK_I_DDC) {
1193                 bool tx_5v = tx_5v_power_present(sd);
1194
1195                 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1196                                 __func__, tx_5v ?  "yes" : "no");
1197
1198                 if (tx_5v) {
1199                         tc358743_enable_edid(sd);
1200                 } else {
1201                         tc358743_enable_interrupts(sd, false);
1202                         tc358743_disable_edid(sd);
1203                         memset(&state->timings, 0, sizeof(state->timings));
1204                         tc358743_erase_bksv(sd);
1205                         tc358743_update_controls(sd);
1206                 }
1207
1208                 sys_int &= ~MASK_I_DDC;
1209                 if (handled)
1210                         *handled = true;
1211         }
1212
1213         if (sys_int & MASK_I_DVI) {
1214                 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1215                                 __func__);
1216
1217                 /* Reset the HDMI PHY to try to trigger proper lock on the
1218                  * incoming video format. Erase BKSV to prevent that old keys
1219                  * are used when a new source is connected. */
1220                 if (no_sync(sd) || no_signal(sd)) {
1221                         tc358743_reset_phy(sd);
1222                         tc358743_erase_bksv(sd);
1223                 }
1224
1225                 sys_int &= ~MASK_I_DVI;
1226                 if (handled)
1227                         *handled = true;
1228         }
1229
1230         if (sys_int & MASK_I_HDMI) {
1231                 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1232                                 __func__);
1233
1234                 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1235                 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1236
1237                 sys_int &= ~MASK_I_HDMI;
1238                 if (handled)
1239                         *handled = true;
1240         }
1241
1242         if (sys_int) {
1243                 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1244                                 __func__, sys_int);
1245         }
1246 }
1247
1248 /* --------------- CORE OPS --------------- */
1249
1250 static int tc358743_log_status(struct v4l2_subdev *sd)
1251 {
1252         struct tc358743_state *state = to_state(sd);
1253         struct v4l2_dv_timings timings;
1254         uint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);
1255         uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1256         u8 vi_status3 =  i2c_rd8(sd, VI_STATUS3);
1257         const int deep_color_mode[4] = { 8, 10, 12, 16 };
1258         static const char * const input_color_space[] = {
1259                 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1260                 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1261                 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1262
1263         v4l2_info(sd, "-----Chip status-----\n");
1264         v4l2_info(sd, "Chip ID: 0x%02x\n",
1265                         (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1266         v4l2_info(sd, "Chip revision: 0x%02x\n",
1267                         i2c_rd16(sd, CHIPID) & MASK_REVID);
1268         v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1269                         !!(sysctl & MASK_IRRST),
1270                         !!(sysctl & MASK_CECRST),
1271                         !!(sysctl & MASK_CTXRST),
1272                         !!(sysctl & MASK_HDMIRST));
1273         v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1274         v4l2_info(sd, "Cable detected (+5V power): %s\n",
1275                         hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1276         v4l2_info(sd, "DDC lines enabled: %s\n",
1277                         (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1278                         "yes" : "no");
1279         v4l2_info(sd, "Hotplug enabled: %s\n",
1280                         (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1281                         "yes" : "no");
1282         v4l2_info(sd, "CEC enabled: %s\n",
1283                         (i2c_rd16(sd, CECEN) & MASK_CECEN) ?  "yes" : "no");
1284         v4l2_info(sd, "-----Signal status-----\n");
1285         v4l2_info(sd, "TMDS signal detected: %s\n",
1286                         hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1287         v4l2_info(sd, "Stable sync signal: %s\n",
1288                         hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1289         v4l2_info(sd, "PHY PLL locked: %s\n",
1290                         hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1291         v4l2_info(sd, "PHY DE detected: %s\n",
1292                         hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1293
1294         if (tc358743_get_detected_timings(sd, &timings)) {
1295                 v4l2_info(sd, "No video detected\n");
1296         } else {
1297                 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1298                                 true);
1299         }
1300         v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1301                         true);
1302
1303         v4l2_info(sd, "-----CSI-TX status-----\n");
1304         v4l2_info(sd, "Lanes needed: %d\n",
1305                         tc358743_num_csi_lanes_needed(sd));
1306         v4l2_info(sd, "Lanes in use: %d\n",
1307                         state->csi_lanes_in_use);
1308         v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1309                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1310                         "yes" : "no");
1311         v4l2_info(sd, "Transmit mode: %s\n",
1312                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1313                         "yes" : "no");
1314         v4l2_info(sd, "Receive mode: %s\n",
1315                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1316                         "yes" : "no");
1317         v4l2_info(sd, "Stopped: %s\n",
1318                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1319                         "yes" : "no");
1320         v4l2_info(sd, "Color space: %s\n",
1321                         state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1322                         "YCbCr 422 16-bit" :
1323                         state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1324                         "RGB 888 24-bit" : "Unsupported");
1325
1326         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1327         v4l2_info(sd, "HDCP encrypted content: %s\n",
1328                         hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1329         v4l2_info(sd, "Input color space: %s %s range\n",
1330                         input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1331                         (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1332         if (!is_hdmi(sd))
1333                 return 0;
1334         v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1335                         "off");
1336         v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1337                         deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1338                                 MASK_S_DEEPCOLOR) >> 2]);
1339         print_avi_infoframe(sd);
1340
1341         return 0;
1342 }
1343
1344 #ifdef CONFIG_VIDEO_ADV_DEBUG
1345 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1346 {
1347         v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1348         v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1349         v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1350         v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1351         v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1352         v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1353         v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1354         v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1355         v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1356         v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1357         v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1358         v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1359         v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1360         v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1361         v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1362         v4l2_info(sd, "0x9300-      : Reserved\n");
1363 }
1364
1365 static int tc358743_get_reg_size(u16 address)
1366 {
1367         /* REF_01 p. 66-72 */
1368         if (address <= 0x00ff)
1369                 return 2;
1370         else if ((address >= 0x0100) && (address <= 0x06FF))
1371                 return 4;
1372         else if ((address >= 0x0700) && (address <= 0x84ff))
1373                 return 2;
1374         else
1375                 return 1;
1376 }
1377
1378 static int tc358743_g_register(struct v4l2_subdev *sd,
1379                                struct v4l2_dbg_register *reg)
1380 {
1381         if (reg->reg > 0xffff) {
1382                 tc358743_print_register_map(sd);
1383                 return -EINVAL;
1384         }
1385
1386         reg->size = tc358743_get_reg_size(reg->reg);
1387
1388         reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1389
1390         return 0;
1391 }
1392
1393 static int tc358743_s_register(struct v4l2_subdev *sd,
1394                                const struct v4l2_dbg_register *reg)
1395 {
1396         if (reg->reg > 0xffff) {
1397                 tc358743_print_register_map(sd);
1398                 return -EINVAL;
1399         }
1400
1401         /* It should not be possible for the user to enable HDCP with a simple
1402          * v4l2-dbg command.
1403          *
1404          * DO NOT REMOVE THIS unless all other issues with HDCP have been
1405          * resolved.
1406          */
1407         if (reg->reg == HDCP_MODE ||
1408             reg->reg == HDCP_REG1 ||
1409             reg->reg == HDCP_REG2 ||
1410             reg->reg == HDCP_REG3 ||
1411             reg->reg == BCAPS)
1412                 return 0;
1413
1414         i2c_wrreg(sd, (u16)reg->reg, reg->val,
1415                         tc358743_get_reg_size(reg->reg));
1416
1417         return 0;
1418 }
1419 #endif
1420
1421 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1422 {
1423         u16 intstatus = i2c_rd16(sd, INTSTATUS);
1424
1425         v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1426
1427         if (intstatus & MASK_HDMI_INT) {
1428                 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1429                 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1430
1431                 if (hdmi_int0 & MASK_I_MISC)
1432                         tc358743_hdmi_misc_int_handler(sd, handled);
1433                 if (hdmi_int1 & MASK_I_CBIT)
1434                         tc358743_hdmi_cbit_int_handler(sd, handled);
1435                 if (hdmi_int1 & MASK_I_CLK)
1436                         tc358743_hdmi_clk_int_handler(sd, handled);
1437                 if (hdmi_int1 & MASK_I_SYS)
1438                         tc358743_hdmi_sys_int_handler(sd, handled);
1439                 if (hdmi_int1 & MASK_I_AUD)
1440                         tc358743_hdmi_audio_int_handler(sd, handled);
1441
1442                 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1443                 intstatus &= ~MASK_HDMI_INT;
1444         }
1445
1446 #ifdef CONFIG_VIDEO_TC358743_CEC
1447         if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) {
1448                 tc358743_cec_isr(sd, intstatus, handled);
1449                 i2c_wr16(sd, INTSTATUS,
1450                          intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
1451                 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT);
1452         }
1453 #endif
1454
1455         if (intstatus & MASK_CSI_INT) {
1456                 u32 csi_int = i2c_rd32(sd, CSI_INT);
1457
1458                 if (csi_int & MASK_INTER)
1459                         tc358743_csi_err_int_handler(sd, handled);
1460
1461                 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1462         }
1463
1464         intstatus = i2c_rd16(sd, INTSTATUS);
1465         if (intstatus) {
1466                 v4l2_dbg(1, debug, sd,
1467                                 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1468                                 __func__, intstatus);
1469         }
1470
1471         return 0;
1472 }
1473
1474 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1475 {
1476         struct tc358743_state *state = dev_id;
1477         bool handled;
1478
1479         tc358743_isr(&state->sd, 0, &handled);
1480
1481         return handled ? IRQ_HANDLED : IRQ_NONE;
1482 }
1483
1484 static void tc358743_irq_poll_timer(struct timer_list *t)
1485 {
1486         struct tc358743_state *state = from_timer(state, t, timer);
1487         unsigned int msecs;
1488
1489         schedule_work(&state->work_i2c_poll);
1490         /*
1491          * If CEC is present, then we need to poll more frequently,
1492          * otherwise we will miss CEC messages.
1493          */
1494         msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
1495         mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
1496 }
1497
1498 static void tc358743_work_i2c_poll(struct work_struct *work)
1499 {
1500         struct tc358743_state *state = container_of(work,
1501                         struct tc358743_state, work_i2c_poll);
1502         bool handled;
1503
1504         tc358743_isr(&state->sd, 0, &handled);
1505 }
1506
1507 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1508                                     struct v4l2_event_subscription *sub)
1509 {
1510         switch (sub->type) {
1511         case V4L2_EVENT_SOURCE_CHANGE:
1512                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1513         case V4L2_EVENT_CTRL:
1514                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1515         default:
1516                 return -EINVAL;
1517         }
1518 }
1519
1520 /* --------------- VIDEO OPS --------------- */
1521
1522 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1523 {
1524         *status = 0;
1525         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1526         *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1527
1528         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1529
1530         return 0;
1531 }
1532
1533 static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1534                                  struct v4l2_dv_timings *timings)
1535 {
1536         struct tc358743_state *state = to_state(sd);
1537
1538         if (!timings)
1539                 return -EINVAL;
1540
1541         if (debug)
1542                 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1543                                 timings, false);
1544
1545         if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1546                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1547                 return 0;
1548         }
1549
1550         if (!v4l2_valid_dv_timings(timings,
1551                                 &tc358743_timings_cap, NULL, NULL)) {
1552                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1553                 return -ERANGE;
1554         }
1555
1556         state->timings = *timings;
1557
1558         enable_stream(sd, false);
1559         tc358743_set_pll(sd);
1560         tc358743_set_csi(sd);
1561
1562         return 0;
1563 }
1564
1565 static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1566                                  struct v4l2_dv_timings *timings)
1567 {
1568         struct tc358743_state *state = to_state(sd);
1569
1570         *timings = state->timings;
1571
1572         return 0;
1573 }
1574
1575 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1576                                     struct v4l2_enum_dv_timings *timings)
1577 {
1578         if (timings->pad != 0)
1579                 return -EINVAL;
1580
1581         return v4l2_enum_dv_timings_cap(timings,
1582                         &tc358743_timings_cap, NULL, NULL);
1583 }
1584
1585 static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1586                 struct v4l2_dv_timings *timings)
1587 {
1588         int ret;
1589
1590         ret = tc358743_get_detected_timings(sd, timings);
1591         if (ret)
1592                 return ret;
1593
1594         if (debug)
1595                 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1596                                 timings, false);
1597
1598         if (!v4l2_valid_dv_timings(timings,
1599                                 &tc358743_timings_cap, NULL, NULL)) {
1600                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1601                 return -ERANGE;
1602         }
1603
1604         return 0;
1605 }
1606
1607 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1608                 struct v4l2_dv_timings_cap *cap)
1609 {
1610         if (cap->pad != 0)
1611                 return -EINVAL;
1612
1613         *cap = tc358743_timings_cap;
1614
1615         return 0;
1616 }
1617
1618 static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1619                              struct v4l2_mbus_config *cfg)
1620 {
1621         struct tc358743_state *state = to_state(sd);
1622
1623         cfg->type = V4L2_MBUS_CSI2;
1624
1625         /* Support for non-continuous CSI-2 clock is missing in the driver */
1626         cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1627
1628         switch (state->csi_lanes_in_use) {
1629         case 1:
1630                 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1631                 break;
1632         case 2:
1633                 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1634                 break;
1635         case 3:
1636                 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1637                 break;
1638         case 4:
1639                 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1640                 break;
1641         default:
1642                 return -EINVAL;
1643         }
1644
1645         return 0;
1646 }
1647
1648 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1649 {
1650         enable_stream(sd, enable);
1651         if (!enable) {
1652                 /* Put all lanes in LP-11 state (STOPSTATE) */
1653                 tc358743_set_csi(sd);
1654         }
1655
1656         return 0;
1657 }
1658
1659 /* --------------- PAD OPS --------------- */
1660
1661 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
1662                 struct v4l2_subdev_pad_config *cfg,
1663                 struct v4l2_subdev_mbus_code_enum *code)
1664 {
1665         switch (code->index) {
1666         case 0:
1667                 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1668                 break;
1669         case 1:
1670                 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1671                 break;
1672         default:
1673                 return -EINVAL;
1674         }
1675         return 0;
1676 }
1677
1678 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1679                 struct v4l2_subdev_pad_config *cfg,
1680                 struct v4l2_subdev_format *format)
1681 {
1682         struct tc358743_state *state = to_state(sd);
1683         u8 vi_rep = i2c_rd8(sd, VI_REP);
1684
1685         if (format->pad != 0)
1686                 return -EINVAL;
1687
1688         format->format.code = state->mbus_fmt_code;
1689         format->format.width = state->timings.bt.width;
1690         format->format.height = state->timings.bt.height;
1691         format->format.field = V4L2_FIELD_NONE;
1692
1693         switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1694         case MASK_VOUT_COLOR_RGB_FULL:
1695         case MASK_VOUT_COLOR_RGB_LIMITED:
1696                 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1697                 break;
1698         case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1699         case MASK_VOUT_COLOR_601_YCBCR_FULL:
1700                 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1701                 break;
1702         case MASK_VOUT_COLOR_709_YCBCR_FULL:
1703         case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1704                 format->format.colorspace = V4L2_COLORSPACE_REC709;
1705                 break;
1706         default:
1707                 format->format.colorspace = 0;
1708                 break;
1709         }
1710
1711         return 0;
1712 }
1713
1714 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1715                 struct v4l2_subdev_pad_config *cfg,
1716                 struct v4l2_subdev_format *format)
1717 {
1718         struct tc358743_state *state = to_state(sd);
1719
1720         u32 code = format->format.code; /* is overwritten by get_fmt */
1721         int ret = tc358743_get_fmt(sd, cfg, format);
1722
1723         format->format.code = code;
1724
1725         if (ret)
1726                 return ret;
1727
1728         switch (code) {
1729         case MEDIA_BUS_FMT_RGB888_1X24:
1730         case MEDIA_BUS_FMT_UYVY8_1X16:
1731                 break;
1732         default:
1733                 return -EINVAL;
1734         }
1735
1736         if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1737                 return 0;
1738
1739         state->mbus_fmt_code = format->format.code;
1740
1741         enable_stream(sd, false);
1742         tc358743_set_pll(sd);
1743         tc358743_set_csi(sd);
1744         tc358743_set_csi_color_space(sd);
1745
1746         return 0;
1747 }
1748
1749 static int tc358743_g_edid(struct v4l2_subdev *sd,
1750                 struct v4l2_subdev_edid *edid)
1751 {
1752         struct tc358743_state *state = to_state(sd);
1753
1754         memset(edid->reserved, 0, sizeof(edid->reserved));
1755
1756         if (edid->pad != 0)
1757                 return -EINVAL;
1758
1759         if (edid->start_block == 0 && edid->blocks == 0) {
1760                 edid->blocks = state->edid_blocks_written;
1761                 return 0;
1762         }
1763
1764         if (state->edid_blocks_written == 0)
1765                 return -ENODATA;
1766
1767         if (edid->start_block >= state->edid_blocks_written ||
1768                         edid->blocks == 0)
1769                 return -EINVAL;
1770
1771         if (edid->start_block + edid->blocks > state->edid_blocks_written)
1772                 edid->blocks = state->edid_blocks_written - edid->start_block;
1773
1774         i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1775                         edid->blocks * EDID_BLOCK_SIZE);
1776
1777         return 0;
1778 }
1779
1780 static int tc358743_s_edid(struct v4l2_subdev *sd,
1781                                 struct v4l2_subdev_edid *edid)
1782 {
1783         struct tc358743_state *state = to_state(sd);
1784         u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1785         u16 pa;
1786         int err;
1787         int i;
1788
1789         v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1790                  __func__, edid->pad, edid->start_block, edid->blocks);
1791
1792         memset(edid->reserved, 0, sizeof(edid->reserved));
1793
1794         if (edid->pad != 0)
1795                 return -EINVAL;
1796
1797         if (edid->start_block != 0)
1798                 return -EINVAL;
1799
1800         if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1801                 edid->blocks = EDID_NUM_BLOCKS_MAX;
1802                 return -E2BIG;
1803         }
1804         pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL);
1805         err = cec_phys_addr_validate(pa, &pa, NULL);
1806         if (err)
1807                 return err;
1808
1809         cec_phys_addr_invalidate(state->cec_adap);
1810
1811         tc358743_disable_edid(sd);
1812
1813         i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1814         i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1815
1816         if (edid->blocks == 0) {
1817                 state->edid_blocks_written = 0;
1818                 return 0;
1819         }
1820
1821         for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
1822                 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1823
1824         state->edid_blocks_written = edid->blocks;
1825
1826         cec_s_phys_addr(state->cec_adap, pa, false);
1827
1828         if (tx_5v_power_present(sd))
1829                 tc358743_enable_edid(sd);
1830
1831         return 0;
1832 }
1833
1834 /* -------------------------------------------------------------------------- */
1835
1836 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1837         .log_status = tc358743_log_status,
1838 #ifdef CONFIG_VIDEO_ADV_DEBUG
1839         .g_register = tc358743_g_register,
1840         .s_register = tc358743_s_register,
1841 #endif
1842         .interrupt_service_routine = tc358743_isr,
1843         .subscribe_event = tc358743_subscribe_event,
1844         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1845 };
1846
1847 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1848         .g_input_status = tc358743_g_input_status,
1849         .s_dv_timings = tc358743_s_dv_timings,
1850         .g_dv_timings = tc358743_g_dv_timings,
1851         .query_dv_timings = tc358743_query_dv_timings,
1852         .g_mbus_config = tc358743_g_mbus_config,
1853         .s_stream = tc358743_s_stream,
1854 };
1855
1856 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1857         .enum_mbus_code = tc358743_enum_mbus_code,
1858         .set_fmt = tc358743_set_fmt,
1859         .get_fmt = tc358743_get_fmt,
1860         .get_edid = tc358743_g_edid,
1861         .set_edid = tc358743_s_edid,
1862         .enum_dv_timings = tc358743_enum_dv_timings,
1863         .dv_timings_cap = tc358743_dv_timings_cap,
1864 };
1865
1866 static const struct v4l2_subdev_ops tc358743_ops = {
1867         .core = &tc358743_core_ops,
1868         .video = &tc358743_video_ops,
1869         .pad = &tc358743_pad_ops,
1870 };
1871
1872 /* --------------- CUSTOM CTRLS --------------- */
1873
1874 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1875         .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1876         .name = "Audio sampling rate",
1877         .type = V4L2_CTRL_TYPE_INTEGER,
1878         .min = 0,
1879         .max = 768000,
1880         .step = 1,
1881         .def = 0,
1882         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1883 };
1884
1885 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1886         .id = TC358743_CID_AUDIO_PRESENT,
1887         .name = "Audio present",
1888         .type = V4L2_CTRL_TYPE_BOOLEAN,
1889         .min = 0,
1890         .max = 1,
1891         .step = 1,
1892         .def = 0,
1893         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1894 };
1895
1896 /* --------------- PROBE / REMOVE --------------- */
1897
1898 #ifdef CONFIG_OF
1899 static void tc358743_gpio_reset(struct tc358743_state *state)
1900 {
1901         usleep_range(5000, 10000);
1902         gpiod_set_value(state->reset_gpio, 1);
1903         usleep_range(1000, 2000);
1904         gpiod_set_value(state->reset_gpio, 0);
1905         msleep(20);
1906 }
1907
1908 static int tc358743_probe_of(struct tc358743_state *state)
1909 {
1910         struct device *dev = &state->i2c_client->dev;
1911         struct v4l2_fwnode_endpoint *endpoint;
1912         struct device_node *ep;
1913         struct clk *refclk;
1914         u32 bps_pr_lane;
1915         int ret = -EINVAL;
1916
1917         refclk = devm_clk_get(dev, "refclk");
1918         if (IS_ERR(refclk)) {
1919                 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1920                         dev_err(dev, "failed to get refclk: %ld\n",
1921                                 PTR_ERR(refclk));
1922                 return PTR_ERR(refclk);
1923         }
1924
1925         ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1926         if (!ep) {
1927                 dev_err(dev, "missing endpoint node\n");
1928                 return -EINVAL;
1929         }
1930
1931         endpoint = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep));
1932         if (IS_ERR(endpoint)) {
1933                 dev_err(dev, "failed to parse endpoint\n");
1934                 return PTR_ERR(endpoint);
1935         }
1936
1937         if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
1938             endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
1939             endpoint->nr_of_link_frequencies == 0) {
1940                 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1941                 goto free_endpoint;
1942         }
1943
1944         if (endpoint->bus.mipi_csi2.num_data_lanes > 4) {
1945                 dev_err(dev, "invalid number of lanes\n");
1946                 goto free_endpoint;
1947         }
1948
1949         state->bus = endpoint->bus.mipi_csi2;
1950
1951         ret = clk_prepare_enable(refclk);
1952         if (ret) {
1953                 dev_err(dev, "Failed! to enable clock\n");
1954                 goto free_endpoint;
1955         }
1956
1957         state->pdata.refclk_hz = clk_get_rate(refclk);
1958         state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1959         state->pdata.enable_hdcp = false;
1960         /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1961         state->pdata.fifo_level = 16;
1962         /*
1963          * The PLL input clock is obtained by dividing refclk by pll_prd.
1964          * It must be between 6 MHz and 40 MHz, lower frequency is better.
1965          */
1966         switch (state->pdata.refclk_hz) {
1967         case 26000000:
1968         case 27000000:
1969         case 42000000:
1970                 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1971                 break;
1972         default:
1973                 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1974                         state->pdata.refclk_hz);
1975                 goto disable_clk;
1976         }
1977
1978         /*
1979          * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1980          * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1981          */
1982         bps_pr_lane = 2 * endpoint->link_frequencies[0];
1983         if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1984                 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1985                 goto disable_clk;
1986         }
1987
1988         /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1989         state->pdata.pll_fbd = bps_pr_lane /
1990                                state->pdata.refclk_hz * state->pdata.pll_prd;
1991
1992         /*
1993          * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1994          * link frequency). In principle it should be possible to calculate
1995          * them based on link frequency and resolution.
1996          */
1997         if (bps_pr_lane != 594000000U)
1998                 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1999         state->pdata.lineinitcnt = 0xe80;
2000         state->pdata.lptxtimecnt = 0x003;
2001         /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
2002         state->pdata.tclk_headercnt = 0x1403;
2003         state->pdata.tclk_trailcnt = 0x00;
2004         /* ths-preparecnt: 3, ths-zerocnt: 1 */
2005         state->pdata.ths_headercnt = 0x0103;
2006         state->pdata.twakeup = 0x4882;
2007         state->pdata.tclk_postcnt = 0x008;
2008         state->pdata.ths_trailcnt = 0x2;
2009         state->pdata.hstxvregcnt = 0;
2010
2011         state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
2012                                                     GPIOD_OUT_LOW);
2013         if (IS_ERR(state->reset_gpio)) {
2014                 dev_err(dev, "failed to get reset gpio\n");
2015                 ret = PTR_ERR(state->reset_gpio);
2016                 goto disable_clk;
2017         }
2018
2019         if (state->reset_gpio)
2020                 tc358743_gpio_reset(state);
2021
2022         ret = 0;
2023         goto free_endpoint;
2024
2025 disable_clk:
2026         clk_disable_unprepare(refclk);
2027 free_endpoint:
2028         v4l2_fwnode_endpoint_free(endpoint);
2029         return ret;
2030 }
2031 #else
2032 static inline int tc358743_probe_of(struct tc358743_state *state)
2033 {
2034         return -ENODEV;
2035 }
2036 #endif
2037
2038 static int tc358743_probe(struct i2c_client *client,
2039                           const struct i2c_device_id *id)
2040 {
2041         static struct v4l2_dv_timings default_timing =
2042                 V4L2_DV_BT_CEA_640X480P59_94;
2043         struct tc358743_state *state;
2044         struct tc358743_platform_data *pdata = client->dev.platform_data;
2045         struct v4l2_subdev *sd;
2046         u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
2047         int err;
2048
2049         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2050                 return -EIO;
2051         v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
2052                 client->addr << 1, client->adapter->name);
2053
2054         state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
2055                         GFP_KERNEL);
2056         if (!state)
2057                 return -ENOMEM;
2058
2059         state->i2c_client = client;
2060
2061         /* platform data */
2062         if (pdata) {
2063                 state->pdata = *pdata;
2064                 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2065         } else {
2066                 err = tc358743_probe_of(state);
2067                 if (err == -ENODEV)
2068                         v4l_err(client, "No platform data!\n");
2069                 if (err)
2070                         return err;
2071         }
2072
2073         sd = &state->sd;
2074         v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
2075         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2076
2077         /* i2c access */
2078         if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
2079                 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
2080                           client->addr << 1);
2081                 return -ENODEV;
2082         }
2083
2084         /* control handlers */
2085         v4l2_ctrl_handler_init(&state->hdl, 3);
2086
2087         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
2088                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2089
2090         /* custom controls */
2091         state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2092                         &tc358743_ctrl_audio_sampling_rate, NULL);
2093
2094         state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2095                         &tc358743_ctrl_audio_present, NULL);
2096
2097         sd->ctrl_handler = &state->hdl;
2098         if (state->hdl.error) {
2099                 err = state->hdl.error;
2100                 goto err_hdl;
2101         }
2102
2103         if (tc358743_update_controls(sd)) {
2104                 err = -ENODEV;
2105                 goto err_hdl;
2106         }
2107
2108         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2109         sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
2110         err = media_entity_pads_init(&sd->entity, 1, &state->pad);
2111         if (err < 0)
2112                 goto err_hdl;
2113
2114         state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
2115
2116         sd->dev = &client->dev;
2117         err = v4l2_async_register_subdev(sd);
2118         if (err < 0)
2119                 goto err_hdl;
2120
2121         mutex_init(&state->confctl_mutex);
2122
2123         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2124                         tc358743_delayed_work_enable_hotplug);
2125
2126 #ifdef CONFIG_VIDEO_TC358743_CEC
2127         state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops,
2128                 state, dev_name(&client->dev),
2129                 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS);
2130         if (IS_ERR(state->cec_adap)) {
2131                 err = PTR_ERR(state->cec_adap);
2132                 goto err_hdl;
2133         }
2134         irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK;
2135 #endif
2136
2137         tc358743_initial_setup(sd);
2138
2139         tc358743_s_dv_timings(sd, &default_timing);
2140
2141         tc358743_set_csi_color_space(sd);
2142
2143         tc358743_init_interrupts(sd);
2144
2145         if (state->i2c_client->irq) {
2146                 err = devm_request_threaded_irq(&client->dev,
2147                                                 state->i2c_client->irq,
2148                                                 NULL, tc358743_irq_handler,
2149                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2150                                                 "tc358743", state);
2151                 if (err)
2152                         goto err_work_queues;
2153         } else {
2154                 INIT_WORK(&state->work_i2c_poll,
2155                           tc358743_work_i2c_poll);
2156                 timer_setup(&state->timer, tc358743_irq_poll_timer, 0);
2157                 state->timer.expires = jiffies +
2158                                        msecs_to_jiffies(POLL_INTERVAL_MS);
2159                 add_timer(&state->timer);
2160         }
2161
2162         err = cec_register_adapter(state->cec_adap, &client->dev);
2163         if (err < 0) {
2164                 pr_err("%s: failed to register the cec device\n", __func__);
2165                 cec_delete_adapter(state->cec_adap);
2166                 state->cec_adap = NULL;
2167                 goto err_work_queues;
2168         }
2169
2170         tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
2171         i2c_wr16(sd, INTMASK, ~irq_mask);
2172
2173         err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
2174         if (err)
2175                 goto err_work_queues;
2176
2177         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2178                   client->addr << 1, client->adapter->name);
2179
2180         return 0;
2181
2182 err_work_queues:
2183         cec_unregister_adapter(state->cec_adap);
2184         if (!state->i2c_client->irq)
2185                 flush_work(&state->work_i2c_poll);
2186         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2187         mutex_destroy(&state->confctl_mutex);
2188 err_hdl:
2189         media_entity_cleanup(&sd->entity);
2190         v4l2_ctrl_handler_free(&state->hdl);
2191         return err;
2192 }
2193
2194 static int tc358743_remove(struct i2c_client *client)
2195 {
2196         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2197         struct tc358743_state *state = to_state(sd);
2198
2199         if (!state->i2c_client->irq) {
2200                 del_timer_sync(&state->timer);
2201                 flush_work(&state->work_i2c_poll);
2202         }
2203         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2204         cec_unregister_adapter(state->cec_adap);
2205         v4l2_async_unregister_subdev(sd);
2206         v4l2_device_unregister_subdev(sd);
2207         mutex_destroy(&state->confctl_mutex);
2208         media_entity_cleanup(&sd->entity);
2209         v4l2_ctrl_handler_free(&state->hdl);
2210
2211         return 0;
2212 }
2213
2214 static const struct i2c_device_id tc358743_id[] = {
2215         {"tc358743", 0},
2216         {}
2217 };
2218
2219 MODULE_DEVICE_TABLE(i2c, tc358743_id);
2220
2221 #if IS_ENABLED(CONFIG_OF)
2222 static const struct of_device_id tc358743_of_match[] = {
2223         { .compatible = "toshiba,tc358743" },
2224         {},
2225 };
2226 MODULE_DEVICE_TABLE(of, tc358743_of_match);
2227 #endif
2228
2229 static struct i2c_driver tc358743_driver = {
2230         .driver = {
2231                 .name = "tc358743",
2232                 .of_match_table = of_match_ptr(tc358743_of_match),
2233         },
2234         .probe = tc358743_probe,
2235         .remove = tc358743_remove,
2236         .id_table = tc358743_id,
2237 };
2238
2239 module_i2c_driver(tc358743_driver);