1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for ST MIPID02 CSI-2 to PARALLEL bridge
5 * Copyright (C) STMicroelectronics SA 2019
6 * Authors: Mickael Guene <mickael.guene@st.com>
7 * for STMicroelectronics.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/of_graph.h>
18 #include <linux/regulator/consumer.h>
19 #include <media/v4l2-async.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
25 #define MIPID02_CLK_LANE_WR_REG1 0x01
26 #define MIPID02_CLK_LANE_REG1 0x02
27 #define MIPID02_CLK_LANE_REG3 0x04
28 #define MIPID02_DATA_LANE0_REG1 0x05
29 #define MIPID02_DATA_LANE0_REG2 0x06
30 #define MIPID02_DATA_LANE1_REG1 0x09
31 #define MIPID02_DATA_LANE1_REG2 0x0a
32 #define MIPID02_MODE_REG1 0x14
33 #define MIPID02_MODE_REG2 0x15
34 #define MIPID02_DATA_ID_RREG 0x17
35 #define MIPID02_DATA_SELECTION_CTRL 0x19
36 #define MIPID02_PIX_WIDTH_CTRL 0x1e
37 #define MIPID02_PIX_WIDTH_CTRL_EMB 0x1f
39 /* Bits definition for MIPID02_CLK_LANE_REG1 */
40 #define CLK_ENABLE BIT(0)
41 /* Bits definition for MIPID02_CLK_LANE_REG3 */
42 #define CLK_MIPI_CSI BIT(1)
43 /* Bits definition for MIPID02_DATA_LANE0_REG1 */
44 #define DATA_ENABLE BIT(0)
45 /* Bits definition for MIPID02_DATA_LANEx_REG2 */
46 #define DATA_MIPI_CSI BIT(0)
47 /* Bits definition for MIPID02_MODE_REG1 */
48 #define MODE_DATA_SWAP BIT(2)
49 #define MODE_NO_BYPASS BIT(6)
50 /* Bits definition for MIPID02_MODE_REG2 */
51 #define MODE_HSYNC_ACTIVE_HIGH BIT(1)
52 #define MODE_VSYNC_ACTIVE_HIGH BIT(2)
53 /* Bits definition for MIPID02_DATA_SELECTION_CTRL */
54 #define SELECTION_MANUAL_DATA BIT(2)
55 #define SELECTION_MANUAL_WIDTH BIT(3)
57 static const u32 mipid02_supported_fmt_codes[] = {
58 MEDIA_BUS_FMT_SBGGR8_1X8, MEDIA_BUS_FMT_SGBRG8_1X8,
59 MEDIA_BUS_FMT_SGRBG8_1X8, MEDIA_BUS_FMT_SRGGB8_1X8,
60 MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10,
61 MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10,
62 MEDIA_BUS_FMT_SBGGR12_1X12, MEDIA_BUS_FMT_SGBRG12_1X12,
63 MEDIA_BUS_FMT_SGRBG12_1X12, MEDIA_BUS_FMT_SRGGB12_1X12,
64 MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_BGR888_1X24,
65 MEDIA_BUS_FMT_RGB565_2X8_LE, MEDIA_BUS_FMT_RGB565_2X8_BE,
66 MEDIA_BUS_FMT_YUYV8_2X8, MEDIA_BUS_FMT_UYVY8_2X8,
67 MEDIA_BUS_FMT_JPEG_1X8
70 /* regulator supplies */
71 static const char * const mipid02_supply_name[] = {
72 "VDDE", /* 1.8V digital I/O supply */
73 "VDDIN", /* 1V8 voltage regulator supply */
76 #define MIPID02_NUM_SUPPLIES ARRAY_SIZE(mipid02_supply_name)
78 #define MIPID02_SINK_0 0
79 #define MIPID02_SINK_1 1
80 #define MIPID02_SOURCE 2
81 #define MIPID02_PAD_NB 3
84 struct i2c_client *i2c_client;
85 struct regulator_bulk_data supplies[MIPID02_NUM_SUPPLIES];
86 struct v4l2_subdev sd;
87 struct media_pad pad[MIPID02_PAD_NB];
89 struct gpio_desc *reset_gpio;
91 struct v4l2_fwnode_endpoint rx;
93 struct v4l2_fwnode_endpoint tx;
95 struct v4l2_async_notifier notifier;
96 struct v4l2_subdev *s_subdev;
104 u8 data_selection_ctrl;
107 u8 pix_width_ctrl_emb;
109 /* lock to protect all members below */
112 struct v4l2_mbus_framefmt fmt;
115 static int bpp_from_code(__u32 code)
118 case MEDIA_BUS_FMT_SBGGR8_1X8:
119 case MEDIA_BUS_FMT_SGBRG8_1X8:
120 case MEDIA_BUS_FMT_SGRBG8_1X8:
121 case MEDIA_BUS_FMT_SRGGB8_1X8:
123 case MEDIA_BUS_FMT_SBGGR10_1X10:
124 case MEDIA_BUS_FMT_SGBRG10_1X10:
125 case MEDIA_BUS_FMT_SGRBG10_1X10:
126 case MEDIA_BUS_FMT_SRGGB10_1X10:
128 case MEDIA_BUS_FMT_SBGGR12_1X12:
129 case MEDIA_BUS_FMT_SGBRG12_1X12:
130 case MEDIA_BUS_FMT_SGRBG12_1X12:
131 case MEDIA_BUS_FMT_SRGGB12_1X12:
133 case MEDIA_BUS_FMT_UYVY8_1X16:
134 case MEDIA_BUS_FMT_YUYV8_2X8:
135 case MEDIA_BUS_FMT_UYVY8_2X8:
136 case MEDIA_BUS_FMT_RGB565_2X8_LE:
137 case MEDIA_BUS_FMT_RGB565_2X8_BE:
139 case MEDIA_BUS_FMT_BGR888_1X24:
146 static u8 data_type_from_code(__u32 code)
149 case MEDIA_BUS_FMT_SBGGR8_1X8:
150 case MEDIA_BUS_FMT_SGBRG8_1X8:
151 case MEDIA_BUS_FMT_SGRBG8_1X8:
152 case MEDIA_BUS_FMT_SRGGB8_1X8:
154 case MEDIA_BUS_FMT_SBGGR10_1X10:
155 case MEDIA_BUS_FMT_SGBRG10_1X10:
156 case MEDIA_BUS_FMT_SGRBG10_1X10:
157 case MEDIA_BUS_FMT_SRGGB10_1X10:
159 case MEDIA_BUS_FMT_SBGGR12_1X12:
160 case MEDIA_BUS_FMT_SGBRG12_1X12:
161 case MEDIA_BUS_FMT_SGRBG12_1X12:
162 case MEDIA_BUS_FMT_SRGGB12_1X12:
164 case MEDIA_BUS_FMT_UYVY8_1X16:
165 case MEDIA_BUS_FMT_YUYV8_2X8:
166 case MEDIA_BUS_FMT_UYVY8_2X8:
168 case MEDIA_BUS_FMT_BGR888_1X24:
170 case MEDIA_BUS_FMT_RGB565_2X8_LE:
171 case MEDIA_BUS_FMT_RGB565_2X8_BE:
178 static void init_format(struct v4l2_mbus_framefmt *fmt)
180 fmt->code = MEDIA_BUS_FMT_SBGGR8_1X8;
181 fmt->field = V4L2_FIELD_NONE;
182 fmt->colorspace = V4L2_COLORSPACE_SRGB;
183 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SRGB);
184 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
185 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SRGB);
190 static __u32 get_fmt_code(__u32 code)
194 for (i = 0; i < ARRAY_SIZE(mipid02_supported_fmt_codes); i++) {
195 if (code == mipid02_supported_fmt_codes[i])
199 return mipid02_supported_fmt_codes[0];
202 static __u32 serial_to_parallel_code(__u32 serial)
204 if (serial == MEDIA_BUS_FMT_UYVY8_1X16)
205 return MEDIA_BUS_FMT_UYVY8_2X8;
206 if (serial == MEDIA_BUS_FMT_BGR888_1X24)
207 return MEDIA_BUS_FMT_BGR888_3X8;
212 static inline struct mipid02_dev *to_mipid02_dev(struct v4l2_subdev *sd)
214 return container_of(sd, struct mipid02_dev, sd);
217 static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val)
219 struct i2c_client *client = bridge->i2c_client;
220 struct i2c_msg msg[2];
227 msg[0].addr = client->addr;
228 msg[0].flags = client->flags;
230 msg[0].len = sizeof(buf);
232 msg[1].addr = client->addr;
233 msg[1].flags = client->flags | I2C_M_RD;
237 ret = i2c_transfer(client->adapter, msg, 2);
239 dev_dbg(&client->dev, "%s: %x i2c_transfer, reg: %x => %d\n",
240 __func__, client->addr, reg, ret);
247 static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val)
249 struct i2c_client *client = bridge->i2c_client;
258 msg.addr = client->addr;
259 msg.flags = client->flags;
261 msg.len = sizeof(buf);
263 ret = i2c_transfer(client->adapter, &msg, 1);
265 dev_dbg(&client->dev, "%s: i2c_transfer, reg: %x => %d\n",
273 static int mipid02_get_regulators(struct mipid02_dev *bridge)
277 for (i = 0; i < MIPID02_NUM_SUPPLIES; i++)
278 bridge->supplies[i].supply = mipid02_supply_name[i];
280 return devm_regulator_bulk_get(&bridge->i2c_client->dev,
281 MIPID02_NUM_SUPPLIES,
285 static void mipid02_apply_reset(struct mipid02_dev *bridge)
287 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
288 usleep_range(5000, 10000);
289 gpiod_set_value_cansleep(bridge->reset_gpio, 1);
290 usleep_range(5000, 10000);
291 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
292 usleep_range(5000, 10000);
295 static int mipid02_set_power_on(struct mipid02_dev *bridge)
297 struct i2c_client *client = bridge->i2c_client;
300 ret = clk_prepare_enable(bridge->xclk);
302 dev_err(&client->dev, "%s: failed to enable clock\n", __func__);
306 ret = regulator_bulk_enable(MIPID02_NUM_SUPPLIES,
309 dev_err(&client->dev, "%s: failed to enable regulators\n",
314 if (bridge->reset_gpio) {
315 dev_dbg(&client->dev, "apply reset");
316 mipid02_apply_reset(bridge);
318 dev_dbg(&client->dev, "don't apply reset");
319 usleep_range(5000, 10000);
325 clk_disable_unprepare(bridge->xclk);
329 static void mipid02_set_power_off(struct mipid02_dev *bridge)
331 regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies);
332 clk_disable_unprepare(bridge->xclk);
335 static int mipid02_detect(struct mipid02_dev *bridge)
340 * There is no version registers. Just try to read register
341 * MIPID02_CLK_LANE_WR_REG1.
343 return mipid02_read_reg(bridge, MIPID02_CLK_LANE_WR_REG1, ®);
346 static u32 mipid02_get_link_freq_from_cid_link_freq(struct mipid02_dev *bridge,
347 struct v4l2_subdev *subdev)
349 struct v4l2_querymenu qm = {.id = V4L2_CID_LINK_FREQ, };
350 struct v4l2_ctrl *ctrl;
353 ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_LINK_FREQ);
356 qm.index = v4l2_ctrl_g_ctrl(ctrl);
358 ret = v4l2_querymenu(subdev->ctrl_handler, &qm);
365 static u32 mipid02_get_link_freq_from_cid_pixel_rate(struct mipid02_dev *bridge,
366 struct v4l2_subdev *subdev)
368 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
369 struct v4l2_ctrl *ctrl;
371 u32 bpp = bpp_from_code(bridge->fmt.code);
373 ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
376 pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
378 return pixel_clock * bpp / (2 * ep->bus.mipi_csi2.num_data_lanes);
382 * We need to know link frequency to setup clk_lane_reg1 timings. Link frequency
383 * will be computed using connected device V4L2_CID_PIXEL_RATE, bit per pixel
384 * and number of lanes.
386 static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge)
388 struct i2c_client *client = bridge->i2c_client;
389 struct v4l2_subdev *subdev = bridge->s_subdev;
392 link_freq = mipid02_get_link_freq_from_cid_link_freq(bridge, subdev);
394 link_freq = mipid02_get_link_freq_from_cid_pixel_rate(bridge,
397 dev_err(&client->dev, "Failed to get link frequency");
402 dev_dbg(&client->dev, "detect link_freq = %d Hz", link_freq);
403 bridge->r.clk_lane_reg1 |= (2000000000 / link_freq) << 2;
408 static int mipid02_configure_clk_lane(struct mipid02_dev *bridge)
410 struct i2c_client *client = bridge->i2c_client;
411 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
412 bool *polarities = ep->bus.mipi_csi2.lane_polarities;
414 /* midid02 doesn't support clock lane remapping */
415 if (ep->bus.mipi_csi2.clock_lane != 0) {
416 dev_err(&client->dev, "clk lane must be map to lane 0\n");
419 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
424 static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb,
425 bool are_lanes_swap, bool *polarities)
427 bool are_pin_swap = are_lanes_swap ? polarities[2] : polarities[1];
429 if (nb == 1 && are_lanes_swap)
433 * data lane 0 as pin swap polarity reversed compared to clock and
437 bridge->r.data_lane0_reg1 = 1 << 1;
438 bridge->r.data_lane0_reg1 |= DATA_ENABLE;
443 static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,
444 bool are_lanes_swap, bool *polarities)
446 bool are_pin_swap = are_lanes_swap ? polarities[1] : polarities[2];
448 if (nb == 1 && !are_lanes_swap)
452 bridge->r.data_lane1_reg1 = 1 << 1;
453 bridge->r.data_lane1_reg1 |= DATA_ENABLE;
458 static int mipid02_configure_from_rx(struct mipid02_dev *bridge)
460 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
461 bool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2;
462 bool *polarities = ep->bus.mipi_csi2.lane_polarities;
463 int nb = ep->bus.mipi_csi2.num_data_lanes;
466 ret = mipid02_configure_clk_lane(bridge);
470 ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,
475 ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,
480 bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;
481 bridge->r.mode_reg1 |= (nb - 1) << 1;
483 return mipid02_configure_from_rx_speed(bridge);
486 static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
488 struct v4l2_fwnode_endpoint *ep = &bridge->tx;
490 bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH;
491 bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width;
492 bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width;
493 if (ep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
494 bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
495 if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
496 bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
501 static int mipid02_configure_from_code(struct mipid02_dev *bridge)
505 bridge->r.data_id_rreg = 0;
507 if (bridge->fmt.code != MEDIA_BUS_FMT_JPEG_1X8) {
508 bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA;
510 data_type = data_type_from_code(bridge->fmt.code);
513 bridge->r.data_id_rreg = data_type;
519 static int mipid02_stream_disable(struct mipid02_dev *bridge)
521 struct i2c_client *client = bridge->i2c_client;
524 /* Disable all lanes */
525 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1, 0);
528 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1, 0);
531 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1, 0);
536 dev_err(&client->dev, "failed to stream off %d", ret);
541 static int mipid02_stream_enable(struct mipid02_dev *bridge)
543 struct i2c_client *client = bridge->i2c_client;
546 if (!bridge->s_subdev)
549 memset(&bridge->r, 0, sizeof(bridge->r));
550 /* build registers content */
551 ret = mipid02_configure_from_rx(bridge);
554 ret = mipid02_configure_from_tx(bridge);
557 ret = mipid02_configure_from_code(bridge);
561 /* write mipi registers */
562 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1,
563 bridge->r.clk_lane_reg1);
566 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI);
569 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1,
570 bridge->r.data_lane0_reg1);
573 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG2,
577 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1,
578 bridge->r.data_lane1_reg1);
581 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG2,
585 ret = mipid02_write_reg(bridge, MIPID02_MODE_REG1,
586 MODE_NO_BYPASS | bridge->r.mode_reg1);
589 ret = mipid02_write_reg(bridge, MIPID02_MODE_REG2,
590 bridge->r.mode_reg2);
593 ret = mipid02_write_reg(bridge, MIPID02_DATA_ID_RREG,
594 bridge->r.data_id_rreg);
597 ret = mipid02_write_reg(bridge, MIPID02_DATA_SELECTION_CTRL,
598 bridge->r.data_selection_ctrl);
601 ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL,
602 bridge->r.pix_width_ctrl);
605 ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL_EMB,
606 bridge->r.pix_width_ctrl_emb);
613 dev_err(&client->dev, "failed to stream on %d", ret);
614 mipid02_stream_disable(bridge);
619 static int mipid02_s_stream(struct v4l2_subdev *sd, int enable)
621 struct mipid02_dev *bridge = to_mipid02_dev(sd);
622 struct i2c_client *client = bridge->i2c_client;
625 dev_dbg(&client->dev, "%s : requested %d / current = %d", __func__,
626 enable, bridge->streaming);
627 mutex_lock(&bridge->lock);
629 if (bridge->streaming == enable)
632 ret = enable ? mipid02_stream_enable(bridge) :
633 mipid02_stream_disable(bridge);
635 bridge->streaming = enable;
638 dev_dbg(&client->dev, "%s current now = %d / %d", __func__,
639 bridge->streaming, ret);
640 mutex_unlock(&bridge->lock);
645 static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,
646 struct v4l2_subdev_state *sd_state,
647 struct v4l2_subdev_mbus_code_enum *code)
649 struct mipid02_dev *bridge = to_mipid02_dev(sd);
654 if (code->index >= ARRAY_SIZE(mipid02_supported_fmt_codes))
657 code->code = mipid02_supported_fmt_codes[code->index];
660 if (code->index == 0)
661 code->code = serial_to_parallel_code(bridge->fmt.code);
672 static int mipid02_get_fmt(struct v4l2_subdev *sd,
673 struct v4l2_subdev_state *sd_state,
674 struct v4l2_subdev_format *format)
676 struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
677 struct mipid02_dev *bridge = to_mipid02_dev(sd);
678 struct i2c_client *client = bridge->i2c_client;
679 struct v4l2_mbus_framefmt *fmt;
681 dev_dbg(&client->dev, "%s probe %d", __func__, format->pad);
683 if (format->pad >= MIPID02_PAD_NB)
685 /* second CSI-2 pad not yet supported */
686 if (format->pad == MIPID02_SINK_1)
689 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
690 fmt = v4l2_subdev_get_try_format(&bridge->sd, sd_state,
695 mutex_lock(&bridge->lock);
698 /* code may need to be converted for source */
699 if (format->pad == MIPID02_SOURCE)
700 mbus_fmt->code = serial_to_parallel_code(mbus_fmt->code);
702 mutex_unlock(&bridge->lock);
707 static void mipid02_set_fmt_source(struct v4l2_subdev *sd,
708 struct v4l2_subdev_state *sd_state,
709 struct v4l2_subdev_format *format)
711 struct mipid02_dev *bridge = to_mipid02_dev(sd);
713 /* source pad mirror active sink pad */
714 format->format = bridge->fmt;
715 /* but code may need to be converted */
716 format->format.code = serial_to_parallel_code(format->format.code);
718 /* only apply format for V4L2_SUBDEV_FORMAT_TRY case */
719 if (format->which != V4L2_SUBDEV_FORMAT_TRY)
722 *v4l2_subdev_get_try_format(sd, sd_state, format->pad) = format->format;
725 static void mipid02_set_fmt_sink(struct v4l2_subdev *sd,
726 struct v4l2_subdev_state *sd_state,
727 struct v4l2_subdev_format *format)
729 struct mipid02_dev *bridge = to_mipid02_dev(sd);
730 struct v4l2_mbus_framefmt *fmt;
732 format->format.code = get_fmt_code(format->format.code);
734 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
735 fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
739 *fmt = format->format;
742 static int mipid02_set_fmt(struct v4l2_subdev *sd,
743 struct v4l2_subdev_state *sd_state,
744 struct v4l2_subdev_format *format)
746 struct mipid02_dev *bridge = to_mipid02_dev(sd);
747 struct i2c_client *client = bridge->i2c_client;
750 dev_dbg(&client->dev, "%s for %d", __func__, format->pad);
752 if (format->pad >= MIPID02_PAD_NB)
754 /* second CSI-2 pad not yet supported */
755 if (format->pad == MIPID02_SINK_1)
758 mutex_lock(&bridge->lock);
760 if (bridge->streaming) {
765 if (format->pad == MIPID02_SOURCE)
766 mipid02_set_fmt_source(sd, sd_state, format);
768 mipid02_set_fmt_sink(sd, sd_state, format);
771 mutex_unlock(&bridge->lock);
776 static const struct v4l2_subdev_video_ops mipid02_video_ops = {
777 .s_stream = mipid02_s_stream,
780 static const struct v4l2_subdev_pad_ops mipid02_pad_ops = {
781 .enum_mbus_code = mipid02_enum_mbus_code,
782 .get_fmt = mipid02_get_fmt,
783 .set_fmt = mipid02_set_fmt,
786 static const struct v4l2_subdev_ops mipid02_subdev_ops = {
787 .video = &mipid02_video_ops,
788 .pad = &mipid02_pad_ops,
791 static const struct media_entity_operations mipid02_subdev_entity_ops = {
792 .link_validate = v4l2_subdev_link_validate,
795 static int mipid02_async_bound(struct v4l2_async_notifier *notifier,
796 struct v4l2_subdev *s_subdev,
797 struct v4l2_async_subdev *asd)
799 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
800 struct i2c_client *client = bridge->i2c_client;
804 dev_dbg(&client->dev, "sensor_async_bound call %p", s_subdev);
806 source_pad = media_entity_get_fwnode_pad(&s_subdev->entity,
808 MEDIA_PAD_FL_SOURCE);
809 if (source_pad < 0) {
810 dev_err(&client->dev, "Couldn't find output pad for subdev %s\n",
815 ret = media_create_pad_link(&s_subdev->entity, source_pad,
816 &bridge->sd.entity, 0,
817 MEDIA_LNK_FL_ENABLED |
818 MEDIA_LNK_FL_IMMUTABLE);
820 dev_err(&client->dev, "Couldn't create media link %d", ret);
824 bridge->s_subdev = s_subdev;
829 static void mipid02_async_unbind(struct v4l2_async_notifier *notifier,
830 struct v4l2_subdev *s_subdev,
831 struct v4l2_async_subdev *asd)
833 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
835 bridge->s_subdev = NULL;
838 static const struct v4l2_async_notifier_operations mipid02_notifier_ops = {
839 .bound = mipid02_async_bound,
840 .unbind = mipid02_async_unbind,
843 static int mipid02_parse_rx_ep(struct mipid02_dev *bridge)
845 struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
846 struct i2c_client *client = bridge->i2c_client;
847 struct v4l2_async_subdev *asd;
848 struct device_node *ep_node;
851 /* parse rx (endpoint 0) */
852 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
855 dev_err(&client->dev, "unable to find port0 ep");
860 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
862 dev_err(&client->dev, "Could not parse v4l2 endpoint %d\n",
864 goto error_of_node_put;
867 /* do some sanity checks */
868 if (ep.bus.mipi_csi2.num_data_lanes > 2) {
869 dev_err(&client->dev, "max supported data lanes is 2 / got %d",
870 ep.bus.mipi_csi2.num_data_lanes);
872 goto error_of_node_put;
875 /* register it for later use */
878 /* register async notifier so we get noticed when sensor is connected */
879 v4l2_async_nf_init(&bridge->notifier);
880 asd = v4l2_async_nf_add_fwnode_remote(&bridge->notifier,
881 of_fwnode_handle(ep_node),
882 struct v4l2_async_subdev);
883 of_node_put(ep_node);
886 dev_err(&client->dev, "fail to register asd to notifier %ld",
890 bridge->notifier.ops = &mipid02_notifier_ops;
892 ret = v4l2_async_subdev_nf_register(&bridge->sd, &bridge->notifier);
894 v4l2_async_nf_cleanup(&bridge->notifier);
899 of_node_put(ep_node);
905 static int mipid02_parse_tx_ep(struct mipid02_dev *bridge)
907 struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_PARALLEL };
908 struct i2c_client *client = bridge->i2c_client;
909 struct device_node *ep_node;
912 /* parse tx (endpoint 2) */
913 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
916 dev_err(&client->dev, "unable to find port1 ep");
921 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
923 dev_err(&client->dev, "Could not parse v4l2 endpoint\n");
924 goto error_of_node_put;
927 of_node_put(ep_node);
933 of_node_put(ep_node);
939 static int mipid02_probe(struct i2c_client *client)
941 struct device *dev = &client->dev;
942 struct mipid02_dev *bridge;
946 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
950 init_format(&bridge->fmt);
952 bridge->i2c_client = client;
953 v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops);
955 /* got and check clock */
956 bridge->xclk = devm_clk_get(dev, "xclk");
957 if (IS_ERR(bridge->xclk)) {
958 dev_err(dev, "failed to get xclk\n");
959 return PTR_ERR(bridge->xclk);
962 clk_freq = clk_get_rate(bridge->xclk);
963 if (clk_freq < 6000000 || clk_freq > 27000000) {
964 dev_err(dev, "xclk freq must be in 6-27 Mhz range. got %d Hz\n",
969 bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset",
972 if (IS_ERR(bridge->reset_gpio)) {
973 dev_err(dev, "failed to get reset GPIO\n");
974 return PTR_ERR(bridge->reset_gpio);
977 ret = mipid02_get_regulators(bridge);
979 dev_err(dev, "failed to get regulators %d", ret);
983 mutex_init(&bridge->lock);
984 bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
985 bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
986 bridge->sd.entity.ops = &mipid02_subdev_entity_ops;
987 bridge->pad[0].flags = MEDIA_PAD_FL_SINK;
988 bridge->pad[1].flags = MEDIA_PAD_FL_SINK;
989 bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE;
990 ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB,
993 dev_err(&client->dev, "pads init failed %d", ret);
997 /* enable clock, power and reset device if available */
998 ret = mipid02_set_power_on(bridge);
1000 goto entity_cleanup;
1002 ret = mipid02_detect(bridge);
1004 dev_err(&client->dev, "failed to detect mipid02 %d", ret);
1008 ret = mipid02_parse_tx_ep(bridge);
1010 dev_err(&client->dev, "failed to parse tx %d", ret);
1014 ret = mipid02_parse_rx_ep(bridge);
1016 dev_err(&client->dev, "failed to parse rx %d", ret);
1020 ret = v4l2_async_register_subdev(&bridge->sd);
1022 dev_err(&client->dev, "v4l2_async_register_subdev failed %d",
1024 goto unregister_notifier;
1027 dev_info(&client->dev, "mipid02 device probe successfully");
1031 unregister_notifier:
1032 v4l2_async_nf_unregister(&bridge->notifier);
1033 v4l2_async_nf_cleanup(&bridge->notifier);
1035 mipid02_set_power_off(bridge);
1037 media_entity_cleanup(&bridge->sd.entity);
1039 mutex_destroy(&bridge->lock);
1044 static int mipid02_remove(struct i2c_client *client)
1046 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1047 struct mipid02_dev *bridge = to_mipid02_dev(sd);
1049 v4l2_async_nf_unregister(&bridge->notifier);
1050 v4l2_async_nf_cleanup(&bridge->notifier);
1051 v4l2_async_unregister_subdev(&bridge->sd);
1052 mipid02_set_power_off(bridge);
1053 media_entity_cleanup(&bridge->sd.entity);
1054 mutex_destroy(&bridge->lock);
1059 static const struct of_device_id mipid02_dt_ids[] = {
1060 { .compatible = "st,st-mipid02" },
1063 MODULE_DEVICE_TABLE(of, mipid02_dt_ids);
1065 static struct i2c_driver mipid02_i2c_driver = {
1067 .name = "st-mipid02",
1068 .of_match_table = mipid02_dt_ids,
1070 .probe_new = mipid02_probe,
1071 .remove = mipid02_remove,
1074 module_i2c_driver(mipid02_i2c_driver);
1076 MODULE_AUTHOR("Mickael Guene <mickael.guene@st.com>");
1077 MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver");
1078 MODULE_LICENSE("GPL v2");