2 * Samsung LSI S5C73M3 8M pixel camera driver
4 * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
6 * Andrzej Hajda <a.hajda@samsung.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/sizes.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/media.h>
25 #include <linux/module.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/slab.h>
28 #include <linux/spi/spi.h>
29 #include <linux/videodev2.h>
30 #include <media/media-entity.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-subdev.h>
34 #include <media/v4l2-mediabus.h>
35 #include <media/s5c73m3.h>
40 module_param_named(debug, s5c73m3_dbg, int, 0644);
42 static int boot_from_rom = 1;
43 module_param(boot_from_rom, int, 0644);
46 module_param(update_fw, int, 0644);
48 #define S5C73M3_EMBEDDED_DATA_MAXLEN SZ_4K
50 static const char * const s5c73m3_supply_names[S5C73M3_MAX_SUPPLIES] = {
51 "vdd-int", /* Digital Core supply (1.2V), CAM_ISP_CORE_1.2V */
52 "vdda", /* Analog Core supply (1.2V), CAM_SENSOR_CORE_1.2V */
53 "vdd-reg", /* Regulator input supply (2.8V), CAM_SENSOR_A2.8V */
54 "vddio-host", /* Digital Host I/O power supply (1.8V...2.8V),
55 CAM_ISP_SENSOR_1.8V */
56 "vddio-cis", /* Digital CIS I/O power (1.2V...1.8V),
58 "vdd-af", /* Lens, CAM_AF_2.8V */
61 static const struct s5c73m3_frame_size s5c73m3_isp_resolutions[] = {
62 { 320, 240, COMM_CHG_MODE_YUV_320_240 },
63 { 352, 288, COMM_CHG_MODE_YUV_352_288 },
64 { 640, 480, COMM_CHG_MODE_YUV_640_480 },
65 { 880, 720, COMM_CHG_MODE_YUV_880_720 },
66 { 960, 720, COMM_CHG_MODE_YUV_960_720 },
67 { 1008, 672, COMM_CHG_MODE_YUV_1008_672 },
68 { 1184, 666, COMM_CHG_MODE_YUV_1184_666 },
69 { 1280, 720, COMM_CHG_MODE_YUV_1280_720 },
70 { 1536, 864, COMM_CHG_MODE_YUV_1536_864 },
71 { 1600, 1200, COMM_CHG_MODE_YUV_1600_1200 },
72 { 1632, 1224, COMM_CHG_MODE_YUV_1632_1224 },
73 { 1920, 1080, COMM_CHG_MODE_YUV_1920_1080 },
74 { 1920, 1440, COMM_CHG_MODE_YUV_1920_1440 },
75 { 2304, 1296, COMM_CHG_MODE_YUV_2304_1296 },
76 { 3264, 2448, COMM_CHG_MODE_YUV_3264_2448 },
79 static const struct s5c73m3_frame_size s5c73m3_jpeg_resolutions[] = {
80 { 640, 480, COMM_CHG_MODE_JPEG_640_480 },
81 { 800, 450, COMM_CHG_MODE_JPEG_800_450 },
82 { 800, 600, COMM_CHG_MODE_JPEG_800_600 },
83 { 1024, 768, COMM_CHG_MODE_JPEG_1024_768 },
84 { 1280, 720, COMM_CHG_MODE_JPEG_1280_720 },
85 { 1280, 960, COMM_CHG_MODE_JPEG_1280_960 },
86 { 1600, 900, COMM_CHG_MODE_JPEG_1600_900 },
87 { 1600, 1200, COMM_CHG_MODE_JPEG_1600_1200 },
88 { 2048, 1152, COMM_CHG_MODE_JPEG_2048_1152 },
89 { 2048, 1536, COMM_CHG_MODE_JPEG_2048_1536 },
90 { 2560, 1440, COMM_CHG_MODE_JPEG_2560_1440 },
91 { 2560, 1920, COMM_CHG_MODE_JPEG_2560_1920 },
92 { 3264, 1836, COMM_CHG_MODE_JPEG_3264_1836 },
93 { 3264, 2176, COMM_CHG_MODE_JPEG_3264_2176 },
94 { 3264, 2448, COMM_CHG_MODE_JPEG_3264_2448 },
97 static const struct s5c73m3_frame_size * const s5c73m3_resolutions[] = {
98 [RES_ISP] = s5c73m3_isp_resolutions,
99 [RES_JPEG] = s5c73m3_jpeg_resolutions
102 static const int s5c73m3_resolutions_len[] = {
103 [RES_ISP] = ARRAY_SIZE(s5c73m3_isp_resolutions),
104 [RES_JPEG] = ARRAY_SIZE(s5c73m3_jpeg_resolutions)
107 static const struct s5c73m3_interval s5c73m3_intervals[] = {
108 { COMM_FRAME_RATE_FIXED_7FPS, {142857, 1000000}, {3264, 2448} },
109 { COMM_FRAME_RATE_FIXED_15FPS, {66667, 1000000}, {3264, 2448} },
110 { COMM_FRAME_RATE_FIXED_20FPS, {50000, 1000000}, {2304, 1296} },
111 { COMM_FRAME_RATE_FIXED_30FPS, {33333, 1000000}, {2304, 1296} },
114 #define S5C73M3_DEFAULT_FRAME_INTERVAL 3 /* 30 fps */
116 static void s5c73m3_fill_mbus_fmt(struct v4l2_mbus_framefmt *mf,
117 const struct s5c73m3_frame_size *fs,
120 mf->width = fs->width;
121 mf->height = fs->height;
123 mf->colorspace = V4L2_COLORSPACE_JPEG;
124 mf->field = V4L2_FIELD_NONE;
127 static int s5c73m3_i2c_write(struct i2c_client *client, u16 addr, u16 data)
129 u8 buf[4] = { addr >> 8, addr & 0xff, data >> 8, data & 0xff };
131 int ret = i2c_master_send(client, buf, sizeof(buf));
133 v4l_dbg(4, s5c73m3_dbg, client, "%s: addr 0x%04x, data 0x%04x\n",
134 __func__, addr, data);
139 return ret < 0 ? ret : -EREMOTEIO;
142 static int s5c73m3_i2c_read(struct i2c_client *client, u16 addr, u16 *data)
145 u8 rbuf[2], wbuf[2] = { addr >> 8, addr & 0xff };
146 struct i2c_msg msg[2] = {
148 .addr = client->addr,
153 .addr = client->addr,
160 * Issue repeated START after writing 2 address bytes and
161 * just one STOP only after reading the data bytes.
163 ret = i2c_transfer(client->adapter, msg, 2);
165 *data = be16_to_cpup((u16 *)rbuf);
166 v4l2_dbg(4, s5c73m3_dbg, client,
167 "%s: addr: 0x%04x, data: 0x%04x\n",
168 __func__, addr, *data);
172 v4l2_err(client, "I2C read failed: addr: %04x, (%d)\n", addr, ret);
174 return ret >= 0 ? -EREMOTEIO : ret;
177 int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data)
179 struct i2c_client *client = state->i2c_client;
182 if ((addr ^ state->i2c_write_address) & 0xffff0000) {
183 ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRH, addr >> 16);
185 state->i2c_write_address = 0;
190 if ((addr ^ state->i2c_write_address) & 0xffff) {
191 ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRL, addr & 0xffff);
193 state->i2c_write_address = 0;
198 state->i2c_write_address = addr;
200 ret = s5c73m3_i2c_write(client, REG_CMDBUF_ADDR, data);
204 state->i2c_write_address += 2;
209 int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data)
211 struct i2c_client *client = state->i2c_client;
214 if ((addr ^ state->i2c_read_address) & 0xffff0000) {
215 ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRH, addr >> 16);
217 state->i2c_read_address = 0;
222 if ((addr ^ state->i2c_read_address) & 0xffff) {
223 ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRL, addr & 0xffff);
225 state->i2c_read_address = 0;
230 state->i2c_read_address = addr;
232 ret = s5c73m3_i2c_read(client, REG_CMDBUF_ADDR, data);
236 state->i2c_read_address += 2;
241 static int s5c73m3_check_status(struct s5c73m3 *state, unsigned int value)
243 unsigned long start = jiffies;
244 unsigned long end = start + msecs_to_jiffies(2000);
249 while (time_is_after_jiffies(end)) {
250 ret = s5c73m3_read(state, REG_STATUS, &status);
251 if (ret < 0 || status == value)
253 usleep_range(500, 1000);
258 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
259 "status check took %dms\n",
260 jiffies_to_msecs(jiffies - start));
262 if (ret == 0 && status != value) {
264 u16 i2c_seq_status = 0;
266 s5c73m3_read(state, REG_I2C_STATUS, &i2c_status);
267 s5c73m3_read(state, REG_I2C_SEQ_STATUS, &i2c_seq_status);
269 v4l2_err(&state->sensor_sd,
270 "wrong status %#x, expected: %#x, i2c_status: %#x/%#x\n",
271 status, value, i2c_status, i2c_seq_status);
279 int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data)
283 ret = s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
287 ret = s5c73m3_write(state, 0x00095000, command);
291 ret = s5c73m3_write(state, 0x00095002, data);
295 return s5c73m3_write(state, REG_STATUS, 0x0001);
298 static int s5c73m3_isp_comm_result(struct s5c73m3 *state, u16 command,
301 return s5c73m3_read(state, COMM_RESULT_OFFSET + command, data);
304 static int s5c73m3_set_af_softlanding(struct s5c73m3 *state)
306 unsigned long start = jiffies;
312 ret = s5c73m3_isp_command(state, COMM_AF_SOFTLANDING,
313 COMM_AF_SOFTLANDING_ON);
315 v4l2_info(&state->sensor_sd, "AF soft-landing failed\n");
320 ret = s5c73m3_isp_comm_result(state, COMM_AF_SOFTLANDING,
326 if (af_softlanding == COMM_AF_SOFTLANDING_RES_COMPLETE) {
338 v4l2_info(&state->sensor_sd, "AF soft-landing %s after %dms\n",
339 msg, jiffies_to_msecs(jiffies - start));
344 static int s5c73m3_load_fw(struct v4l2_subdev *sd)
346 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
347 struct i2c_client *client = state->i2c_client;
348 const struct firmware *fw;
352 snprintf(fw_name, sizeof(fw_name), "SlimISP_%.2s.bin",
353 state->fw_file_version);
354 ret = request_firmware(&fw, fw_name, &client->dev);
356 v4l2_err(sd, "Firmware request failed (%s)\n", fw_name);
360 v4l2_info(sd, "Loading firmware (%s, %zu B)\n", fw_name, fw->size);
362 ret = s5c73m3_spi_write(state, fw->data, fw->size, 64);
365 state->isp_ready = 1;
367 v4l2_err(sd, "SPI write failed\n");
369 release_firmware(fw);
374 static int s5c73m3_set_frame_size(struct s5c73m3 *state)
376 const struct s5c73m3_frame_size *prev_size =
377 state->sensor_pix_size[RES_ISP];
378 const struct s5c73m3_frame_size *cap_size =
379 state->sensor_pix_size[RES_JPEG];
380 unsigned int chg_mode;
382 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
383 "Preview size: %dx%d, reg_val: 0x%x\n",
384 prev_size->width, prev_size->height, prev_size->reg_val);
386 chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW;
388 if (state->mbus_code == S5C73M3_JPEG_FMT) {
389 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
390 "Capture size: %dx%d, reg_val: 0x%x\n",
391 cap_size->width, cap_size->height, cap_size->reg_val);
392 chg_mode |= cap_size->reg_val;
395 return s5c73m3_isp_command(state, COMM_CHG_MODE, chg_mode);
398 static int s5c73m3_set_frame_rate(struct s5c73m3 *state)
402 if (state->ctrls.stabilization->val)
405 if (WARN_ON(state->fiv == NULL))
408 ret = s5c73m3_isp_command(state, COMM_FRAME_RATE, state->fiv->fps_reg);
410 state->apply_fiv = 0;
415 static int __s5c73m3_s_stream(struct s5c73m3 *state, struct v4l2_subdev *sd,
421 if (on && state->apply_fmt) {
422 if (state->mbus_code == S5C73M3_JPEG_FMT)
423 mode = COMM_IMG_OUTPUT_INTERLEAVED;
425 mode = COMM_IMG_OUTPUT_YUV;
427 ret = s5c73m3_isp_command(state, COMM_IMG_OUTPUT, mode);
429 ret = s5c73m3_set_frame_size(state);
432 state->apply_fmt = 0;
435 ret = s5c73m3_isp_command(state, COMM_SENSOR_STREAMING, !!on);
439 state->streaming = !!on;
444 if (state->apply_fiv) {
445 ret = s5c73m3_set_frame_rate(state);
447 v4l2_err(sd, "Error setting frame rate(%d)\n", ret);
450 return s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
453 static int s5c73m3_oif_s_stream(struct v4l2_subdev *sd, int on)
455 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
458 mutex_lock(&state->lock);
459 ret = __s5c73m3_s_stream(state, sd, on);
460 mutex_unlock(&state->lock);
465 static int s5c73m3_system_status_wait(struct s5c73m3 *state, u32 value,
466 unsigned int delay, unsigned int steps)
470 while (steps-- > 0) {
471 int ret = s5c73m3_read(state, 0x30100010, ®);
476 usleep_range(delay, delay + 25);
481 static int s5c73m3_read_fw_version(struct s5c73m3 *state)
483 struct v4l2_subdev *sd = &state->sensor_sd;
488 offset = state->isp_ready ? 0x60 : 0;
490 for (i = 0; i < S5C73M3_SENSOR_FW_LEN / 2; i++) {
491 ret = s5c73m3_read(state, offset + i * 2, data);
494 state->sensor_fw[i * 2] = (char)(*data & 0xff);
495 state->sensor_fw[i * 2 + 1] = (char)(*data >> 8);
497 state->sensor_fw[S5C73M3_SENSOR_FW_LEN] = '\0';
500 for (i = 0; i < S5C73M3_SENSOR_TYPE_LEN / 2; i++) {
501 ret = s5c73m3_read(state, offset + 6 + i * 2, data);
504 state->sensor_type[i * 2] = (char)(*data & 0xff);
505 state->sensor_type[i * 2 + 1] = (char)(*data >> 8);
507 state->sensor_type[S5C73M3_SENSOR_TYPE_LEN] = '\0';
509 ret = s5c73m3_read(state, offset + 0x14, data);
511 ret = s5c73m3_read(state, offset + 0x16, data + 1);
513 state->fw_size = data[0] + (data[1] << 16);
516 v4l2_info(sd, "Sensor type: %s, FW version: %s\n",
517 state->sensor_type, state->sensor_fw);
521 static int s5c73m3_fw_update_from(struct s5c73m3 *state)
523 struct v4l2_subdev *sd = &state->sensor_sd;
524 u16 status = COMM_FW_UPDATE_NOT_READY;
528 v4l2_warn(sd, "Updating F-ROM firmware.\n");
530 if (status == COMM_FW_UPDATE_NOT_READY) {
531 ret = s5c73m3_isp_command(state, COMM_FW_UPDATE, 0);
536 ret = s5c73m3_read(state, 0x00095906, &status);
540 case COMM_FW_UPDATE_FAIL:
541 v4l2_warn(sd, "Updating F-ROM firmware failed.\n");
543 case COMM_FW_UPDATE_SUCCESS:
544 v4l2_warn(sd, "Updating F-ROM firmware finished.\n");
549 } while (count < 500);
551 v4l2_warn(sd, "Updating F-ROM firmware timed-out.\n");
555 static int s5c73m3_spi_boot(struct s5c73m3 *state, bool load_fw)
557 struct v4l2_subdev *sd = &state->sensor_sd;
561 ret = s5c73m3_write(state, 0x30000004, 0xffff);
565 usleep_range(400, 500);
567 /* Check booting status */
568 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
570 v4l2_err(sd, "booting failed: %d\n", ret);
574 /* P,M,S and Boot Mode */
575 ret = s5c73m3_write(state, 0x30100014, 0x2146);
579 ret = s5c73m3_write(state, 0x30100010, 0x210c);
583 usleep_range(200, 250);
585 /* Check SPI status */
586 ret = s5c73m3_system_status_wait(state, 0x210d, 100, 300);
588 v4l2_err(sd, "SPI not ready: %d\n", ret);
590 /* Firmware download over SPI */
595 ret = s5c73m3_write(state, 0x30000004, 0xfffd);
600 ret = s5c73m3_write(state, 0x301000a4, 0x0183);
605 ret = s5c73m3_write(state, 0x30000004, 0xffff);
606 if (ret < 0 || !load_fw)
609 ret = s5c73m3_read_fw_version(state);
613 if (load_fw && update_fw) {
614 ret = s5c73m3_fw_update_from(state);
621 static int s5c73m3_set_timing_register_for_vdd(struct s5c73m3 *state)
623 static const u32 regs[][2] = {
624 { 0x30100018, 0x0618 },
625 { 0x3010001c, 0x10c1 },
626 { 0x30100020, 0x249e }
631 for (i = 0; i < ARRAY_SIZE(regs); i++) {
632 ret = s5c73m3_write(state, regs[i][0], regs[i][1]);
640 static void s5c73m3_set_fw_file_version(struct s5c73m3 *state)
642 switch (state->sensor_fw[0]) {
645 state->fw_file_version[0] = 'G';
649 state->fw_file_version[0] = 'Z';
653 switch (state->sensor_fw[1]) {
655 state->fw_file_version[1] = state->sensor_fw[1];
660 static int s5c73m3_get_fw_version(struct s5c73m3 *state)
662 struct v4l2_subdev *sd = &state->sensor_sd;
666 ret = s5c73m3_write(state, 0x30000004, 0xffff);
669 usleep_range(400, 500);
671 /* Check booting status */
672 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
675 v4l2_err(sd, "%s: booting failed: %d\n", __func__, ret);
679 /* Change I/O Driver Current in order to read from F-ROM */
680 ret = s5c73m3_write(state, 0x30100120, 0x0820);
681 ret = s5c73m3_write(state, 0x30100124, 0x0820);
684 ret = s5c73m3_write(state, 0x00010418, 0x0008);
686 /* P,M,S and Boot Mode */
687 ret = s5c73m3_write(state, 0x30100014, 0x2146);
690 ret = s5c73m3_write(state, 0x30100010, 0x230c);
694 usleep_range(200, 250);
696 /* Check SPI status */
697 ret = s5c73m3_system_status_wait(state, 0x230e, 100, 300);
699 v4l2_err(sd, "SPI not ready: %d\n", ret);
702 ret = s5c73m3_write(state, 0x30000004, 0xfffd);
707 ret = s5c73m3_write(state, 0x301000a4, 0x0183);
711 s5c73m3_set_timing_register_for_vdd(state);
713 ret = s5c73m3_read_fw_version(state);
715 s5c73m3_set_fw_file_version(state);
720 static int s5c73m3_rom_boot(struct s5c73m3 *state, bool load_fw)
722 static const u32 boot_regs[][2] = {
723 { 0x3100010c, 0x0044 },
724 { 0x31000108, 0x000d },
725 { 0x31000304, 0x0001 },
726 { 0x00010000, 0x5800 },
727 { 0x00010002, 0x0002 },
728 { 0x31000000, 0x0001 },
729 { 0x30100014, 0x1b85 },
730 { 0x30100010, 0x230c }
732 struct v4l2_subdev *sd = &state->sensor_sd;
736 ret = s5c73m3_write(state, 0x30000004, 0xffff);
739 usleep_range(400, 450);
741 /* Check booting status */
742 ret = s5c73m3_system_status_wait(state, 0x0c, 100, 4);
744 v4l2_err(sd, "Booting failed: %d\n", ret);
748 for (i = 0; i < ARRAY_SIZE(boot_regs); i++) {
749 ret = s5c73m3_write(state, boot_regs[i][0], boot_regs[i][1]);
755 /* Check the binary read status */
756 ret = s5c73m3_system_status_wait(state, 0x230e, 1000, 150);
758 v4l2_err(sd, "Binary read failed: %d\n", ret);
763 ret = s5c73m3_write(state, 0x30000004, 0xfffd);
767 ret = s5c73m3_write(state, 0x301000a4, 0x0183);
771 ret = s5c73m3_write(state, 0x30000004, 0xffff);
775 state->isp_ready = 1;
777 return s5c73m3_read_fw_version(state);
780 static int s5c73m3_isp_init(struct s5c73m3 *state)
784 state->i2c_read_address = 0;
785 state->i2c_write_address = 0;
787 ret = s5c73m3_i2c_write(state->i2c_client, AHB_MSB_ADDR_PTR, 0x3310);
792 return s5c73m3_rom_boot(state, true);
794 return s5c73m3_spi_boot(state, true);
797 static const struct s5c73m3_frame_size *s5c73m3_find_frame_size(
798 struct v4l2_mbus_framefmt *fmt,
799 enum s5c73m3_resolution_types idx)
801 const struct s5c73m3_frame_size *fs;
802 const struct s5c73m3_frame_size *best_fs;
803 int best_dist = INT_MAX;
806 fs = s5c73m3_resolutions[idx];
808 for (i = 0; i < s5c73m3_resolutions_len[idx]; ++i) {
809 int dist = abs(fs->width - fmt->width) +
810 abs(fs->height - fmt->height);
811 if (dist < best_dist) {
821 static void s5c73m3_oif_try_format(struct s5c73m3 *state,
822 struct v4l2_subdev_fh *fh,
823 struct v4l2_subdev_format *fmt,
824 const struct s5c73m3_frame_size **fs)
830 *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
831 code = S5C73M3_ISP_FMT;
834 *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
835 code = S5C73M3_JPEG_FMT;
839 if (fmt->format.code == S5C73M3_JPEG_FMT)
840 code = S5C73M3_JPEG_FMT;
842 code = S5C73M3_ISP_FMT;
844 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
845 *fs = state->oif_pix_size[RES_ISP];
847 *fs = s5c73m3_find_frame_size(
848 v4l2_subdev_get_try_format(fh,
854 s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
857 static void s5c73m3_try_format(struct s5c73m3 *state,
858 struct v4l2_subdev_fh *fh,
859 struct v4l2_subdev_format *fmt,
860 const struct s5c73m3_frame_size **fs)
864 if (fmt->pad == S5C73M3_ISP_PAD) {
865 *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
866 code = S5C73M3_ISP_FMT;
868 *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
869 code = S5C73M3_JPEG_FMT;
872 s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
875 static int s5c73m3_oif_g_frame_interval(struct v4l2_subdev *sd,
876 struct v4l2_subdev_frame_interval *fi)
878 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
880 if (fi->pad != OIF_SOURCE_PAD)
883 mutex_lock(&state->lock);
884 fi->interval = state->fiv->interval;
885 mutex_unlock(&state->lock);
890 static int __s5c73m3_set_frame_interval(struct s5c73m3 *state,
891 struct v4l2_subdev_frame_interval *fi)
893 const struct s5c73m3_frame_size *prev_size =
894 state->sensor_pix_size[RES_ISP];
895 const struct s5c73m3_interval *fiv = &s5c73m3_intervals[0];
896 unsigned int ret, min_err = UINT_MAX;
897 unsigned int i, fr_time;
899 if (fi->interval.denominator == 0)
902 fr_time = fi->interval.numerator * 1000 / fi->interval.denominator;
904 for (i = 0; i < ARRAY_SIZE(s5c73m3_intervals); i++) {
905 const struct s5c73m3_interval *iv = &s5c73m3_intervals[i];
907 if (prev_size->width > iv->size.width ||
908 prev_size->height > iv->size.height)
911 ret = abs(iv->interval.numerator / 1000 - fr_time);
919 v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
920 "Changed frame interval to %u us\n", fiv->interval.numerator);
924 static int s5c73m3_oif_s_frame_interval(struct v4l2_subdev *sd,
925 struct v4l2_subdev_frame_interval *fi)
927 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
930 if (fi->pad != OIF_SOURCE_PAD)
933 v4l2_dbg(1, s5c73m3_dbg, sd, "Setting %d/%d frame interval\n",
934 fi->interval.numerator, fi->interval.denominator);
936 mutex_lock(&state->lock);
938 ret = __s5c73m3_set_frame_interval(state, fi);
940 if (state->streaming)
941 ret = s5c73m3_set_frame_rate(state);
943 state->apply_fiv = 1;
945 mutex_unlock(&state->lock);
949 static int s5c73m3_oif_enum_frame_interval(struct v4l2_subdev *sd,
950 struct v4l2_subdev_fh *fh,
951 struct v4l2_subdev_frame_interval_enum *fie)
953 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
954 const struct s5c73m3_interval *fi;
957 if (fie->pad != OIF_SOURCE_PAD)
959 if (fie->index >= ARRAY_SIZE(s5c73m3_intervals))
962 mutex_lock(&state->lock);
963 fi = &s5c73m3_intervals[fie->index];
964 if (fie->width > fi->size.width || fie->height > fi->size.height)
967 fie->interval = fi->interval;
968 mutex_unlock(&state->lock);
973 static int s5c73m3_oif_get_pad_code(int pad, int index)
975 if (pad == OIF_SOURCE_PAD) {
978 return (index == 0) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
984 return (pad == OIF_ISP_PAD) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
987 static int s5c73m3_get_fmt(struct v4l2_subdev *sd,
988 struct v4l2_subdev_fh *fh,
989 struct v4l2_subdev_format *fmt)
991 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
992 const struct s5c73m3_frame_size *fs;
995 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
996 fmt->format = *v4l2_subdev_get_try_format(fh, fmt->pad);
1000 mutex_lock(&state->lock);
1003 case S5C73M3_ISP_PAD:
1004 code = S5C73M3_ISP_FMT;
1005 fs = state->sensor_pix_size[RES_ISP];
1007 case S5C73M3_JPEG_PAD:
1008 code = S5C73M3_JPEG_FMT;
1009 fs = state->sensor_pix_size[RES_JPEG];
1012 mutex_unlock(&state->lock);
1015 s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
1017 mutex_unlock(&state->lock);
1021 static int s5c73m3_oif_get_fmt(struct v4l2_subdev *sd,
1022 struct v4l2_subdev_fh *fh,
1023 struct v4l2_subdev_format *fmt)
1025 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1026 const struct s5c73m3_frame_size *fs;
1029 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1030 fmt->format = *v4l2_subdev_get_try_format(fh, fmt->pad);
1034 mutex_lock(&state->lock);
1038 code = S5C73M3_ISP_FMT;
1039 fs = state->oif_pix_size[RES_ISP];
1042 code = S5C73M3_JPEG_FMT;
1043 fs = state->oif_pix_size[RES_JPEG];
1045 case OIF_SOURCE_PAD:
1046 code = state->mbus_code;
1047 fs = state->oif_pix_size[RES_ISP];
1050 mutex_unlock(&state->lock);
1053 s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
1055 mutex_unlock(&state->lock);
1059 static int s5c73m3_set_fmt(struct v4l2_subdev *sd,
1060 struct v4l2_subdev_fh *fh,
1061 struct v4l2_subdev_format *fmt)
1063 const struct s5c73m3_frame_size *frame_size = NULL;
1064 struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
1065 struct v4l2_mbus_framefmt *mf;
1068 mutex_lock(&state->lock);
1070 s5c73m3_try_format(state, fh, fmt, &frame_size);
1072 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1073 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1077 case S5C73M3_ISP_PAD:
1078 state->sensor_pix_size[RES_ISP] = frame_size;
1080 case S5C73M3_JPEG_PAD:
1081 state->sensor_pix_size[RES_JPEG] = frame_size;
1087 if (state->streaming)
1090 state->apply_fmt = 1;
1093 mutex_unlock(&state->lock);
1098 static int s5c73m3_oif_set_fmt(struct v4l2_subdev *sd,
1099 struct v4l2_subdev_fh *fh,
1100 struct v4l2_subdev_format *fmt)
1102 const struct s5c73m3_frame_size *frame_size = NULL;
1103 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1104 struct v4l2_mbus_framefmt *mf;
1107 mutex_lock(&state->lock);
1109 s5c73m3_oif_try_format(state, fh, fmt, &frame_size);
1111 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1112 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1114 if (fmt->pad == OIF_ISP_PAD) {
1115 mf = v4l2_subdev_get_try_format(fh, OIF_SOURCE_PAD);
1116 mf->width = fmt->format.width;
1117 mf->height = fmt->format.height;
1122 state->oif_pix_size[RES_ISP] = frame_size;
1125 state->oif_pix_size[RES_JPEG] = frame_size;
1127 case OIF_SOURCE_PAD:
1128 state->mbus_code = fmt->format.code;
1134 if (state->streaming)
1137 state->apply_fmt = 1;
1140 mutex_unlock(&state->lock);
1145 static int s5c73m3_oif_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1146 struct v4l2_mbus_frame_desc *fd)
1148 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1151 if (pad != OIF_SOURCE_PAD || fd == NULL)
1154 mutex_lock(&state->lock);
1155 fd->num_entries = 2;
1156 for (i = 0; i < fd->num_entries; i++)
1157 fd->entry[i] = state->frame_desc.entry[i];
1158 mutex_unlock(&state->lock);
1163 static int s5c73m3_oif_set_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1164 struct v4l2_mbus_frame_desc *fd)
1166 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1167 struct v4l2_mbus_frame_desc *frame_desc = &state->frame_desc;
1170 if (pad != OIF_SOURCE_PAD || fd == NULL)
1173 fd->entry[0].length = 10 * SZ_1M;
1174 fd->entry[1].length = max_t(u32, fd->entry[1].length,
1175 S5C73M3_EMBEDDED_DATA_MAXLEN);
1176 fd->num_entries = 2;
1178 mutex_lock(&state->lock);
1179 for (i = 0; i < fd->num_entries; i++)
1180 frame_desc->entry[i] = fd->entry[i];
1181 mutex_unlock(&state->lock);
1186 static int s5c73m3_enum_mbus_code(struct v4l2_subdev *sd,
1187 struct v4l2_subdev_fh *fh,
1188 struct v4l2_subdev_mbus_code_enum *code)
1190 static const int codes[] = {
1191 [S5C73M3_ISP_PAD] = S5C73M3_ISP_FMT,
1192 [S5C73M3_JPEG_PAD] = S5C73M3_JPEG_FMT};
1194 if (code->index > 0 || code->pad >= S5C73M3_NUM_PADS)
1197 code->code = codes[code->pad];
1202 static int s5c73m3_oif_enum_mbus_code(struct v4l2_subdev *sd,
1203 struct v4l2_subdev_fh *fh,
1204 struct v4l2_subdev_mbus_code_enum *code)
1208 ret = s5c73m3_oif_get_pad_code(code->pad, code->index);
1217 static int s5c73m3_enum_frame_size(struct v4l2_subdev *sd,
1218 struct v4l2_subdev_fh *fh,
1219 struct v4l2_subdev_frame_size_enum *fse)
1223 if (fse->pad == S5C73M3_ISP_PAD) {
1224 if (fse->code != S5C73M3_ISP_FMT)
1228 if (fse->code != S5C73M3_JPEG_FMT)
1233 if (fse->index >= s5c73m3_resolutions_len[idx])
1236 fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
1237 fse->max_width = fse->min_width;
1238 fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
1239 fse->min_height = fse->max_height;
1244 static int s5c73m3_oif_enum_frame_size(struct v4l2_subdev *sd,
1245 struct v4l2_subdev_fh *fh,
1246 struct v4l2_subdev_frame_size_enum *fse)
1250 if (fse->pad == OIF_SOURCE_PAD) {
1254 switch (fse->code) {
1255 case S5C73M3_JPEG_FMT:
1256 case S5C73M3_ISP_FMT: {
1257 struct v4l2_mbus_framefmt *mf =
1258 v4l2_subdev_get_try_format(fh, OIF_ISP_PAD);
1260 fse->max_width = fse->min_width = mf->width;
1261 fse->max_height = fse->min_height = mf->height;
1269 if (fse->code != s5c73m3_oif_get_pad_code(fse->pad, 0))
1272 if (fse->pad == OIF_JPEG_PAD)
1277 if (fse->index >= s5c73m3_resolutions_len[idx])
1280 fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
1281 fse->max_width = fse->min_width;
1282 fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
1283 fse->min_height = fse->max_height;
1288 static int s5c73m3_oif_log_status(struct v4l2_subdev *sd)
1290 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1292 v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
1294 v4l2_info(sd, "power: %d, apply_fmt: %d\n", state->power,
1300 static int s5c73m3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1302 struct v4l2_mbus_framefmt *mf;
1304 mf = v4l2_subdev_get_try_format(fh, S5C73M3_ISP_PAD);
1305 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
1308 mf = v4l2_subdev_get_try_format(fh, S5C73M3_JPEG_PAD);
1309 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
1315 static int s5c73m3_oif_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1317 struct v4l2_mbus_framefmt *mf;
1319 mf = v4l2_subdev_get_try_format(fh, OIF_ISP_PAD);
1320 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
1323 mf = v4l2_subdev_get_try_format(fh, OIF_JPEG_PAD);
1324 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
1327 mf = v4l2_subdev_get_try_format(fh, OIF_SOURCE_PAD);
1328 s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
1333 static int s5c73m3_gpio_set_value(struct s5c73m3 *priv, int id, u32 val)
1335 if (!gpio_is_valid(priv->gpio[id].gpio))
1337 gpio_set_value(priv->gpio[id].gpio, !!val);
1341 static int s5c73m3_gpio_assert(struct s5c73m3 *priv, int id)
1343 return s5c73m3_gpio_set_value(priv, id, priv->gpio[id].level);
1346 static int s5c73m3_gpio_deassert(struct s5c73m3 *priv, int id)
1348 return s5c73m3_gpio_set_value(priv, id, !priv->gpio[id].level);
1351 static int __s5c73m3_power_on(struct s5c73m3 *state)
1355 for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++) {
1356 ret = regulator_enable(state->supplies[i].consumer);
1361 s5c73m3_gpio_deassert(state, STBY);
1362 usleep_range(100, 200);
1364 s5c73m3_gpio_deassert(state, RST);
1365 usleep_range(50, 100);
1369 for (--i; i >= 0; i--)
1370 regulator_disable(state->supplies[i].consumer);
1374 static int __s5c73m3_power_off(struct s5c73m3 *state)
1378 if (s5c73m3_gpio_assert(state, RST))
1379 usleep_range(10, 50);
1381 if (s5c73m3_gpio_assert(state, STBY))
1382 usleep_range(100, 200);
1383 state->streaming = 0;
1384 state->isp_ready = 0;
1386 for (i = S5C73M3_MAX_SUPPLIES - 1; i >= 0; i--) {
1387 ret = regulator_disable(state->supplies[i].consumer);
1393 for (++i; i < S5C73M3_MAX_SUPPLIES; i++) {
1394 int r = regulator_enable(state->supplies[i].consumer);
1396 v4l2_err(&state->oif_sd, "Failed to reenable %s: %d\n",
1397 state->supplies[i].supply, r);
1402 static int s5c73m3_oif_set_power(struct v4l2_subdev *sd, int on)
1404 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1407 mutex_lock(&state->lock);
1409 if (on && !state->power) {
1410 ret = __s5c73m3_power_on(state);
1412 ret = s5c73m3_isp_init(state);
1414 state->apply_fiv = 1;
1415 state->apply_fmt = 1;
1417 } else if (!on == state->power) {
1418 ret = s5c73m3_set_af_softlanding(state);
1420 ret = __s5c73m3_power_off(state);
1422 v4l2_err(sd, "Soft landing lens failed\n");
1425 state->power += on ? 1 : -1;
1427 v4l2_dbg(1, s5c73m3_dbg, sd, "%s: power: %d\n",
1428 __func__, state->power);
1430 mutex_unlock(&state->lock);
1434 static int s5c73m3_oif_registered(struct v4l2_subdev *sd)
1436 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1439 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->sensor_sd);
1441 v4l2_err(sd->v4l2_dev, "Failed to register %s\n",
1442 state->oif_sd.name);
1446 ret = media_entity_create_link(&state->sensor_sd.entity,
1447 S5C73M3_ISP_PAD, &state->oif_sd.entity, OIF_ISP_PAD,
1448 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1450 ret = media_entity_create_link(&state->sensor_sd.entity,
1451 S5C73M3_JPEG_PAD, &state->oif_sd.entity, OIF_JPEG_PAD,
1452 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1454 mutex_lock(&state->lock);
1455 ret = __s5c73m3_power_on(state);
1457 s5c73m3_get_fw_version(state);
1459 __s5c73m3_power_off(state);
1460 mutex_unlock(&state->lock);
1462 v4l2_dbg(1, s5c73m3_dbg, sd, "%s: Booting %s (%d)\n",
1463 __func__, ret ? "failed" : "succeded", ret);
1468 static void s5c73m3_oif_unregistered(struct v4l2_subdev *sd)
1470 struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1471 v4l2_device_unregister_subdev(&state->sensor_sd);
1474 static const struct v4l2_subdev_internal_ops s5c73m3_internal_ops = {
1475 .open = s5c73m3_open,
1478 static const struct v4l2_subdev_pad_ops s5c73m3_pad_ops = {
1479 .enum_mbus_code = s5c73m3_enum_mbus_code,
1480 .enum_frame_size = s5c73m3_enum_frame_size,
1481 .get_fmt = s5c73m3_get_fmt,
1482 .set_fmt = s5c73m3_set_fmt,
1485 static const struct v4l2_subdev_ops s5c73m3_subdev_ops = {
1486 .pad = &s5c73m3_pad_ops,
1489 static const struct v4l2_subdev_internal_ops oif_internal_ops = {
1490 .registered = s5c73m3_oif_registered,
1491 .unregistered = s5c73m3_oif_unregistered,
1492 .open = s5c73m3_oif_open,
1495 static const struct v4l2_subdev_pad_ops s5c73m3_oif_pad_ops = {
1496 .enum_mbus_code = s5c73m3_oif_enum_mbus_code,
1497 .enum_frame_size = s5c73m3_oif_enum_frame_size,
1498 .enum_frame_interval = s5c73m3_oif_enum_frame_interval,
1499 .get_fmt = s5c73m3_oif_get_fmt,
1500 .set_fmt = s5c73m3_oif_set_fmt,
1501 .get_frame_desc = s5c73m3_oif_get_frame_desc,
1502 .set_frame_desc = s5c73m3_oif_set_frame_desc,
1505 static const struct v4l2_subdev_core_ops s5c73m3_oif_core_ops = {
1506 .s_power = s5c73m3_oif_set_power,
1507 .log_status = s5c73m3_oif_log_status,
1510 static const struct v4l2_subdev_video_ops s5c73m3_oif_video_ops = {
1511 .s_stream = s5c73m3_oif_s_stream,
1512 .g_frame_interval = s5c73m3_oif_g_frame_interval,
1513 .s_frame_interval = s5c73m3_oif_s_frame_interval,
1516 static const struct v4l2_subdev_ops oif_subdev_ops = {
1517 .core = &s5c73m3_oif_core_ops,
1518 .pad = &s5c73m3_oif_pad_ops,
1519 .video = &s5c73m3_oif_video_ops,
1522 static int s5c73m3_configure_gpios(struct s5c73m3 *state,
1523 const struct s5c73m3_platform_data *pdata)
1525 struct device *dev = &state->i2c_client->dev;
1526 const struct s5c73m3_gpio *gpio;
1527 unsigned long flags;
1530 state->gpio[STBY].gpio = -EINVAL;
1531 state->gpio[RST].gpio = -EINVAL;
1533 gpio = &pdata->gpio_stby;
1534 if (gpio_is_valid(gpio->gpio)) {
1535 flags = (gpio->level ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW)
1537 ret = devm_gpio_request_one(dev, gpio->gpio, flags,
1542 state->gpio[STBY] = *gpio;
1545 gpio = &pdata->gpio_reset;
1546 if (gpio_is_valid(gpio->gpio)) {
1547 flags = (gpio->level ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW)
1549 ret = devm_gpio_request_one(dev, gpio->gpio, flags,
1554 state->gpio[RST] = *gpio;
1560 static int s5c73m3_probe(struct i2c_client *client,
1561 const struct i2c_device_id *id)
1563 struct device *dev = &client->dev;
1564 const struct s5c73m3_platform_data *pdata = client->dev.platform_data;
1565 struct v4l2_subdev *sd;
1566 struct v4l2_subdev *oif_sd;
1567 struct s5c73m3 *state;
1570 if (pdata == NULL) {
1571 dev_err(&client->dev, "Platform data not specified\n");
1575 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1579 mutex_init(&state->lock);
1580 sd = &state->sensor_sd;
1581 oif_sd = &state->oif_sd;
1583 v4l2_subdev_init(sd, &s5c73m3_subdev_ops);
1584 sd->owner = client->dev.driver->owner;
1585 v4l2_set_subdevdata(sd, state);
1586 strlcpy(sd->name, "S5C73M3", sizeof(sd->name));
1588 sd->internal_ops = &s5c73m3_internal_ops;
1589 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1591 state->sensor_pads[S5C73M3_JPEG_PAD].flags = MEDIA_PAD_FL_SOURCE;
1592 state->sensor_pads[S5C73M3_ISP_PAD].flags = MEDIA_PAD_FL_SOURCE;
1593 sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
1595 ret = media_entity_init(&sd->entity, S5C73M3_NUM_PADS,
1596 state->sensor_pads, 0);
1600 v4l2_i2c_subdev_init(oif_sd, client, &oif_subdev_ops);
1601 strcpy(oif_sd->name, "S5C73M3-OIF");
1603 oif_sd->internal_ops = &oif_internal_ops;
1604 oif_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1606 state->oif_pads[OIF_ISP_PAD].flags = MEDIA_PAD_FL_SINK;
1607 state->oif_pads[OIF_JPEG_PAD].flags = MEDIA_PAD_FL_SINK;
1608 state->oif_pads[OIF_SOURCE_PAD].flags = MEDIA_PAD_FL_SOURCE;
1609 oif_sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
1611 ret = media_entity_init(&oif_sd->entity, OIF_NUM_PADS,
1612 state->oif_pads, 0);
1616 state->mclk_frequency = pdata->mclk_frequency;
1617 state->bus_type = pdata->bus_type;
1618 state->i2c_client = client;
1620 ret = s5c73m3_configure_gpios(state, pdata);
1624 for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++)
1625 state->supplies[i].supply = s5c73m3_supply_names[i];
1627 ret = devm_regulator_bulk_get(dev, S5C73M3_MAX_SUPPLIES,
1630 dev_err(dev, "failed to get regulators\n");
1634 ret = s5c73m3_init_controls(state);
1638 state->sensor_pix_size[RES_ISP] = &s5c73m3_isp_resolutions[1];
1639 state->sensor_pix_size[RES_JPEG] = &s5c73m3_jpeg_resolutions[1];
1640 state->oif_pix_size[RES_ISP] = state->sensor_pix_size[RES_ISP];
1641 state->oif_pix_size[RES_JPEG] = state->sensor_pix_size[RES_JPEG];
1643 state->mbus_code = S5C73M3_ISP_FMT;
1645 state->fiv = &s5c73m3_intervals[S5C73M3_DEFAULT_FRAME_INTERVAL];
1647 state->fw_file_version[0] = 'G';
1648 state->fw_file_version[1] = 'C';
1650 ret = s5c73m3_register_spi_driver(state);
1654 v4l2_info(sd, "%s: completed successfully\n", __func__);
1658 media_entity_cleanup(&sd->entity);
1662 static int s5c73m3_remove(struct i2c_client *client)
1664 struct v4l2_subdev *oif_sd = i2c_get_clientdata(client);
1665 struct s5c73m3 *state = oif_sd_to_s5c73m3(oif_sd);
1666 struct v4l2_subdev *sensor_sd = &state->sensor_sd;
1668 v4l2_device_unregister_subdev(oif_sd);
1670 v4l2_ctrl_handler_free(oif_sd->ctrl_handler);
1671 media_entity_cleanup(&oif_sd->entity);
1673 v4l2_device_unregister_subdev(sensor_sd);
1674 media_entity_cleanup(&sensor_sd->entity);
1676 s5c73m3_unregister_spi_driver(state);
1681 static const struct i2c_device_id s5c73m3_id[] = {
1685 MODULE_DEVICE_TABLE(i2c, s5c73m3_id);
1687 static struct i2c_driver s5c73m3_i2c_driver = {
1689 .name = DRIVER_NAME,
1691 .probe = s5c73m3_probe,
1692 .remove = s5c73m3_remove,
1693 .id_table = s5c73m3_id,
1696 module_i2c_driver(s5c73m3_i2c_driver);
1698 MODULE_DESCRIPTION("Samsung S5C73M3 camera driver");
1699 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1700 MODULE_LICENSE("GPL");