1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2020 Kévin L'hôpital <kevin.lhopital@bootlin.com>
4 * Copyright 2020 Bootlin
5 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/i2c.h>
12 #include <linux/module.h>
13 #include <linux/of_graph.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/videodev2.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-fwnode.h>
20 #include <media/v4l2-image-sizes.h>
21 #include <media/v4l2-mediabus.h>
25 #define OV8865_EXTCLK_RATE 24000000
27 /* Register definitions */
31 #define OV8865_SW_STANDBY_REG 0x100
32 #define OV8865_SW_STANDBY_STREAM_ON BIT(0)
34 #define OV8865_SW_RESET_REG 0x103
35 #define OV8865_SW_RESET_RESET BIT(0)
37 #define OV8865_PLL_CTRL0_REG 0x300
38 #define OV8865_PLL_CTRL0_PRE_DIV(v) ((v) & GENMASK(2, 0))
39 #define OV8865_PLL_CTRL1_REG 0x301
40 #define OV8865_PLL_CTRL1_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8)
41 #define OV8865_PLL_CTRL2_REG 0x302
42 #define OV8865_PLL_CTRL2_MUL_L(v) ((v) & GENMASK(7, 0))
43 #define OV8865_PLL_CTRL3_REG 0x303
44 #define OV8865_PLL_CTRL3_M_DIV(v) (((v) - 1) & GENMASK(3, 0))
45 #define OV8865_PLL_CTRL4_REG 0x304
46 #define OV8865_PLL_CTRL4_MIPI_DIV(v) ((v) & GENMASK(1, 0))
47 #define OV8865_PLL_CTRL5_REG 0x305
48 #define OV8865_PLL_CTRL5_SYS_PRE_DIV(v) ((v) & GENMASK(1, 0))
49 #define OV8865_PLL_CTRL6_REG 0x306
50 #define OV8865_PLL_CTRL6_SYS_DIV(v) (((v) - 1) & BIT(0))
52 #define OV8865_PLL_CTRL8_REG 0x308
53 #define OV8865_PLL_CTRL9_REG 0x309
54 #define OV8865_PLL_CTRLA_REG 0x30a
55 #define OV8865_PLL_CTRLA_PRE_DIV_HALF(v) (((v) - 1) & BIT(0))
56 #define OV8865_PLL_CTRLB_REG 0x30b
57 #define OV8865_PLL_CTRLB_PRE_DIV(v) ((v) & GENMASK(2, 0))
58 #define OV8865_PLL_CTRLC_REG 0x30c
59 #define OV8865_PLL_CTRLC_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8)
60 #define OV8865_PLL_CTRLD_REG 0x30d
61 #define OV8865_PLL_CTRLD_MUL_L(v) ((v) & GENMASK(7, 0))
62 #define OV8865_PLL_CTRLE_REG 0x30e
63 #define OV8865_PLL_CTRLE_SYS_DIV(v) ((v) & GENMASK(2, 0))
64 #define OV8865_PLL_CTRLF_REG 0x30f
65 #define OV8865_PLL_CTRLF_SYS_PRE_DIV(v) (((v) - 1) & GENMASK(3, 0))
66 #define OV8865_PLL_CTRL10_REG 0x310
67 #define OV8865_PLL_CTRL11_REG 0x311
68 #define OV8865_PLL_CTRL12_REG 0x312
69 #define OV8865_PLL_CTRL12_PRE_DIV_HALF(v) ((((v) - 1) << 4) & BIT(4))
70 #define OV8865_PLL_CTRL12_DAC_DIV(v) (((v) - 1) & GENMASK(3, 0))
72 #define OV8865_PLL_CTRL1B_REG 0x31b
73 #define OV8865_PLL_CTRL1C_REG 0x31c
75 #define OV8865_PLL_CTRL1E_REG 0x31e
76 #define OV8865_PLL_CTRL1E_PLL1_NO_LAT BIT(3)
78 #define OV8865_PAD_OEN0_REG 0x3000
80 #define OV8865_PAD_OEN2_REG 0x3002
82 #define OV8865_CLK_RST5_REG 0x3005
84 #define OV8865_CHIP_ID_HH_REG 0x300a
85 #define OV8865_CHIP_ID_HH_VALUE 0x00
86 #define OV8865_CHIP_ID_H_REG 0x300b
87 #define OV8865_CHIP_ID_H_VALUE 0x88
88 #define OV8865_CHIP_ID_L_REG 0x300c
89 #define OV8865_CHIP_ID_L_VALUE 0x65
90 #define OV8865_PAD_OUT2_REG 0x300d
92 #define OV8865_PAD_SEL2_REG 0x3010
93 #define OV8865_PAD_PK_REG 0x3011
94 #define OV8865_PAD_PK_DRIVE_STRENGTH_1X (0 << 5)
95 #define OV8865_PAD_PK_DRIVE_STRENGTH_2X (1 << 5)
96 #define OV8865_PAD_PK_DRIVE_STRENGTH_3X (2 << 5)
97 #define OV8865_PAD_PK_DRIVE_STRENGTH_4X (3 << 5)
99 #define OV8865_PUMP_CLK_DIV_REG 0x3015
100 #define OV8865_PUMP_CLK_DIV_PUMP_N(v) (((v) << 4) & GENMASK(6, 4))
101 #define OV8865_PUMP_CLK_DIV_PUMP_P(v) ((v) & GENMASK(2, 0))
103 #define OV8865_MIPI_SC_CTRL0_REG 0x3018
104 #define OV8865_MIPI_SC_CTRL0_LANES(v) ((((v) - 1) << 5) & \
106 #define OV8865_MIPI_SC_CTRL0_MIPI_EN BIT(4)
107 #define OV8865_MIPI_SC_CTRL0_UNKNOWN BIT(1)
108 #define OV8865_MIPI_SC_CTRL0_LANES_PD_MIPI BIT(0)
109 #define OV8865_MIPI_SC_CTRL1_REG 0x3019
110 #define OV8865_CLK_RST0_REG 0x301a
111 #define OV8865_CLK_RST1_REG 0x301b
112 #define OV8865_CLK_RST2_REG 0x301c
113 #define OV8865_CLK_RST3_REG 0x301d
114 #define OV8865_CLK_RST4_REG 0x301e
116 #define OV8865_PCLK_SEL_REG 0x3020
117 #define OV8865_PCLK_SEL_PCLK_DIV_MASK BIT(3)
118 #define OV8865_PCLK_SEL_PCLK_DIV(v) ((((v) - 1) << 3) & BIT(3))
120 #define OV8865_MISC_CTRL_REG 0x3021
121 #define OV8865_MIPI_SC_CTRL2_REG 0x3022
122 #define OV8865_MIPI_SC_CTRL2_CLK_LANES_PD_MIPI BIT(1)
123 #define OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC BIT(0)
125 #define OV8865_MIPI_BIT_SEL_REG 0x3031
126 #define OV8865_MIPI_BIT_SEL(v) (((v) << 0) & GENMASK(4, 0))
127 #define OV8865_CLK_SEL0_REG 0x3032
128 #define OV8865_CLK_SEL0_PLL1_SYS_SEL(v) (((v) << 7) & BIT(7))
129 #define OV8865_CLK_SEL1_REG 0x3033
130 #define OV8865_CLK_SEL1_MIPI_EOF BIT(5)
131 #define OV8865_CLK_SEL1_UNKNOWN BIT(2)
132 #define OV8865_CLK_SEL1_PLL_SCLK_SEL_MASK BIT(1)
133 #define OV8865_CLK_SEL1_PLL_SCLK_SEL(v) (((v) << 1) & BIT(1))
135 #define OV8865_SCLK_CTRL_REG 0x3106
136 #define OV8865_SCLK_CTRL_SCLK_DIV(v) (((v) << 4) & GENMASK(7, 4))
137 #define OV8865_SCLK_CTRL_SCLK_PRE_DIV(v) (((v) << 2) & GENMASK(3, 2))
138 #define OV8865_SCLK_CTRL_UNKNOWN BIT(0)
142 #define OV8865_EXPOSURE_CTRL_HH_REG 0x3500
143 #define OV8865_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16)
144 #define OV8865_EXPOSURE_CTRL_H_REG 0x3501
145 #define OV8865_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8)
146 #define OV8865_EXPOSURE_CTRL_L_REG 0x3502
147 #define OV8865_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0))
148 #define OV8865_EXPOSURE_GAIN_MANUAL_REG 0x3503
150 #define OV8865_GAIN_CTRL_H_REG 0x3508
151 #define OV8865_GAIN_CTRL_H(v) (((v) & GENMASK(12, 8)) >> 8)
152 #define OV8865_GAIN_CTRL_L_REG 0x3509
153 #define OV8865_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0))
157 #define OV8865_CROP_START_X_H_REG 0x3800
158 #define OV8865_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
159 #define OV8865_CROP_START_X_L_REG 0x3801
160 #define OV8865_CROP_START_X_L(v) ((v) & GENMASK(7, 0))
161 #define OV8865_CROP_START_Y_H_REG 0x3802
162 #define OV8865_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
163 #define OV8865_CROP_START_Y_L_REG 0x3803
164 #define OV8865_CROP_START_Y_L(v) ((v) & GENMASK(7, 0))
165 #define OV8865_CROP_END_X_H_REG 0x3804
166 #define OV8865_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
167 #define OV8865_CROP_END_X_L_REG 0x3805
168 #define OV8865_CROP_END_X_L(v) ((v) & GENMASK(7, 0))
169 #define OV8865_CROP_END_Y_H_REG 0x3806
170 #define OV8865_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
171 #define OV8865_CROP_END_Y_L_REG 0x3807
172 #define OV8865_CROP_END_Y_L(v) ((v) & GENMASK(7, 0))
173 #define OV8865_OUTPUT_SIZE_X_H_REG 0x3808
174 #define OV8865_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
175 #define OV8865_OUTPUT_SIZE_X_L_REG 0x3809
176 #define OV8865_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0))
177 #define OV8865_OUTPUT_SIZE_Y_H_REG 0x380a
178 #define OV8865_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
179 #define OV8865_OUTPUT_SIZE_Y_L_REG 0x380b
180 #define OV8865_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0))
181 #define OV8865_HTS_H_REG 0x380c
182 #define OV8865_HTS_H(v) (((v) & GENMASK(11, 8)) >> 8)
183 #define OV8865_HTS_L_REG 0x380d
184 #define OV8865_HTS_L(v) ((v) & GENMASK(7, 0))
185 #define OV8865_VTS_H_REG 0x380e
186 #define OV8865_VTS_H(v) (((v) & GENMASK(11, 8)) >> 8)
187 #define OV8865_VTS_L_REG 0x380f
188 #define OV8865_VTS_L(v) ((v) & GENMASK(7, 0))
189 #define OV8865_OFFSET_X_H_REG 0x3810
190 #define OV8865_OFFSET_X_H(v) (((v) & GENMASK(15, 8)) >> 8)
191 #define OV8865_OFFSET_X_L_REG 0x3811
192 #define OV8865_OFFSET_X_L(v) ((v) & GENMASK(7, 0))
193 #define OV8865_OFFSET_Y_H_REG 0x3812
194 #define OV8865_OFFSET_Y_H(v) (((v) & GENMASK(14, 8)) >> 8)
195 #define OV8865_OFFSET_Y_L_REG 0x3813
196 #define OV8865_OFFSET_Y_L(v) ((v) & GENMASK(7, 0))
197 #define OV8865_INC_X_ODD_REG 0x3814
198 #define OV8865_INC_X_ODD(v) ((v) & GENMASK(4, 0))
199 #define OV8865_INC_X_EVEN_REG 0x3815
200 #define OV8865_INC_X_EVEN(v) ((v) & GENMASK(4, 0))
201 #define OV8865_VSYNC_START_H_REG 0x3816
202 #define OV8865_VSYNC_START_H(v) (((v) & GENMASK(15, 8)) >> 8)
203 #define OV8865_VSYNC_START_L_REG 0x3817
204 #define OV8865_VSYNC_START_L(v) ((v) & GENMASK(7, 0))
205 #define OV8865_VSYNC_END_H_REG 0x3818
206 #define OV8865_VSYNC_END_H(v) (((v) & GENMASK(15, 8)) >> 8)
207 #define OV8865_VSYNC_END_L_REG 0x3819
208 #define OV8865_VSYNC_END_L(v) ((v) & GENMASK(7, 0))
209 #define OV8865_HSYNC_FIRST_H_REG 0x381a
210 #define OV8865_HSYNC_FIRST_H(v) (((v) & GENMASK(15, 8)) >> 8)
211 #define OV8865_HSYNC_FIRST_L_REG 0x381b
212 #define OV8865_HSYNC_FIRST_L(v) ((v) & GENMASK(7, 0))
214 #define OV8865_FORMAT1_REG 0x3820
215 #define OV8865_FORMAT1_FLIP_VERT_ISP_EN BIT(2)
216 #define OV8865_FORMAT1_FLIP_VERT_SENSOR_EN BIT(1)
217 #define OV8865_FORMAT2_REG 0x3821
218 #define OV8865_FORMAT2_HSYNC_EN BIT(6)
219 #define OV8865_FORMAT2_FST_VBIN_EN BIT(5)
220 #define OV8865_FORMAT2_FST_HBIN_EN BIT(4)
221 #define OV8865_FORMAT2_ISP_HORZ_VAR2_EN BIT(3)
222 #define OV8865_FORMAT2_FLIP_HORZ_ISP_EN BIT(2)
223 #define OV8865_FORMAT2_FLIP_HORZ_SENSOR_EN BIT(1)
224 #define OV8865_FORMAT2_SYNC_HBIN_EN BIT(0)
226 #define OV8865_INC_Y_ODD_REG 0x382a
227 #define OV8865_INC_Y_ODD(v) ((v) & GENMASK(4, 0))
228 #define OV8865_INC_Y_EVEN_REG 0x382b
229 #define OV8865_INC_Y_EVEN(v) ((v) & GENMASK(4, 0))
231 #define OV8865_ABLC_NUM_REG 0x3830
232 #define OV8865_ABLC_NUM(v) ((v) & GENMASK(4, 0))
234 #define OV8865_ZLINE_NUM_REG 0x3836
235 #define OV8865_ZLINE_NUM(v) ((v) & GENMASK(4, 0))
237 #define OV8865_AUTO_SIZE_CTRL_REG 0x3841
238 #define OV8865_AUTO_SIZE_CTRL_OFFSET_Y_REG BIT(5)
239 #define OV8865_AUTO_SIZE_CTRL_OFFSET_X_REG BIT(4)
240 #define OV8865_AUTO_SIZE_CTRL_CROP_END_Y_REG BIT(3)
241 #define OV8865_AUTO_SIZE_CTRL_CROP_END_X_REG BIT(2)
242 #define OV8865_AUTO_SIZE_CTRL_CROP_START_Y_REG BIT(1)
243 #define OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG BIT(0)
244 #define OV8865_AUTO_SIZE_X_OFFSET_H_REG 0x3842
245 #define OV8865_AUTO_SIZE_X_OFFSET_L_REG 0x3843
246 #define OV8865_AUTO_SIZE_Y_OFFSET_H_REG 0x3844
247 #define OV8865_AUTO_SIZE_Y_OFFSET_L_REG 0x3845
248 #define OV8865_AUTO_SIZE_BOUNDARIES_REG 0x3846
249 #define OV8865_AUTO_SIZE_BOUNDARIES_Y(v) (((v) << 4) & GENMASK(7, 4))
250 #define OV8865_AUTO_SIZE_BOUNDARIES_X(v) ((v) & GENMASK(3, 0))
254 #define OV8865_PSRAM_CTRL8_REG 0x3f08
258 #define OV8865_BLC_CTRL0_REG 0x4000
259 #define OV8865_BLC_CTRL0_TRIG_RANGE_EN BIT(7)
260 #define OV8865_BLC_CTRL0_TRIG_FORMAT_EN BIT(6)
261 #define OV8865_BLC_CTRL0_TRIG_GAIN_EN BIT(5)
262 #define OV8865_BLC_CTRL0_TRIG_EXPOSURE_EN BIT(4)
263 #define OV8865_BLC_CTRL0_TRIG_MANUAL_EN BIT(3)
264 #define OV8865_BLC_CTRL0_FREEZE_EN BIT(2)
265 #define OV8865_BLC_CTRL0_ALWAYS_EN BIT(1)
266 #define OV8865_BLC_CTRL0_FILTER_EN BIT(0)
267 #define OV8865_BLC_CTRL1_REG 0x4001
268 #define OV8865_BLC_CTRL1_DITHER_EN BIT(7)
269 #define OV8865_BLC_CTRL1_ZERO_LINE_DIFF_EN BIT(6)
270 #define OV8865_BLC_CTRL1_COL_SHIFT_256 (0 << 4)
271 #define OV8865_BLC_CTRL1_COL_SHIFT_128 (1 << 4)
272 #define OV8865_BLC_CTRL1_COL_SHIFT_64 (2 << 4)
273 #define OV8865_BLC_CTRL1_COL_SHIFT_32 (3 << 4)
274 #define OV8865_BLC_CTRL1_OFFSET_LIMIT_EN BIT(2)
275 #define OV8865_BLC_CTRL1_COLUMN_CANCEL_EN BIT(1)
276 #define OV8865_BLC_CTRL2_REG 0x4002
277 #define OV8865_BLC_CTRL3_REG 0x4003
278 #define OV8865_BLC_CTRL4_REG 0x4004
279 #define OV8865_BLC_CTRL5_REG 0x4005
280 #define OV8865_BLC_CTRL6_REG 0x4006
281 #define OV8865_BLC_CTRL7_REG 0x4007
282 #define OV8865_BLC_CTRL8_REG 0x4008
283 #define OV8865_BLC_CTRL9_REG 0x4009
284 #define OV8865_BLC_CTRLA_REG 0x400a
285 #define OV8865_BLC_CTRLB_REG 0x400b
286 #define OV8865_BLC_CTRLC_REG 0x400c
287 #define OV8865_BLC_CTRLD_REG 0x400d
288 #define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v) ((v) & GENMASK(7, 0))
290 #define OV8865_BLC_CTRL1F_REG 0x401f
291 #define OV8865_BLC_CTRL1F_RB_REVERSE BIT(3)
292 #define OV8865_BLC_CTRL1F_INTERPOL_X_EN BIT(2)
293 #define OV8865_BLC_CTRL1F_INTERPOL_Y_EN BIT(1)
295 #define OV8865_BLC_ANCHOR_LEFT_START_H_REG 0x4020
296 #define OV8865_BLC_ANCHOR_LEFT_START_H(v) (((v) & GENMASK(11, 8)) >> 8)
297 #define OV8865_BLC_ANCHOR_LEFT_START_L_REG 0x4021
298 #define OV8865_BLC_ANCHOR_LEFT_START_L(v) ((v) & GENMASK(7, 0))
299 #define OV8865_BLC_ANCHOR_LEFT_END_H_REG 0x4022
300 #define OV8865_BLC_ANCHOR_LEFT_END_H(v) (((v) & GENMASK(11, 8)) >> 8)
301 #define OV8865_BLC_ANCHOR_LEFT_END_L_REG 0x4023
302 #define OV8865_BLC_ANCHOR_LEFT_END_L(v) ((v) & GENMASK(7, 0))
303 #define OV8865_BLC_ANCHOR_RIGHT_START_H_REG 0x4024
304 #define OV8865_BLC_ANCHOR_RIGHT_START_H(v) (((v) & GENMASK(11, 8)) >> 8)
305 #define OV8865_BLC_ANCHOR_RIGHT_START_L_REG 0x4025
306 #define OV8865_BLC_ANCHOR_RIGHT_START_L(v) ((v) & GENMASK(7, 0))
307 #define OV8865_BLC_ANCHOR_RIGHT_END_H_REG 0x4026
308 #define OV8865_BLC_ANCHOR_RIGHT_END_H(v) (((v) & GENMASK(11, 8)) >> 8)
309 #define OV8865_BLC_ANCHOR_RIGHT_END_L_REG 0x4027
310 #define OV8865_BLC_ANCHOR_RIGHT_END_L(v) ((v) & GENMASK(7, 0))
312 #define OV8865_BLC_TOP_ZLINE_START_REG 0x4028
313 #define OV8865_BLC_TOP_ZLINE_START(v) ((v) & GENMASK(5, 0))
314 #define OV8865_BLC_TOP_ZLINE_NUM_REG 0x4029
315 #define OV8865_BLC_TOP_ZLINE_NUM(v) ((v) & GENMASK(4, 0))
316 #define OV8865_BLC_TOP_BLKLINE_START_REG 0x402a
317 #define OV8865_BLC_TOP_BLKLINE_START(v) ((v) & GENMASK(5, 0))
318 #define OV8865_BLC_TOP_BLKLINE_NUM_REG 0x402b
319 #define OV8865_BLC_TOP_BLKLINE_NUM(v) ((v) & GENMASK(4, 0))
320 #define OV8865_BLC_BOT_ZLINE_START_REG 0x402c
321 #define OV8865_BLC_BOT_ZLINE_START(v) ((v) & GENMASK(5, 0))
322 #define OV8865_BLC_BOT_ZLINE_NUM_REG 0x402d
323 #define OV8865_BLC_BOT_ZLINE_NUM(v) ((v) & GENMASK(4, 0))
324 #define OV8865_BLC_BOT_BLKLINE_START_REG 0x402e
325 #define OV8865_BLC_BOT_BLKLINE_START(v) ((v) & GENMASK(5, 0))
326 #define OV8865_BLC_BOT_BLKLINE_NUM_REG 0x402f
327 #define OV8865_BLC_BOT_BLKLINE_NUM(v) ((v) & GENMASK(4, 0))
329 #define OV8865_BLC_OFFSET_LIMIT_REG 0x4034
330 #define OV8865_BLC_OFFSET_LIMIT(v) ((v) & GENMASK(7, 0))
334 #define OV8865_VFIFO_READ_START_H_REG 0x4600
335 #define OV8865_VFIFO_READ_START_H(v) (((v) & GENMASK(15, 8)) >> 8)
336 #define OV8865_VFIFO_READ_START_L_REG 0x4601
337 #define OV8865_VFIFO_READ_START_L(v) ((v) & GENMASK(7, 0))
341 #define OV8865_MIPI_CTRL0_REG 0x4800
342 #define OV8865_MIPI_CTRL1_REG 0x4801
343 #define OV8865_MIPI_CTRL2_REG 0x4802
344 #define OV8865_MIPI_CTRL3_REG 0x4803
345 #define OV8865_MIPI_CTRL4_REG 0x4804
346 #define OV8865_MIPI_CTRL5_REG 0x4805
347 #define OV8865_MIPI_CTRL6_REG 0x4806
348 #define OV8865_MIPI_CTRL7_REG 0x4807
349 #define OV8865_MIPI_CTRL8_REG 0x4808
351 #define OV8865_MIPI_FCNT_MAX_H_REG 0x4810
352 #define OV8865_MIPI_FCNT_MAX_L_REG 0x4811
354 #define OV8865_MIPI_CTRL13_REG 0x4813
355 #define OV8865_MIPI_CTRL14_REG 0x4814
356 #define OV8865_MIPI_CTRL15_REG 0x4815
357 #define OV8865_MIPI_EMBEDDED_DT_REG 0x4816
359 #define OV8865_MIPI_HS_ZERO_MIN_H_REG 0x4818
360 #define OV8865_MIPI_HS_ZERO_MIN_L_REG 0x4819
361 #define OV8865_MIPI_HS_TRAIL_MIN_H_REG 0x481a
362 #define OV8865_MIPI_HS_TRAIL_MIN_L_REG 0x481b
363 #define OV8865_MIPI_CLK_ZERO_MIN_H_REG 0x481c
364 #define OV8865_MIPI_CLK_ZERO_MIN_L_REG 0x481d
365 #define OV8865_MIPI_CLK_PREPARE_MAX_REG 0x481e
366 #define OV8865_MIPI_CLK_PREPARE_MIN_REG 0x481f
367 #define OV8865_MIPI_CLK_POST_MIN_H_REG 0x4820
368 #define OV8865_MIPI_CLK_POST_MIN_L_REG 0x4821
369 #define OV8865_MIPI_CLK_TRAIL_MIN_H_REG 0x4822
370 #define OV8865_MIPI_CLK_TRAIL_MIN_L_REG 0x4823
371 #define OV8865_MIPI_LPX_P_MIN_H_REG 0x4824
372 #define OV8865_MIPI_LPX_P_MIN_L_REG 0x4825
373 #define OV8865_MIPI_HS_PREPARE_MIN_REG 0x4826
374 #define OV8865_MIPI_HS_PREPARE_MAX_REG 0x4827
375 #define OV8865_MIPI_HS_EXIT_MIN_H_REG 0x4828
376 #define OV8865_MIPI_HS_EXIT_MIN_L_REG 0x4829
377 #define OV8865_MIPI_UI_HS_ZERO_MIN_REG 0x482a
378 #define OV8865_MIPI_UI_HS_TRAIL_MIN_REG 0x482b
379 #define OV8865_MIPI_UI_CLK_ZERO_MIN_REG 0x482c
380 #define OV8865_MIPI_UI_CLK_PREPARE_REG 0x482d
381 #define OV8865_MIPI_UI_CLK_POST_MIN_REG 0x482e
382 #define OV8865_MIPI_UI_CLK_TRAIL_MIN_REG 0x482f
383 #define OV8865_MIPI_UI_LPX_P_MIN_REG 0x4830
384 #define OV8865_MIPI_UI_HS_PREPARE_REG 0x4831
385 #define OV8865_MIPI_UI_HS_EXIT_MIN_REG 0x4832
386 #define OV8865_MIPI_PKT_START_SIZE_REG 0x4833
388 #define OV8865_MIPI_PCLK_PERIOD_REG 0x4837
389 #define OV8865_MIPI_LP_GPIO0_REG 0x4838
390 #define OV8865_MIPI_LP_GPIO1_REG 0x4839
392 #define OV8865_MIPI_CTRL3C_REG 0x483c
393 #define OV8865_MIPI_LP_GPIO4_REG 0x483d
395 #define OV8865_MIPI_CTRL4A_REG 0x484a
396 #define OV8865_MIPI_CTRL4B_REG 0x484b
397 #define OV8865_MIPI_CTRL4C_REG 0x484c
398 #define OV8865_MIPI_LANE_TEST_PATTERN_REG 0x484d
399 #define OV8865_MIPI_FRAME_END_DELAY_REG 0x484e
400 #define OV8865_MIPI_CLOCK_TEST_PATTERN_REG 0x484f
401 #define OV8865_MIPI_LANE_SEL01_REG 0x4850
402 #define OV8865_MIPI_LANE_SEL01_LANE0(v) (((v) << 0) & GENMASK(2, 0))
403 #define OV8865_MIPI_LANE_SEL01_LANE1(v) (((v) << 4) & GENMASK(6, 4))
404 #define OV8865_MIPI_LANE_SEL23_REG 0x4851
405 #define OV8865_MIPI_LANE_SEL23_LANE2(v) (((v) << 0) & GENMASK(2, 0))
406 #define OV8865_MIPI_LANE_SEL23_LANE3(v) (((v) << 4) & GENMASK(6, 4))
410 #define OV8865_ISP_CTRL0_REG 0x5000
411 #define OV8865_ISP_CTRL0_LENC_EN BIT(7)
412 #define OV8865_ISP_CTRL0_WHITE_BALANCE_EN BIT(4)
413 #define OV8865_ISP_CTRL0_DPC_BLACK_EN BIT(2)
414 #define OV8865_ISP_CTRL0_DPC_WHITE_EN BIT(1)
415 #define OV8865_ISP_CTRL1_REG 0x5001
416 #define OV8865_ISP_CTRL1_BLC_EN BIT(0)
417 #define OV8865_ISP_CTRL2_REG 0x5002
418 #define OV8865_ISP_CTRL2_DEBUG BIT(3)
419 #define OV8865_ISP_CTRL2_VARIOPIXEL_EN BIT(2)
420 #define OV8865_ISP_CTRL2_VSYNC_LATCH_EN BIT(0)
421 #define OV8865_ISP_CTRL3_REG 0x5003
423 #define OV8865_ISP_GAIN_RED_H_REG 0x5018
424 #define OV8865_ISP_GAIN_RED_H(v) (((v) & GENMASK(13, 6)) >> 6)
425 #define OV8865_ISP_GAIN_RED_L_REG 0x5019
426 #define OV8865_ISP_GAIN_RED_L(v) ((v) & GENMASK(5, 0))
427 #define OV8865_ISP_GAIN_GREEN_H_REG 0x501a
428 #define OV8865_ISP_GAIN_GREEN_H(v) (((v) & GENMASK(13, 6)) >> 6)
429 #define OV8865_ISP_GAIN_GREEN_L_REG 0x501b
430 #define OV8865_ISP_GAIN_GREEN_L(v) ((v) & GENMASK(5, 0))
431 #define OV8865_ISP_GAIN_BLUE_H_REG 0x501c
432 #define OV8865_ISP_GAIN_BLUE_H(v) (((v) & GENMASK(13, 6)) >> 6)
433 #define OV8865_ISP_GAIN_BLUE_L_REG 0x501d
434 #define OV8865_ISP_GAIN_BLUE_L(v) ((v) & GENMASK(5, 0))
438 #define OV8865_VAP_CTRL0_REG 0x5900
439 #define OV8865_VAP_CTRL1_REG 0x5901
440 #define OV8865_VAP_CTRL1_HSUB_COEF(v) ((((v) - 1) << 2) & \
442 #define OV8865_VAP_CTRL1_VSUB_COEF(v) (((v) - 1) & GENMASK(1, 0))
446 #define OV8865_PRE_CTRL0_REG 0x5e00
447 #define OV8865_PRE_CTRL0_PATTERN_EN BIT(7)
448 #define OV8865_PRE_CTRL0_ROLLING_BAR_EN BIT(6)
449 #define OV8865_PRE_CTRL0_TRANSPARENT_MODE BIT(5)
450 #define OV8865_PRE_CTRL0_SQUARES_BW_MODE BIT(4)
451 #define OV8865_PRE_CTRL0_PATTERN_COLOR_BARS 0
452 #define OV8865_PRE_CTRL0_PATTERN_RANDOM_DATA 1
453 #define OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES 2
454 #define OV8865_PRE_CTRL0_PATTERN_BLACK 3
458 #define ov8865_subdev_sensor(s) \
459 container_of(s, struct ov8865_sensor, subdev)
461 #define ov8865_ctrl_subdev(c) \
462 (&container_of((c)->handler, struct ov8865_sensor, \
463 ctrls.handler)->subdev)
465 /* Data structures */
467 struct ov8865_register_value {
470 unsigned int delay_ms;
478 * +-+ pll_pre_div_half (0x30a [0])
480 * +-+ pll_pre_div (0x300 [2:0], special values:
481 * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
482 * +-+ pll_mul (0x301 [1:0], 0x302 [7:0])
484 * +-+ m_div (0x303 [3:0])
488 * | +-+ mipi_div (0x304 [1:0], special values: 0: 4, 1: 5, 2: 6, 3: 8)
490 * | +-+ pclk_div (0x3020 [3])
494 * +-+ sys_pre_div (0x305 [1:0], special values: 0: 3, 1: 4, 2: 5, 3: 6)
496 * +-+ sys_div (0x306 [0])
498 * +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
500 * +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
502 * +-+ sclk_pre_div (0x3106 [3:2], special values:
503 * | 0: 1, 1: 2, 2: 4, 3: 1)
505 * +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
510 struct ov8865_pll1_config {
511 unsigned int pll_pre_div_half;
512 unsigned int pll_pre_div;
513 unsigned int pll_mul;
515 unsigned int mipi_div;
516 unsigned int pclk_div;
517 unsigned int sys_pre_div;
518 unsigned int sys_div;
526 * +-+ pll_pre_div_half (0x312 [4])
528 * +-+ pll_pre_div (0x30b [2:0], special values:
529 * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
530 * +-+ pll_mul (0x30c [1:0], 0x30d [7:0])
532 * +-+ dac_div (0x312 [3:0])
536 * +-+ sys_pre_div (0x30f [3:0])
538 * +-+ sys_div (0x30e [2:0], special values:
539 * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 3.5, 6: 4, 7:5)
541 * +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
543 * +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
545 * +-+ sclk_pre_div (0x3106 [3:2], special values:
546 * | 0: 1, 1: 2, 2: 4, 3: 1)
548 * +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
553 struct ov8865_pll2_config {
554 unsigned int pll_pre_div_half;
555 unsigned int pll_pre_div;
556 unsigned int pll_mul;
557 unsigned int dac_div;
558 unsigned int sys_pre_div;
559 unsigned int sys_div;
562 struct ov8865_sclk_config {
563 unsigned int sys_sel;
564 unsigned int sclk_sel;
565 unsigned int sclk_pre_div;
566 unsigned int sclk_div;
570 * General formulas for (array-centered) mode calculation:
571 * - photo_array_width = 3296
572 * - crop_start_x = (photo_array_width - output_size_x) / 2
573 * - crop_end_x = crop_start_x + offset_x + output_size_x - 1
575 * - photo_array_height = 2480
576 * - crop_start_y = (photo_array_height - output_size_y) / 2
577 * - crop_end_y = crop_start_y + offset_y + output_size_y - 1
581 unsigned int crop_start_x;
582 unsigned int offset_x;
583 unsigned int output_size_x;
584 unsigned int crop_end_x;
587 unsigned int crop_start_y;
588 unsigned int offset_y;
589 unsigned int output_size_y;
590 unsigned int crop_end_y;
593 /* With auto size, only output and total sizes need to be set. */
595 unsigned int size_auto_boundary_x;
596 unsigned int size_auto_boundary_y;
601 unsigned int variopixel_hsub_coef;
602 unsigned int variopixel_vsub_coef;
604 /* Bits for the format register, used for binning. */
608 unsigned int inc_x_odd;
609 unsigned int inc_x_even;
610 unsigned int inc_y_odd;
611 unsigned int inc_y_even;
613 unsigned int vfifo_read_start;
615 unsigned int ablc_num;
616 unsigned int zline_num;
618 unsigned int blc_top_zero_line_start;
619 unsigned int blc_top_zero_line_num;
620 unsigned int blc_top_black_line_start;
621 unsigned int blc_top_black_line_num;
623 unsigned int blc_bottom_zero_line_start;
624 unsigned int blc_bottom_zero_line_num;
625 unsigned int blc_bottom_black_line_start;
626 unsigned int blc_bottom_black_line_num;
628 u8 blc_col_shift_mask;
630 unsigned int blc_anchor_left_start;
631 unsigned int blc_anchor_left_end;
632 unsigned int blc_anchor_right_start;
633 unsigned int blc_anchor_right_end;
635 struct v4l2_fract frame_interval;
637 const struct ov8865_pll1_config *pll1_config;
638 const struct ov8865_pll2_config *pll2_config;
639 const struct ov8865_sclk_config *sclk_config;
641 const struct ov8865_register_value *register_values;
642 unsigned int register_values_count;
645 struct ov8865_state {
646 const struct ov8865_mode *mode;
652 struct ov8865_ctrls {
653 struct v4l2_ctrl *link_freq;
654 struct v4l2_ctrl *pixel_rate;
656 struct v4l2_ctrl_handler handler;
659 struct ov8865_sensor {
661 struct i2c_client *i2c_client;
662 struct gpio_desc *reset;
663 struct gpio_desc *powerdown;
664 struct regulator *avdd;
665 struct regulator *dvdd;
666 struct regulator *dovdd;
669 struct v4l2_fwnode_endpoint endpoint;
670 struct v4l2_subdev subdev;
671 struct media_pad pad;
675 struct ov8865_state state;
676 struct ov8865_ctrls ctrls;
679 /* Static definitions */
686 static const struct ov8865_pll1_config ov8865_pll1_config_native = {
687 .pll_pre_div_half = 1,
703 static const struct ov8865_pll2_config ov8865_pll2_config_native = {
704 .pll_pre_div_half = 1,
718 static const struct ov8865_pll2_config ov8865_pll2_config_binning = {
719 .pll_pre_div_half = 1,
727 static const struct ov8865_sclk_config ov8865_sclk_config_native = {
734 static const struct ov8865_register_value ov8865_register_values_native[] = {
804 { OV8865_PSRAM_CTRL8_REG, 0x16 },
811 static const struct ov8865_register_value ov8865_register_values_binning[] = {
881 { OV8865_PSRAM_CTRL8_REG, 0x0b },
888 static const struct ov8865_mode ov8865_modes[] = {
892 .output_size_x = 3264,
896 .output_size_y = 2448,
900 .size_auto_boundary_x = 8,
901 .size_auto_boundary_y = 4,
903 /* Subsample increase */
910 .vfifo_read_start = 16,
917 .blc_top_zero_line_start = 0,
918 .blc_top_zero_line_num = 2,
919 .blc_top_black_line_start = 4,
920 .blc_top_black_line_num = 4,
922 .blc_bottom_zero_line_start = 2,
923 .blc_bottom_zero_line_num = 2,
924 .blc_bottom_black_line_start = 8,
925 .blc_bottom_black_line_num = 2,
927 .blc_anchor_left_start = 576,
928 .blc_anchor_left_end = 831,
929 .blc_anchor_right_start = 1984,
930 .blc_anchor_right_end = 2239,
933 .frame_interval = { 1, 30 },
936 .pll1_config = &ov8865_pll1_config_native,
937 .pll2_config = &ov8865_pll2_config_native,
938 .sclk_config = &ov8865_sclk_config_native,
941 .register_values = ov8865_register_values_native,
942 .register_values_count =
943 ARRAY_SIZE(ov8865_register_values_native),
948 .output_size_x = 3264,
952 .output_size_y = 1836,
956 .size_auto_boundary_x = 8,
957 .size_auto_boundary_y = 4,
959 /* Subsample increase */
966 .vfifo_read_start = 16,
973 .blc_top_zero_line_start = 0,
974 .blc_top_zero_line_num = 2,
975 .blc_top_black_line_start = 4,
976 .blc_top_black_line_num = 4,
978 .blc_bottom_zero_line_start = 2,
979 .blc_bottom_zero_line_num = 2,
980 .blc_bottom_black_line_start = 8,
981 .blc_bottom_black_line_num = 2,
983 .blc_anchor_left_start = 576,
984 .blc_anchor_left_end = 831,
985 .blc_anchor_right_start = 1984,
986 .blc_anchor_right_end = 2239,
989 .frame_interval = { 1, 30 },
992 .pll1_config = &ov8865_pll1_config_native,
993 .pll2_config = &ov8865_pll2_config_native,
994 .sclk_config = &ov8865_sclk_config_native,
997 .register_values = ov8865_register_values_native,
998 .register_values_count =
999 ARRAY_SIZE(ov8865_register_values_native),
1004 .output_size_x = 1632,
1008 .output_size_y = 1224,
1012 .size_auto_boundary_x = 8,
1013 .size_auto_boundary_y = 8,
1015 /* Subsample increase */
1026 .vfifo_read_start = 116,
1033 .blc_top_zero_line_start = 0,
1034 .blc_top_zero_line_num = 2,
1035 .blc_top_black_line_start = 4,
1036 .blc_top_black_line_num = 4,
1038 .blc_bottom_zero_line_start = 2,
1039 .blc_bottom_zero_line_num = 2,
1040 .blc_bottom_black_line_start = 8,
1041 .blc_bottom_black_line_num = 2,
1043 .blc_anchor_left_start = 288,
1044 .blc_anchor_left_end = 415,
1045 .blc_anchor_right_start = 992,
1046 .blc_anchor_right_end = 1119,
1048 /* Frame Interval */
1049 .frame_interval = { 1, 30 },
1052 .pll1_config = &ov8865_pll1_config_native,
1053 .pll2_config = &ov8865_pll2_config_binning,
1054 .sclk_config = &ov8865_sclk_config_native,
1057 .register_values = ov8865_register_values_binning,
1058 .register_values_count =
1059 ARRAY_SIZE(ov8865_register_values_binning),
1061 /* 800x600 (SVGA) */
1064 .output_size_x = 800,
1068 .output_size_y = 600,
1072 .size_auto_boundary_x = 8,
1073 .size_auto_boundary_y = 8,
1075 /* Subsample increase */
1084 .variopixel_hsub_coef = 2,
1085 .variopixel_vsub_coef = 1,
1090 .vfifo_read_start = 80,
1097 .blc_top_zero_line_start = 0,
1098 .blc_top_zero_line_num = 2,
1099 .blc_top_black_line_start = 2,
1100 .blc_top_black_line_num = 2,
1102 .blc_bottom_zero_line_start = 0,
1103 .blc_bottom_zero_line_num = 0,
1104 .blc_bottom_black_line_start = 4,
1105 .blc_bottom_black_line_num = 2,
1107 .blc_col_shift_mask = OV8865_BLC_CTRL1_COL_SHIFT_128,
1109 .blc_anchor_left_start = 288,
1110 .blc_anchor_left_end = 415,
1111 .blc_anchor_right_start = 992,
1112 .blc_anchor_right_end = 1119,
1114 /* Frame Interval */
1115 .frame_interval = { 1, 90 },
1118 .pll1_config = &ov8865_pll1_config_native,
1119 .pll2_config = &ov8865_pll2_config_binning,
1120 .sclk_config = &ov8865_sclk_config_native,
1123 .register_values = ov8865_register_values_binning,
1124 .register_values_count =
1125 ARRAY_SIZE(ov8865_register_values_binning),
1129 static const u32 ov8865_mbus_codes[] = {
1130 MEDIA_BUS_FMT_SBGGR10_1X10,
1133 static const struct ov8865_register_value ov8865_init_sequence[] = {
1268 static const s64 ov8865_link_freq_menu[] = {
1272 static const char *const ov8865_test_pattern_menu[] = {
1276 "Color bars with rolling bar",
1278 "Color squares with rolling bar"
1281 static const u8 ov8865_test_pattern_bits[] = {
1283 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_RANDOM_DATA,
1284 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_COLOR_BARS,
1285 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_ROLLING_BAR_EN |
1286 OV8865_PRE_CTRL0_PATTERN_COLOR_BARS,
1287 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES,
1288 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_ROLLING_BAR_EN |
1289 OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES,
1294 static int ov8865_read(struct ov8865_sensor *sensor, u16 address, u8 *value)
1296 unsigned char data[2] = { address >> 8, address & 0xff };
1297 struct i2c_client *client = sensor->i2c_client;
1300 ret = i2c_master_send(client, data, sizeof(data));
1302 dev_dbg(&client->dev, "i2c send error at address %#04x\n",
1307 ret = i2c_master_recv(client, value, 1);
1309 dev_dbg(&client->dev, "i2c recv error at address %#04x\n",
1317 static int ov8865_write(struct ov8865_sensor *sensor, u16 address, u8 value)
1319 unsigned char data[3] = { address >> 8, address & 0xff, value };
1320 struct i2c_client *client = sensor->i2c_client;
1323 ret = i2c_master_send(client, data, sizeof(data));
1325 dev_dbg(&client->dev, "i2c send error at address %#04x\n",
1333 static int ov8865_write_sequence(struct ov8865_sensor *sensor,
1334 const struct ov8865_register_value *sequence,
1335 unsigned int sequence_count)
1340 for (i = 0; i < sequence_count; i++) {
1341 ret = ov8865_write(sensor, sequence[i].address,
1346 if (sequence[i].delay_ms)
1347 msleep(sequence[i].delay_ms);
1353 static int ov8865_update_bits(struct ov8865_sensor *sensor, u16 address,
1359 ret = ov8865_read(sensor, address, &value);
1366 return ov8865_write(sensor, address, value);
1371 static int ov8865_sw_reset(struct ov8865_sensor *sensor)
1373 return ov8865_write(sensor, OV8865_SW_RESET_REG, OV8865_SW_RESET_RESET);
1376 static int ov8865_sw_standby(struct ov8865_sensor *sensor, int standby)
1381 value = OV8865_SW_STANDBY_STREAM_ON;
1383 return ov8865_write(sensor, OV8865_SW_STANDBY_REG, value);
1386 static int ov8865_chip_id_check(struct ov8865_sensor *sensor)
1388 u16 regs[] = { OV8865_CHIP_ID_HH_REG, OV8865_CHIP_ID_H_REG,
1389 OV8865_CHIP_ID_L_REG };
1390 u8 values[] = { OV8865_CHIP_ID_HH_VALUE, OV8865_CHIP_ID_H_VALUE,
1391 OV8865_CHIP_ID_L_VALUE };
1396 for (i = 0; i < ARRAY_SIZE(regs); i++) {
1397 ret = ov8865_read(sensor, regs[i], &value);
1401 if (value != values[i]) {
1402 dev_err(sensor->dev,
1403 "chip id value mismatch: %#x instead of %#x\n",
1412 static int ov8865_charge_pump_configure(struct ov8865_sensor *sensor)
1414 return ov8865_write(sensor, OV8865_PUMP_CLK_DIV_REG,
1415 OV8865_PUMP_CLK_DIV_PUMP_P(1));
1418 static int ov8865_mipi_configure(struct ov8865_sensor *sensor)
1420 struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
1421 &sensor->endpoint.bus.mipi_csi2;
1422 unsigned int lanes_count = bus_mipi_csi2->num_data_lanes;
1425 ret = ov8865_write(sensor, OV8865_MIPI_SC_CTRL0_REG,
1426 OV8865_MIPI_SC_CTRL0_LANES(lanes_count) |
1427 OV8865_MIPI_SC_CTRL0_MIPI_EN |
1428 OV8865_MIPI_SC_CTRL0_UNKNOWN);
1432 ret = ov8865_write(sensor, OV8865_MIPI_SC_CTRL2_REG,
1433 OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC);
1437 if (lanes_count >= 2) {
1438 ret = ov8865_write(sensor, OV8865_MIPI_LANE_SEL01_REG,
1439 OV8865_MIPI_LANE_SEL01_LANE0(0) |
1440 OV8865_MIPI_LANE_SEL01_LANE1(1));
1445 if (lanes_count >= 4) {
1446 ret = ov8865_write(sensor, OV8865_MIPI_LANE_SEL23_REG,
1447 OV8865_MIPI_LANE_SEL23_LANE2(2) |
1448 OV8865_MIPI_LANE_SEL23_LANE3(3));
1453 ret = ov8865_update_bits(sensor, OV8865_CLK_SEL1_REG,
1454 OV8865_CLK_SEL1_MIPI_EOF,
1455 OV8865_CLK_SEL1_MIPI_EOF);
1460 * This value might need to change depending on PCLK rate,
1461 * but it's unclear how. This value seems to generally work
1462 * while the default value was found to cause transmission errors.
1464 return ov8865_write(sensor, OV8865_MIPI_PCLK_PERIOD_REG, 0x16);
1467 static int ov8865_black_level_configure(struct ov8865_sensor *sensor)
1471 /* Trigger BLC on relevant events and enable filter. */
1472 ret = ov8865_write(sensor, OV8865_BLC_CTRL0_REG,
1473 OV8865_BLC_CTRL0_TRIG_RANGE_EN |
1474 OV8865_BLC_CTRL0_TRIG_FORMAT_EN |
1475 OV8865_BLC_CTRL0_TRIG_GAIN_EN |
1476 OV8865_BLC_CTRL0_TRIG_EXPOSURE_EN |
1477 OV8865_BLC_CTRL0_FILTER_EN);
1481 /* Lower BLC offset trigger threshold. */
1482 ret = ov8865_write(sensor, OV8865_BLC_CTRLD_REG,
1483 OV8865_BLC_CTRLD_OFFSET_TRIGGER(16));
1487 ret = ov8865_write(sensor, OV8865_BLC_CTRL1F_REG, 0);
1491 /* Increase BLC offset maximum limit. */
1492 return ov8865_write(sensor, OV8865_BLC_OFFSET_LIMIT_REG,
1493 OV8865_BLC_OFFSET_LIMIT(63));
1496 static int ov8865_isp_configure(struct ov8865_sensor *sensor)
1500 /* Disable lens correction. */
1501 ret = ov8865_write(sensor, OV8865_ISP_CTRL0_REG,
1502 OV8865_ISP_CTRL0_WHITE_BALANCE_EN |
1503 OV8865_ISP_CTRL0_DPC_BLACK_EN |
1504 OV8865_ISP_CTRL0_DPC_WHITE_EN);
1508 return ov8865_write(sensor, OV8865_ISP_CTRL1_REG,
1509 OV8865_ISP_CTRL1_BLC_EN);
1512 static unsigned long ov8865_mode_pll1_rate(struct ov8865_sensor *sensor,
1513 const struct ov8865_mode *mode)
1515 const struct ov8865_pll1_config *config = mode->pll1_config;
1516 unsigned long extclk_rate;
1517 unsigned long pll1_rate;
1519 extclk_rate = clk_get_rate(sensor->extclk);
1520 pll1_rate = extclk_rate * config->pll_mul / config->pll_pre_div_half;
1522 switch (config->pll_pre_div) {
1543 pll1_rate /= config->pll_pre_div;
1550 static int ov8865_mode_pll1_configure(struct ov8865_sensor *sensor,
1551 const struct ov8865_mode *mode,
1554 const struct ov8865_pll1_config *config = mode->pll1_config;
1558 switch (mbus_code) {
1559 case MEDIA_BUS_FMT_SBGGR10_1X10:
1560 value = OV8865_MIPI_BIT_SEL(10);
1566 ret = ov8865_write(sensor, OV8865_MIPI_BIT_SEL_REG, value);
1570 ret = ov8865_write(sensor, OV8865_PLL_CTRLA_REG,
1571 OV8865_PLL_CTRLA_PRE_DIV_HALF(config->pll_pre_div_half));
1575 ret = ov8865_write(sensor, OV8865_PLL_CTRL0_REG,
1576 OV8865_PLL_CTRL0_PRE_DIV(config->pll_pre_div));
1580 ret = ov8865_write(sensor, OV8865_PLL_CTRL1_REG,
1581 OV8865_PLL_CTRL1_MUL_H(config->pll_mul));
1585 ret = ov8865_write(sensor, OV8865_PLL_CTRL2_REG,
1586 OV8865_PLL_CTRL2_MUL_L(config->pll_mul));
1590 ret = ov8865_write(sensor, OV8865_PLL_CTRL3_REG,
1591 OV8865_PLL_CTRL3_M_DIV(config->m_div));
1595 ret = ov8865_write(sensor, OV8865_PLL_CTRL4_REG,
1596 OV8865_PLL_CTRL4_MIPI_DIV(config->mipi_div));
1600 ret = ov8865_update_bits(sensor, OV8865_PCLK_SEL_REG,
1601 OV8865_PCLK_SEL_PCLK_DIV_MASK,
1602 OV8865_PCLK_SEL_PCLK_DIV(config->pclk_div));
1606 ret = ov8865_write(sensor, OV8865_PLL_CTRL5_REG,
1607 OV8865_PLL_CTRL5_SYS_PRE_DIV(config->sys_pre_div));
1611 ret = ov8865_write(sensor, OV8865_PLL_CTRL6_REG,
1612 OV8865_PLL_CTRL6_SYS_DIV(config->sys_div));
1616 return ov8865_update_bits(sensor, OV8865_PLL_CTRL1E_REG,
1617 OV8865_PLL_CTRL1E_PLL1_NO_LAT,
1618 OV8865_PLL_CTRL1E_PLL1_NO_LAT);
1621 static int ov8865_mode_pll2_configure(struct ov8865_sensor *sensor,
1622 const struct ov8865_mode *mode)
1624 const struct ov8865_pll2_config *config = mode->pll2_config;
1627 ret = ov8865_write(sensor, OV8865_PLL_CTRL12_REG,
1628 OV8865_PLL_CTRL12_PRE_DIV_HALF(config->pll_pre_div_half) |
1629 OV8865_PLL_CTRL12_DAC_DIV(config->dac_div));
1633 ret = ov8865_write(sensor, OV8865_PLL_CTRLB_REG,
1634 OV8865_PLL_CTRLB_PRE_DIV(config->pll_pre_div));
1638 ret = ov8865_write(sensor, OV8865_PLL_CTRLC_REG,
1639 OV8865_PLL_CTRLC_MUL_H(config->pll_mul));
1643 ret = ov8865_write(sensor, OV8865_PLL_CTRLD_REG,
1644 OV8865_PLL_CTRLD_MUL_L(config->pll_mul));
1648 ret = ov8865_write(sensor, OV8865_PLL_CTRLF_REG,
1649 OV8865_PLL_CTRLF_SYS_PRE_DIV(config->sys_pre_div));
1653 return ov8865_write(sensor, OV8865_PLL_CTRLE_REG,
1654 OV8865_PLL_CTRLE_SYS_DIV(config->sys_div));
1657 static int ov8865_mode_sclk_configure(struct ov8865_sensor *sensor,
1658 const struct ov8865_mode *mode)
1660 const struct ov8865_sclk_config *config = mode->sclk_config;
1663 ret = ov8865_write(sensor, OV8865_CLK_SEL0_REG,
1664 OV8865_CLK_SEL0_PLL1_SYS_SEL(config->sys_sel));
1668 ret = ov8865_update_bits(sensor, OV8865_CLK_SEL1_REG,
1669 OV8865_CLK_SEL1_PLL_SCLK_SEL_MASK,
1670 OV8865_CLK_SEL1_PLL_SCLK_SEL(config->sclk_sel));
1674 return ov8865_write(sensor, OV8865_SCLK_CTRL_REG,
1675 OV8865_SCLK_CTRL_UNKNOWN |
1676 OV8865_SCLK_CTRL_SCLK_DIV(config->sclk_div) |
1677 OV8865_SCLK_CTRL_SCLK_PRE_DIV(config->sclk_pre_div));
1680 static int ov8865_mode_binning_configure(struct ov8865_sensor *sensor,
1681 const struct ov8865_mode *mode)
1683 unsigned int variopixel_hsub_coef, variopixel_vsub_coef;
1687 ret = ov8865_write(sensor, OV8865_FORMAT1_REG, 0);
1691 value = OV8865_FORMAT2_HSYNC_EN;
1693 if (mode->binning_x)
1694 value |= OV8865_FORMAT2_FST_HBIN_EN;
1696 if (mode->binning_y)
1697 value |= OV8865_FORMAT2_FST_VBIN_EN;
1699 if (mode->sync_hbin)
1700 value |= OV8865_FORMAT2_SYNC_HBIN_EN;
1702 if (mode->horz_var2)
1703 value |= OV8865_FORMAT2_ISP_HORZ_VAR2_EN;
1705 ret = ov8865_write(sensor, OV8865_FORMAT2_REG, value);
1709 ret = ov8865_update_bits(sensor, OV8865_ISP_CTRL2_REG,
1710 OV8865_ISP_CTRL2_VARIOPIXEL_EN,
1712 OV8865_ISP_CTRL2_VARIOPIXEL_EN : 0);
1716 if (mode->variopixel) {
1717 /* VarioPixel coefs needs to be > 1. */
1718 variopixel_hsub_coef = mode->variopixel_hsub_coef;
1719 variopixel_vsub_coef = mode->variopixel_vsub_coef;
1721 variopixel_hsub_coef = 1;
1722 variopixel_vsub_coef = 1;
1725 ret = ov8865_write(sensor, OV8865_VAP_CTRL1_REG,
1726 OV8865_VAP_CTRL1_HSUB_COEF(variopixel_hsub_coef) |
1727 OV8865_VAP_CTRL1_VSUB_COEF(variopixel_vsub_coef));
1731 ret = ov8865_write(sensor, OV8865_INC_X_ODD_REG,
1732 OV8865_INC_X_ODD(mode->inc_x_odd));
1736 ret = ov8865_write(sensor, OV8865_INC_X_EVEN_REG,
1737 OV8865_INC_X_EVEN(mode->inc_x_even));
1741 ret = ov8865_write(sensor, OV8865_INC_Y_ODD_REG,
1742 OV8865_INC_Y_ODD(mode->inc_y_odd));
1746 return ov8865_write(sensor, OV8865_INC_Y_EVEN_REG,
1747 OV8865_INC_Y_EVEN(mode->inc_y_even));
1750 static int ov8865_mode_black_level_configure(struct ov8865_sensor *sensor,
1751 const struct ov8865_mode *mode)
1755 /* Note that a zero value for blc_col_shift_mask is the default 256. */
1756 ret = ov8865_write(sensor, OV8865_BLC_CTRL1_REG,
1757 mode->blc_col_shift_mask |
1758 OV8865_BLC_CTRL1_OFFSET_LIMIT_EN);
1762 /* BLC top zero line */
1764 ret = ov8865_write(sensor, OV8865_BLC_TOP_ZLINE_START_REG,
1765 OV8865_BLC_TOP_ZLINE_START(mode->blc_top_zero_line_start));
1769 ret = ov8865_write(sensor, OV8865_BLC_TOP_ZLINE_NUM_REG,
1770 OV8865_BLC_TOP_ZLINE_NUM(mode->blc_top_zero_line_num));
1774 /* BLC top black line */
1776 ret = ov8865_write(sensor, OV8865_BLC_TOP_BLKLINE_START_REG,
1777 OV8865_BLC_TOP_BLKLINE_START(mode->blc_top_black_line_start));
1781 ret = ov8865_write(sensor, OV8865_BLC_TOP_BLKLINE_NUM_REG,
1782 OV8865_BLC_TOP_BLKLINE_NUM(mode->blc_top_black_line_num));
1786 /* BLC bottom zero line */
1788 ret = ov8865_write(sensor, OV8865_BLC_BOT_ZLINE_START_REG,
1789 OV8865_BLC_BOT_ZLINE_START(mode->blc_bottom_zero_line_start));
1793 ret = ov8865_write(sensor, OV8865_BLC_BOT_ZLINE_NUM_REG,
1794 OV8865_BLC_BOT_ZLINE_NUM(mode->blc_bottom_zero_line_num));
1798 /* BLC bottom black line */
1800 ret = ov8865_write(sensor, OV8865_BLC_BOT_BLKLINE_START_REG,
1801 OV8865_BLC_BOT_BLKLINE_START(mode->blc_bottom_black_line_start));
1805 ret = ov8865_write(sensor, OV8865_BLC_BOT_BLKLINE_NUM_REG,
1806 OV8865_BLC_BOT_BLKLINE_NUM(mode->blc_bottom_black_line_num));
1812 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_START_H_REG,
1813 OV8865_BLC_ANCHOR_LEFT_START_H(mode->blc_anchor_left_start));
1817 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_START_L_REG,
1818 OV8865_BLC_ANCHOR_LEFT_START_L(mode->blc_anchor_left_start));
1822 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_END_H_REG,
1823 OV8865_BLC_ANCHOR_LEFT_END_H(mode->blc_anchor_left_end));
1827 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_END_L_REG,
1828 OV8865_BLC_ANCHOR_LEFT_END_L(mode->blc_anchor_left_end));
1832 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_START_H_REG,
1833 OV8865_BLC_ANCHOR_RIGHT_START_H(mode->blc_anchor_right_start));
1837 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_START_L_REG,
1838 OV8865_BLC_ANCHOR_RIGHT_START_L(mode->blc_anchor_right_start));
1842 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_END_H_REG,
1843 OV8865_BLC_ANCHOR_RIGHT_END_H(mode->blc_anchor_right_end));
1847 return ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_END_L_REG,
1848 OV8865_BLC_ANCHOR_RIGHT_END_L(mode->blc_anchor_right_end));
1851 static int ov8865_mode_configure(struct ov8865_sensor *sensor,
1852 const struct ov8865_mode *mode, u32 mbus_code)
1858 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_X_H_REG,
1859 OV8865_OUTPUT_SIZE_X_H(mode->output_size_x));
1863 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_X_L_REG,
1864 OV8865_OUTPUT_SIZE_X_L(mode->output_size_x));
1868 /* Horizontal Total Size */
1870 ret = ov8865_write(sensor, OV8865_HTS_H_REG, OV8865_HTS_H(mode->hts));
1874 ret = ov8865_write(sensor, OV8865_HTS_L_REG, OV8865_HTS_L(mode->hts));
1880 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_Y_H_REG,
1881 OV8865_OUTPUT_SIZE_Y_H(mode->output_size_y));
1885 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_Y_L_REG,
1886 OV8865_OUTPUT_SIZE_Y_L(mode->output_size_y));
1890 /* Vertical Total Size */
1892 ret = ov8865_write(sensor, OV8865_VTS_H_REG, OV8865_VTS_H(mode->vts));
1896 ret = ov8865_write(sensor, OV8865_VTS_L_REG, OV8865_VTS_L(mode->vts));
1900 if (mode->size_auto) {
1903 ret = ov8865_write(sensor, OV8865_AUTO_SIZE_CTRL_REG,
1904 OV8865_AUTO_SIZE_CTRL_OFFSET_Y_REG |
1905 OV8865_AUTO_SIZE_CTRL_OFFSET_X_REG |
1906 OV8865_AUTO_SIZE_CTRL_CROP_END_Y_REG |
1907 OV8865_AUTO_SIZE_CTRL_CROP_END_X_REG |
1908 OV8865_AUTO_SIZE_CTRL_CROP_START_Y_REG |
1909 OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG);
1913 ret = ov8865_write(sensor, OV8865_AUTO_SIZE_BOUNDARIES_REG,
1914 OV8865_AUTO_SIZE_BOUNDARIES_Y(mode->size_auto_boundary_y) |
1915 OV8865_AUTO_SIZE_BOUNDARIES_X(mode->size_auto_boundary_x));
1921 ret = ov8865_write(sensor, OV8865_CROP_START_X_H_REG,
1922 OV8865_CROP_START_X_H(mode->crop_start_x));
1926 ret = ov8865_write(sensor, OV8865_CROP_START_X_L_REG,
1927 OV8865_CROP_START_X_L(mode->crop_start_x));
1933 ret = ov8865_write(sensor, OV8865_OFFSET_X_H_REG,
1934 OV8865_OFFSET_X_H(mode->offset_x));
1938 ret = ov8865_write(sensor, OV8865_OFFSET_X_L_REG,
1939 OV8865_OFFSET_X_L(mode->offset_x));
1945 ret = ov8865_write(sensor, OV8865_CROP_END_X_H_REG,
1946 OV8865_CROP_END_X_H(mode->crop_end_x));
1950 ret = ov8865_write(sensor, OV8865_CROP_END_X_L_REG,
1951 OV8865_CROP_END_X_L(mode->crop_end_x));
1957 ret = ov8865_write(sensor, OV8865_CROP_START_Y_H_REG,
1958 OV8865_CROP_START_Y_H(mode->crop_start_y));
1962 ret = ov8865_write(sensor, OV8865_CROP_START_Y_L_REG,
1963 OV8865_CROP_START_Y_L(mode->crop_start_y));
1969 ret = ov8865_write(sensor, OV8865_OFFSET_Y_H_REG,
1970 OV8865_OFFSET_Y_H(mode->offset_y));
1974 ret = ov8865_write(sensor, OV8865_OFFSET_Y_L_REG,
1975 OV8865_OFFSET_Y_L(mode->offset_y));
1981 ret = ov8865_write(sensor, OV8865_CROP_END_Y_H_REG,
1982 OV8865_CROP_END_Y_H(mode->crop_end_y));
1986 ret = ov8865_write(sensor, OV8865_CROP_END_Y_L_REG,
1987 OV8865_CROP_END_Y_L(mode->crop_end_y));
1994 ret = ov8865_write(sensor, OV8865_VFIFO_READ_START_H_REG,
1995 OV8865_VFIFO_READ_START_H(mode->vfifo_read_start));
1999 ret = ov8865_write(sensor, OV8865_VFIFO_READ_START_L_REG,
2000 OV8865_VFIFO_READ_START_L(mode->vfifo_read_start));
2004 ret = ov8865_write(sensor, OV8865_ABLC_NUM_REG,
2005 OV8865_ABLC_NUM(mode->ablc_num));
2009 ret = ov8865_write(sensor, OV8865_ZLINE_NUM_REG,
2010 OV8865_ZLINE_NUM(mode->zline_num));
2016 ret = ov8865_mode_binning_configure(sensor, mode);
2022 ret = ov8865_mode_black_level_configure(sensor, mode);
2028 ret = ov8865_mode_pll1_configure(sensor, mode, mbus_code);
2032 ret = ov8865_mode_pll2_configure(sensor, mode);
2036 ret = ov8865_mode_sclk_configure(sensor, mode);
2040 /* Extra registers */
2042 if (mode->register_values) {
2043 ret = ov8865_write_sequence(sensor, mode->register_values,
2044 mode->register_values_count);
2052 static unsigned long ov8865_mode_mipi_clk_rate(struct ov8865_sensor *sensor,
2053 const struct ov8865_mode *mode)
2055 const struct ov8865_pll1_config *config = mode->pll1_config;
2056 unsigned long pll1_rate;
2058 pll1_rate = ov8865_mode_pll1_rate(sensor, mode);
2060 return pll1_rate / config->m_div / 2;
2065 static int ov8865_exposure_configure(struct ov8865_sensor *sensor, u32 exposure)
2069 ret = ov8865_write(sensor, OV8865_EXPOSURE_CTRL_HH_REG,
2070 OV8865_EXPOSURE_CTRL_HH(exposure));
2074 ret = ov8865_write(sensor, OV8865_EXPOSURE_CTRL_H_REG,
2075 OV8865_EXPOSURE_CTRL_H(exposure));
2079 return ov8865_write(sensor, OV8865_EXPOSURE_CTRL_L_REG,
2080 OV8865_EXPOSURE_CTRL_L(exposure));
2085 static int ov8865_gain_configure(struct ov8865_sensor *sensor, u32 gain)
2089 ret = ov8865_write(sensor, OV8865_GAIN_CTRL_H_REG,
2090 OV8865_GAIN_CTRL_H(gain));
2094 return ov8865_write(sensor, OV8865_GAIN_CTRL_L_REG,
2095 OV8865_GAIN_CTRL_L(gain));
2100 static int ov8865_red_balance_configure(struct ov8865_sensor *sensor,
2105 ret = ov8865_write(sensor, OV8865_ISP_GAIN_RED_H_REG,
2106 OV8865_ISP_GAIN_RED_H(red_balance));
2110 return ov8865_write(sensor, OV8865_ISP_GAIN_RED_L_REG,
2111 OV8865_ISP_GAIN_RED_L(red_balance));
2114 static int ov8865_blue_balance_configure(struct ov8865_sensor *sensor,
2119 ret = ov8865_write(sensor, OV8865_ISP_GAIN_BLUE_H_REG,
2120 OV8865_ISP_GAIN_BLUE_H(blue_balance));
2124 return ov8865_write(sensor, OV8865_ISP_GAIN_BLUE_L_REG,
2125 OV8865_ISP_GAIN_BLUE_L(blue_balance));
2130 static int ov8865_flip_vert_configure(struct ov8865_sensor *sensor, bool enable)
2132 u8 bits = OV8865_FORMAT1_FLIP_VERT_ISP_EN |
2133 OV8865_FORMAT1_FLIP_VERT_SENSOR_EN;
2135 return ov8865_update_bits(sensor, OV8865_FORMAT1_REG, bits,
2139 static int ov8865_flip_horz_configure(struct ov8865_sensor *sensor, bool enable)
2141 u8 bits = OV8865_FORMAT2_FLIP_HORZ_ISP_EN |
2142 OV8865_FORMAT2_FLIP_HORZ_SENSOR_EN;
2144 return ov8865_update_bits(sensor, OV8865_FORMAT2_REG, bits,
2150 static int ov8865_test_pattern_configure(struct ov8865_sensor *sensor,
2153 if (index >= ARRAY_SIZE(ov8865_test_pattern_bits))
2156 return ov8865_write(sensor, OV8865_PRE_CTRL0_REG,
2157 ov8865_test_pattern_bits[index]);
2162 static int ov8865_state_mipi_configure(struct ov8865_sensor *sensor,
2163 const struct ov8865_mode *mode,
2166 struct ov8865_ctrls *ctrls = &sensor->ctrls;
2167 struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
2168 &sensor->endpoint.bus.mipi_csi2;
2169 unsigned long mipi_clk_rate;
2170 unsigned int bits_per_sample;
2171 unsigned int lanes_count;
2173 s64 mipi_pixel_rate;
2175 mipi_clk_rate = ov8865_mode_mipi_clk_rate(sensor, mode);
2179 for (i = 0; i < ARRAY_SIZE(ov8865_link_freq_menu); i++) {
2180 s64 freq = ov8865_link_freq_menu[i];
2182 if (freq == mipi_clk_rate)
2186 for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) {
2187 u64 freq = sensor->endpoint.link_frequencies[j];
2189 if (freq == mipi_clk_rate)
2193 if (i == ARRAY_SIZE(ov8865_link_freq_menu)) {
2194 dev_err(sensor->dev,
2195 "failed to find %lu clk rate in link freq\n",
2197 } else if (j == sensor->endpoint.nr_of_link_frequencies) {
2198 dev_err(sensor->dev,
2199 "failed to find %lu clk rate in endpoint link-frequencies\n",
2202 __v4l2_ctrl_s_ctrl(ctrls->link_freq, i);
2205 switch (mbus_code) {
2206 case MEDIA_BUS_FMT_SBGGR10_1X10:
2207 bits_per_sample = 10;
2213 lanes_count = bus_mipi_csi2->num_data_lanes;
2214 mipi_pixel_rate = mipi_clk_rate * 2 * lanes_count / bits_per_sample;
2216 __v4l2_ctrl_s_ctrl_int64(ctrls->pixel_rate, mipi_pixel_rate);
2221 static int ov8865_state_configure(struct ov8865_sensor *sensor,
2222 const struct ov8865_mode *mode,
2227 if (sensor->state.streaming)
2230 /* State will be configured at first power on otherwise. */
2231 if (pm_runtime_enabled(sensor->dev) &&
2232 !pm_runtime_suspended(sensor->dev)) {
2233 ret = ov8865_mode_configure(sensor, mode, mbus_code);
2238 ret = ov8865_state_mipi_configure(sensor, mode, mbus_code);
2242 sensor->state.mode = mode;
2243 sensor->state.mbus_code = mbus_code;
2248 static int ov8865_state_init(struct ov8865_sensor *sensor)
2250 return ov8865_state_configure(sensor, &ov8865_modes[0],
2251 ov8865_mbus_codes[0]);
2256 static int ov8865_sensor_init(struct ov8865_sensor *sensor)
2260 ret = ov8865_sw_reset(sensor);
2262 dev_err(sensor->dev, "failed to perform sw reset\n");
2266 ret = ov8865_sw_standby(sensor, 1);
2268 dev_err(sensor->dev, "failed to set sensor standby\n");
2272 ret = ov8865_chip_id_check(sensor);
2274 dev_err(sensor->dev, "failed to check sensor chip id\n");
2278 ret = ov8865_write_sequence(sensor, ov8865_init_sequence,
2279 ARRAY_SIZE(ov8865_init_sequence));
2281 dev_err(sensor->dev, "failed to write init sequence\n");
2285 ret = ov8865_charge_pump_configure(sensor);
2287 dev_err(sensor->dev, "failed to configure pad\n");
2291 ret = ov8865_mipi_configure(sensor);
2293 dev_err(sensor->dev, "failed to configure MIPI\n");
2297 ret = ov8865_isp_configure(sensor);
2299 dev_err(sensor->dev, "failed to configure ISP\n");
2303 ret = ov8865_black_level_configure(sensor);
2305 dev_err(sensor->dev, "failed to configure black level\n");
2309 /* Configure current mode. */
2310 ret = ov8865_state_configure(sensor, sensor->state.mode,
2311 sensor->state.mbus_code);
2313 dev_err(sensor->dev, "failed to configure state\n");
2320 static int ov8865_sensor_power(struct ov8865_sensor *sensor, bool on)
2322 /* Keep initialized to zero for disable label. */
2326 gpiod_set_value_cansleep(sensor->reset, 1);
2327 gpiod_set_value_cansleep(sensor->powerdown, 1);
2329 ret = regulator_enable(sensor->dovdd);
2331 dev_err(sensor->dev,
2332 "failed to enable DOVDD regulator\n");
2336 ret = regulator_enable(sensor->avdd);
2338 dev_err(sensor->dev,
2339 "failed to enable AVDD regulator\n");
2343 ret = regulator_enable(sensor->dvdd);
2345 dev_err(sensor->dev,
2346 "failed to enable DVDD regulator\n");
2350 ret = clk_prepare_enable(sensor->extclk);
2352 dev_err(sensor->dev, "failed to enable EXTCLK clock\n");
2356 gpiod_set_value_cansleep(sensor->reset, 0);
2357 gpiod_set_value_cansleep(sensor->powerdown, 0);
2359 /* Time to enter streaming mode according to power timings. */
2360 usleep_range(10000, 12000);
2363 gpiod_set_value_cansleep(sensor->powerdown, 1);
2364 gpiod_set_value_cansleep(sensor->reset, 1);
2366 clk_disable_unprepare(sensor->extclk);
2368 regulator_disable(sensor->dvdd);
2369 regulator_disable(sensor->avdd);
2370 regulator_disable(sensor->dovdd);
2378 static int ov8865_s_ctrl(struct v4l2_ctrl *ctrl)
2380 struct v4l2_subdev *subdev = ov8865_ctrl_subdev(ctrl);
2381 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2385 /* Wait for the sensor to be on before setting controls. */
2386 if (pm_runtime_suspended(sensor->dev))
2390 case V4L2_CID_EXPOSURE:
2391 ret = ov8865_exposure_configure(sensor, ctrl->val);
2396 ret = ov8865_gain_configure(sensor, ctrl->val);
2400 case V4L2_CID_RED_BALANCE:
2401 return ov8865_red_balance_configure(sensor, ctrl->val);
2402 case V4L2_CID_BLUE_BALANCE:
2403 return ov8865_blue_balance_configure(sensor, ctrl->val);
2404 case V4L2_CID_HFLIP:
2405 return ov8865_flip_horz_configure(sensor, !!ctrl->val);
2406 case V4L2_CID_VFLIP:
2407 return ov8865_flip_vert_configure(sensor, !!ctrl->val);
2408 case V4L2_CID_TEST_PATTERN:
2409 index = (unsigned int)ctrl->val;
2410 return ov8865_test_pattern_configure(sensor, index);
2418 static const struct v4l2_ctrl_ops ov8865_ctrl_ops = {
2419 .s_ctrl = ov8865_s_ctrl,
2422 static int ov8865_ctrls_init(struct ov8865_sensor *sensor)
2424 struct ov8865_ctrls *ctrls = &sensor->ctrls;
2425 struct v4l2_ctrl_handler *handler = &ctrls->handler;
2426 const struct v4l2_ctrl_ops *ops = &ov8865_ctrl_ops;
2429 v4l2_ctrl_handler_init(handler, 32);
2431 /* Use our mutex for ctrl locking. */
2432 handler->lock = &sensor->mutex;
2436 v4l2_ctrl_new_std(handler, ops, V4L2_CID_EXPOSURE, 16, 1048575, 16,
2441 v4l2_ctrl_new_std(handler, ops, V4L2_CID_GAIN, 128, 8191, 128, 128);
2445 v4l2_ctrl_new_std(handler, ops, V4L2_CID_RED_BALANCE, 1, 32767, 1,
2448 v4l2_ctrl_new_std(handler, ops, V4L2_CID_BLUE_BALANCE, 1, 32767, 1,
2453 v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
2454 v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
2458 v4l2_ctrl_new_std_menu_items(handler, ops, V4L2_CID_TEST_PATTERN,
2459 ARRAY_SIZE(ov8865_test_pattern_menu) - 1,
2460 0, 0, ov8865_test_pattern_menu);
2465 v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
2466 ARRAY_SIZE(ov8865_link_freq_menu) - 1,
2467 0, ov8865_link_freq_menu);
2470 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 1,
2473 if (handler->error) {
2474 ret = handler->error;
2478 ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2479 ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2481 sensor->subdev.ctrl_handler = handler;
2486 v4l2_ctrl_handler_free(handler);
2491 /* Subdev Video Operations */
2493 static int ov8865_s_stream(struct v4l2_subdev *subdev, int enable)
2495 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2496 struct ov8865_state *state = &sensor->state;
2500 ret = pm_runtime_get_sync(sensor->dev);
2502 pm_runtime_put_noidle(sensor->dev);
2507 mutex_lock(&sensor->mutex);
2508 ret = ov8865_sw_standby(sensor, !enable);
2509 mutex_unlock(&sensor->mutex);
2514 state->streaming = !!enable;
2517 pm_runtime_put(sensor->dev);
2522 static int ov8865_g_frame_interval(struct v4l2_subdev *subdev,
2523 struct v4l2_subdev_frame_interval *interval)
2525 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2526 const struct ov8865_mode *mode;
2529 mutex_lock(&sensor->mutex);
2531 mode = sensor->state.mode;
2532 interval->interval = mode->frame_interval;
2534 mutex_unlock(&sensor->mutex);
2539 static const struct v4l2_subdev_video_ops ov8865_subdev_video_ops = {
2540 .s_stream = ov8865_s_stream,
2541 .g_frame_interval = ov8865_g_frame_interval,
2542 .s_frame_interval = ov8865_g_frame_interval,
2545 /* Subdev Pad Operations */
2547 static int ov8865_enum_mbus_code(struct v4l2_subdev *subdev,
2548 struct v4l2_subdev_pad_config *config,
2549 struct v4l2_subdev_mbus_code_enum *code_enum)
2551 if (code_enum->index >= ARRAY_SIZE(ov8865_mbus_codes))
2554 code_enum->code = ov8865_mbus_codes[code_enum->index];
2559 static void ov8865_mbus_format_fill(struct v4l2_mbus_framefmt *mbus_format,
2561 const struct ov8865_mode *mode)
2563 mbus_format->width = mode->output_size_x;
2564 mbus_format->height = mode->output_size_y;
2565 mbus_format->code = mbus_code;
2567 mbus_format->field = V4L2_FIELD_NONE;
2568 mbus_format->colorspace = V4L2_COLORSPACE_RAW;
2569 mbus_format->ycbcr_enc =
2570 V4L2_MAP_YCBCR_ENC_DEFAULT(mbus_format->colorspace);
2571 mbus_format->quantization = V4L2_QUANTIZATION_FULL_RANGE;
2572 mbus_format->xfer_func =
2573 V4L2_MAP_XFER_FUNC_DEFAULT(mbus_format->colorspace);
2576 static int ov8865_get_fmt(struct v4l2_subdev *subdev,
2577 struct v4l2_subdev_pad_config *config,
2578 struct v4l2_subdev_format *format)
2580 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2581 struct v4l2_mbus_framefmt *mbus_format = &format->format;
2583 mutex_lock(&sensor->mutex);
2585 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
2586 *mbus_format = *v4l2_subdev_get_try_format(subdev, config,
2589 ov8865_mbus_format_fill(mbus_format, sensor->state.mbus_code,
2590 sensor->state.mode);
2592 mutex_unlock(&sensor->mutex);
2597 static int ov8865_set_fmt(struct v4l2_subdev *subdev,
2598 struct v4l2_subdev_pad_config *config,
2599 struct v4l2_subdev_format *format)
2601 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2602 struct v4l2_mbus_framefmt *mbus_format = &format->format;
2603 const struct ov8865_mode *mode;
2608 mutex_lock(&sensor->mutex);
2610 if (sensor->state.streaming) {
2615 /* Try to find requested mbus code. */
2616 for (index = 0; index < ARRAY_SIZE(ov8865_mbus_codes); index++) {
2617 if (ov8865_mbus_codes[index] == mbus_format->code) {
2618 mbus_code = mbus_format->code;
2623 /* Fallback to default. */
2625 mbus_code = ov8865_mbus_codes[0];
2627 /* Find the mode with nearest dimensions. */
2628 mode = v4l2_find_nearest_size(ov8865_modes, ARRAY_SIZE(ov8865_modes),
2629 output_size_x, output_size_y,
2630 mbus_format->width, mbus_format->height);
2636 ov8865_mbus_format_fill(mbus_format, mbus_code, mode);
2638 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
2639 *v4l2_subdev_get_try_format(subdev, config, format->pad) =
2641 else if (sensor->state.mode != mode ||
2642 sensor->state.mbus_code != mbus_code)
2643 ret = ov8865_state_configure(sensor, mode, mbus_code);
2646 mutex_unlock(&sensor->mutex);
2651 static int ov8865_enum_frame_size(struct v4l2_subdev *subdev,
2652 struct v4l2_subdev_pad_config *config,
2653 struct v4l2_subdev_frame_size_enum *size_enum)
2655 const struct ov8865_mode *mode;
2657 if (size_enum->index >= ARRAY_SIZE(ov8865_modes))
2660 mode = &ov8865_modes[size_enum->index];
2662 size_enum->min_width = size_enum->max_width = mode->output_size_x;
2663 size_enum->min_height = size_enum->max_height = mode->output_size_y;
2668 static int ov8865_enum_frame_interval(struct v4l2_subdev *subdev,
2669 struct v4l2_subdev_pad_config *config,
2670 struct v4l2_subdev_frame_interval_enum *interval_enum)
2672 const struct ov8865_mode *mode = NULL;
2673 unsigned int mode_index;
2674 unsigned int interval_index;
2676 if (interval_enum->index > 0)
2679 * Multiple modes with the same dimensions may have different frame
2680 * intervals, so look up each relevant mode.
2682 for (mode_index = 0, interval_index = 0;
2683 mode_index < ARRAY_SIZE(ov8865_modes); mode_index++) {
2684 mode = &ov8865_modes[mode_index];
2686 if (mode->output_size_x == interval_enum->width &&
2687 mode->output_size_y == interval_enum->height) {
2688 if (interval_index == interval_enum->index)
2695 if (mode_index == ARRAY_SIZE(ov8865_modes) || !mode)
2698 interval_enum->interval = mode->frame_interval;
2703 static const struct v4l2_subdev_pad_ops ov8865_subdev_pad_ops = {
2704 .enum_mbus_code = ov8865_enum_mbus_code,
2705 .get_fmt = ov8865_get_fmt,
2706 .set_fmt = ov8865_set_fmt,
2707 .enum_frame_size = ov8865_enum_frame_size,
2708 .enum_frame_interval = ov8865_enum_frame_interval,
2711 static const struct v4l2_subdev_ops ov8865_subdev_ops = {
2712 .video = &ov8865_subdev_video_ops,
2713 .pad = &ov8865_subdev_pad_ops,
2716 static int ov8865_suspend(struct device *dev)
2718 struct i2c_client *client = to_i2c_client(dev);
2719 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
2720 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2721 struct ov8865_state *state = &sensor->state;
2724 mutex_lock(&sensor->mutex);
2726 if (state->streaming) {
2727 ret = ov8865_sw_standby(sensor, true);
2732 ret = ov8865_sensor_power(sensor, false);
2734 ov8865_sw_standby(sensor, false);
2737 mutex_unlock(&sensor->mutex);
2742 static int ov8865_resume(struct device *dev)
2744 struct i2c_client *client = to_i2c_client(dev);
2745 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
2746 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2747 struct ov8865_state *state = &sensor->state;
2750 mutex_lock(&sensor->mutex);
2752 ret = ov8865_sensor_power(sensor, true);
2756 ret = ov8865_sensor_init(sensor);
2760 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
2764 if (state->streaming) {
2765 ret = ov8865_sw_standby(sensor, false);
2773 ov8865_sensor_power(sensor, false);
2776 mutex_unlock(&sensor->mutex);
2781 static int ov8865_probe(struct i2c_client *client)
2783 struct device *dev = &client->dev;
2784 struct fwnode_handle *handle;
2785 struct ov8865_sensor *sensor;
2786 struct v4l2_subdev *subdev;
2787 struct media_pad *pad;
2791 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
2796 sensor->i2c_client = client;
2798 /* Graph Endpoint */
2800 handle = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
2802 dev_err(dev, "unable to find endpoint node\n");
2806 sensor->endpoint.bus_type = V4L2_MBUS_CSI2_DPHY;
2808 ret = v4l2_fwnode_endpoint_alloc_parse(handle, &sensor->endpoint);
2809 fwnode_handle_put(handle);
2811 dev_err(dev, "failed to parse endpoint node\n");
2817 sensor->powerdown = devm_gpiod_get_optional(dev, "powerdown",
2819 if (IS_ERR(sensor->powerdown)) {
2820 ret = PTR_ERR(sensor->powerdown);
2821 goto error_endpoint;
2824 sensor->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
2825 if (IS_ERR(sensor->reset)) {
2826 ret = PTR_ERR(sensor->reset);
2827 goto error_endpoint;
2832 /* DVDD: digital core */
2833 sensor->dvdd = devm_regulator_get(dev, "dvdd");
2834 if (IS_ERR(sensor->dvdd)) {
2835 dev_err(dev, "cannot get DVDD (digital core) regulator\n");
2836 ret = PTR_ERR(sensor->dvdd);
2837 goto error_endpoint;
2840 /* DOVDD: digital I/O */
2841 sensor->dovdd = devm_regulator_get(dev, "dovdd");
2842 if (IS_ERR(sensor->dovdd)) {
2843 dev_err(dev, "cannot get DOVDD (digital I/O) regulator\n");
2844 ret = PTR_ERR(sensor->dovdd);
2845 goto error_endpoint;
2849 sensor->avdd = devm_regulator_get(dev, "avdd");
2850 if (IS_ERR(sensor->avdd)) {
2851 dev_err(dev, "cannot get AVDD (analog) regulator\n");
2852 ret = PTR_ERR(sensor->avdd);
2853 goto error_endpoint;
2856 /* External Clock */
2858 sensor->extclk = devm_clk_get(dev, NULL);
2859 if (IS_ERR(sensor->extclk)) {
2860 dev_err(dev, "failed to get external clock\n");
2861 ret = PTR_ERR(sensor->extclk);
2862 goto error_endpoint;
2865 rate = clk_get_rate(sensor->extclk);
2866 if (rate != OV8865_EXTCLK_RATE) {
2867 dev_err(dev, "clock rate %lu Hz is unsupported\n", rate);
2869 goto error_endpoint;
2872 /* Subdev, entity and pad */
2874 subdev = &sensor->subdev;
2875 v4l2_i2c_subdev_init(subdev, client, &ov8865_subdev_ops);
2877 subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2878 subdev->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2881 pad->flags = MEDIA_PAD_FL_SOURCE;
2883 ret = media_entity_pads_init(&subdev->entity, 1, pad);
2889 mutex_init(&sensor->mutex);
2893 ret = ov8865_ctrls_init(sensor);
2897 ret = ov8865_state_init(sensor);
2903 pm_runtime_enable(sensor->dev);
2904 pm_runtime_set_suspended(sensor->dev);
2906 /* V4L2 subdev register */
2908 ret = v4l2_async_register_subdev_sensor_common(subdev);
2915 pm_runtime_disable(sensor->dev);
2918 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
2921 mutex_destroy(&sensor->mutex);
2924 media_entity_cleanup(&sensor->subdev.entity);
2927 v4l2_fwnode_endpoint_free(&sensor->endpoint);
2932 static int ov8865_remove(struct i2c_client *client)
2934 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
2935 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);
2937 v4l2_async_unregister_subdev(subdev);
2938 pm_runtime_disable(sensor->dev);
2939 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
2940 mutex_destroy(&sensor->mutex);
2941 media_entity_cleanup(&subdev->entity);
2943 v4l2_fwnode_endpoint_free(&sensor->endpoint);
2948 static const struct dev_pm_ops ov8865_pm_ops = {
2949 SET_RUNTIME_PM_OPS(ov8865_suspend, ov8865_resume, NULL)
2952 static const struct of_device_id ov8865_of_match[] = {
2953 { .compatible = "ovti,ov8865" },
2956 MODULE_DEVICE_TABLE(of, ov8865_of_match);
2958 static struct i2c_driver ov8865_driver = {
2961 .of_match_table = ov8865_of_match,
2962 .pm = &ov8865_pm_ops,
2964 .probe_new = ov8865_probe,
2965 .remove = ov8865_remove,
2968 module_i2c_driver(ov8865_driver);
2970 MODULE_AUTHOR("Paul Kocialkowski <paul.kocialkowski@bootlin.com>");
2971 MODULE_DESCRIPTION("V4L2 driver for the OmniVision OV8865 image sensor");
2972 MODULE_LICENSE("GPL v2");