1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
5 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
8 #include <linux/videodev2.h>
9 #include <linux/slab.h>
10 #include <linux/i2c.h>
11 #include <linux/log2.h>
12 #include <linux/delay.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/v4l2-mediabus.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
18 #include <media/v4l2-async.h>
19 #include <media/v4l2-common.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
26 * MT9M111, MT9M112 and MT9M131:
27 * i2c address is 0x48 or 0x5d (depending on SADDR pin)
28 * The platform has to define struct i2c_board_info objects and link to them
29 * from struct soc_camera_host_desc
33 * Sensor core register addresses (0x000..0x0ff)
35 #define MT9M111_CHIP_VERSION 0x000
36 #define MT9M111_ROW_START 0x001
37 #define MT9M111_COLUMN_START 0x002
38 #define MT9M111_WINDOW_HEIGHT 0x003
39 #define MT9M111_WINDOW_WIDTH 0x004
40 #define MT9M111_HORIZONTAL_BLANKING_B 0x005
41 #define MT9M111_VERTICAL_BLANKING_B 0x006
42 #define MT9M111_HORIZONTAL_BLANKING_A 0x007
43 #define MT9M111_VERTICAL_BLANKING_A 0x008
44 #define MT9M111_SHUTTER_WIDTH 0x009
45 #define MT9M111_ROW_SPEED 0x00a
46 #define MT9M111_EXTRA_DELAY 0x00b
47 #define MT9M111_SHUTTER_DELAY 0x00c
48 #define MT9M111_RESET 0x00d
49 #define MT9M111_READ_MODE_B 0x020
50 #define MT9M111_READ_MODE_A 0x021
51 #define MT9M111_FLASH_CONTROL 0x023
52 #define MT9M111_GREEN1_GAIN 0x02b
53 #define MT9M111_BLUE_GAIN 0x02c
54 #define MT9M111_RED_GAIN 0x02d
55 #define MT9M111_GREEN2_GAIN 0x02e
56 #define MT9M111_GLOBAL_GAIN 0x02f
57 #define MT9M111_CONTEXT_CONTROL 0x0c8
58 #define MT9M111_PAGE_MAP 0x0f0
59 #define MT9M111_BYTE_WISE_ADDR 0x0f1
61 #define MT9M111_RESET_SYNC_CHANGES (1 << 15)
62 #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
63 #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
64 #define MT9M111_RESET_RESET_SOC (1 << 5)
65 #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
66 #define MT9M111_RESET_CHIP_ENABLE (1 << 3)
67 #define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
68 #define MT9M111_RESET_RESTART_FRAME (1 << 1)
69 #define MT9M111_RESET_RESET_MODE (1 << 0)
71 #define MT9M111_RM_FULL_POWER_RD (0 << 10)
72 #define MT9M111_RM_LOW_POWER_RD (1 << 10)
73 #define MT9M111_RM_COL_SKIP_4X (1 << 5)
74 #define MT9M111_RM_ROW_SKIP_4X (1 << 4)
75 #define MT9M111_RM_COL_SKIP_2X (1 << 3)
76 #define MT9M111_RM_ROW_SKIP_2X (1 << 2)
77 #define MT9M111_RMB_MIRROR_COLS (1 << 1)
78 #define MT9M111_RMB_MIRROR_ROWS (1 << 0)
79 #define MT9M111_CTXT_CTRL_RESTART (1 << 15)
80 #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
81 #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
82 #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
83 #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
84 #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
85 #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
86 #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
87 #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
88 #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
91 * Colorpipe register addresses (0x100..0x1ff)
93 #define MT9M111_OPER_MODE_CTRL 0x106
94 #define MT9M111_OUTPUT_FORMAT_CTRL 0x108
95 #define MT9M111_TPG_CTRL 0x148
96 #define MT9M111_REDUCER_XZOOM_B 0x1a0
97 #define MT9M111_REDUCER_XSIZE_B 0x1a1
98 #define MT9M111_REDUCER_YZOOM_B 0x1a3
99 #define MT9M111_REDUCER_YSIZE_B 0x1a4
100 #define MT9M111_REDUCER_XZOOM_A 0x1a6
101 #define MT9M111_REDUCER_XSIZE_A 0x1a7
102 #define MT9M111_REDUCER_YZOOM_A 0x1a9
103 #define MT9M111_REDUCER_YSIZE_A 0x1aa
104 #define MT9M111_EFFECTS_MODE 0x1e2
106 #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
107 #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
109 #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
110 #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
111 #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
112 #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
113 #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
114 #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
115 #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
116 #define MT9M111_OUTFMT_RGB (1 << 8)
117 #define MT9M111_OUTFMT_RGB565 (0 << 6)
118 #define MT9M111_OUTFMT_RGB555 (1 << 6)
119 #define MT9M111_OUTFMT_RGB444x (2 << 6)
120 #define MT9M111_OUTFMT_RGBx444 (3 << 6)
121 #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
122 #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
123 #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
124 #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
125 #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
126 #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
127 #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
128 #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
129 #define MT9M111_TPG_SEL_MASK GENMASK(2, 0)
130 #define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0)
131 #define MT9M111_RM_PWR_MASK BIT(10)
132 #define MT9M111_RM_SKIP2_MASK GENMASK(3, 2)
135 * Camera control register addresses (0x200..0x2ff not implemented)
138 #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
139 #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
140 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
141 #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
142 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
145 #define MT9M111_MIN_DARK_ROWS 8
146 #define MT9M111_MIN_DARK_COLS 26
147 #define MT9M111_MAX_HEIGHT 1024
148 #define MT9M111_MAX_WIDTH 1280
150 struct mt9m111_context {
158 u16 output_fmt_ctrl2;
162 static struct mt9m111_context context_a = {
163 .read_mode = MT9M111_READ_MODE_A,
164 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
165 .blanking_v = MT9M111_VERTICAL_BLANKING_A,
166 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
167 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
168 .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
169 .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
170 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
171 .control = MT9M111_CTXT_CTRL_RESTART,
174 static struct mt9m111_context context_b = {
175 .read_mode = MT9M111_READ_MODE_B,
176 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
177 .blanking_v = MT9M111_VERTICAL_BLANKING_B,
178 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
179 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
180 .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
181 .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
182 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
183 .control = MT9M111_CTXT_CTRL_RESTART |
184 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
185 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
186 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
187 MT9M111_CTXT_CTRL_HBLANK_SEL_B,
190 /* MT9M111 has only one fixed colorspace per pixelcode */
191 struct mt9m111_datafmt {
193 enum v4l2_colorspace colorspace;
196 static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
197 {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB},
198 {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_SRGB},
199 {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB},
200 {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_SRGB},
201 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
202 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
203 {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
204 {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
205 {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
206 {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
207 {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
208 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
211 enum mt9m111_mode_id {
212 MT9M111_MODE_SXGA_8FPS,
213 MT9M111_MODE_SXGA_15FPS,
214 MT9M111_MODE_QSXGA_30FPS,
218 struct mt9m111_mode_info {
219 unsigned int sensor_w;
220 unsigned int sensor_h;
221 unsigned int max_image_w;
222 unsigned int max_image_h;
223 unsigned int max_fps;
224 unsigned int reg_val;
225 unsigned int reg_mask;
229 struct v4l2_subdev subdev;
230 struct v4l2_ctrl_handler hdl;
231 struct v4l2_ctrl *gain;
232 struct mt9m111_context *ctx;
233 struct v4l2_rect rect; /* cropping rectangle */
235 unsigned int width; /* output */
236 unsigned int height; /* sizes */
237 struct v4l2_fract frame_interval;
238 const struct mt9m111_mode_info *current_mode;
239 struct mutex power_lock; /* lock to protect power_count */
241 const struct mt9m111_datafmt *fmt;
242 int lastpage; /* PageMap cache value */
243 struct regulator *regulator;
245 /* user point of view - 0: falling 1: rising edge */
246 unsigned int pclk_sample:1;
247 struct media_pad pad;
250 static const struct mt9m111_mode_info mt9m111_mode_data[MT9M111_NUM_MODES] = {
251 [MT9M111_MODE_SXGA_8FPS] = {
257 .reg_val = MT9M111_RM_LOW_POWER_RD,
258 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
260 [MT9M111_MODE_SXGA_15FPS] = {
266 .reg_val = MT9M111_RM_FULL_POWER_RD,
267 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
269 [MT9M111_MODE_QSXGA_30FPS] = {
275 .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X |
276 MT9M111_RM_ROW_SKIP_2X,
277 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
281 /* Find a data format by a pixel code */
282 static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111,
286 for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++)
287 if (mt9m111_colour_fmts[i].code == code)
288 return mt9m111_colour_fmts + i;
293 static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
295 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
298 static int reg_page_map_set(struct i2c_client *client, const u16 reg)
302 struct mt9m111 *mt9m111 = to_mt9m111(client);
305 if (page == mt9m111->lastpage)
310 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
312 mt9m111->lastpage = page;
316 static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
320 ret = reg_page_map_set(client, reg);
322 ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
324 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
328 static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
333 ret = reg_page_map_set(client, reg);
335 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
336 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
340 static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
345 ret = mt9m111_reg_read(client, reg);
347 ret = mt9m111_reg_write(client, reg, ret | data);
351 static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
356 ret = mt9m111_reg_read(client, reg);
358 ret = mt9m111_reg_write(client, reg, ret & ~data);
362 static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
363 const u16 data, const u16 mask)
367 ret = mt9m111_reg_read(client, reg);
369 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
373 static int mt9m111_set_context(struct mt9m111 *mt9m111,
374 struct mt9m111_context *ctx)
376 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
377 return reg_write(CONTEXT_CONTROL, ctx->control);
380 static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
381 struct mt9m111_context *ctx, struct v4l2_rect *rect,
382 unsigned int width, unsigned int height)
384 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
385 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width);
387 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height);
389 ret = mt9m111_reg_write(client, ctx->reducer_xsize, width);
391 ret = mt9m111_reg_write(client, ctx->reducer_ysize, height);
395 static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect,
396 int width, int height, u32 code)
398 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
401 ret = reg_write(COLUMN_START, rect->left);
403 ret = reg_write(ROW_START, rect->top);
406 ret = reg_write(WINDOW_WIDTH, rect->width);
408 ret = reg_write(WINDOW_HEIGHT, rect->height);
410 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
411 /* IFP in use, down-scaling possible */
413 ret = mt9m111_setup_rect_ctx(mt9m111, &context_b,
414 rect, width, height);
416 ret = mt9m111_setup_rect_ctx(mt9m111, &context_a,
417 rect, width, height);
420 dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n",
421 __func__, code, rect->width, rect->height, rect->left, rect->top,
427 static int mt9m111_enable(struct mt9m111 *mt9m111)
429 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
430 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
433 static int mt9m111_reset(struct mt9m111 *mt9m111)
435 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
438 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
440 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
442 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
443 | MT9M111_RESET_RESET_SOC);
448 static int mt9m111_set_selection(struct v4l2_subdev *sd,
449 struct v4l2_subdev_state *sd_state,
450 struct v4l2_subdev_selection *sel)
452 struct i2c_client *client = v4l2_get_subdevdata(sd);
453 struct mt9m111 *mt9m111 = to_mt9m111(client);
454 struct v4l2_rect rect = sel->r;
458 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
459 sel->target != V4L2_SEL_TGT_CROP)
462 if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
463 mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
464 /* Bayer format - even size lengths */
466 /* Let the user play with the starting pixel */
469 /* FIXME: the datasheet doesn't specify minimum sizes */
470 v4l_bound_align_image(&rect.width, 2, MT9M111_MAX_WIDTH, align,
471 &rect.height, 2, MT9M111_MAX_HEIGHT, align, 0);
472 rect.left = clamp(rect.left, MT9M111_MIN_DARK_COLS,
473 MT9M111_MIN_DARK_COLS + MT9M111_MAX_WIDTH -
475 rect.top = clamp(rect.top, MT9M111_MIN_DARK_ROWS,
476 MT9M111_MIN_DARK_ROWS + MT9M111_MAX_HEIGHT -
479 width = min(mt9m111->width, rect.width);
480 height = min(mt9m111->height, rect.height);
482 ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code);
484 mt9m111->rect = rect;
485 mt9m111->width = width;
486 mt9m111->height = height;
492 static int mt9m111_get_selection(struct v4l2_subdev *sd,
493 struct v4l2_subdev_state *sd_state,
494 struct v4l2_subdev_selection *sel)
496 struct i2c_client *client = v4l2_get_subdevdata(sd);
497 struct mt9m111 *mt9m111 = to_mt9m111(client);
499 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
502 switch (sel->target) {
503 case V4L2_SEL_TGT_CROP_BOUNDS:
504 sel->r.left = MT9M111_MIN_DARK_COLS;
505 sel->r.top = MT9M111_MIN_DARK_ROWS;
506 sel->r.width = MT9M111_MAX_WIDTH;
507 sel->r.height = MT9M111_MAX_HEIGHT;
509 case V4L2_SEL_TGT_CROP:
510 sel->r = mt9m111->rect;
517 static int mt9m111_get_fmt(struct v4l2_subdev *sd,
518 struct v4l2_subdev_state *sd_state,
519 struct v4l2_subdev_format *format)
521 struct v4l2_mbus_framefmt *mf = &format->format;
522 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
527 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
528 mf = v4l2_subdev_state_get_format(sd_state, format->pad);
529 format->format = *mf;
533 mf->width = mt9m111->width;
534 mf->height = mt9m111->height;
535 mf->code = mt9m111->fmt->code;
536 mf->colorspace = mt9m111->fmt->colorspace;
537 mf->field = V4L2_FIELD_NONE;
538 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
539 mf->quantization = V4L2_QUANTIZATION_DEFAULT;
540 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
545 static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
548 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
549 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
550 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
551 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
552 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
553 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
554 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
558 case MEDIA_BUS_FMT_SBGGR8_1X8:
559 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
562 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
563 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
565 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
566 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
567 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
569 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
570 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
572 case MEDIA_BUS_FMT_RGB565_2X8_LE:
573 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
574 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
576 case MEDIA_BUS_FMT_RGB565_2X8_BE:
577 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
579 case MEDIA_BUS_FMT_BGR565_2X8_BE:
580 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
581 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
583 case MEDIA_BUS_FMT_BGR565_2X8_LE:
584 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
585 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
586 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
588 case MEDIA_BUS_FMT_UYVY8_2X8:
591 case MEDIA_BUS_FMT_VYUY8_2X8:
592 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
594 case MEDIA_BUS_FMT_YUYV8_2X8:
595 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
597 case MEDIA_BUS_FMT_YVYU8_2X8:
598 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
599 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
602 dev_err(&client->dev, "Pixel format not handled: %x\n", code);
606 /* receiver samples on falling edge, chip-hw default is rising */
607 if (mt9m111->pclk_sample == 0)
608 mask_outfmt2 |= MT9M111_OUTFMT_INV_PIX_CLOCK;
610 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
611 data_outfmt2, mask_outfmt2);
613 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
614 data_outfmt2, mask_outfmt2);
619 static int mt9m111_set_fmt(struct v4l2_subdev *sd,
620 struct v4l2_subdev_state *sd_state,
621 struct v4l2_subdev_format *format)
623 struct v4l2_mbus_framefmt *mf = &format->format;
624 struct i2c_client *client = v4l2_get_subdevdata(sd);
625 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
626 const struct mt9m111_datafmt *fmt;
627 struct v4l2_rect *rect = &mt9m111->rect;
631 if (mt9m111->is_streaming)
637 fmt = mt9m111_find_datafmt(mt9m111, mf->code);
639 bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
640 fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE;
643 * With Bayer format enforce even side lengths, but let the user play
644 * with the starting pixel
647 rect->width = ALIGN(rect->width, 2);
648 rect->height = ALIGN(rect->height, 2);
651 if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
652 /* IFP bypass mode, no scaling */
653 mf->width = rect->width;
654 mf->height = rect->height;
657 if (mf->width > rect->width)
658 mf->width = rect->width;
659 if (mf->height > rect->height)
660 mf->height = rect->height;
663 dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__,
664 mf->width, mf->height, fmt->code);
666 mf->code = fmt->code;
667 mf->colorspace = fmt->colorspace;
668 mf->field = V4L2_FIELD_NONE;
669 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
670 mf->quantization = V4L2_QUANTIZATION_DEFAULT;
671 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
673 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
674 *v4l2_subdev_state_get_format(sd_state, 0) = *mf;
678 ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code);
680 ret = mt9m111_set_pixfmt(mt9m111, mf->code);
682 mt9m111->width = mf->width;
683 mt9m111->height = mf->height;
690 static const struct mt9m111_mode_info *
691 mt9m111_find_mode(struct mt9m111 *mt9m111, unsigned int req_fps,
692 unsigned int width, unsigned int height)
694 const struct mt9m111_mode_info *mode;
695 struct v4l2_rect *sensor_rect = &mt9m111->rect;
696 unsigned int gap, gap_best = (unsigned int) -1;
697 int i, best_gap_idx = MT9M111_MODE_SXGA_15FPS;
698 bool skip_30fps = false;
701 * The fps selection is based on the row, column skipping mechanism.
702 * So ensure that the sensor window is set to default else the fps
703 * aren't calculated correctly within the sensor hw.
705 if (sensor_rect->width != MT9M111_MAX_WIDTH ||
706 sensor_rect->height != MT9M111_MAX_HEIGHT) {
707 dev_info(mt9m111->subdev.dev,
708 "Framerate selection is not supported for cropped "
713 /* 30fps only supported for images not exceeding 640x512 */
714 if (width > MT9M111_MAX_WIDTH / 2 || height > MT9M111_MAX_HEIGHT / 2) {
715 dev_dbg(mt9m111->subdev.dev,
716 "Framerates > 15fps are supported only for images "
717 "not exceeding 640x512\n");
721 /* find best matched fps */
722 for (i = 0; i < MT9M111_NUM_MODES; i++) {
723 unsigned int fps = mt9m111_mode_data[i].max_fps;
725 if (fps == 30 && skip_30fps)
728 gap = abs(fps - req_fps);
729 if (gap < gap_best) {
736 * Use context a/b default timing values instead of calculate blanking
739 mode = &mt9m111_mode_data[best_gap_idx];
740 mt9m111->ctx = (best_gap_idx == MT9M111_MODE_QSXGA_30FPS) ? &context_a :
745 #ifdef CONFIG_VIDEO_ADV_DEBUG
746 static int mt9m111_g_register(struct v4l2_subdev *sd,
747 struct v4l2_dbg_register *reg)
749 struct i2c_client *client = v4l2_get_subdevdata(sd);
752 if (reg->reg > 0x2ff)
755 val = mt9m111_reg_read(client, reg->reg);
759 if (reg->val > 0xffff)
765 static int mt9m111_s_register(struct v4l2_subdev *sd,
766 const struct v4l2_dbg_register *reg)
768 struct i2c_client *client = v4l2_get_subdevdata(sd);
770 if (reg->reg > 0x2ff)
773 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
780 static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
782 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
786 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
788 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
793 static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
795 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
798 data = reg_read(GLOBAL_GAIN);
800 return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
801 (1 << ((data >> 9) & 1));
805 static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
807 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
810 if (gain > 63 * 2 * 2)
813 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
814 val = (1 << 10) | (1 << 9) | (gain / 4);
815 else if ((gain >= 64) && (gain < 64 * 2))
816 val = (1 << 9) | (gain / 2);
820 return reg_write(GLOBAL_GAIN, val);
823 static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val)
825 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
827 if (val == V4L2_EXPOSURE_AUTO)
828 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
829 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
832 static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
834 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
837 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
838 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
841 static const char * const mt9m111_test_pattern_menu[] = {
843 "Vertical monochrome gradient",
852 static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val)
854 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
856 return mt9m111_reg_mask(client, MT9M111_TPG_CTRL, val,
857 MT9M111_TPG_SEL_MASK);
860 static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val)
862 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
863 static const struct v4l2_control colorfx[] = {
864 { V4L2_COLORFX_NONE, 0 },
865 { V4L2_COLORFX_BW, 1 },
866 { V4L2_COLORFX_SEPIA, 2 },
867 { V4L2_COLORFX_NEGATIVE, 3 },
868 { V4L2_COLORFX_SOLARIZATION, 4 },
872 for (i = 0; i < ARRAY_SIZE(colorfx); i++) {
873 if (colorfx[i].id == val) {
874 return mt9m111_reg_mask(client, MT9M111_EFFECTS_MODE,
876 MT9M111_EFFECTS_MODE_MASK);
883 static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
885 struct mt9m111 *mt9m111 = container_of(ctrl->handler,
886 struct mt9m111, hdl);
890 return mt9m111_set_flip(mt9m111, ctrl->val,
891 MT9M111_RMB_MIRROR_ROWS);
893 return mt9m111_set_flip(mt9m111, ctrl->val,
894 MT9M111_RMB_MIRROR_COLS);
896 return mt9m111_set_global_gain(mt9m111, ctrl->val);
897 case V4L2_CID_EXPOSURE_AUTO:
898 return mt9m111_set_autoexposure(mt9m111, ctrl->val);
899 case V4L2_CID_AUTO_WHITE_BALANCE:
900 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
901 case V4L2_CID_TEST_PATTERN:
902 return mt9m111_set_test_pattern(mt9m111, ctrl->val);
903 case V4L2_CID_COLORFX:
904 return mt9m111_set_colorfx(mt9m111, ctrl->val);
910 static int mt9m111_suspend(struct mt9m111 *mt9m111)
912 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
915 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
917 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
919 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
920 MT9M111_RESET_OUTPUT_DISABLE |
921 MT9M111_RESET_ANALOG_STANDBY);
923 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
928 static void mt9m111_restore_state(struct mt9m111 *mt9m111)
930 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
932 mt9m111_set_context(mt9m111, mt9m111->ctx);
933 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
934 mt9m111_setup_geometry(mt9m111, &mt9m111->rect,
935 mt9m111->width, mt9m111->height, mt9m111->fmt->code);
936 v4l2_ctrl_handler_setup(&mt9m111->hdl);
937 mt9m111_reg_mask(client, mt9m111->ctx->read_mode,
938 mt9m111->current_mode->reg_val,
939 mt9m111->current_mode->reg_mask);
942 static int mt9m111_resume(struct mt9m111 *mt9m111)
944 int ret = mt9m111_enable(mt9m111);
946 ret = mt9m111_reset(mt9m111);
948 mt9m111_restore_state(mt9m111);
953 static int mt9m111_init(struct mt9m111 *mt9m111)
955 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
958 ret = mt9m111_enable(mt9m111);
960 ret = mt9m111_reset(mt9m111);
962 ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
964 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
968 static int mt9m111_power_on(struct mt9m111 *mt9m111)
970 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
973 ret = clk_prepare_enable(mt9m111->clk);
977 ret = regulator_enable(mt9m111->regulator);
979 goto out_clk_disable;
981 ret = mt9m111_resume(mt9m111);
983 goto out_regulator_disable;
987 out_regulator_disable:
988 regulator_disable(mt9m111->regulator);
991 clk_disable_unprepare(mt9m111->clk);
993 dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret);
998 static void mt9m111_power_off(struct mt9m111 *mt9m111)
1000 mt9m111_suspend(mt9m111);
1001 regulator_disable(mt9m111->regulator);
1002 clk_disable_unprepare(mt9m111->clk);
1005 static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
1007 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
1010 mutex_lock(&mt9m111->power_lock);
1013 * If the power count is modified from 0 to != 0 or from != 0 to 0,
1014 * update the power state.
1016 if (mt9m111->power_count == !on) {
1018 ret = mt9m111_power_on(mt9m111);
1020 mt9m111_power_off(mt9m111);
1024 /* Update the power count. */
1025 mt9m111->power_count += on ? 1 : -1;
1026 WARN_ON(mt9m111->power_count < 0);
1029 mutex_unlock(&mt9m111->power_lock);
1033 static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
1034 .s_ctrl = mt9m111_s_ctrl,
1037 static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
1038 .s_power = mt9m111_s_power,
1039 .log_status = v4l2_ctrl_subdev_log_status,
1040 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1041 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1042 #ifdef CONFIG_VIDEO_ADV_DEBUG
1043 .g_register = mt9m111_g_register,
1044 .s_register = mt9m111_s_register,
1048 static int mt9m111_get_frame_interval(struct v4l2_subdev *sd,
1049 struct v4l2_subdev_state *sd_state,
1050 struct v4l2_subdev_frame_interval *fi)
1052 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
1055 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1056 * subdev active state API.
1058 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1061 fi->interval = mt9m111->frame_interval;
1066 static int mt9m111_set_frame_interval(struct v4l2_subdev *sd,
1067 struct v4l2_subdev_state *sd_state,
1068 struct v4l2_subdev_frame_interval *fi)
1070 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
1071 const struct mt9m111_mode_info *mode;
1072 struct v4l2_fract *fract = &fi->interval;
1075 if (mt9m111->is_streaming)
1079 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1080 * subdev active state API.
1082 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1088 if (fract->numerator == 0) {
1089 fract->denominator = 30;
1090 fract->numerator = 1;
1093 fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator);
1095 /* Find best fitting mode. Do not update the mode if no one was found. */
1096 mode = mt9m111_find_mode(mt9m111, fps, mt9m111->width, mt9m111->height);
1100 if (mode->max_fps != fps) {
1101 fract->denominator = mode->max_fps;
1102 fract->numerator = 1;
1105 mt9m111->current_mode = mode;
1106 mt9m111->frame_interval = fi->interval;
1111 static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd,
1112 struct v4l2_subdev_state *sd_state,
1113 struct v4l2_subdev_mbus_code_enum *code)
1115 if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts))
1118 code->code = mt9m111_colour_fmts[code->index].code;
1122 static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable)
1124 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
1126 mt9m111->is_streaming = !!enable;
1130 static int mt9m111_init_state(struct v4l2_subdev *sd,
1131 struct v4l2_subdev_state *sd_state)
1133 struct v4l2_mbus_framefmt *format =
1134 v4l2_subdev_state_get_format(sd_state, 0);
1136 format->width = MT9M111_MAX_WIDTH;
1137 format->height = MT9M111_MAX_HEIGHT;
1138 format->code = mt9m111_colour_fmts[0].code;
1139 format->colorspace = mt9m111_colour_fmts[0].colorspace;
1140 format->field = V4L2_FIELD_NONE;
1141 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1142 format->quantization = V4L2_QUANTIZATION_DEFAULT;
1143 format->xfer_func = V4L2_XFER_FUNC_DEFAULT;
1148 static int mt9m111_get_mbus_config(struct v4l2_subdev *sd,
1150 struct v4l2_mbus_config *cfg)
1152 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
1154 cfg->type = V4L2_MBUS_PARALLEL;
1156 cfg->bus.parallel.flags = V4L2_MBUS_MASTER |
1157 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1158 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1159 V4L2_MBUS_DATA_ACTIVE_HIGH;
1161 cfg->bus.parallel.flags |= mt9m111->pclk_sample ?
1162 V4L2_MBUS_PCLK_SAMPLE_RISING :
1163 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1168 static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
1169 .s_stream = mt9m111_s_stream,
1172 static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = {
1173 .enum_mbus_code = mt9m111_enum_mbus_code,
1174 .get_selection = mt9m111_get_selection,
1175 .set_selection = mt9m111_set_selection,
1176 .get_fmt = mt9m111_get_fmt,
1177 .set_fmt = mt9m111_set_fmt,
1178 .get_frame_interval = mt9m111_get_frame_interval,
1179 .set_frame_interval = mt9m111_set_frame_interval,
1180 .get_mbus_config = mt9m111_get_mbus_config,
1183 static const struct v4l2_subdev_ops mt9m111_subdev_ops = {
1184 .core = &mt9m111_subdev_core_ops,
1185 .video = &mt9m111_subdev_video_ops,
1186 .pad = &mt9m111_subdev_pad_ops,
1189 static const struct v4l2_subdev_internal_ops mt9m111_internal_ops = {
1190 .init_state = mt9m111_init_state,
1194 * Interface active, can use i2c. If it fails, it can indeed mean, that
1195 * this wasn't our capture interface, so, we wait for the right one
1197 static int mt9m111_video_probe(struct i2c_client *client)
1199 struct mt9m111 *mt9m111 = to_mt9m111(client);
1203 ret = mt9m111_s_power(&mt9m111->subdev, 1);
1207 data = reg_read(CHIP_VERSION);
1210 case 0x143a: /* MT9M111 or MT9M131 */
1211 dev_info(&client->dev,
1212 "Detected a MT9M111/MT9M131 chip ID %x\n", data);
1214 case 0x148c: /* MT9M112 */
1215 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
1218 dev_err(&client->dev,
1219 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
1225 ret = mt9m111_init(mt9m111);
1229 ret = v4l2_ctrl_handler_setup(&mt9m111->hdl);
1232 mt9m111_s_power(&mt9m111->subdev, 0);
1236 static int mt9m111_probe_fw(struct i2c_client *client, struct mt9m111 *mt9m111)
1238 struct v4l2_fwnode_endpoint bus_cfg = {
1239 .bus_type = V4L2_MBUS_PARALLEL
1241 struct fwnode_handle *np;
1244 np = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
1248 ret = v4l2_fwnode_endpoint_parse(np, &bus_cfg);
1252 mt9m111->pclk_sample = !!(bus_cfg.bus.parallel.flags &
1253 V4L2_MBUS_PCLK_SAMPLE_RISING);
1256 fwnode_handle_put(np);
1260 static int mt9m111_probe(struct i2c_client *client)
1262 struct mt9m111 *mt9m111;
1263 struct i2c_adapter *adapter = client->adapter;
1266 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
1267 dev_warn(&adapter->dev,
1268 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
1272 mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL);
1276 if (dev_fwnode(&client->dev)) {
1277 ret = mt9m111_probe_fw(client, mt9m111);
1282 mt9m111->clk = devm_clk_get(&client->dev, "mclk");
1283 if (IS_ERR(mt9m111->clk))
1284 return PTR_ERR(mt9m111->clk);
1286 mt9m111->regulator = devm_regulator_get(&client->dev, "vdd");
1287 if (IS_ERR(mt9m111->regulator)) {
1288 dev_err(&client->dev, "regulator not found: %ld\n",
1289 PTR_ERR(mt9m111->regulator));
1290 return PTR_ERR(mt9m111->regulator);
1293 /* Default HIGHPOWER context */
1294 mt9m111->ctx = &context_b;
1296 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
1297 mt9m111->subdev.internal_ops = &mt9m111_internal_ops;
1298 mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1299 V4L2_SUBDEV_FL_HAS_EVENTS;
1301 v4l2_ctrl_handler_init(&mt9m111->hdl, 7);
1302 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
1303 V4L2_CID_VFLIP, 0, 1, 1, 0);
1304 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
1305 V4L2_CID_HFLIP, 0, 1, 1, 0);
1306 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
1307 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1308 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
1309 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
1310 v4l2_ctrl_new_std_menu(&mt9m111->hdl,
1311 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
1312 V4L2_EXPOSURE_AUTO);
1313 v4l2_ctrl_new_std_menu_items(&mt9m111->hdl,
1314 &mt9m111_ctrl_ops, V4L2_CID_TEST_PATTERN,
1315 ARRAY_SIZE(mt9m111_test_pattern_menu) - 1, 0, 0,
1316 mt9m111_test_pattern_menu);
1317 v4l2_ctrl_new_std_menu(&mt9m111->hdl, &mt9m111_ctrl_ops,
1318 V4L2_CID_COLORFX, V4L2_COLORFX_SOLARIZATION,
1319 ~(BIT(V4L2_COLORFX_NONE) |
1320 BIT(V4L2_COLORFX_BW) |
1321 BIT(V4L2_COLORFX_SEPIA) |
1322 BIT(V4L2_COLORFX_NEGATIVE) |
1323 BIT(V4L2_COLORFX_SOLARIZATION)),
1325 mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
1326 if (mt9m111->hdl.error) {
1327 ret = mt9m111->hdl.error;
1331 mt9m111->pad.flags = MEDIA_PAD_FL_SOURCE;
1332 mt9m111->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1333 ret = media_entity_pads_init(&mt9m111->subdev.entity, 1, &mt9m111->pad);
1337 mt9m111->current_mode = &mt9m111_mode_data[MT9M111_MODE_SXGA_15FPS];
1338 mt9m111->frame_interval.numerator = 1;
1339 mt9m111->frame_interval.denominator = mt9m111->current_mode->max_fps;
1341 /* Second stage probe - when a capture adapter is there */
1342 mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
1343 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
1344 mt9m111->rect.width = MT9M111_MAX_WIDTH;
1345 mt9m111->rect.height = MT9M111_MAX_HEIGHT;
1346 mt9m111->width = mt9m111->rect.width;
1347 mt9m111->height = mt9m111->rect.height;
1348 mt9m111->fmt = &mt9m111_colour_fmts[0];
1349 mt9m111->lastpage = -1;
1350 mutex_init(&mt9m111->power_lock);
1352 ret = mt9m111_video_probe(client);
1354 goto out_entityclean;
1356 mt9m111->subdev.dev = &client->dev;
1357 ret = v4l2_async_register_subdev(&mt9m111->subdev);
1359 goto out_entityclean;
1364 media_entity_cleanup(&mt9m111->subdev.entity);
1366 v4l2_ctrl_handler_free(&mt9m111->hdl);
1371 static void mt9m111_remove(struct i2c_client *client)
1373 struct mt9m111 *mt9m111 = to_mt9m111(client);
1375 v4l2_async_unregister_subdev(&mt9m111->subdev);
1376 media_entity_cleanup(&mt9m111->subdev.entity);
1377 v4l2_ctrl_handler_free(&mt9m111->hdl);
1379 static const struct of_device_id mt9m111_of_match[] = {
1380 { .compatible = "micron,mt9m111", },
1383 MODULE_DEVICE_TABLE(of, mt9m111_of_match);
1385 static const struct i2c_device_id mt9m111_id[] = {
1389 MODULE_DEVICE_TABLE(i2c, mt9m111_id);
1391 static struct i2c_driver mt9m111_i2c_driver = {
1394 .of_match_table = mt9m111_of_match,
1396 .probe = mt9m111_probe,
1397 .remove = mt9m111_remove,
1398 .id_table = mt9m111_id,
1401 module_i2c_driver(mt9m111_i2c_driver);
1403 MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
1404 MODULE_AUTHOR("Robert Jarzmik");
1405 MODULE_LICENSE("GPL");