0af9b335be120751519e11bca8aa098d82ef428c
[linux-2.6-microblaze.git] / drivers / media / dvb-frontends / ts2020.c
1 /*
2     Montage Technology TS2020 - Silicon Tuner driver
3     Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
4
5     Copyright (C) 2009-2012 TurboSight.com
6
7     This program is free software; you can redistribute it and/or modify
8     it under the terms of the GNU General Public License as published by
9     the Free Software Foundation; either version 2 of the License, or
10     (at your option) any later version.
11
12     This program is distributed in the hope that it will be useful,
13     but WITHOUT ANY WARRANTY; without even the implied warranty of
14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15     GNU General Public License for more details.
16
17     You should have received a copy of the GNU General Public License
18     along with this program; if not, write to the Free Software
19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21
22 #include <media/dvb_frontend.h>
23 #include "ts2020.h"
24 #include <linux/regmap.h>
25 #include <linux/math64.h>
26
27 #define TS2020_XTAL_FREQ   27000 /* in kHz */
28 #define FREQ_OFFSET_LOW_SYM_RATE 3000
29
30 struct ts2020_priv {
31         struct i2c_client *client;
32         struct mutex regmap_mutex;
33         struct regmap_config regmap_config;
34         struct regmap *regmap;
35         struct dvb_frontend *fe;
36         struct delayed_work stat_work;
37         int (*get_agc_pwm)(struct dvb_frontend *fe, u8 *_agc_pwm);
38         /* i2c details */
39         struct i2c_adapter *i2c;
40         int i2c_address;
41         bool loop_through:1;
42         u8 clk_out:2;
43         u8 clk_out_div:5;
44         bool dont_poll:1;
45         u32 frequency_div; /* LO output divider switch frequency */
46         u32 frequency_khz; /* actual used LO frequency */
47 #define TS2020_M88TS2020 0
48 #define TS2020_M88TS2022 1
49         u8 tuner;
50 };
51
52 struct ts2020_reg_val {
53         u8 reg;
54         u8 val;
55 };
56
57 static void ts2020_stat_work(struct work_struct *work);
58
59 static void ts2020_release(struct dvb_frontend *fe)
60 {
61         struct ts2020_priv *priv = fe->tuner_priv;
62         struct i2c_client *client = priv->client;
63
64         dev_dbg(&client->dev, "\n");
65
66         i2c_unregister_device(client);
67 }
68
69 static int ts2020_sleep(struct dvb_frontend *fe)
70 {
71         struct ts2020_priv *priv = fe->tuner_priv;
72         int ret;
73         u8 u8tmp;
74
75         if (priv->tuner == TS2020_M88TS2020)
76                 u8tmp = 0x0a; /* XXX: probably wrong */
77         else
78                 u8tmp = 0x00;
79
80         ret = regmap_write(priv->regmap, u8tmp, 0x00);
81         if (ret < 0)
82                 return ret;
83
84         /* stop statistics polling */
85         if (!priv->dont_poll)
86                 cancel_delayed_work_sync(&priv->stat_work);
87         return 0;
88 }
89
90 static int ts2020_init(struct dvb_frontend *fe)
91 {
92         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
93         struct ts2020_priv *priv = fe->tuner_priv;
94         int i;
95         u8 u8tmp;
96
97         if (priv->tuner == TS2020_M88TS2020) {
98                 regmap_write(priv->regmap, 0x42, 0x73);
99                 regmap_write(priv->regmap, 0x05, priv->clk_out_div);
100                 regmap_write(priv->regmap, 0x20, 0x27);
101                 regmap_write(priv->regmap, 0x07, 0x02);
102                 regmap_write(priv->regmap, 0x11, 0xff);
103                 regmap_write(priv->regmap, 0x60, 0xf9);
104                 regmap_write(priv->regmap, 0x08, 0x01);
105                 regmap_write(priv->regmap, 0x00, 0x41);
106         } else {
107                 static const struct ts2020_reg_val reg_vals[] = {
108                         {0x7d, 0x9d},
109                         {0x7c, 0x9a},
110                         {0x7a, 0x76},
111                         {0x3b, 0x01},
112                         {0x63, 0x88},
113                         {0x61, 0x85},
114                         {0x22, 0x30},
115                         {0x30, 0x40},
116                         {0x20, 0x23},
117                         {0x24, 0x02},
118                         {0x12, 0xa0},
119                 };
120
121                 regmap_write(priv->regmap, 0x00, 0x01);
122                 regmap_write(priv->regmap, 0x00, 0x03);
123
124                 switch (priv->clk_out) {
125                 case TS2020_CLK_OUT_DISABLED:
126                         u8tmp = 0x60;
127                         break;
128                 case TS2020_CLK_OUT_ENABLED:
129                         u8tmp = 0x70;
130                         regmap_write(priv->regmap, 0x05, priv->clk_out_div);
131                         break;
132                 case TS2020_CLK_OUT_ENABLED_XTALOUT:
133                         u8tmp = 0x6c;
134                         break;
135                 default:
136                         u8tmp = 0x60;
137                         break;
138                 }
139
140                 regmap_write(priv->regmap, 0x42, u8tmp);
141
142                 if (priv->loop_through)
143                         u8tmp = 0xec;
144                 else
145                         u8tmp = 0x6c;
146
147                 regmap_write(priv->regmap, 0x62, u8tmp);
148
149                 for (i = 0; i < ARRAY_SIZE(reg_vals); i++)
150                         regmap_write(priv->regmap, reg_vals[i].reg,
151                                      reg_vals[i].val);
152         }
153
154         /* Initialise v5 stats here */
155         c->strength.len = 1;
156         c->strength.stat[0].scale = FE_SCALE_DECIBEL;
157         c->strength.stat[0].uvalue = 0;
158
159         /* Start statistics polling by invoking the work function */
160         ts2020_stat_work(&priv->stat_work.work);
161         return 0;
162 }
163
164 static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
165 {
166         struct ts2020_priv *priv = fe->tuner_priv;
167         int ret;
168         ret = regmap_write(priv->regmap, 0x51, 0x1f - offset);
169         ret |= regmap_write(priv->regmap, 0x51, 0x1f);
170         ret |= regmap_write(priv->regmap, 0x50, offset);
171         ret |= regmap_write(priv->regmap, 0x50, 0x00);
172         msleep(20);
173         return ret;
174 }
175
176 static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
177 {
178         struct ts2020_priv *dev = fe->tuner_priv;
179         int ret;
180         unsigned int utmp;
181
182         ret = regmap_read(dev->regmap, 0x3d, &utmp);
183         if (ret)
184                 return ret;
185
186         utmp &= 0x7f;
187         if (utmp < 0x16)
188                 utmp = 0xa1;
189         else if (utmp == 0x16)
190                 utmp = 0x99;
191         else
192                 utmp = 0xf9;
193
194         regmap_write(dev->regmap, 0x60, utmp);
195         ret = ts2020_tuner_gate_ctrl(fe, 0x08);
196
197         return ret;
198 }
199
200 static int ts2020_set_params(struct dvb_frontend *fe)
201 {
202         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
203         struct ts2020_priv *priv = fe->tuner_priv;
204         int ret;
205         unsigned int utmp;
206         u32 f3db, gdiv28;
207         u16 u16tmp, value, lpf_coeff;
208         u8 buf[3], reg10, lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
209         unsigned int f_ref_khz, f_vco_khz, div_ref, div_out, pll_n;
210         unsigned int frequency_khz = c->frequency;
211
212         /*
213          * Integer-N PLL synthesizer
214          * kHz is used for all calculations to keep calculations within 32-bit
215          */
216         f_ref_khz = TS2020_XTAL_FREQ;
217         div_ref = DIV_ROUND_CLOSEST(f_ref_khz, 2000);
218
219         /* select LO output divider */
220         if (frequency_khz < priv->frequency_div) {
221                 div_out = 4;
222                 reg10 = 0x10;
223         } else {
224                 div_out = 2;
225                 reg10 = 0x00;
226         }
227
228         f_vco_khz = frequency_khz * div_out;
229         pll_n = f_vco_khz * div_ref / f_ref_khz;
230         pll_n += pll_n % 2;
231         priv->frequency_khz = pll_n * f_ref_khz / div_ref / div_out;
232
233         pr_debug("frequency=%u offset=%d f_vco_khz=%u pll_n=%u div_ref=%u div_out=%u\n",
234                  priv->frequency_khz, priv->frequency_khz - c->frequency,
235                  f_vco_khz, pll_n, div_ref, div_out);
236
237         if (priv->tuner == TS2020_M88TS2020) {
238                 lpf_coeff = 2766;
239                 reg10 |= 0x01;
240                 ret = regmap_write(priv->regmap, 0x10, reg10);
241         } else {
242                 lpf_coeff = 3200;
243                 reg10 |= 0x0b;
244                 ret = regmap_write(priv->regmap, 0x10, reg10);
245                 ret |= regmap_write(priv->regmap, 0x11, 0x40);
246         }
247
248         u16tmp = pll_n - 1024;
249         buf[0] = (u16tmp >> 8) & 0xff;
250         buf[1] = (u16tmp >> 0) & 0xff;
251         buf[2] = div_ref - 8;
252
253         ret |= regmap_write(priv->regmap, 0x01, buf[0]);
254         ret |= regmap_write(priv->regmap, 0x02, buf[1]);
255         ret |= regmap_write(priv->regmap, 0x03, buf[2]);
256
257         ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
258         if (ret < 0)
259                 return -ENODEV;
260
261         ret |= ts2020_tuner_gate_ctrl(fe, 0x08);
262
263         /* Tuner RF */
264         if (priv->tuner == TS2020_M88TS2020)
265                 ret |= ts2020_set_tuner_rf(fe);
266
267         gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
268         ret |= regmap_write(priv->regmap, 0x04, gdiv28 & 0xff);
269         ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
270         if (ret < 0)
271                 return -ENODEV;
272
273         if (priv->tuner == TS2020_M88TS2022) {
274                 ret = regmap_write(priv->regmap, 0x25, 0x00);
275                 ret |= regmap_write(priv->regmap, 0x27, 0x70);
276                 ret |= regmap_write(priv->regmap, 0x41, 0x09);
277                 ret |= regmap_write(priv->regmap, 0x08, 0x0b);
278                 if (ret < 0)
279                         return -ENODEV;
280         }
281
282         regmap_read(priv->regmap, 0x26, &utmp);
283         value = utmp;
284
285         f3db = (c->bandwidth_hz / 1000 / 2) + 2000;
286         f3db += FREQ_OFFSET_LOW_SYM_RATE; /* FIXME: ~always too wide filter */
287         f3db = clamp(f3db, 7000U, 40000U);
288
289         gdiv28 = gdiv28 * 207 / (value * 2 + 151);
290         mlpf_max = gdiv28 * 135 / 100;
291         mlpf_min = gdiv28 * 78 / 100;
292         if (mlpf_max > 63)
293                 mlpf_max = 63;
294
295         nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
296                 (TS2020_XTAL_FREQ / 1000)  + 1) / 2;
297         if (nlpf > 23)
298                 nlpf = 23;
299         if (nlpf < 1)
300                 nlpf = 1;
301
302         lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
303                 * lpf_coeff * 2  / f3db + 1) / 2;
304
305         if (lpf_mxdiv < mlpf_min) {
306                 nlpf++;
307                 lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
308                         * lpf_coeff * 2  / f3db + 1) / 2;
309         }
310
311         if (lpf_mxdiv > mlpf_max)
312                 lpf_mxdiv = mlpf_max;
313
314         ret = regmap_write(priv->regmap, 0x04, lpf_mxdiv);
315         ret |= regmap_write(priv->regmap, 0x06, nlpf);
316
317         ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
318
319         ret |= ts2020_tuner_gate_ctrl(fe, 0x01);
320
321         msleep(80);
322
323         return (ret < 0) ? -EINVAL : 0;
324 }
325
326 static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
327 {
328         struct ts2020_priv *priv = fe->tuner_priv;
329
330         *frequency = priv->frequency_khz;
331         return 0;
332 }
333
334 static int ts2020_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
335 {
336         *frequency = 0; /* Zero-IF */
337         return 0;
338 }
339
340 /*
341  * Get the tuner gain.
342  * @fe: The front end for which we're determining the gain
343  * @v_agc: The voltage of the AGC from the demodulator (0-2600mV)
344  * @_gain: Where to store the gain (in 0.001dB units)
345  *
346  * Returns 0 or a negative error code.
347  */
348 static int ts2020_read_tuner_gain(struct dvb_frontend *fe, unsigned v_agc,
349                                   __s64 *_gain)
350 {
351         struct ts2020_priv *priv = fe->tuner_priv;
352         unsigned long gain1, gain2, gain3;
353         unsigned utmp;
354         int ret;
355
356         /* Read the RF gain */
357         ret = regmap_read(priv->regmap, 0x3d, &utmp);
358         if (ret < 0)
359                 return ret;
360         gain1 = utmp & 0x1f;
361
362         /* Read the baseband gain */
363         ret = regmap_read(priv->regmap, 0x21, &utmp);
364         if (ret < 0)
365                 return ret;
366         gain2 = utmp & 0x1f;
367
368         switch (priv->tuner) {
369         case TS2020_M88TS2020:
370                 gain1 = clamp_t(long, gain1, 0, 15);
371                 gain2 = clamp_t(long, gain2, 0, 13);
372                 v_agc = clamp_t(long, v_agc, 400, 1100);
373
374                 *_gain = -((__s64)gain1 * 2330 +
375                            gain2 * 3500 +
376                            v_agc * 24 / 10 * 10 +
377                            10000);
378                 /* gain in range -19600 to -116850 in units of 0.001dB */
379                 break;
380
381         case TS2020_M88TS2022:
382                 ret = regmap_read(priv->regmap, 0x66, &utmp);
383                 if (ret < 0)
384                         return ret;
385                 gain3 = (utmp >> 3) & 0x07;
386
387                 gain1 = clamp_t(long, gain1, 0, 15);
388                 gain2 = clamp_t(long, gain2, 2, 16);
389                 gain3 = clamp_t(long, gain3, 0, 6);
390                 v_agc = clamp_t(long, v_agc, 600, 1600);
391
392                 *_gain = -((__s64)gain1 * 2650 +
393                            gain2 * 3380 +
394                            gain3 * 2850 +
395                            v_agc * 176 / 100 * 10 -
396                            30000);
397                 /* gain in range -47320 to -158950 in units of 0.001dB */
398                 break;
399         }
400
401         return 0;
402 }
403
404 /*
405  * Get the AGC information from the demodulator and use that to calculate the
406  * tuner gain.
407  */
408 static int ts2020_get_tuner_gain(struct dvb_frontend *fe, __s64 *_gain)
409 {
410         struct ts2020_priv *priv = fe->tuner_priv;
411         int v_agc = 0, ret;
412         u8 agc_pwm;
413
414         /* Read the AGC PWM rate from the demodulator */
415         if (priv->get_agc_pwm) {
416                 ret = priv->get_agc_pwm(fe, &agc_pwm);
417                 if (ret < 0)
418                         return ret;
419
420                 switch (priv->tuner) {
421                 case TS2020_M88TS2020:
422                         v_agc = (int)agc_pwm * 20 - 1166;
423                         break;
424                 case TS2020_M88TS2022:
425                         v_agc = (int)agc_pwm * 16 - 670;
426                         break;
427                 }
428
429                 if (v_agc < 0)
430                         v_agc = 0;
431         }
432
433         return ts2020_read_tuner_gain(fe, v_agc, _gain);
434 }
435
436 /*
437  * Gather statistics on a regular basis
438  */
439 static void ts2020_stat_work(struct work_struct *work)
440 {
441         struct ts2020_priv *priv = container_of(work, struct ts2020_priv,
442                                                stat_work.work);
443         struct i2c_client *client = priv->client;
444         struct dtv_frontend_properties *c = &priv->fe->dtv_property_cache;
445         int ret;
446
447         dev_dbg(&client->dev, "\n");
448
449         ret = ts2020_get_tuner_gain(priv->fe, &c->strength.stat[0].svalue);
450         if (ret < 0)
451                 goto err;
452
453         c->strength.stat[0].scale = FE_SCALE_DECIBEL;
454
455         if (!priv->dont_poll)
456                 schedule_delayed_work(&priv->stat_work, msecs_to_jiffies(2000));
457         return;
458 err:
459         dev_dbg(&client->dev, "failed=%d\n", ret);
460 }
461
462 /*
463  * Read TS2020 signal strength in v3 format.
464  */
465 static int ts2020_read_signal_strength(struct dvb_frontend *fe,
466                                        u16 *_signal_strength)
467 {
468         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
469         struct ts2020_priv *priv = fe->tuner_priv;
470         unsigned strength;
471         __s64 gain;
472
473         if (priv->dont_poll)
474                 ts2020_stat_work(&priv->stat_work.work);
475
476         if (c->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
477                 *_signal_strength = 0;
478                 return 0;
479         }
480
481         gain = c->strength.stat[0].svalue;
482
483         /* Calculate the signal strength based on the total gain of the tuner */
484         if (gain < -85000)
485                 /* 0%: no signal or weak signal */
486                 strength = 0;
487         else if (gain < -65000)
488                 /* 0% - 60%: weak signal */
489                 strength = 0 + div64_s64((85000 + gain) * 3, 1000);
490         else if (gain < -45000)
491                 /* 60% - 90%: normal signal */
492                 strength = 60 + div64_s64((65000 + gain) * 3, 2000);
493         else
494                 /* 90% - 99%: strong signal */
495                 strength = 90 + div64_s64((45000 + gain), 5000);
496
497         *_signal_strength = strength * 65535 / 100;
498         return 0;
499 }
500
501 static const struct dvb_tuner_ops ts2020_tuner_ops = {
502         .info = {
503                 .name = "TS2020",
504                 .frequency_min_hz =  950 * MHz,
505                 .frequency_max_hz = 2150 * MHz
506         },
507         .init = ts2020_init,
508         .release = ts2020_release,
509         .sleep = ts2020_sleep,
510         .set_params = ts2020_set_params,
511         .get_frequency = ts2020_get_frequency,
512         .get_if_frequency = ts2020_get_if_frequency,
513         .get_rf_strength = ts2020_read_signal_strength,
514 };
515
516 struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
517                                         const struct ts2020_config *config,
518                                         struct i2c_adapter *i2c)
519 {
520         struct i2c_client *client;
521         struct i2c_board_info board_info;
522
523         /* This is only used by ts2020_probe() so can be on the stack */
524         struct ts2020_config pdata;
525
526         memcpy(&pdata, config, sizeof(pdata));
527         pdata.fe = fe;
528         pdata.attach_in_use = true;
529
530         memset(&board_info, 0, sizeof(board_info));
531         strscpy(board_info.type, "ts2020", I2C_NAME_SIZE);
532         board_info.addr = config->tuner_address;
533         board_info.platform_data = &pdata;
534         client = i2c_new_device(i2c, &board_info);
535         if (!client || !client->dev.driver)
536                 return NULL;
537
538         return fe;
539 }
540 EXPORT_SYMBOL(ts2020_attach);
541
542 /*
543  * We implement own regmap locking due to legacy DVB attach which uses frontend
544  * gate control callback to control I2C bus access. We can open / close gate and
545  * serialize whole open / I2C-operation / close sequence at the same.
546  */
547 static void ts2020_regmap_lock(void *__dev)
548 {
549         struct ts2020_priv *dev = __dev;
550
551         mutex_lock(&dev->regmap_mutex);
552         if (dev->fe->ops.i2c_gate_ctrl)
553                 dev->fe->ops.i2c_gate_ctrl(dev->fe, 1);
554 }
555
556 static void ts2020_regmap_unlock(void *__dev)
557 {
558         struct ts2020_priv *dev = __dev;
559
560         if (dev->fe->ops.i2c_gate_ctrl)
561                 dev->fe->ops.i2c_gate_ctrl(dev->fe, 0);
562         mutex_unlock(&dev->regmap_mutex);
563 }
564
565 static int ts2020_probe(struct i2c_client *client,
566                 const struct i2c_device_id *id)
567 {
568         struct ts2020_config *pdata = client->dev.platform_data;
569         struct dvb_frontend *fe = pdata->fe;
570         struct ts2020_priv *dev;
571         int ret;
572         u8 u8tmp;
573         unsigned int utmp;
574         char *chip_str;
575
576         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
577         if (!dev) {
578                 ret = -ENOMEM;
579                 goto err;
580         }
581
582         /* create regmap */
583         mutex_init(&dev->regmap_mutex);
584         dev->regmap_config.reg_bits = 8,
585         dev->regmap_config.val_bits = 8,
586         dev->regmap_config.lock = ts2020_regmap_lock,
587         dev->regmap_config.unlock = ts2020_regmap_unlock,
588         dev->regmap_config.lock_arg = dev,
589         dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
590         if (IS_ERR(dev->regmap)) {
591                 ret = PTR_ERR(dev->regmap);
592                 goto err_kfree;
593         }
594
595         dev->i2c = client->adapter;
596         dev->i2c_address = client->addr;
597         dev->loop_through = pdata->loop_through;
598         dev->clk_out = pdata->clk_out;
599         dev->clk_out_div = pdata->clk_out_div;
600         dev->dont_poll = pdata->dont_poll;
601         dev->frequency_div = pdata->frequency_div;
602         dev->fe = fe;
603         dev->get_agc_pwm = pdata->get_agc_pwm;
604         fe->tuner_priv = dev;
605         dev->client = client;
606         INIT_DELAYED_WORK(&dev->stat_work, ts2020_stat_work);
607
608         /* check if the tuner is there */
609         ret = regmap_read(dev->regmap, 0x00, &utmp);
610         if (ret)
611                 goto err_regmap_exit;
612
613         if ((utmp & 0x03) == 0x00) {
614                 ret = regmap_write(dev->regmap, 0x00, 0x01);
615                 if (ret)
616                         goto err_regmap_exit;
617
618                 usleep_range(2000, 50000);
619         }
620
621         ret = regmap_write(dev->regmap, 0x00, 0x03);
622         if (ret)
623                 goto err_regmap_exit;
624
625         usleep_range(2000, 50000);
626
627         ret = regmap_read(dev->regmap, 0x00, &utmp);
628         if (ret)
629                 goto err_regmap_exit;
630
631         dev_dbg(&client->dev, "chip_id=%02x\n", utmp);
632
633         switch (utmp) {
634         case 0x01:
635         case 0x41:
636         case 0x81:
637                 dev->tuner = TS2020_M88TS2020;
638                 chip_str = "TS2020";
639                 if (!dev->frequency_div)
640                         dev->frequency_div = 1060000;
641                 break;
642         case 0xc3:
643         case 0x83:
644                 dev->tuner = TS2020_M88TS2022;
645                 chip_str = "TS2022";
646                 if (!dev->frequency_div)
647                         dev->frequency_div = 1103000;
648                 break;
649         default:
650                 ret = -ENODEV;
651                 goto err_regmap_exit;
652         }
653
654         if (dev->tuner == TS2020_M88TS2022) {
655                 switch (dev->clk_out) {
656                 case TS2020_CLK_OUT_DISABLED:
657                         u8tmp = 0x60;
658                         break;
659                 case TS2020_CLK_OUT_ENABLED:
660                         u8tmp = 0x70;
661                         ret = regmap_write(dev->regmap, 0x05, dev->clk_out_div);
662                         if (ret)
663                                 goto err_regmap_exit;
664                         break;
665                 case TS2020_CLK_OUT_ENABLED_XTALOUT:
666                         u8tmp = 0x6c;
667                         break;
668                 default:
669                         ret = -EINVAL;
670                         goto err_regmap_exit;
671                 }
672
673                 ret = regmap_write(dev->regmap, 0x42, u8tmp);
674                 if (ret)
675                         goto err_regmap_exit;
676
677                 if (dev->loop_through)
678                         u8tmp = 0xec;
679                 else
680                         u8tmp = 0x6c;
681
682                 ret = regmap_write(dev->regmap, 0x62, u8tmp);
683                 if (ret)
684                         goto err_regmap_exit;
685         }
686
687         /* sleep */
688         ret = regmap_write(dev->regmap, 0x00, 0x00);
689         if (ret)
690                 goto err_regmap_exit;
691
692         dev_info(&client->dev,
693                  "Montage Technology %s successfully identified\n", chip_str);
694
695         memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
696                         sizeof(struct dvb_tuner_ops));
697         if (!pdata->attach_in_use)
698                 fe->ops.tuner_ops.release = NULL;
699
700         i2c_set_clientdata(client, dev);
701         return 0;
702 err_regmap_exit:
703         regmap_exit(dev->regmap);
704 err_kfree:
705         kfree(dev);
706 err:
707         dev_dbg(&client->dev, "failed=%d\n", ret);
708         return ret;
709 }
710
711 static int ts2020_remove(struct i2c_client *client)
712 {
713         struct ts2020_priv *dev = i2c_get_clientdata(client);
714
715         dev_dbg(&client->dev, "\n");
716
717         /* stop statistics polling */
718         if (!dev->dont_poll)
719                 cancel_delayed_work_sync(&dev->stat_work);
720
721         regmap_exit(dev->regmap);
722         kfree(dev);
723         return 0;
724 }
725
726 static const struct i2c_device_id ts2020_id_table[] = {
727         {"ts2020", 0},
728         {"ts2022", 0},
729         {}
730 };
731 MODULE_DEVICE_TABLE(i2c, ts2020_id_table);
732
733 static struct i2c_driver ts2020_driver = {
734         .driver = {
735                 .name   = "ts2020",
736         },
737         .probe          = ts2020_probe,
738         .remove         = ts2020_remove,
739         .id_table       = ts2020_id_table,
740 };
741
742 module_i2c_driver(ts2020_driver);
743
744 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
745 MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
746 MODULE_LICENSE("GPL");