2 * Driver for the ST STV0910 DVB-S/S2 demodulator.
4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
5 * Marcus Metzler <mocm@metzlerbros.de>
6 * developed for Digital Devices GmbH
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 only, as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/firmware.h>
24 #include <linux/i2c.h>
25 #include <asm/div64.h>
27 #include <media/dvb_frontend.h>
29 #include "stv0910_regs.h"
31 #define EXT_CLOCK 30000000
32 #define TUNING_DELAY 200
33 #define BER_SRC_S 0x20
34 #define BER_SRC_S2 0x20
36 static LIST_HEAD(stvlist);
38 enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
40 enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
43 DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
44 DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,
45 DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,
46 DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,
47 DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
48 DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
49 DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
53 enum fe_stv0910_mod_cod {
54 FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
55 FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
56 FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
57 FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
58 FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
59 FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
60 FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
64 enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
66 static inline u32 muldiv32(u32 a, u32 b, u32 c)
70 tmp64 = (u64)a * (u64)b;
77 struct list_head stvlist;
80 struct i2c_adapter *i2c;
81 struct mutex i2c_lock; /* shared I2C access protect */
82 struct mutex reg_lock; /* shared register write protect */
90 struct stv_base *base;
91 struct dvb_frontend fe;
99 unsigned long tune_time;
104 enum receive_mode receive_mode;
111 u8 last_viterbi_rate;
112 enum fe_code_rate puncture_rate;
113 enum fe_stv0910_mod_cod mod_cod;
114 enum dvbs2_fectype fectype;
116 enum fe_stv0910_roll_off feroll_off;
118 int is_standard_broadcast;
121 u32 cur_scrambling_code;
123 u32 last_bernumerator;
124 u32 last_berdenominator;
140 static int write_reg(struct stv *state, u16 reg, u8 val)
142 struct i2c_adapter *adap = state->base->i2c;
143 u8 data[3] = {reg >> 8, reg & 0xff, val};
144 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
145 .buf = data, .len = 3};
147 if (i2c_transfer(adap, &msg, 1) != 1) {
148 dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
149 state->base->adr, reg, val);
155 static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
156 u16 reg, u8 *val, int count)
158 u8 msg[2] = {reg >> 8, reg & 0xff};
159 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
160 .buf = msg, .len = 2},
161 {.addr = adr, .flags = I2C_M_RD,
162 .buf = val, .len = count } };
164 if (i2c_transfer(adapter, msgs, 2) != 2) {
165 dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
172 static int read_reg(struct stv *state, u16 reg, u8 *val)
174 return i2c_read_regs16(state->base->i2c, state->base->adr,
178 static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
180 return i2c_read_regs16(state->base->i2c, state->base->adr,
184 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
189 mutex_lock(&state->base->reg_lock);
190 status = read_reg(state, reg, &tmp);
192 status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
193 mutex_unlock(&state->base->reg_lock);
197 static int write_field(struct stv *state, u32 field, u8 val)
200 u8 shift, mask, old, new;
202 status = read_reg(state, field >> 16, &old);
206 shift = (field >> 12) & 0xf;
207 new = ((val << shift) & mask) | (old & ~mask);
210 return write_reg(state, field >> 16, new);
213 #define SET_FIELD(_reg, _val) \
214 write_field(state, state->nr ? FSTV0910_P2_##_reg : \
215 FSTV0910_P1_##_reg, _val)
217 #define SET_REG(_reg, _val) \
218 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
219 RSTV0910_P1_##_reg, _val)
221 #define GET_REG(_reg, _val) \
222 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
223 RSTV0910_P1_##_reg, _val)
225 static const struct slookup s1_sn_lookup[] = {
226 { 0, 9242 }, /* C/N= 0dB */
227 { 5, 9105 }, /* C/N= 0.5dB */
228 { 10, 8950 }, /* C/N= 1.0dB */
229 { 15, 8780 }, /* C/N= 1.5dB */
230 { 20, 8566 }, /* C/N= 2.0dB */
231 { 25, 8366 }, /* C/N= 2.5dB */
232 { 30, 8146 }, /* C/N= 3.0dB */
233 { 35, 7908 }, /* C/N= 3.5dB */
234 { 40, 7666 }, /* C/N= 4.0dB */
235 { 45, 7405 }, /* C/N= 4.5dB */
236 { 50, 7136 }, /* C/N= 5.0dB */
237 { 55, 6861 }, /* C/N= 5.5dB */
238 { 60, 6576 }, /* C/N= 6.0dB */
239 { 65, 6330 }, /* C/N= 6.5dB */
240 { 70, 6048 }, /* C/N= 7.0dB */
241 { 75, 5768 }, /* C/N= 7.5dB */
242 { 80, 5492 }, /* C/N= 8.0dB */
243 { 85, 5224 }, /* C/N= 8.5dB */
244 { 90, 4959 }, /* C/N= 9.0dB */
245 { 95, 4709 }, /* C/N= 9.5dB */
246 { 100, 4467 }, /* C/N=10.0dB */
247 { 105, 4236 }, /* C/N=10.5dB */
248 { 110, 4013 }, /* C/N=11.0dB */
249 { 115, 3800 }, /* C/N=11.5dB */
250 { 120, 3598 }, /* C/N=12.0dB */
251 { 125, 3406 }, /* C/N=12.5dB */
252 { 130, 3225 }, /* C/N=13.0dB */
253 { 135, 3052 }, /* C/N=13.5dB */
254 { 140, 2889 }, /* C/N=14.0dB */
255 { 145, 2733 }, /* C/N=14.5dB */
256 { 150, 2587 }, /* C/N=15.0dB */
257 { 160, 2318 }, /* C/N=16.0dB */
258 { 170, 2077 }, /* C/N=17.0dB */
259 { 180, 1862 }, /* C/N=18.0dB */
260 { 190, 1670 }, /* C/N=19.0dB */
261 { 200, 1499 }, /* C/N=20.0dB */
262 { 210, 1347 }, /* C/N=21.0dB */
263 { 220, 1213 }, /* C/N=22.0dB */
264 { 230, 1095 }, /* C/N=23.0dB */
265 { 240, 992 }, /* C/N=24.0dB */
266 { 250, 900 }, /* C/N=25.0dB */
267 { 260, 826 }, /* C/N=26.0dB */
268 { 270, 758 }, /* C/N=27.0dB */
269 { 280, 702 }, /* C/N=28.0dB */
270 { 290, 653 }, /* C/N=29.0dB */
271 { 300, 613 }, /* C/N=30.0dB */
272 { 310, 579 }, /* C/N=31.0dB */
273 { 320, 550 }, /* C/N=32.0dB */
274 { 330, 526 }, /* C/N=33.0dB */
275 { 350, 490 }, /* C/N=33.0dB */
276 { 400, 445 }, /* C/N=40.0dB */
277 { 450, 430 }, /* C/N=45.0dB */
278 { 500, 426 }, /* C/N=50.0dB */
279 { 510, 425 } /* C/N=51.0dB */
282 static const struct slookup s2_sn_lookup[] = {
283 { -30, 13950 }, /* C/N=-2.5dB */
284 { -25, 13580 }, /* C/N=-2.5dB */
285 { -20, 13150 }, /* C/N=-2.0dB */
286 { -15, 12760 }, /* C/N=-1.5dB */
287 { -10, 12345 }, /* C/N=-1.0dB */
288 { -5, 11900 }, /* C/N=-0.5dB */
289 { 0, 11520 }, /* C/N= 0dB */
290 { 5, 11080 }, /* C/N= 0.5dB */
291 { 10, 10630 }, /* C/N= 1.0dB */
292 { 15, 10210 }, /* C/N= 1.5dB */
293 { 20, 9790 }, /* C/N= 2.0dB */
294 { 25, 9390 }, /* C/N= 2.5dB */
295 { 30, 8970 }, /* C/N= 3.0dB */
296 { 35, 8575 }, /* C/N= 3.5dB */
297 { 40, 8180 }, /* C/N= 4.0dB */
298 { 45, 7800 }, /* C/N= 4.5dB */
299 { 50, 7430 }, /* C/N= 5.0dB */
300 { 55, 7080 }, /* C/N= 5.5dB */
301 { 60, 6720 }, /* C/N= 6.0dB */
302 { 65, 6320 }, /* C/N= 6.5dB */
303 { 70, 6060 }, /* C/N= 7.0dB */
304 { 75, 5760 }, /* C/N= 7.5dB */
305 { 80, 5480 }, /* C/N= 8.0dB */
306 { 85, 5200 }, /* C/N= 8.5dB */
307 { 90, 4930 }, /* C/N= 9.0dB */
308 { 95, 4680 }, /* C/N= 9.5dB */
309 { 100, 4425 }, /* C/N=10.0dB */
310 { 105, 4210 }, /* C/N=10.5dB */
311 { 110, 3980 }, /* C/N=11.0dB */
312 { 115, 3765 }, /* C/N=11.5dB */
313 { 120, 3570 }, /* C/N=12.0dB */
314 { 125, 3315 }, /* C/N=12.5dB */
315 { 130, 3140 }, /* C/N=13.0dB */
316 { 135, 2980 }, /* C/N=13.5dB */
317 { 140, 2820 }, /* C/N=14.0dB */
318 { 145, 2670 }, /* C/N=14.5dB */
319 { 150, 2535 }, /* C/N=15.0dB */
320 { 160, 2270 }, /* C/N=16.0dB */
321 { 170, 2035 }, /* C/N=17.0dB */
322 { 180, 1825 }, /* C/N=18.0dB */
323 { 190, 1650 }, /* C/N=19.0dB */
324 { 200, 1485 }, /* C/N=20.0dB */
325 { 210, 1340 }, /* C/N=21.0dB */
326 { 220, 1212 }, /* C/N=22.0dB */
327 { 230, 1100 }, /* C/N=23.0dB */
328 { 240, 1000 }, /* C/N=24.0dB */
329 { 250, 910 }, /* C/N=25.0dB */
330 { 260, 836 }, /* C/N=26.0dB */
331 { 270, 772 }, /* C/N=27.0dB */
332 { 280, 718 }, /* C/N=28.0dB */
333 { 290, 671 }, /* C/N=29.0dB */
334 { 300, 635 }, /* C/N=30.0dB */
335 { 310, 602 }, /* C/N=31.0dB */
336 { 320, 575 }, /* C/N=32.0dB */
337 { 330, 550 }, /* C/N=33.0dB */
338 { 350, 517 }, /* C/N=35.0dB */
339 { 400, 480 }, /* C/N=40.0dB */
340 { 450, 466 }, /* C/N=45.0dB */
341 { 500, 464 }, /* C/N=50.0dB */
342 { 510, 463 }, /* C/N=51.0dB */
345 static const struct slookup padc_lookup[] = {
346 { 0, 118000 }, /* PADC= +0dBm */
347 { -100, 93600 }, /* PADC= -1dBm */
348 { -200, 74500 }, /* PADC= -2dBm */
349 { -300, 59100 }, /* PADC= -3dBm */
350 { -400, 47000 }, /* PADC= -4dBm */
351 { -500, 37300 }, /* PADC= -5dBm */
352 { -600, 29650 }, /* PADC= -6dBm */
353 { -700, 23520 }, /* PADC= -7dBm */
354 { -900, 14850 }, /* PADC= -9dBm */
355 { -1100, 9380 }, /* PADC=-11dBm */
356 { -1300, 5910 }, /* PADC=-13dBm */
357 { -1500, 3730 }, /* PADC=-15dBm */
358 { -1700, 2354 }, /* PADC=-17dBm */
359 { -1900, 1485 }, /* PADC=-19dBm */
360 { -2000, 1179 }, /* PADC=-20dBm */
361 { -2100, 1000 }, /* PADC=-21dBm */
364 /*********************************************************************
365 * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
366 *********************************************************************/
367 static const u8 s2car_loop[] = {
369 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
370 * 20MPon 20MPoff 30MPon 30MPoff
374 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
376 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
378 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
380 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
382 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
384 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
386 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
388 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
390 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
392 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
394 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
396 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
398 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
400 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
402 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
404 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
406 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
408 /**********************************************************************
409 * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
410 **********************************************************************/
413 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
414 * 20MPoff 30MPon 30MPoff
418 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
420 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
422 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
424 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
426 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
428 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
430 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
432 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
434 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
436 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
438 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
441 static u8 get_optim_cloop(struct stv *state,
442 enum fe_stv0910_mod_cod mod_cod, u32 pilots)
446 if (mod_cod >= FE_32APSK_910)
447 i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
448 else if (mod_cod >= FE_QPSK_14)
449 i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
451 if (state->symbol_rate <= 3000000)
453 else if (state->symbol_rate <= 7000000)
455 else if (state->symbol_rate <= 15000000)
457 else if (state->symbol_rate <= 25000000)
465 return s2car_loop[i];
468 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
485 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
486 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
487 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
488 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
489 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
490 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
491 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
493 symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
494 ((u32)symb_freq1 << 8) | (u32)symb_freq0;
495 timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
498 if ((timing_offset & (1 << 23)) != 0)
499 timing_offset |= 0xFF000000; /* Sign extent */
501 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
502 timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
504 *p_symbol_rate = symbol_rate + timing_offset;
509 static int get_signal_parameters(struct stv *state)
516 if (state->receive_mode == RCVMODE_DVBS2) {
517 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
518 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
519 state->pilots = (tmp & 0x01) != 0;
520 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
522 } else if (state->receive_mode == RCVMODE_DVBS) {
523 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
524 state->puncture_rate = FEC_NONE;
525 switch (tmp & 0x1F) {
527 state->puncture_rate = FEC_1_2;
530 state->puncture_rate = FEC_2_3;
533 state->puncture_rate = FEC_3_4;
536 state->puncture_rate = FEC_5_6;
539 state->puncture_rate = FEC_7_8;
543 state->is_standard_broadcast = 1;
544 state->feroll_off = FE_SAT_35;
549 static int tracking_optimization(struct stv *state)
553 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
556 switch (state->receive_mode) {
567 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
569 if (state->receive_mode == RCVMODE_DVBS2) {
570 /* Disable Reed-Solomon */
571 write_shared_reg(state,
572 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
575 if (state->fectype == DVBS2_64K) {
576 u8 aclc = get_optim_cloop(state, state->mod_cod,
579 if (state->mod_cod <= FE_QPSK_910) {
580 write_reg(state, RSTV0910_P2_ACLC2S2Q +
581 state->regoff, aclc);
582 } else if (state->mod_cod <= FE_8PSK_910) {
583 write_reg(state, RSTV0910_P2_ACLC2S2Q +
584 state->regoff, 0x2a);
585 write_reg(state, RSTV0910_P2_ACLC2S28 +
586 state->regoff, aclc);
587 } else if (state->mod_cod <= FE_16APSK_910) {
588 write_reg(state, RSTV0910_P2_ACLC2S2Q +
589 state->regoff, 0x2a);
590 write_reg(state, RSTV0910_P2_ACLC2S216A +
591 state->regoff, aclc);
592 } else if (state->mod_cod <= FE_32APSK_910) {
593 write_reg(state, RSTV0910_P2_ACLC2S2Q +
594 state->regoff, 0x2a);
595 write_reg(state, RSTV0910_P2_ACLC2S232A +
596 state->regoff, aclc);
603 static s32 table_lookup(const struct slookup *table,
604 int table_size, u32 reg_value)
608 int imax = table_size - 1;
612 /* Assumes Table[0].RegValue > Table[imax].RegValue */
613 if (reg_value >= table[0].reg_value) {
614 value = table[0].value;
615 } else if (reg_value <= table[imax].reg_value) {
616 value = table[imax].value;
618 while ((imax - imin) > 1) {
619 i = (imax + imin) / 2;
620 if ((table[imin].reg_value >= reg_value) &&
621 (reg_value >= table[i].reg_value))
627 reg_diff = table[imax].reg_value - table[imin].reg_value;
628 value = table[imin].value;
630 value += ((s32)(reg_value - table[imin].reg_value) *
631 (s32)(table[imax].value
632 - table[imin].value))
639 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
645 const struct slookup *lookup;
647 *signal_to_noise = 0;
652 if (state->receive_mode == RCVMODE_DVBS2) {
653 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
655 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
657 n_lookup = ARRAY_SIZE(s2_sn_lookup);
658 lookup = s2_sn_lookup;
660 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
662 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
664 n_lookup = ARRAY_SIZE(s1_sn_lookup);
665 lookup = s1_sn_lookup;
667 data = (((u16)data1) << 8) | (u16)data0;
668 *signal_to_noise = table_lookup(lookup, n_lookup, data);
672 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
677 int status = read_regs(state,
678 RSTV0910_P2_ERRCNT12 + state->regoff,
684 if ((regs[0] & 0x80) == 0) {
685 state->last_berdenominator = 1ULL << ((state->berscale * 2) +
687 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
688 ((u32)regs[1] << 8) | regs[2];
689 if (state->last_bernumerator < 256 && state->berscale < 6) {
690 state->berscale += 1;
691 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
693 0x20 | state->berscale);
694 } else if (state->last_bernumerator > 1024 &&
695 state->berscale > 2) {
696 state->berscale -= 1;
697 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
698 state->regoff, 0x20 |
702 *bernumerator = state->last_bernumerator;
703 *berdenominator = state->last_berdenominator;
707 static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
709 static const u32 nbch[][2] = {
710 { 0, 0}, /* DUMMY_PLF */
711 {16200, 3240}, /* QPSK_1_4, */
712 {21600, 5400}, /* QPSK_1_3, */
713 {25920, 6480}, /* QPSK_2_5, */
714 {32400, 7200}, /* QPSK_1_2, */
715 {38880, 9720}, /* QPSK_3_5, */
716 {43200, 10800}, /* QPSK_2_3, */
717 {48600, 11880}, /* QPSK_3_4, */
718 {51840, 12600}, /* QPSK_4_5, */
719 {54000, 13320}, /* QPSK_5_6, */
720 {57600, 14400}, /* QPSK_8_9, */
721 {58320, 16000}, /* QPSK_9_10, */
722 {43200, 9720}, /* 8PSK_3_5, */
723 {48600, 10800}, /* 8PSK_2_3, */
724 {51840, 11880}, /* 8PSK_3_4, */
725 {54000, 13320}, /* 8PSK_5_6, */
726 {57600, 14400}, /* 8PSK_8_9, */
727 {58320, 16000}, /* 8PSK_9_10, */
728 {43200, 10800}, /* 16APSK_2_3, */
729 {48600, 11880}, /* 16APSK_3_4, */
730 {51840, 12600}, /* 16APSK_4_5, */
731 {54000, 13320}, /* 16APSK_5_6, */
732 {57600, 14400}, /* 16APSK_8_9, */
733 {58320, 16000}, /* 16APSK_9_10 */
734 {48600, 11880}, /* 32APSK_3_4, */
735 {51840, 12600}, /* 32APSK_4_5, */
736 {54000, 13320}, /* 32APSK_5_6, */
737 {57600, 14400}, /* 32APSK_8_9, */
738 {58320, 16000}, /* 32APSK_9_10 */
741 if (mod_cod >= DVBS2_QPSK_1_4 &&
742 mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
743 return nbch[mod_cod][fectype];
747 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
752 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
758 if ((regs[0] & 0x80) == 0) {
759 state->last_berdenominator =
760 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
762 (state->berscale * 2);
763 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
764 ((u32)regs[1] << 8) | regs[2];
765 if (state->last_bernumerator < 256 && state->berscale < 6) {
766 state->berscale += 1;
767 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
768 0x20 | state->berscale);
769 } else if (state->last_bernumerator > 1024 &&
770 state->berscale > 2) {
771 state->berscale -= 1;
772 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
773 0x20 | state->berscale);
776 *bernumerator = state->last_bernumerator;
777 *berdenominator = state->last_berdenominator;
781 static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
787 switch (state->receive_mode) {
789 return get_bit_error_rate_s(state,
790 bernumerator, berdenominator);
792 return get_bit_error_rate_s2(state,
793 bernumerator, berdenominator);
800 static int set_mclock(struct stv *state, u32 master_clock)
804 u32 quartz = state->base->extclk / 1000000;
805 u32 fphi = master_clock / 1000000;
806 u32 ndiv = (fphi * odf * idf) / quartz;
810 if (ndiv >= 7 && ndiv <= 71)
812 else if (ndiv >= 72 && ndiv <= 79)
814 else if (ndiv >= 80 && ndiv <= 87)
816 else if (ndiv >= 88 && ndiv <= 95)
818 else if (ndiv >= 96 && ndiv <= 103)
820 else if (ndiv >= 104 && ndiv <= 111)
822 else if (ndiv >= 112 && ndiv <= 119)
824 else if (ndiv >= 120 && ndiv <= 127)
826 else if (ndiv >= 128 && ndiv <= 135)
828 else if (ndiv >= 136 && ndiv <= 143)
830 else if (ndiv >= 144 && ndiv <= 151)
832 else if (ndiv >= 152 && ndiv <= 159)
834 else if (ndiv >= 160 && ndiv <= 167)
836 else if (ndiv >= 168 && ndiv <= 175)
838 else if (ndiv >= 176 && ndiv <= 183)
840 else if (ndiv >= 184 && ndiv <= 191)
842 else if (ndiv >= 192 && ndiv <= 199)
844 else if (ndiv >= 200 && ndiv <= 207)
846 else if (ndiv >= 208 && ndiv <= 215)
848 else if (ndiv >= 216 && ndiv <= 223)
850 else if (ndiv >= 224 && ndiv <= 225)
853 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
854 write_reg(state, RSTV0910_NCOARSE2, odf);
855 write_reg(state, RSTV0910_NCOARSE1, ndiv);
857 fvco = (quartz * 2 * ndiv) / idf;
858 state->base->mclk = fvco / (2 * odf) * 1000000;
863 static int stop(struct stv *state)
865 if (state->started) {
868 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
869 state->tscfgh | 0x01);
870 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
871 tmp &= ~0x01; /* release reset DVBS2 packet delin */
872 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
874 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
876 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
879 state->receive_mode = RCVMODE_NONE;
883 static void set_pls(struct stv *state, u32 pls_code)
885 if (pls_code == state->cur_scrambling_code)
888 /* PLROOT2 bit 2 = gold code */
889 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
891 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
892 (pls_code >> 8) & 0xff);
893 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
894 0x04 | ((pls_code >> 16) & 0x03));
895 state->cur_scrambling_code = pls_code;
898 static void set_isi(struct stv *state, u32 isi)
900 if (isi == NO_STREAM_ID_FILTER)
902 if (isi == 0x80000000) {
903 SET_FIELD(FORCE_CONTINUOUS, 1);
904 SET_FIELD(TSOUT_NOSYNC, 1);
906 SET_FIELD(FILTER_EN, 1);
907 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
909 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
911 SET_FIELD(ALGOSWRST, 1);
912 SET_FIELD(ALGOSWRST, 0);
915 static void set_stream_modes(struct stv *state,
916 struct dtv_frontend_properties *p)
918 set_isi(state, p->stream_id);
919 set_pls(state, p->scrambling_sequence_index);
922 static int init_search_param(struct stv *state,
923 struct dtv_frontend_properties *p)
925 SET_FIELD(FORCE_CONTINUOUS, 0);
926 SET_FIELD(FRAME_MODE, 0);
927 SET_FIELD(FILTER_EN, 0);
928 SET_FIELD(TSOUT_NOSYNC, 0);
929 SET_FIELD(TSFIFO_EMBINDVB, 0);
930 SET_FIELD(TSDEL_SYNCBYTE, 0);
931 SET_REG(UPLCCST0, 0xe0);
932 SET_FIELD(TSINS_TOKEN, 0);
933 SET_FIELD(HYSTERESIS_THRESHOLD, 0);
934 SET_FIELD(ISIOBS_MODE, 1);
936 set_stream_modes(state, p);
940 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
966 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
969 static int set_vth_default(struct stv *state)
971 state->vth[0] = 0xd7;
972 state->vth[1] = 0x85;
973 state->vth[2] = 0x58;
974 state->vth[3] = 0x3a;
975 state->vth[4] = 0x34;
976 state->vth[5] = 0x28;
977 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
986 static int set_vth(struct stv *state)
988 static const struct slookup vthlookup_table[] = {
989 {250, 8780}, /* C/N= 1.5dB */
990 {100, 7405}, /* C/N= 4.5dB */
991 {40, 6330}, /* C/N= 6.5dB */
992 {12, 5224}, /* C/N= 8.5dB */
993 {5, 4236} /* C/N=10.5dB */
998 int status = read_regs(state,
999 RSTV0910_P2_NNOSDATAT1 + state->regoff,
1001 u16 reg_value = (tmp[0] << 8) | tmp[1];
1002 s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
1005 for (i = 0; i < 6; i += 1)
1006 if (state->vth[i] > vth)
1007 state->vth[i] = vth;
1009 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1018 static int start(struct stv *state, struct dtv_frontend_properties *p)
1024 if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
1027 state->receive_mode = RCVMODE_NONE;
1028 state->demod_lock_time = 0;
1032 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1034 init_search_param(state, p);
1036 if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
1037 state->demod_timeout = 3000;
1038 state->fec_timeout = 2000;
1039 } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
1040 state->demod_timeout = 2500;
1041 state->fec_timeout = 1300;
1042 } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
1043 state->demod_timeout = 1000;
1044 state->fec_timeout = 650;
1045 } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
1046 state->demod_timeout = 700;
1047 state->fec_timeout = 350;
1048 } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
1049 state->demod_timeout = 400;
1050 state->fec_timeout = 200;
1051 } else { /* SR >=20Msps */
1052 state->demod_timeout = 300;
1053 state->fec_timeout = 200;
1056 /* Set the Init Symbol rate */
1057 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1058 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1059 ((symb >> 8) & 0x7F));
1060 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1062 state->demod_bits |= 0x80;
1063 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1065 /* FE_STV0910_SetSearchStandard */
1066 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd);
1067 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1068 reg_dmdcfgmd |= 0xC0);
1070 write_shared_reg(state,
1071 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1074 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
1075 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1077 enable_puncture_rate(state, FEC_NONE);
1079 /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
1080 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1081 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1082 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1083 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1084 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1085 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1087 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1088 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1089 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1090 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1093 * Reset CAR3, bug DVBS2->DVBS1 lock
1094 * Note: The bit is only pulsed -> no lock on shared register needed
1096 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1097 write_reg(state, RSTV0910_TSTRES0, 0);
1099 set_vth_default(state);
1101 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1103 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1105 if (p->symbol_rate <= 5000000)
1106 freq = (state->search_range / 2000) + 80;
1108 freq = (state->search_range / 2000) + 1600;
1109 freq = (freq << 16) / (state->base->mclk / 1000);
1111 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1112 (freq >> 8) & 0xff);
1113 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1114 /* CFR Low Setting */
1116 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1117 (freq >> 8) & 0xff);
1118 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1120 /* init the demod frequency offset to 0 */
1121 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1122 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1124 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1126 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1128 state->demod_lock_time += TUNING_DELAY;
1134 static int init_diseqc(struct stv *state)
1136 u16 offs = state->nr ? 0x40 : 0; /* Address offset */
1137 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1139 /* Disable receiver */
1140 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1141 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1142 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1143 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1147 static int probe(struct stv *state)
1151 state->receive_mode = RCVMODE_NONE;
1154 if (read_reg(state, RSTV0910_MID, &id) < 0)
1160 /* Configure the I2C repeater to off */
1161 write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1162 /* Configure the I2C repeater to off */
1163 write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1164 /* Set the I2C to oversampling ratio */
1165 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1167 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
1168 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
1169 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
1170 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1171 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
1174 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1176 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1178 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1179 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1181 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1182 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1183 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1184 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1186 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1187 write_reg(state, RSTV0910_TSTRES0, 0x00);
1189 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1190 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1192 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1193 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1195 set_mclock(state, 135000000);
1198 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1199 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1200 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1201 write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1203 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1205 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1206 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1207 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1208 write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1210 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1212 /* Reset stream merger */
1213 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1214 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1215 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1216 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1218 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1219 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1221 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
1222 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
1224 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
1225 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
1231 static int gate_ctrl(struct dvb_frontend *fe, int enable)
1233 struct stv *state = fe->demodulator_priv;
1234 u8 i2crpt = state->i2crpt & ~0x86;
1237 * mutex_lock note: Concurrent I2C gate bus accesses must be
1238 * prevented (STV0910 = dual demod on a single IC with a single I2C
1239 * gate/bus, and two tuners attached), similar to most (if not all)
1240 * other I2C host interfaces/busses.
1242 * enable=1 (open I2C gate) will grab the lock
1243 * enable=0 (close I2C gate) releases the lock
1247 mutex_lock(&state->base->i2c_lock);
1253 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
1254 RSTV0910_P1_I2CRPT, i2crpt) < 0) {
1255 /* don't hold the I2C bus lock on failure */
1256 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1257 mutex_unlock(&state->base->i2c_lock);
1258 dev_err(&state->base->i2c->dev,
1259 "%s() write_reg failure (enable=%d)\n",
1264 state->i2crpt = i2crpt;
1267 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1268 mutex_unlock(&state->base->i2c_lock);
1272 static void release(struct dvb_frontend *fe)
1274 struct stv *state = fe->demodulator_priv;
1276 state->base->count--;
1277 if (state->base->count == 0) {
1278 list_del(&state->base->stvlist);
1284 static int set_parameters(struct dvb_frontend *fe)
1287 struct stv *state = fe->demodulator_priv;
1288 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1291 if (fe->ops.tuner_ops.set_params)
1292 fe->ops.tuner_ops.set_params(fe);
1293 state->symbol_rate = p->symbol_rate;
1294 stat = start(state, p);
1298 static int manage_matype_info(struct stv *state)
1300 if (!state->started)
1302 if (state->receive_mode == RCVMODE_DVBS2) {
1305 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
1308 (enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
1309 state->is_vcm = (bbheader[0] & 0x10) == 0;
1310 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1311 } else if (state->receive_mode == RCVMODE_DVBS) {
1313 state->is_standard_broadcast = 1;
1314 state->feroll_off = FE_SAT_35;
1319 static int read_snr(struct dvb_frontend *fe)
1321 struct stv *state = fe->demodulator_priv;
1322 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1325 if (!get_signal_to_noise(state, &snrval)) {
1326 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1327 p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */
1329 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1335 static int read_ber(struct dvb_frontend *fe)
1337 struct stv *state = fe->demodulator_priv;
1338 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1341 get_bit_error_rate(state, &n, &d);
1343 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1344 p->pre_bit_error.stat[0].uvalue = n;
1345 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1346 p->pre_bit_count.stat[0].uvalue = d;
1351 static void read_signal_strength(struct dvb_frontend *fe)
1353 struct stv *state = fe->demodulator_priv;
1354 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1357 s32 padc, power = 0;
1360 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
1362 agc = (((u32)reg[0]) << 8) | reg[1];
1364 for (i = 0; i < 5; i += 1) {
1365 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
1366 power += (u32)reg[0] * (u32)reg[0]
1367 + (u32)reg[1] * (u32)reg[1];
1368 usleep_range(3000, 4000);
1372 padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
1374 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1375 p->strength.stat[0].svalue = (padc - agc);
1378 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
1380 struct stv *state = fe->demodulator_priv;
1381 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1384 enum receive_mode cur_receive_mode = RCVMODE_NONE;
1389 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1391 if (dmd_state & 0x40) {
1392 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1394 cur_receive_mode = (dmd_state & 0x20) ?
1395 RCVMODE_DVBS : RCVMODE_DVBS2;
1397 if (cur_receive_mode == RCVMODE_NONE) {
1400 /* reset signal statistics */
1401 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1402 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1403 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1404 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1409 *status |= (FE_HAS_SIGNAL
1414 if (state->receive_mode == RCVMODE_NONE) {
1415 state->receive_mode = cur_receive_mode;
1416 state->demod_lock_time = jiffies;
1417 state->first_time_lock = 1;
1419 get_signal_parameters(state);
1420 tracking_optimization(state);
1422 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1424 usleep_range(3000, 4000);
1425 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1426 state->tscfgh | 0x01);
1427 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1430 if (dmd_state & 0x40) {
1431 if (state->receive_mode == RCVMODE_DVBS2) {
1435 RSTV0910_P2_PDELSTATUS1 + state->regoff,
1437 feclock = (pdelstatus & 0x02) != 0;
1442 RSTV0910_P2_VSTATUSVIT + state->regoff,
1444 feclock = (vstatus & 0x08) != 0;
1449 *status |= FE_HAS_LOCK;
1451 if (state->first_time_lock) {
1454 state->first_time_lock = 0;
1456 manage_matype_info(state);
1458 if (state->receive_mode == RCVMODE_DVBS2) {
1460 * FSTV0910_P2_MANUALSX_ROLLOFF,
1461 * FSTV0910_P2_MANUALS2_ROLLOFF = 0
1463 state->demod_bits &= ~0x84;
1465 RSTV0910_P2_DEMOD + state->regoff,
1468 RSTV0910_P2_PDELCTRL2 + state->regoff,
1470 /* reset DVBS2 packet delinator error counter */
1473 RSTV0910_P2_PDELCTRL2 + state->regoff,
1475 /* reset DVBS2 packet delinator error counter */
1478 RSTV0910_P2_PDELCTRL2 + state->regoff,
1481 state->berscale = 2;
1482 state->last_bernumerator = 0;
1483 state->last_berdenominator = 1;
1484 /* force to PRE BCH Rate */
1486 RSTV0910_P2_ERRCTRL1 + state->regoff,
1487 BER_SRC_S2 | state->berscale);
1489 state->berscale = 2;
1490 state->last_bernumerator = 0;
1491 state->last_berdenominator = 1;
1492 /* force to PRE RS Rate */
1494 RSTV0910_P2_ERRCTRL1 + state->regoff,
1495 BER_SRC_S | state->berscale);
1497 /* Reset the Total packet counter */
1499 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
1501 * Reset the packet Error counter2 (and Set it to
1502 * infinit error count mode)
1505 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1507 set_vth_default(state);
1508 if (state->receive_mode == RCVMODE_DVBS)
1509 enable_puncture_rate(state,
1510 state->puncture_rate);
1513 /* Use highest signaled ModCod for quality */
1514 if (state->is_vcm) {
1516 enum fe_stv0910_mod_cod mod_cod;
1518 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
1520 mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
1522 if (mod_cod > state->mod_cod)
1523 state->mod_cod = mod_cod;
1527 /* read signal statistics */
1529 /* read signal strength */
1530 read_signal_strength(fe);
1532 /* read carrier/noise on FE_HAS_CARRIER */
1533 if (*status & FE_HAS_CARRIER)
1536 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1539 if (*status & FE_HAS_VITERBI) {
1542 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1543 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1549 static int get_frontend(struct dvb_frontend *fe,
1550 struct dtv_frontend_properties *p)
1552 struct stv *state = fe->demodulator_priv;
1556 if (state->receive_mode == RCVMODE_DVBS2) {
1558 const enum fe_modulation modcod2mod[0x20] = {
1559 QPSK, QPSK, QPSK, QPSK,
1560 QPSK, QPSK, QPSK, QPSK,
1561 QPSK, QPSK, QPSK, QPSK,
1562 PSK_8, PSK_8, PSK_8, PSK_8,
1563 PSK_8, PSK_8, APSK_16, APSK_16,
1564 APSK_16, APSK_16, APSK_16, APSK_16,
1565 APSK_32, APSK_32, APSK_32, APSK_32,
1568 const enum fe_code_rate modcod2fec[0x20] = {
1569 FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
1570 FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
1571 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1572 FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
1573 FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
1574 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1575 FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
1578 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1579 mc = ((tmp & 0x7c) >> 2);
1580 p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
1581 p->modulation = modcod2mod[mc];
1582 p->fec_inner = modcod2fec[mc];
1583 } else if (state->receive_mode == RCVMODE_DVBS) {
1584 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1585 switch (tmp & 0x1F) {
1587 p->fec_inner = FEC_1_2;
1590 p->fec_inner = FEC_2_3;
1593 p->fec_inner = FEC_3_4;
1596 p->fec_inner = FEC_5_6;
1599 p->fec_inner = FEC_7_8;
1602 p->fec_inner = FEC_NONE;
1605 p->rolloff = ROLLOFF_35;
1608 if (state->receive_mode != RCVMODE_NONE) {
1609 get_cur_symbol_rate(state, &symbolrate);
1610 p->symbol_rate = symbolrate;
1615 static int tune(struct dvb_frontend *fe, bool re_tune,
1616 unsigned int mode_flags,
1617 unsigned int *delay, enum fe_status *status)
1619 struct stv *state = fe->demodulator_priv;
1623 r = set_parameters(fe);
1626 state->tune_time = jiffies;
1629 r = read_status(fe, status);
1633 if (*status & FE_HAS_LOCK)
1640 static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
1642 return DVBFE_ALGO_HW;
1645 static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1647 struct stv *state = fe->demodulator_priv;
1648 u16 offs = state->nr ? 0x40 : 0;
1652 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1654 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1661 static int wait_dis(struct stv *state, u8 flag, u8 val)
1665 u16 offs = state->nr ? 0x40 : 0;
1667 for (i = 0; i < 10; i++) {
1668 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1669 if ((stat & flag) == val)
1671 usleep_range(10000, 11000);
1676 static int send_master_cmd(struct dvb_frontend *fe,
1677 struct dvb_diseqc_master_cmd *cmd)
1679 struct stv *state = fe->demodulator_priv;
1682 SET_FIELD(DISEQC_MODE, 2);
1683 SET_FIELD(DIS_PRECHARGE, 1);
1684 for (i = 0; i < cmd->msg_len; i++) {
1685 wait_dis(state, 0x40, 0x00);
1686 SET_REG(DISTXFIFO, cmd->msg[i]);
1688 SET_FIELD(DIS_PRECHARGE, 0);
1689 wait_dis(state, 0x20, 0x20);
1693 static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
1695 struct stv *state = fe->demodulator_priv;
1698 if (burst == SEC_MINI_A) {
1699 SET_FIELD(DISEQC_MODE, 3);
1702 SET_FIELD(DISEQC_MODE, 2);
1706 SET_FIELD(DIS_PRECHARGE, 1);
1707 wait_dis(state, 0x40, 0x00);
1708 SET_REG(DISTXFIFO, value);
1709 SET_FIELD(DIS_PRECHARGE, 0);
1710 wait_dis(state, 0x20, 0x20);
1715 static int sleep(struct dvb_frontend *fe)
1717 struct stv *state = fe->demodulator_priv;
1723 static const struct dvb_frontend_ops stv0910_ops = {
1724 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1726 .name = "ST STV0910",
1727 .frequency_min_hz = 950 * MHz,
1728 .frequency_max_hz = 2150 * MHz,
1729 .symbol_rate_min = 100000,
1730 .symbol_rate_max = 70000000,
1731 .caps = FE_CAN_INVERSION_AUTO |
1734 FE_CAN_2G_MODULATION |
1739 .i2c_gate_ctrl = gate_ctrl,
1740 .set_frontend = set_parameters,
1741 .get_frontend_algo = get_algo,
1742 .get_frontend = get_frontend,
1744 .read_status = read_status,
1745 .set_tone = set_tone,
1747 .diseqc_send_master_cmd = send_master_cmd,
1748 .diseqc_send_burst = send_burst,
1751 static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
1755 list_for_each_entry(p, &stvlist, stvlist)
1756 if (p->i2c == i2c && p->adr == adr)
1761 static void stv0910_init_stats(struct stv *state)
1763 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1765 p->strength.len = 1;
1766 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1768 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1769 p->pre_bit_error.len = 1;
1770 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1771 p->pre_bit_count.len = 1;
1772 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1775 struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
1776 struct stv0910_cfg *cfg,
1780 struct stv_base *base;
1782 state = kzalloc(sizeof(*state), GFP_KERNEL);
1786 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1787 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1788 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
1789 /* use safe tsspeed value if unspecified through stv0910_cfg */
1790 state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
1792 state->regoff = state->nr ? 0 : 0x200;
1793 state->search_range = 16000000;
1794 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1795 state->receive_mode = RCVMODE_NONE;
1796 state->cur_scrambling_code = (~0U);
1797 state->single = cfg->single ? 1 : 0;
1799 base = match_base(i2c, cfg->adr);
1804 base = kzalloc(sizeof(*base), GFP_KERNEL);
1808 base->adr = cfg->adr;
1810 base->extclk = cfg->clk ? cfg->clk : 30000000;
1812 mutex_init(&base->i2c_lock);
1813 mutex_init(&base->reg_lock);
1815 if (probe(state) < 0) {
1816 dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
1817 cfg->adr, dev_name(&i2c->dev));
1821 list_add(&base->stvlist, &stvlist);
1823 state->fe.ops = stv0910_ops;
1824 state->fe.demodulator_priv = state;
1827 dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
1828 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
1830 stv0910_init_stats(state);
1838 EXPORT_SYMBOL_GPL(stv0910_attach);
1840 MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
1841 MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
1842 MODULE_LICENSE("GPL");