2 Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
5 Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 http://products.zarlink.com/product_profiles/MT312.htm
24 http://products.zarlink.com/product_profiles/SL1935.htm
27 #include <linux/delay.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/string.h>
33 #include <linux/slab.h>
35 #include <media/dvb_frontend.h>
36 #include "mt312_priv.h"
39 /* Max transfer size done by I2C transfer functions */
40 #define MAX_XFER_SIZE 64
43 struct i2c_adapter *i2c;
44 /* configuration settings */
45 const struct mt312_config *config;
46 struct dvb_frontend frontend;
54 #define dprintk(args...) \
57 printk(KERN_DEBUG "mt312: " args); \
60 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
61 #define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */
63 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
64 u8 *buf, const size_t count)
67 struct i2c_msg msg[2];
68 u8 regbuf[1] = { reg };
70 msg[0].addr = state->config->demod_address;
74 msg[1].addr = state->config->demod_address;
75 msg[1].flags = I2C_M_RD;
79 ret = i2c_transfer(state->i2c, msg, 2);
82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
88 dprintk("R(%d):", reg & 0x7f);
89 for (i = 0; i < count; i++)
90 printk(KERN_CONT " %02x", buf[i]);
97 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
98 const u8 *src, const size_t count)
101 u8 buf[MAX_XFER_SIZE];
104 if (1 + count > sizeof(buf)) {
106 "mt312: write: len=%zu is too big!\n", count);
112 dprintk("W(%d):", reg & 0x7f);
113 for (i = 0; i < count; i++)
114 printk(KERN_CONT " %02x", src[i]);
119 memcpy(&buf[1], src, count);
121 msg.addr = state->config->demod_address;
126 ret = i2c_transfer(state->i2c, &msg, 1);
129 dprintk("%s: ret == %d\n", __func__, ret);
136 static inline int mt312_readreg(struct mt312_state *state,
137 const enum mt312_reg_addr reg, u8 *val)
139 return mt312_read(state, reg, val, 1);
142 static inline int mt312_writereg(struct mt312_state *state,
143 const enum mt312_reg_addr reg, const u8 val)
145 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
148 return mt312_write(state, reg, &tmp, 1);
151 static inline u32 mt312_div(u32 a, u32 b)
153 return (a + (b / 2)) / b;
156 static int mt312_reset(struct mt312_state *state, const u8 full)
158 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
161 static int mt312_get_inversion(struct mt312_state *state,
162 enum fe_spectral_inversion *i)
167 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
171 if (vit_mode & 0x80) /* auto inversion was used */
172 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
177 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
186 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
190 if (sym_rate_h & 0x80) {
191 /* symbol rate search was used */
192 ret = mt312_writereg(state, MON_CTRL, 0x03);
196 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
200 monitor = (buf[0] << 8) | buf[1];
202 dprintk("sr(auto) = %u\n",
203 mt312_div(monitor * 15625, 4));
205 ret = mt312_writereg(state, MON_CTRL, 0x05);
209 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
213 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
215 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
219 sym_rat_op = (buf[0] << 8) | buf[1];
221 dprintk("sym_rat_op=%d dec_ratio=%d\n",
222 sym_rat_op, dec_ratio);
223 dprintk("*sr(manual) = %lu\n",
224 (((state->xtal * 8192) / (sym_rat_op + 8192)) *
231 static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
233 const enum fe_code_rate fec_tab[8] =
234 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
235 FEC_AUTO, FEC_AUTO };
240 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
244 *cr = fec_tab[(fec_status >> 4) & 0x07];
249 static int mt312_initfe(struct dvb_frontend *fe)
251 struct mt312_state *state = fe->demodulator_priv;
256 ret = mt312_writereg(state, CONFIG,
257 (state->freq_mult == 6 ? 0x88 : 0x8c));
261 /* wait at least 150 usec */
265 ret = mt312_reset(state, 1);
269 /* Per datasheet, write correct values. 09/28/03 ACCJr.
270 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
272 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
273 0x01, 0x00, 0x00, 0x00 };
275 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
283 ret = mt312_writereg(state, GPP_CTRL, 0x80);
287 /* configure ZL10313 for optimal ADC performance */
290 ret = mt312_write(state, HW_CTRL, buf, 2);
294 /* enable MPEG output and ADCs */
295 ret = mt312_writereg(state, HW_CTRL, 0x00);
299 ret = mt312_writereg(state, MPEG_CTRL, 0x00);
307 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
310 buf[1] = mt312_div(state->xtal, 22000 * 4);
312 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
316 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
320 /* different MOCLK polarity */
330 ret = mt312_writereg(state, OP_CTRL, buf[0]);
338 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
342 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
349 static int mt312_send_master_cmd(struct dvb_frontend *fe,
350 struct dvb_diseqc_master_cmd *c)
352 struct mt312_state *state = fe->demodulator_priv;
356 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
359 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
363 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
367 ret = mt312_writereg(state, DISEQC_MODE,
368 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
373 /* is there a better way to wait for message to be transmitted */
376 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
377 if (c->msg[0] & 0x02) {
378 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
386 static int mt312_send_burst(struct dvb_frontend *fe,
387 const enum fe_sec_mini_cmd c)
389 struct mt312_state *state = fe->demodulator_priv;
390 const u8 mini_tab[2] = { 0x02, 0x03 };
398 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
402 ret = mt312_writereg(state, DISEQC_MODE,
403 (diseqc_mode & 0x40) | mini_tab[c]);
410 static int mt312_set_tone(struct dvb_frontend *fe,
411 const enum fe_sec_tone_mode t)
413 struct mt312_state *state = fe->demodulator_priv;
414 const u8 tone_tab[2] = { 0x01, 0x00 };
419 if (t > SEC_TONE_OFF)
422 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
426 ret = mt312_writereg(state, DISEQC_MODE,
427 (diseqc_mode & 0x40) | tone_tab[t]);
434 static int mt312_set_voltage(struct dvb_frontend *fe,
435 const enum fe_sec_voltage v)
437 struct mt312_state *state = fe->demodulator_priv;
438 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
441 if (v > SEC_VOLTAGE_OFF)
445 if (state->config->voltage_inverted)
448 return mt312_writereg(state, DISEQC_MODE, val);
451 static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s)
453 struct mt312_state *state = fe->demodulator_priv;
459 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
463 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n",
464 status[0], status[1], status[2]);
466 if (status[0] & 0xc0)
467 *s |= FE_HAS_SIGNAL; /* signal noise ratio */
468 if (status[0] & 0x04)
469 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
470 if (status[2] & 0x02)
471 *s |= FE_HAS_VITERBI; /* viterbi lock */
472 if (status[2] & 0x04)
473 *s |= FE_HAS_SYNC; /* byte align lock */
474 if (status[0] & 0x01)
475 *s |= FE_HAS_LOCK; /* qpsk lock */
480 static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
482 struct mt312_state *state = fe->demodulator_priv;
486 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
490 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
495 static int mt312_read_signal_strength(struct dvb_frontend *fe,
496 u16 *signal_strength)
498 struct mt312_state *state = fe->demodulator_priv;
504 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
508 agc = (buf[0] << 6) | (buf[1] >> 2);
509 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
511 *signal_strength = agc;
513 dprintk("agc=%08x err_db=%hd\n", agc, err_db);
518 static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
520 struct mt312_state *state = fe->demodulator_priv;
524 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
528 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
533 static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
535 struct mt312_state *state = fe->demodulator_priv;
539 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
543 *ubc = (buf[0] << 8) | buf[1];
548 static int mt312_set_frontend(struct dvb_frontend *fe)
550 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
551 struct mt312_state *state = fe->demodulator_priv;
553 u8 buf[5], config_val;
556 const u8 fec_tab[10] =
557 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
558 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
560 dprintk("%s: Freq %d\n", __func__, p->frequency);
562 if ((p->frequency < fe->ops.info.frequency_min_hz / kHz)
563 || (p->frequency > fe->ops.info.frequency_max_hz / kHz))
566 if (((int)p->inversion < INVERSION_OFF)
567 || (p->inversion > INVERSION_ON))
570 if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
571 || (p->symbol_rate > fe->ops.info.symbol_rate_max))
574 if (((int)p->fec_inner < FEC_NONE)
575 || (p->fec_inner > FEC_AUTO))
578 if ((p->fec_inner == FEC_4_5)
579 || (p->fec_inner == FEC_8_9))
584 /* For now we will do this only for the VP310.
585 * It should be better for the mt312 as well,
586 * but tuning will be slower. ACCJr 09/29/03
588 ret = mt312_readreg(state, CONFIG, &config_val);
591 if (p->symbol_rate >= 30000000) {
592 /* Note that 30MS/s should use 90MHz */
593 if (state->freq_mult == 6) {
594 /* We are running 60MHz */
595 state->freq_mult = 9;
596 ret = mt312_initfe(fe);
601 if (state->freq_mult == 9) {
602 /* We are running 90MHz */
603 state->freq_mult = 6;
604 ret = mt312_initfe(fe);
619 if (fe->ops.tuner_ops.set_params) {
620 fe->ops.tuner_ops.set_params(fe);
621 if (fe->ops.i2c_gate_ctrl)
622 fe->ops.i2c_gate_ctrl(fe, 0);
625 /* sr = (u16)(sr * 256.0 / 1000000.0) */
626 sr = mt312_div(p->symbol_rate * 4, 15625);
629 buf[0] = (sr >> 8) & 0x3f;
630 buf[1] = (sr >> 0) & 0xff;
633 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
636 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
638 if (p->symbol_rate < 10000000)
639 buf[3] |= 0x04; /* use afc mode */
644 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
648 mt312_reset(state, 0);
653 static int mt312_get_frontend(struct dvb_frontend *fe,
654 struct dtv_frontend_properties *p)
656 struct mt312_state *state = fe->demodulator_priv;
659 ret = mt312_get_inversion(state, &p->inversion);
663 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
667 ret = mt312_get_code_rate(state, &p->fec_inner);
674 static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
676 struct mt312_state *state = fe->demodulator_priv;
683 ret = mt312_readreg(state, GPP_CTRL, &val);
687 /* preserve this bit to not accidentally shutdown ADC */
697 ret = mt312_writereg(state, GPP_CTRL, val);
703 static int mt312_sleep(struct dvb_frontend *fe)
705 struct mt312_state *state = fe->demodulator_priv;
709 /* reset all registers to defaults */
710 ret = mt312_reset(state, 1);
714 if (state->id == ID_ZL10313) {
716 ret = mt312_writereg(state, GPP_CTRL, 0x00);
720 /* full shutdown of ADCs, mpeg bus tristated */
721 ret = mt312_writereg(state, HW_CTRL, 0x0d);
726 ret = mt312_readreg(state, CONFIG, &config);
731 ret = mt312_writereg(state, CONFIG, config & 0x7f);
738 static int mt312_get_tune_settings(struct dvb_frontend *fe,
739 struct dvb_frontend_tune_settings *fesettings)
741 fesettings->min_delay_ms = 50;
742 fesettings->step_size = 0;
743 fesettings->max_drift = 0;
747 static void mt312_release(struct dvb_frontend *fe)
749 struct mt312_state *state = fe->demodulator_priv;
753 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
754 static const struct dvb_frontend_ops mt312_ops = {
755 .delsys = { SYS_DVBS },
757 .name = "Zarlink ???? DVB-S",
758 .frequency_min_hz = 950 * MHz,
759 .frequency_max_hz = 2150 * MHz,
760 /* FIXME: adjust freq to real used xtal */
761 .frequency_stepsize_hz = MT312_PLL_CLK / 128,
762 .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
763 .symbol_rate_max = MT312_SYS_CLK / 2,
765 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
766 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
767 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
771 .release = mt312_release,
773 .init = mt312_initfe,
774 .sleep = mt312_sleep,
775 .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
777 .set_frontend = mt312_set_frontend,
778 .get_frontend = mt312_get_frontend,
779 .get_tune_settings = mt312_get_tune_settings,
781 .read_status = mt312_read_status,
782 .read_ber = mt312_read_ber,
783 .read_signal_strength = mt312_read_signal_strength,
784 .read_snr = mt312_read_snr,
785 .read_ucblocks = mt312_read_ucblocks,
787 .diseqc_send_master_cmd = mt312_send_master_cmd,
788 .diseqc_send_burst = mt312_send_burst,
789 .set_tone = mt312_set_tone,
790 .set_voltage = mt312_set_voltage,
793 struct dvb_frontend *mt312_attach(const struct mt312_config *config,
794 struct i2c_adapter *i2c)
796 struct mt312_state *state = NULL;
798 /* allocate memory for the internal state */
799 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
803 /* setup the state */
804 state->config = config;
807 /* check if the demod is there */
808 if (mt312_readreg(state, ID, &state->id) < 0)
811 /* create dvb_frontend */
812 memcpy(&state->frontend.ops, &mt312_ops,
813 sizeof(struct dvb_frontend_ops));
814 state->frontend.demodulator_priv = state;
818 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
819 state->xtal = MT312_PLL_CLK;
820 state->freq_mult = 9;
823 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
824 state->xtal = MT312_PLL_CLK;
825 state->freq_mult = 6;
828 strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S");
829 state->xtal = MT312_PLL_CLK_10_111;
830 state->freq_mult = 9;
833 printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n");
837 return &state->frontend;
843 EXPORT_SYMBOL(mt312_attach);
845 module_param(debug, int, 0644);
846 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
848 MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
849 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
850 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
851 MODULE_LICENSE("GPL");