2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
20 #include <media/dvb_frontend.h>
25 enum mb86a20s_bandwidth {
27 MB86A20S_13SEG_PARTIAL = 1,
32 static u8 mb86a20s_subchannel[] = {
33 0xb0, 0xc0, 0xd0, 0xe0,
34 0xf0, 0x00, 0x10, 0x20,
37 struct mb86a20s_state {
38 struct i2c_adapter *i2c;
39 const struct mb86a20s_config *config;
42 struct dvb_frontend frontend;
45 enum mb86a20s_bandwidth bw;
49 u32 estimated_rate[NUM_LAYERS];
50 unsigned long get_strength_time;
60 #define BER_SAMPLING_RATE 1 /* Seconds */
63 * Initialization sequence: Use whatevere default values that PV SBTVD
64 * does on its initialisation, obtained via USB snoop
66 static struct regdata mb86a20s_init1[] = {
70 { 0x50, 0xd1 }, { 0x51, 0x20 },
73 static struct regdata mb86a20s_init2[] = {
74 { 0x50, 0xd1 }, { 0x51, 0x22 },
80 { 0x04, 0x08 }, { 0x05, 0x05 },
81 { 0x04, 0x0e }, { 0x05, 0x00 },
82 { 0x04, 0x0f }, { 0x05, 0x14 },
83 { 0x04, 0x0b }, { 0x05, 0x8c },
84 { 0x04, 0x00 }, { 0x05, 0x00 },
85 { 0x04, 0x01 }, { 0x05, 0x07 },
86 { 0x04, 0x02 }, { 0x05, 0x0f },
87 { 0x04, 0x03 }, { 0x05, 0xa0 },
88 { 0x04, 0x09 }, { 0x05, 0x00 },
89 { 0x04, 0x0a }, { 0x05, 0xff },
90 { 0x04, 0x27 }, { 0x05, 0x64 },
91 { 0x04, 0x28 }, { 0x05, 0x00 },
92 { 0x04, 0x1e }, { 0x05, 0xff },
93 { 0x04, 0x29 }, { 0x05, 0x0a },
94 { 0x04, 0x32 }, { 0x05, 0x0a },
95 { 0x04, 0x14 }, { 0x05, 0x02 },
96 { 0x04, 0x04 }, { 0x05, 0x00 },
97 { 0x04, 0x05 }, { 0x05, 0x22 },
98 { 0x04, 0x06 }, { 0x05, 0x0e },
99 { 0x04, 0x07 }, { 0x05, 0xd8 },
100 { 0x04, 0x12 }, { 0x05, 0x00 },
101 { 0x04, 0x13 }, { 0x05, 0xff },
104 * On this demod, when the bit count reaches the count below,
105 * it collects the bit error count. The bit counters are initialized
106 * to 65535 here. This warrants that all of them will be quickly
107 * calculated when device gets locked. As TMCC is parsed, the values
108 * will be adjusted later in the driver's code.
110 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
111 { 0x50, 0xa7 }, { 0x51, 0x00 },
112 { 0x50, 0xa8 }, { 0x51, 0xff },
113 { 0x50, 0xa9 }, { 0x51, 0xff },
114 { 0x50, 0xaa }, { 0x51, 0x00 },
115 { 0x50, 0xab }, { 0x51, 0xff },
116 { 0x50, 0xac }, { 0x51, 0xff },
117 { 0x50, 0xad }, { 0x51, 0x00 },
118 { 0x50, 0xae }, { 0x51, 0xff },
119 { 0x50, 0xaf }, { 0x51, 0xff },
122 * On this demod, post BER counts blocks. When the count reaches the
123 * value below, it collects the block error count. The block counters
124 * are initialized to 127 here. This warrants that all of them will be
125 * quickly calculated when device gets locked. As TMCC is parsed, the
126 * values will be adjusted later in the driver's code.
128 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
129 { 0x50, 0xdc }, { 0x51, 0x00 },
130 { 0x50, 0xdd }, { 0x51, 0x7f },
131 { 0x50, 0xde }, { 0x51, 0x00 },
132 { 0x50, 0xdf }, { 0x51, 0x7f },
133 { 0x50, 0xe0 }, { 0x51, 0x00 },
134 { 0x50, 0xe1 }, { 0x51, 0x7f },
137 * On this demod, when the block count reaches the count below,
138 * it collects the block error count. The block counters are initialized
139 * to 127 here. This warrants that all of them will be quickly
140 * calculated when device gets locked. As TMCC is parsed, the values
141 * will be adjusted later in the driver's code.
143 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
144 { 0x50, 0xb2 }, { 0x51, 0x00 },
145 { 0x50, 0xb3 }, { 0x51, 0x7f },
146 { 0x50, 0xb4 }, { 0x51, 0x00 },
147 { 0x50, 0xb5 }, { 0x51, 0x7f },
148 { 0x50, 0xb6 }, { 0x51, 0x00 },
149 { 0x50, 0xb7 }, { 0x51, 0x7f },
151 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
152 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
153 { 0x45, 0x04 }, /* CN symbol 4 */
154 { 0x48, 0x04 }, /* CN manual mode */
155 { 0x50, 0xd5 }, { 0x51, 0x01 },
156 { 0x50, 0xd6 }, { 0x51, 0x1f },
157 { 0x50, 0xd2 }, { 0x51, 0x03 },
158 { 0x50, 0xd7 }, { 0x51, 0x3f },
160 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
161 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
162 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
163 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
164 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
165 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
166 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
167 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
168 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
169 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
170 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
171 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
172 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
173 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
174 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
175 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
176 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
177 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
178 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
179 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
180 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
181 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
182 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
183 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
184 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
185 { 0x50, 0x1e }, { 0x51, 0x5d },
186 { 0x50, 0x22 }, { 0x51, 0x00 },
187 { 0x50, 0x23 }, { 0x51, 0xc8 },
188 { 0x50, 0x24 }, { 0x51, 0x00 },
189 { 0x50, 0x25 }, { 0x51, 0xf0 },
190 { 0x50, 0x26 }, { 0x51, 0x00 },
191 { 0x50, 0x27 }, { 0x51, 0xc3 },
192 { 0x50, 0x39 }, { 0x51, 0x02 },
193 { 0x50, 0xd5 }, { 0x51, 0x01 },
197 static struct regdata mb86a20s_reset_reception[] = {
204 static struct regdata mb86a20s_per_ber_reset[] = {
205 { 0x53, 0x00 }, /* pre BER Counter reset */
208 { 0x5f, 0x00 }, /* post BER Counter reset */
211 { 0x50, 0xb1 }, /* PER Counter reset */
217 * I2C read/write functions and macros
220 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
221 u8 i2c_addr, u8 reg, u8 data)
223 u8 buf[] = { reg, data };
224 struct i2c_msg msg = {
225 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
229 rc = i2c_transfer(state->i2c, &msg, 1);
231 dev_err(&state->i2c->dev,
232 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
233 __func__, rc, reg, data);
240 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
241 u8 i2c_addr, struct regdata *rd, int size)
245 for (i = 0; i < size; i++) {
246 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
254 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
259 struct i2c_msg msg[] = {
260 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
261 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
264 rc = i2c_transfer(state->i2c, msg, 2);
267 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
269 return (rc < 0) ? rc : -EIO;
275 #define mb86a20s_readreg(state, reg) \
276 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
277 #define mb86a20s_writereg(state, reg, val) \
278 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
279 #define mb86a20s_writeregdata(state, regdata) \
280 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
281 regdata, ARRAY_SIZE(regdata))
284 * Ancillary internal routines (likely compiled inlined)
286 * The functions below assume that gateway lock has already obtained
289 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
291 struct mb86a20s_state *state = fe->demodulator_priv;
296 val = mb86a20s_readreg(state, 0x0a);
302 *status |= FE_HAS_SIGNAL;
305 *status |= FE_HAS_CARRIER;
308 *status |= FE_HAS_VITERBI;
311 *status |= FE_HAS_SYNC;
314 * Actually, on state S8, it starts receiving TS, but the TS
315 * output is only on normal state after the transition to S9.
318 *status |= FE_HAS_LOCK;
320 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
321 __func__, *status, val);
326 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
328 struct mb86a20s_state *state = fe->demodulator_priv;
329 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
331 unsigned rf_max, rf_min, rf;
333 if (state->get_strength_time &&
334 (!time_after(jiffies, state->get_strength_time)))
335 return c->strength.stat[0].uvalue;
337 /* Reset its value if an error happen */
338 c->strength.stat[0].uvalue = 0;
340 /* Does a binary search to get RF strength */
344 rf = (rf_max + rf_min) / 2;
345 rc = mb86a20s_writereg(state, 0x04, 0x1f);
348 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
351 rc = mb86a20s_writereg(state, 0x04, 0x20);
354 rc = mb86a20s_writereg(state, 0x05, rf);
358 rc = mb86a20s_readreg(state, 0x02);
362 rf_min = (rf_max + rf_min) / 2;
364 rf_max = (rf_max + rf_min) / 2;
365 if (rf_max - rf_min < 4) {
366 rf = (rf_max + rf_min) / 2;
368 /* Rescale it from 2^12 (4096) to 2^16 */
369 rf = rf << (16 - 12);
373 dev_dbg(&state->i2c->dev,
374 "%s: signal strength = %d (%d < RF=%d < %d)\n",
375 __func__, rf, rf_min, rf >> 4, rf_max);
376 c->strength.stat[0].uvalue = rf;
377 state->get_strength_time = jiffies +
378 msecs_to_jiffies(1000);
384 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
388 static unsigned char reg[] = {
389 [0] = 0x86, /* Layer A */
390 [1] = 0x8a, /* Layer B */
391 [2] = 0x8e, /* Layer C */
394 if (layer >= ARRAY_SIZE(reg))
396 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
399 rc = mb86a20s_readreg(state, 0x6e);
402 switch ((rc >> 4) & 0x07) {
416 static int mb86a20s_get_fec(struct mb86a20s_state *state,
421 static unsigned char reg[] = {
422 [0] = 0x87, /* Layer A */
423 [1] = 0x8b, /* Layer B */
424 [2] = 0x8f, /* Layer C */
427 if (layer >= ARRAY_SIZE(reg))
429 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
432 rc = mb86a20s_readreg(state, 0x6e);
435 switch ((rc >> 4) & 0x07) {
451 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
455 int interleaving[] = {
459 static unsigned char reg[] = {
460 [0] = 0x88, /* Layer A */
461 [1] = 0x8c, /* Layer B */
462 [2] = 0x90, /* Layer C */
465 if (layer >= ARRAY_SIZE(reg))
467 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
470 rc = mb86a20s_readreg(state, 0x6e);
474 return interleaving[(rc >> 4) & 0x07];
477 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
481 static unsigned char reg[] = {
482 [0] = 0x89, /* Layer A */
483 [1] = 0x8d, /* Layer B */
484 [2] = 0x91, /* Layer C */
487 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
489 if (layer >= ARRAY_SIZE(reg))
492 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
495 rc = mb86a20s_readreg(state, 0x6e);
498 count = (rc >> 4) & 0x0f;
500 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
505 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
507 struct mb86a20s_state *state = fe->demodulator_priv;
508 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
510 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
512 /* Fixed parameters */
513 c->delivery_system = SYS_ISDBT;
514 c->bandwidth_hz = 6000000;
516 /* Initialize values that will be later autodetected */
517 c->isdbt_layer_enabled = 0;
518 c->transmission_mode = TRANSMISSION_MODE_AUTO;
519 c->guard_interval = GUARD_INTERVAL_AUTO;
520 c->isdbt_sb_mode = 0;
521 c->isdbt_sb_segment_count = 0;
525 * Estimates the bit rate using the per-segment bit rate given by
526 * ABNT/NBR 15601 spec (table 4).
528 static u32 isdbt_rate[3][5][4] = {
530 { 280850, 312060, 330420, 340430 }, /* 1/2 */
531 { 374470, 416080, 440560, 453910 }, /* 2/3 */
532 { 421280, 468090, 495630, 510650 }, /* 3/4 */
533 { 468090, 520100, 550700, 567390 }, /* 5/6 */
534 { 491500, 546110, 578230, 595760 }, /* 7/8 */
536 { 561710, 624130, 660840, 680870 }, /* 1/2 */
537 { 748950, 832170, 881120, 907820 }, /* 2/3 */
538 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
539 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
540 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
542 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
543 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
544 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
545 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
546 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
550 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
551 u32 modulation, u32 forward_error_correction,
555 struct mb86a20s_state *state = fe->demodulator_priv;
560 * If modulation/fec/guard is not detected, the default is
561 * to consider the lowest bit rate, to avoid taking too long time
564 switch (modulation) {
578 switch (forward_error_correction) {
598 switch (guard_interval) {
600 case GUARD_INTERVAL_1_4:
603 case GUARD_INTERVAL_1_8:
606 case GUARD_INTERVAL_1_16:
609 case GUARD_INTERVAL_1_32:
614 /* Samples BER at BER_SAMPLING_RATE seconds */
615 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
617 /* Avoids sampling too quickly or to overflow the register */
620 else if (rate > (1 << 24) - 1)
621 rate = (1 << 24) - 1;
623 dev_dbg(&state->i2c->dev,
624 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
625 __func__, 'A' + layer,
626 segment * isdbt_rate[mod][fec][guard]/1000,
629 state->estimated_rate[layer] = rate;
632 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
634 struct mb86a20s_state *state = fe->demodulator_priv;
635 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
638 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
640 /* Reset frontend cache to default values */
641 mb86a20s_reset_frontend_cache(fe);
643 /* Check for partial reception */
644 rc = mb86a20s_writereg(state, 0x6d, 0x85);
647 rc = mb86a20s_readreg(state, 0x6e);
650 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
652 /* Get per-layer data */
654 for (layer = 0; layer < NUM_LAYERS; layer++) {
655 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
656 __func__, 'A' + layer);
658 rc = mb86a20s_get_segment_count(state, layer);
660 goto noperlayer_error;
661 if (rc >= 0 && rc < 14) {
662 c->layer[layer].segment_count = rc;
664 c->layer[layer].segment_count = 0;
665 state->estimated_rate[layer] = 0;
668 c->isdbt_layer_enabled |= 1 << layer;
669 rc = mb86a20s_get_modulation(state, layer);
671 goto noperlayer_error;
672 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
674 c->layer[layer].modulation = rc;
675 rc = mb86a20s_get_fec(state, layer);
677 goto noperlayer_error;
678 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
680 c->layer[layer].fec = rc;
681 rc = mb86a20s_get_interleaving(state, layer);
683 goto noperlayer_error;
684 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
686 c->layer[layer].interleaving = rc;
687 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
690 c->layer[layer].segment_count);
693 rc = mb86a20s_writereg(state, 0x6d, 0x84);
696 if ((rc & 0x60) == 0x20) {
697 c->isdbt_sb_mode = 1;
698 /* At least, one segment should exist */
699 if (!c->isdbt_sb_segment_count)
700 c->isdbt_sb_segment_count = 1;
703 /* Get transmission mode and guard interval */
704 rc = mb86a20s_readreg(state, 0x07);
707 c->transmission_mode = TRANSMISSION_MODE_AUTO;
708 if ((rc & 0x60) == 0x20) {
709 /* Only modes 2 and 3 are supported */
710 switch ((rc >> 2) & 0x03) {
712 c->transmission_mode = TRANSMISSION_MODE_4K;
715 c->transmission_mode = TRANSMISSION_MODE_8K;
719 c->guard_interval = GUARD_INTERVAL_AUTO;
721 /* Guard interval 1/32 is not supported */
724 c->guard_interval = GUARD_INTERVAL_1_4;
727 c->guard_interval = GUARD_INTERVAL_1_8;
730 c->guard_interval = GUARD_INTERVAL_1_16;
738 /* per-layer info is incomplete; discard all per-layer */
739 c->isdbt_layer_enabled = 0;
744 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
746 struct mb86a20s_state *state = fe->demodulator_priv;
747 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
750 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
752 /* Reset the counters, if the channel changed */
753 if (state->last_frequency != c->frequency) {
754 memset(&c->cnr, 0, sizeof(c->cnr));
755 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
756 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
757 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
758 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
759 memset(&c->block_error, 0, sizeof(c->block_error));
760 memset(&c->block_count, 0, sizeof(c->block_count));
762 state->last_frequency = c->frequency;
765 /* Clear status for most stats */
767 /* BER/PER counter reset */
768 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
772 /* CNR counter reset */
773 rc = mb86a20s_readreg(state, 0x45);
777 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
780 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
784 /* MER counter reset */
785 rc = mb86a20s_writereg(state, 0x50, 0x50);
788 rc = mb86a20s_readreg(state, 0x51);
792 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
795 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
801 dev_err(&state->i2c->dev,
802 "%s: Can't reset FE statistics (error %d).\n",
808 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
810 u32 *error, u32 *count)
812 struct mb86a20s_state *state = fe->demodulator_priv;
815 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
817 if (layer >= NUM_LAYERS)
820 /* Check if the BER measures are already available */
821 rc = mb86a20s_readreg(state, 0x54);
825 /* Check if data is available for that layer */
826 if (!(rc & (1 << layer))) {
827 dev_dbg(&state->i2c->dev,
828 "%s: preBER for layer %c is not available yet.\n",
829 __func__, 'A' + layer);
833 /* Read Bit Error Count */
834 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
838 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
842 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
847 dev_dbg(&state->i2c->dev,
848 "%s: bit error before Viterbi for layer %c: %d.\n",
849 __func__, 'A' + layer, *error);
852 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
855 rc = mb86a20s_readreg(state, 0x51);
859 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
862 rc = mb86a20s_readreg(state, 0x51);
866 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
869 rc = mb86a20s_readreg(state, 0x51);
874 dev_dbg(&state->i2c->dev,
875 "%s: bit count before Viterbi for layer %c: %d.\n",
876 __func__, 'A' + layer, *count);
880 * As we get TMCC data from the frontend, we can better estimate the
881 * BER bit counters, in order to do the BER measure during a longer
882 * time. Use those data, if available, to update the bit count
886 if (state->estimated_rate[layer]
887 && state->estimated_rate[layer] != *count) {
888 dev_dbg(&state->i2c->dev,
889 "%s: updating layer %c preBER counter to %d.\n",
890 __func__, 'A' + layer, state->estimated_rate[layer]);
892 /* Turn off BER before Viterbi */
893 rc = mb86a20s_writereg(state, 0x52, 0x00);
895 /* Update counter for this layer */
896 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
899 rc = mb86a20s_writereg(state, 0x51,
900 state->estimated_rate[layer] >> 16);
903 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
906 rc = mb86a20s_writereg(state, 0x51,
907 state->estimated_rate[layer] >> 8);
910 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
913 rc = mb86a20s_writereg(state, 0x51,
914 state->estimated_rate[layer]);
918 /* Turn on BER before Viterbi */
919 rc = mb86a20s_writereg(state, 0x52, 0x01);
921 /* Reset all preBER counters */
922 rc = mb86a20s_writereg(state, 0x53, 0x00);
925 rc = mb86a20s_writereg(state, 0x53, 0x07);
927 /* Reset counter to collect new data */
928 rc = mb86a20s_readreg(state, 0x53);
932 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
935 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
941 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
943 u32 *error, u32 *count)
945 struct mb86a20s_state *state = fe->demodulator_priv;
946 u32 counter, collect_rate;
949 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
951 if (layer >= NUM_LAYERS)
954 /* Check if the BER measures are already available */
955 rc = mb86a20s_readreg(state, 0x60);
959 /* Check if data is available for that layer */
960 if (!(rc & (1 << layer))) {
961 dev_dbg(&state->i2c->dev,
962 "%s: post BER for layer %c is not available yet.\n",
963 __func__, 'A' + layer);
967 /* Read Bit Error Count */
968 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
972 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
976 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
981 dev_dbg(&state->i2c->dev,
982 "%s: post bit error for layer %c: %d.\n",
983 __func__, 'A' + layer, *error);
986 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
989 rc = mb86a20s_readreg(state, 0x51);
993 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
996 rc = mb86a20s_readreg(state, 0x51);
1000 *count = counter * 204 * 8;
1002 dev_dbg(&state->i2c->dev,
1003 "%s: post bit count for layer %c: %d.\n",
1004 __func__, 'A' + layer, *count);
1007 * As we get TMCC data from the frontend, we can better estimate the
1008 * BER bit counters, in order to do the BER measure during a longer
1009 * time. Use those data, if available, to update the bit count
1013 if (!state->estimated_rate[layer])
1014 goto reset_measurement;
1016 collect_rate = state->estimated_rate[layer] / 204 / 8;
1017 if (collect_rate < 32)
1019 if (collect_rate > 65535)
1020 collect_rate = 65535;
1021 if (collect_rate != counter) {
1022 dev_dbg(&state->i2c->dev,
1023 "%s: updating postBER counter on layer %c to %d.\n",
1024 __func__, 'A' + layer, collect_rate);
1026 /* Turn off BER after Viterbi */
1027 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1029 /* Update counter for this layer */
1030 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1033 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1036 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1039 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1043 /* Turn on BER after Viterbi */
1044 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1046 /* Reset all preBER counters */
1047 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1050 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1056 /* Reset counter to collect new data */
1057 rc = mb86a20s_readreg(state, 0x5f);
1061 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1064 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1069 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1071 u32 *error, u32 *count)
1073 struct mb86a20s_state *state = fe->demodulator_priv;
1076 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1078 if (layer >= NUM_LAYERS)
1081 /* Check if the PER measures are already available */
1082 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1085 rc = mb86a20s_readreg(state, 0x51);
1089 /* Check if data is available for that layer */
1091 if (!(rc & (1 << layer))) {
1092 dev_dbg(&state->i2c->dev,
1093 "%s: block counts for layer %c aren't available yet.\n",
1094 __func__, 'A' + layer);
1098 /* Read Packet error Count */
1099 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1102 rc = mb86a20s_readreg(state, 0x51);
1106 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1109 rc = mb86a20s_readreg(state, 0x51);
1113 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1114 __func__, 'A' + layer, *error);
1116 /* Read Bit Count */
1117 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1120 rc = mb86a20s_readreg(state, 0x51);
1124 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1127 rc = mb86a20s_readreg(state, 0x51);
1132 dev_dbg(&state->i2c->dev,
1133 "%s: block count for layer %c: %d.\n",
1134 __func__, 'A' + layer, *count);
1137 * As we get TMCC data from the frontend, we can better estimate the
1138 * BER bit counters, in order to do the BER measure during a longer
1139 * time. Use those data, if available, to update the bit count
1143 if (!state->estimated_rate[layer])
1144 goto reset_measurement;
1146 collect_rate = state->estimated_rate[layer] / 204 / 8;
1147 if (collect_rate < 32)
1149 if (collect_rate > 65535)
1150 collect_rate = 65535;
1152 if (collect_rate != *count) {
1153 dev_dbg(&state->i2c->dev,
1154 "%s: updating PER counter on layer %c to %d.\n",
1155 __func__, 'A' + layer, collect_rate);
1157 /* Stop PER measurement */
1158 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1161 rc = mb86a20s_writereg(state, 0x51, 0x00);
1165 /* Update this layer's counter */
1166 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1169 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1172 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1175 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1179 /* start PER measurement */
1180 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1183 rc = mb86a20s_writereg(state, 0x51, 0x07);
1187 /* Reset all counters to collect new data */
1188 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1191 rc = mb86a20s_writereg(state, 0x51, 0x07);
1194 rc = mb86a20s_writereg(state, 0x51, 0x00);
1200 /* Reset counter to collect new data */
1201 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1204 rc = mb86a20s_readreg(state, 0x51);
1208 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1211 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1216 struct linear_segments {
1221 * All tables below return a dB/1000 measurement
1224 static const struct linear_segments cnr_to_db_table[] = {
1258 static const struct linear_segments cnr_64qam_table[] = {
1292 static const struct linear_segments cnr_16qam_table[] = {
1326 static const struct linear_segments cnr_qpsk_table[] = {
1360 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1367 if (value >= segments[0].x)
1368 return segments[0].y;
1369 if (value < segments[len-1].x)
1370 return segments[len-1].y;
1372 for (i = 1; i < len - 1; i++) {
1373 /* If value is identical, no need to interpolate */
1374 if (value == segments[i].x)
1375 return segments[i].y;
1376 if (value > segments[i].x)
1380 /* Linear interpolation between the two (x,y) points */
1381 dy = segments[i].y - segments[i - 1].y;
1382 dx = segments[i - 1].x - segments[i].x;
1383 tmp64 = value - segments[i].x;
1386 ret = segments[i].y - tmp64;
1391 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1393 struct mb86a20s_state *state = fe->demodulator_priv;
1394 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1395 u32 cnr_linear, cnr;
1398 /* Check if CNR is available */
1399 rc = mb86a20s_readreg(state, 0x45);
1404 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1410 rc = mb86a20s_readreg(state, 0x46);
1413 cnr_linear = rc << 8;
1415 rc = mb86a20s_readreg(state, 0x46);
1420 cnr = interpolate_value(cnr_linear,
1421 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1423 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1424 c->cnr.stat[0].svalue = cnr;
1426 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1427 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1429 /* CNR counter reset */
1430 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1433 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1438 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1440 struct mb86a20s_state *state = fe->demodulator_priv;
1441 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1444 const struct linear_segments *segs;
1447 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1449 /* Check if the measures are already available */
1450 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1453 rc = mb86a20s_readreg(state, 0x51);
1457 /* Check if data is available */
1459 dev_dbg(&state->i2c->dev,
1460 "%s: MER measures aren't available yet.\n", __func__);
1464 /* Read all layers */
1465 for (layer = 0; layer < NUM_LAYERS; layer++) {
1466 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1467 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1471 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1474 rc = mb86a20s_readreg(state, 0x51);
1478 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1481 rc = mb86a20s_readreg(state, 0x51);
1485 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1488 rc = mb86a20s_readreg(state, 0x51);
1493 switch (c->layer[layer].modulation) {
1496 segs = cnr_qpsk_table;
1497 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1500 segs = cnr_16qam_table;
1501 segs_len = ARRAY_SIZE(cnr_16qam_table);
1505 segs = cnr_64qam_table;
1506 segs_len = ARRAY_SIZE(cnr_64qam_table);
1509 cnr = interpolate_value(mer, segs, segs_len);
1511 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1512 c->cnr.stat[1 + layer].svalue = cnr;
1514 dev_dbg(&state->i2c->dev,
1515 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1516 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1520 /* Start a new MER measurement */
1521 /* MER counter reset */
1522 rc = mb86a20s_writereg(state, 0x50, 0x50);
1525 rc = mb86a20s_readreg(state, 0x51);
1530 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1533 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1540 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1542 struct mb86a20s_state *state = fe->demodulator_priv;
1543 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1546 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1548 /* Fill the length of each status counter */
1550 /* Only global stats */
1551 c->strength.len = 1;
1553 /* Per-layer stats - 3 layers + global */
1554 c->cnr.len = NUM_LAYERS + 1;
1555 c->pre_bit_error.len = NUM_LAYERS + 1;
1556 c->pre_bit_count.len = NUM_LAYERS + 1;
1557 c->post_bit_error.len = NUM_LAYERS + 1;
1558 c->post_bit_count.len = NUM_LAYERS + 1;
1559 c->block_error.len = NUM_LAYERS + 1;
1560 c->block_count.len = NUM_LAYERS + 1;
1562 /* Signal is always available */
1563 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1564 c->strength.stat[0].uvalue = 0;
1566 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1567 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1568 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1569 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1570 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1571 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1572 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1573 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1574 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1578 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1580 struct mb86a20s_state *state = fe->demodulator_priv;
1581 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1583 u32 bit_error = 0, bit_count = 0;
1584 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1585 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1586 u32 block_error = 0, block_count = 0;
1587 u32 t_block_error = 0, t_block_count = 0;
1588 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1591 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1593 mb86a20s_get_main_CNR(fe);
1595 /* Get per-layer stats */
1596 mb86a20s_get_blk_error_layer_CNR(fe);
1599 * At state 7, only CNR is available
1600 * For BER measures, state=9 is required
1601 * FIXME: we may get MER measures with state=8
1606 for (layer = 0; layer < NUM_LAYERS; layer++) {
1607 if (c->isdbt_layer_enabled & (1 << layer)) {
1608 /* Layer is active and has rc segments */
1611 /* Handle BER before vterbi */
1612 rc = mb86a20s_get_pre_ber(fe, layer,
1613 &bit_error, &bit_count);
1615 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1616 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1617 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1618 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1619 } else if (rc != -EBUSY) {
1621 * If an I/O error happened,
1622 * measures are now unavailable
1624 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1625 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1626 dev_err(&state->i2c->dev,
1627 "%s: Can't get BER for layer %c (error %d).\n",
1628 __func__, 'A' + layer, rc);
1630 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1633 /* Handle BER post vterbi */
1634 rc = mb86a20s_get_post_ber(fe, layer,
1635 &bit_error, &bit_count);
1637 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1638 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1639 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1640 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1641 } else if (rc != -EBUSY) {
1643 * If an I/O error happened,
1644 * measures are now unavailable
1646 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1647 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1648 dev_err(&state->i2c->dev,
1649 "%s: Can't get BER for layer %c (error %d).\n",
1650 __func__, 'A' + layer, rc);
1652 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1655 /* Handle Block errors for PER/UCB reports */
1656 rc = mb86a20s_get_blk_error(fe, layer,
1660 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1661 c->block_error.stat[1 + layer].uvalue += block_error;
1662 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1663 c->block_count.stat[1 + layer].uvalue += block_count;
1664 } else if (rc != -EBUSY) {
1666 * If an I/O error happened,
1667 * measures are now unavailable
1669 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1670 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1671 dev_err(&state->i2c->dev,
1672 "%s: Can't get PER for layer %c (error %d).\n",
1673 __func__, 'A' + layer, rc);
1676 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1679 /* Update total preBER */
1680 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1681 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1683 /* Update total postBER */
1684 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1685 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1687 /* Update total PER */
1688 t_block_error += c->block_error.stat[1 + layer].uvalue;
1689 t_block_count += c->block_count.stat[1 + layer].uvalue;
1694 * Start showing global count if at least one error count is
1697 if (pre_ber_layers) {
1699 * At least one per-layer BER measure was read. We can now
1700 * calculate the total BER
1702 * Total Bit Error/Count is calculated as the sum of the
1703 * bit errors on all active layers.
1705 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1706 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1707 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1708 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1710 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1711 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1715 * Start showing global count if at least one error count is
1718 if (post_ber_layers) {
1720 * At least one per-layer BER measure was read. We can now
1721 * calculate the total BER
1723 * Total Bit Error/Count is calculated as the sum of the
1724 * bit errors on all active layers.
1726 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1727 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1728 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1729 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1731 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1732 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1737 * At least one per-layer UCB measure was read. We can now
1738 * calculate the total UCB
1740 * Total block Error/Count is calculated as the sum of the
1741 * block errors on all active layers.
1743 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1744 c->block_error.stat[0].uvalue = t_block_error;
1745 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1746 c->block_count.stat[0].uvalue = t_block_count;
1748 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1749 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1756 * The functions below are called via DVB callbacks, so they need to
1757 * properly use the I2C gate control
1760 static int mb86a20s_initfe(struct dvb_frontend *fe)
1762 struct mb86a20s_state *state = fe->demodulator_priv;
1766 u8 regD5 = 1, reg71, reg09 = 0x3a;
1768 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1770 if (fe->ops.i2c_gate_ctrl)
1771 fe->ops.i2c_gate_ctrl(fe, 0);
1773 /* Initialize the frontend */
1774 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1778 if (!state->inversion)
1780 rc = mb86a20s_writereg(state, 0x09, reg09);
1787 rc = mb86a20s_writereg(state, 0x39, reg71);
1790 rc = mb86a20s_writereg(state, 0x71, state->bw);
1793 if (state->subchannel) {
1794 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1799 fclk = state->config->fclk;
1803 /* Adjust IF frequency to match tuner */
1804 if (fe->ops.tuner_ops.get_if_frequency)
1805 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1807 if (!state->if_freq)
1808 state->if_freq = 3300000;
1810 pll = (((u64)1) << 34) * state->if_freq;
1811 do_div(pll, 63 * fclk);
1812 pll = (1 << 25) - pll;
1813 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1816 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1819 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1822 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1825 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1826 __func__, fclk, state->if_freq, (long long)pll);
1828 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1829 pll = state->if_freq * 1677721600L;
1830 do_div(pll, 1628571429L);
1831 rc = mb86a20s_writereg(state, 0x28, 0x20);
1834 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1837 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1840 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1843 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1844 __func__, state->if_freq, (long long)pll);
1846 if (!state->config->is_serial)
1849 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1852 rc = mb86a20s_writereg(state, 0x51, regD5);
1856 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1862 if (fe->ops.i2c_gate_ctrl)
1863 fe->ops.i2c_gate_ctrl(fe, 1);
1866 state->need_init = true;
1867 dev_info(&state->i2c->dev,
1868 "mb86a20s: Init failed. Will try again later\n");
1870 state->need_init = false;
1871 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1876 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1878 struct mb86a20s_state *state = fe->demodulator_priv;
1879 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1881 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1883 if (!c->isdbt_layer_enabled)
1884 c->isdbt_layer_enabled = 7;
1886 if (c->isdbt_layer_enabled == 1)
1887 state->bw = MB86A20S_1SEG;
1888 else if (c->isdbt_partial_reception)
1889 state->bw = MB86A20S_13SEG_PARTIAL;
1891 state->bw = MB86A20S_13SEG;
1893 if (c->inversion == INVERSION_ON)
1894 state->inversion = true;
1896 state->inversion = false;
1898 if (!c->isdbt_sb_mode) {
1899 state->subchannel = 0;
1901 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1902 c->isdbt_sb_subchannel = 0;
1904 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1908 * Gate should already be opened, but it doesn't hurt to
1911 if (fe->ops.i2c_gate_ctrl)
1912 fe->ops.i2c_gate_ctrl(fe, 1);
1913 fe->ops.tuner_ops.set_params(fe);
1915 if (fe->ops.tuner_ops.get_if_frequency)
1916 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1919 * Make it more reliable: if, for some reason, the initial
1920 * device initialization doesn't happen, initialize it when
1921 * a SBTVD parameters are adjusted.
1923 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1924 * the agc callback logic is not called during DVB attach time,
1925 * causing mb86a20s to not be initialized with Kworld SBTVD.
1926 * So, this hack is needed, in order to make Kworld SBTVD to work.
1928 * It is also needed to change the IF after the initial init.
1930 * HACK: Always init the frontend when set_frontend is called:
1931 * it was noticed that, on some devices, it fails to lock on a
1932 * different channel. So, it is better to reset everything, even
1933 * wasting some time, than to loose channel lock.
1935 mb86a20s_initfe(fe);
1937 if (fe->ops.i2c_gate_ctrl)
1938 fe->ops.i2c_gate_ctrl(fe, 0);
1940 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1941 mb86a20s_reset_counters(fe);
1942 mb86a20s_stats_not_ready(fe);
1944 if (fe->ops.i2c_gate_ctrl)
1945 fe->ops.i2c_gate_ctrl(fe, 1);
1950 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1951 enum fe_status *status)
1953 struct mb86a20s_state *state = fe->demodulator_priv;
1956 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1958 if (fe->ops.i2c_gate_ctrl)
1959 fe->ops.i2c_gate_ctrl(fe, 0);
1962 status_nr = mb86a20s_read_status(fe, status);
1963 if (status_nr < 7) {
1964 mb86a20s_stats_not_ready(fe);
1965 mb86a20s_reset_frontend_cache(fe);
1967 if (status_nr < 0) {
1968 dev_err(&state->i2c->dev,
1969 "%s: Can't read frontend lock status\n", __func__);
1974 /* Get signal strength */
1975 rc = mb86a20s_read_signal_strength(fe);
1977 dev_err(&state->i2c->dev,
1978 "%s: Can't reset VBER registers.\n", __func__);
1979 mb86a20s_stats_not_ready(fe);
1980 mb86a20s_reset_frontend_cache(fe);
1982 rc = 0; /* Status is OK */
1986 if (status_nr >= 7) {
1988 rc = mb86a20s_get_frontend(fe);
1990 dev_err(&state->i2c->dev,
1991 "%s: Can't get FE TMCC data.\n", __func__);
1992 rc = 0; /* Status is OK */
1996 /* Get statistics */
1997 rc = mb86a20s_get_stats(fe, status_nr);
1998 if (rc < 0 && rc != -EBUSY) {
1999 dev_err(&state->i2c->dev,
2000 "%s: Can't get FE statistics.\n", __func__);
2004 rc = 0; /* Don't return EBUSY to userspace */
2009 mb86a20s_stats_not_ready(fe);
2012 if (fe->ops.i2c_gate_ctrl)
2013 fe->ops.i2c_gate_ctrl(fe, 1);
2018 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2021 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2024 *strength = c->strength.stat[0].uvalue;
2029 static int mb86a20s_tune(struct dvb_frontend *fe,
2031 unsigned int mode_flags,
2032 unsigned int *delay,
2033 enum fe_status *status)
2035 struct mb86a20s_state *state = fe->demodulator_priv;
2038 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2041 rc = mb86a20s_set_frontend(fe);
2043 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2044 mb86a20s_read_status_and_stats(fe, status);
2049 static void mb86a20s_release(struct dvb_frontend *fe)
2051 struct mb86a20s_state *state = fe->demodulator_priv;
2053 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2058 static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
2060 return DVBFE_ALGO_HW;
2063 static const struct dvb_frontend_ops mb86a20s_ops;
2065 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2066 struct i2c_adapter *i2c)
2068 struct mb86a20s_state *state;
2071 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2073 /* allocate memory for the internal state */
2074 state = kzalloc(sizeof(*state), GFP_KERNEL);
2078 /* setup the state */
2079 state->config = config;
2082 /* create dvb_frontend */
2083 memcpy(&state->frontend.ops, &mb86a20s_ops,
2084 sizeof(struct dvb_frontend_ops));
2085 state->frontend.demodulator_priv = state;
2087 /* Check if it is a mb86a20s frontend */
2088 rev = mb86a20s_readreg(state, 0);
2092 "Frontend revision %d is unknown - aborting.\n",
2097 dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n");
2098 return &state->frontend;
2100 EXPORT_SYMBOL(mb86a20s_attach);
2102 static const struct dvb_frontend_ops mb86a20s_ops = {
2103 .delsys = { SYS_ISDBT },
2104 /* Use dib8000 values per default */
2106 .name = "Fujitsu mb86A20s",
2107 .caps = FE_CAN_RECOVER |
2108 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2109 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2110 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2111 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2112 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2113 /* Actually, those values depend on the used tuner */
2114 .frequency_min_hz = 45 * MHz,
2115 .frequency_max_hz = 864 * MHz,
2116 .frequency_stepsize_hz = 62500,
2119 .release = mb86a20s_release,
2121 .init = mb86a20s_initfe,
2122 .set_frontend = mb86a20s_set_frontend,
2123 .read_status = mb86a20s_read_status_and_stats,
2124 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2125 .tune = mb86a20s_tune,
2126 .get_frontend_algo = mb86a20s_get_frontend_algo,
2129 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2130 MODULE_AUTHOR("Mauro Carvalho Chehab");
2131 MODULE_LICENSE("GPL");