2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
20 #include "dvb_frontend.h"
26 module_param(debug, int, 0644);
27 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
29 enum mb86a20s_bandwidth {
31 MB86A20S_13SEG_PARTIAL = 1,
36 u8 mb86a20s_subchannel[] = {
37 0xb0, 0xc0, 0xd0, 0xe0,
38 0xf0, 0x00, 0x10, 0x20,
41 struct mb86a20s_state {
42 struct i2c_adapter *i2c;
43 const struct mb86a20s_config *config;
46 struct dvb_frontend frontend;
49 enum mb86a20s_bandwidth bw;
53 u32 estimated_rate[NUM_LAYERS];
54 unsigned long get_strength_time;
64 #define BER_SAMPLING_RATE 1 /* Seconds */
67 * Initialization sequence: Use whatevere default values that PV SBTVD
68 * does on its initialisation, obtained via USB snoop
70 static struct regdata mb86a20s_init1[] = {
74 { 0x50, 0xd1 }, { 0x51, 0x20 },
77 static struct regdata mb86a20s_init2[] = {
78 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
82 { 0x04, 0x08 }, { 0x05, 0x03 },
83 { 0x04, 0x0e }, { 0x05, 0x00 },
84 { 0x04, 0x0f }, { 0x05, 0x37 },
85 { 0x04, 0x0b }, { 0x05, 0x78 },
86 { 0x04, 0x00 }, { 0x05, 0x00 },
87 { 0x04, 0x01 }, { 0x05, 0x1e },
88 { 0x04, 0x02 }, { 0x05, 0x07 },
89 { 0x04, 0x03 }, { 0x05, 0xd0 },
90 { 0x04, 0x09 }, { 0x05, 0x00 },
91 { 0x04, 0x0a }, { 0x05, 0xff },
92 { 0x04, 0x27 }, { 0x05, 0x00 },
93 { 0x04, 0x28 }, { 0x05, 0x00 },
94 { 0x04, 0x1e }, { 0x05, 0x00 },
95 { 0x04, 0x29 }, { 0x05, 0x64 },
96 { 0x04, 0x32 }, { 0x05, 0x02 },
97 { 0x04, 0x14 }, { 0x05, 0x02 },
98 { 0x04, 0x04 }, { 0x05, 0x00 },
99 { 0x04, 0x05 }, { 0x05, 0x22 },
100 { 0x04, 0x06 }, { 0x05, 0x0e },
101 { 0x04, 0x07 }, { 0x05, 0xd8 },
102 { 0x04, 0x12 }, { 0x05, 0x00 },
103 { 0x04, 0x13 }, { 0x05, 0xff },
104 { 0x04, 0x15 }, { 0x05, 0x4e },
105 { 0x04, 0x16 }, { 0x05, 0x20 },
108 * On this demod, when the bit count reaches the count below,
109 * it collects the bit error count. The bit counters are initialized
110 * to 65535 here. This warrants that all of them will be quickly
111 * calculated when device gets locked. As TMCC is parsed, the values
112 * will be adjusted later in the driver's code.
114 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
115 { 0x50, 0xa7 }, { 0x51, 0x00 },
116 { 0x50, 0xa8 }, { 0x51, 0xff },
117 { 0x50, 0xa9 }, { 0x51, 0xff },
118 { 0x50, 0xaa }, { 0x51, 0x00 },
119 { 0x50, 0xab }, { 0x51, 0xff },
120 { 0x50, 0xac }, { 0x51, 0xff },
121 { 0x50, 0xad }, { 0x51, 0x00 },
122 { 0x50, 0xae }, { 0x51, 0xff },
123 { 0x50, 0xaf }, { 0x51, 0xff },
126 * On this demod, post BER counts blocks. When the count reaches the
127 * value below, it collects the block error count. The block counters
128 * are initialized to 127 here. This warrants that all of them will be
129 * quickly calculated when device gets locked. As TMCC is parsed, the
130 * values will be adjusted later in the driver's code.
132 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
133 { 0x50, 0xdc }, { 0x51, 0x00 },
134 { 0x50, 0xdd }, { 0x51, 0x7f },
135 { 0x50, 0xde }, { 0x51, 0x00 },
136 { 0x50, 0xdf }, { 0x51, 0x7f },
137 { 0x50, 0xe0 }, { 0x51, 0x00 },
138 { 0x50, 0xe1 }, { 0x51, 0x7f },
141 * On this demod, when the block count reaches the count below,
142 * it collects the block error count. The block counters are initialized
143 * to 127 here. This warrants that all of them will be quickly
144 * calculated when device gets locked. As TMCC is parsed, the values
145 * will be adjusted later in the driver's code.
147 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
148 { 0x50, 0xb2 }, { 0x51, 0x00 },
149 { 0x50, 0xb3 }, { 0x51, 0x7f },
150 { 0x50, 0xb4 }, { 0x51, 0x00 },
151 { 0x50, 0xb5 }, { 0x51, 0x7f },
152 { 0x50, 0xb6 }, { 0x51, 0x00 },
153 { 0x50, 0xb7 }, { 0x51, 0x7f },
155 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
156 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
157 { 0x45, 0x04 }, /* CN symbol 4 */
158 { 0x48, 0x04 }, /* CN manual mode */
160 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
161 { 0x50, 0xd6 }, { 0x51, 0x1f },
162 { 0x50, 0xd2 }, { 0x51, 0x03 },
163 { 0x50, 0xd7 }, { 0x51, 0xbf },
164 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
165 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
167 { 0x04, 0x40 }, { 0x05, 0x00 },
168 { 0x28, 0x00 }, { 0x2b, 0x08 },
169 { 0x28, 0x05 }, { 0x2b, 0x00 },
171 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
172 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
173 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
174 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
175 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
176 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
177 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
178 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
179 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
180 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
181 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
182 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
183 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
184 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
185 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
186 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
187 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
188 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
189 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
190 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
191 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
192 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
193 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
194 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
195 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
196 { 0x50, 0x1e }, { 0x51, 0x5d },
197 { 0x50, 0x22 }, { 0x51, 0x00 },
198 { 0x50, 0x23 }, { 0x51, 0xc8 },
199 { 0x50, 0x24 }, { 0x51, 0x00 },
200 { 0x50, 0x25 }, { 0x51, 0xf0 },
201 { 0x50, 0x26 }, { 0x51, 0x00 },
202 { 0x50, 0x27 }, { 0x51, 0xc3 },
203 { 0x50, 0x39 }, { 0x51, 0x02 },
206 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
210 static struct regdata mb86a20s_reset_reception[] = {
217 static struct regdata mb86a20s_per_ber_reset[] = {
218 { 0x53, 0x00 }, /* pre BER Counter reset */
221 { 0x5f, 0x00 }, /* post BER Counter reset */
224 { 0x50, 0xb1 }, /* PER Counter reset */
230 * I2C read/write functions and macros
233 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
234 u8 i2c_addr, u8 reg, u8 data)
236 u8 buf[] = { reg, data };
237 struct i2c_msg msg = {
238 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
242 rc = i2c_transfer(state->i2c, &msg, 1);
244 dev_err(&state->i2c->dev,
245 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
246 __func__, rc, reg, data);
253 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
254 u8 i2c_addr, struct regdata *rd, int size)
258 for (i = 0; i < size; i++) {
259 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
267 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
272 struct i2c_msg msg[] = {
273 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
274 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
277 rc = i2c_transfer(state->i2c, msg, 2);
280 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
282 return (rc < 0) ? rc : -EIO;
288 #define mb86a20s_readreg(state, reg) \
289 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
290 #define mb86a20s_writereg(state, reg, val) \
291 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
292 #define mb86a20s_writeregdata(state, regdata) \
293 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
294 regdata, ARRAY_SIZE(regdata))
297 * Ancillary internal routines (likely compiled inlined)
299 * The functions below assume that gateway lock has already obtained
302 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
304 struct mb86a20s_state *state = fe->demodulator_priv;
309 val = mb86a20s_readreg(state, 0x0a) & 0xf;
314 *status |= FE_HAS_SIGNAL;
317 *status |= FE_HAS_CARRIER;
320 *status |= FE_HAS_VITERBI;
323 *status |= FE_HAS_SYNC;
325 if (val >= 8) /* Maybe 9? */
326 *status |= FE_HAS_LOCK;
328 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
329 __func__, *status, val);
334 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
336 struct mb86a20s_state *state = fe->demodulator_priv;
337 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
339 unsigned rf_max, rf_min, rf;
341 if (state->get_strength_time &&
342 (!time_after(jiffies, state->get_strength_time)))
343 return c->strength.stat[0].uvalue;
345 /* Reset its value if an error happen */
346 c->strength.stat[0].uvalue = 0;
348 /* Does a binary search to get RF strength */
352 rf = (rf_max + rf_min) / 2;
353 rc = mb86a20s_writereg(state, 0x04, 0x1f);
356 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
359 rc = mb86a20s_writereg(state, 0x04, 0x20);
362 rc = mb86a20s_writereg(state, 0x05, rf);
366 rc = mb86a20s_readreg(state, 0x02);
370 rf_min = (rf_max + rf_min) / 2;
372 rf_max = (rf_max + rf_min) / 2;
373 if (rf_max - rf_min < 4) {
374 rf = (rf_max + rf_min) / 2;
376 /* Rescale it from 2^12 (4096) to 2^16 */
377 rf = rf << (16 - 12);
381 dev_dbg(&state->i2c->dev,
382 "%s: signal strength = %d (%d < RF=%d < %d)\n",
383 __func__, rf, rf_min, rf >> 4, rf_max);
384 c->strength.stat[0].uvalue = rf;
385 state->get_strength_time = jiffies +
386 msecs_to_jiffies(1000);
392 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
396 static unsigned char reg[] = {
397 [0] = 0x86, /* Layer A */
398 [1] = 0x8a, /* Layer B */
399 [2] = 0x8e, /* Layer C */
402 if (layer >= ARRAY_SIZE(reg))
404 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
407 rc = mb86a20s_readreg(state, 0x6e);
410 switch ((rc >> 4) & 0x07) {
424 static int mb86a20s_get_fec(struct mb86a20s_state *state,
429 static unsigned char reg[] = {
430 [0] = 0x87, /* Layer A */
431 [1] = 0x8b, /* Layer B */
432 [2] = 0x8f, /* Layer C */
435 if (layer >= ARRAY_SIZE(reg))
437 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
440 rc = mb86a20s_readreg(state, 0x6e);
443 switch ((rc >> 4) & 0x07) {
459 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
464 static unsigned char reg[] = {
465 [0] = 0x88, /* Layer A */
466 [1] = 0x8c, /* Layer B */
467 [2] = 0x90, /* Layer C */
470 if (layer >= ARRAY_SIZE(reg))
472 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
475 rc = mb86a20s_readreg(state, 0x6e);
479 switch ((rc >> 4) & 0x07) {
481 return GUARD_INTERVAL_1_4;
483 return GUARD_INTERVAL_1_8;
485 return GUARD_INTERVAL_1_16;
487 return GUARD_INTERVAL_1_32;
491 return GUARD_INTERVAL_AUTO;
495 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
499 static unsigned char reg[] = {
500 [0] = 0x89, /* Layer A */
501 [1] = 0x8d, /* Layer B */
502 [2] = 0x91, /* Layer C */
505 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
507 if (layer >= ARRAY_SIZE(reg))
510 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
513 rc = mb86a20s_readreg(state, 0x6e);
516 count = (rc >> 4) & 0x0f;
518 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
523 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
525 struct mb86a20s_state *state = fe->demodulator_priv;
526 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
528 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
530 /* Fixed parameters */
531 c->delivery_system = SYS_ISDBT;
532 c->bandwidth_hz = 6000000;
534 /* Initialize values that will be later autodetected */
535 c->isdbt_layer_enabled = 0;
536 c->transmission_mode = TRANSMISSION_MODE_AUTO;
537 c->guard_interval = GUARD_INTERVAL_AUTO;
538 c->isdbt_sb_mode = 0;
539 c->isdbt_sb_segment_count = 0;
543 * Estimates the bit rate using the per-segment bit rate given by
544 * ABNT/NBR 15601 spec (table 4).
546 static u32 isdbt_rate[3][5][4] = {
548 { 280850, 312060, 330420, 340430 }, /* 1/2 */
549 { 374470, 416080, 440560, 453910 }, /* 2/3 */
550 { 421280, 468090, 495630, 510650 }, /* 3/4 */
551 { 468090, 520100, 550700, 567390 }, /* 5/6 */
552 { 491500, 546110, 578230, 595760 }, /* 7/8 */
554 { 561710, 624130, 660840, 680870 }, /* 1/2 */
555 { 748950, 832170, 881120, 907820 }, /* 2/3 */
556 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
557 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
558 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
560 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
561 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
562 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
563 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
564 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
568 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
569 u32 modulation, u32 forward_error_correction,
573 struct mb86a20s_state *state = fe->demodulator_priv;
578 * If modulation/fec/interleaving is not detected, the default is
579 * to consider the lowest bit rate, to avoid taking too long time
582 switch (modulation) {
596 switch (forward_error_correction) {
616 switch (interleaving) {
618 case GUARD_INTERVAL_1_4:
621 case GUARD_INTERVAL_1_8:
624 case GUARD_INTERVAL_1_16:
627 case GUARD_INTERVAL_1_32:
632 /* Samples BER at BER_SAMPLING_RATE seconds */
633 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
635 /* Avoids sampling too quickly or to overflow the register */
638 else if (rate > (1 << 24) - 1)
639 rate = (1 << 24) - 1;
641 dev_dbg(&state->i2c->dev,
642 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
643 __func__, 'A' + layer,
644 segment * isdbt_rate[mod][fec][guard]/1000,
647 state->estimated_rate[layer] = rate;
650 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
652 struct mb86a20s_state *state = fe->demodulator_priv;
653 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
656 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
658 /* Reset frontend cache to default values */
659 mb86a20s_reset_frontend_cache(fe);
661 /* Check for partial reception */
662 rc = mb86a20s_writereg(state, 0x6d, 0x85);
665 rc = mb86a20s_readreg(state, 0x6e);
668 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
670 /* Get per-layer data */
672 for (layer = 0; layer < NUM_LAYERS; layer++) {
673 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
674 __func__, 'A' + layer);
676 rc = mb86a20s_get_segment_count(state, layer);
678 goto noperlayer_error;
679 if (rc >= 0 && rc < 14) {
680 c->layer[layer].segment_count = rc;
682 c->layer[layer].segment_count = 0;
683 state->estimated_rate[layer] = 0;
686 c->isdbt_layer_enabled |= 1 << layer;
687 rc = mb86a20s_get_modulation(state, layer);
689 goto noperlayer_error;
690 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
692 c->layer[layer].modulation = rc;
693 rc = mb86a20s_get_fec(state, layer);
695 goto noperlayer_error;
696 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
698 c->layer[layer].fec = rc;
699 rc = mb86a20s_get_interleaving(state, layer);
701 goto noperlayer_error;
702 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
704 c->layer[layer].interleaving = rc;
705 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
707 c->layer[layer].interleaving,
708 c->layer[layer].segment_count);
711 rc = mb86a20s_writereg(state, 0x6d, 0x84);
714 if ((rc & 0x60) == 0x20) {
715 c->isdbt_sb_mode = 1;
716 /* At least, one segment should exist */
717 if (!c->isdbt_sb_segment_count)
718 c->isdbt_sb_segment_count = 1;
721 /* Get transmission mode and guard interval */
722 rc = mb86a20s_readreg(state, 0x07);
725 if ((rc & 0x60) == 0x20) {
726 switch (rc & 0x0c >> 2) {
728 c->transmission_mode = TRANSMISSION_MODE_2K;
731 c->transmission_mode = TRANSMISSION_MODE_4K;
734 c->transmission_mode = TRANSMISSION_MODE_8K;
741 c->guard_interval = GUARD_INTERVAL_1_4;
744 c->guard_interval = GUARD_INTERVAL_1_8;
747 c->guard_interval = GUARD_INTERVAL_1_16;
755 /* per-layer info is incomplete; discard all per-layer */
756 c->isdbt_layer_enabled = 0;
761 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
763 struct mb86a20s_state *state = fe->demodulator_priv;
764 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
767 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
769 /* Reset the counters, if the channel changed */
770 if (state->last_frequency != c->frequency) {
771 memset(&c->cnr, 0, sizeof(c->cnr));
772 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
773 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
774 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
775 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
776 memset(&c->block_error, 0, sizeof(c->block_error));
777 memset(&c->block_count, 0, sizeof(c->block_count));
779 state->last_frequency = c->frequency;
782 /* Clear status for most stats */
784 /* BER/PER counter reset */
785 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
789 /* CNR counter reset */
790 rc = mb86a20s_readreg(state, 0x45);
794 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
797 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
801 /* MER counter reset */
802 rc = mb86a20s_writereg(state, 0x50, 0x50);
805 rc = mb86a20s_readreg(state, 0x51);
809 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
812 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
818 dev_err(&state->i2c->dev,
819 "%s: Can't reset FE statistics (error %d).\n",
825 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
827 u32 *error, u32 *count)
829 struct mb86a20s_state *state = fe->demodulator_priv;
832 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
834 if (layer >= NUM_LAYERS)
837 /* Check if the BER measures are already available */
838 rc = mb86a20s_readreg(state, 0x54);
842 /* Check if data is available for that layer */
843 if (!(rc & (1 << layer))) {
844 dev_dbg(&state->i2c->dev,
845 "%s: preBER for layer %c is not available yet.\n",
846 __func__, 'A' + layer);
850 /* Read Bit Error Count */
851 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
855 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
859 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
864 dev_dbg(&state->i2c->dev,
865 "%s: bit error before Viterbi for layer %c: %d.\n",
866 __func__, 'A' + layer, *error);
869 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
872 rc = mb86a20s_readreg(state, 0x51);
876 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
879 rc = mb86a20s_readreg(state, 0x51);
883 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
886 rc = mb86a20s_readreg(state, 0x51);
891 dev_dbg(&state->i2c->dev,
892 "%s: bit count before Viterbi for layer %c: %d.\n",
893 __func__, 'A' + layer, *count);
897 * As we get TMCC data from the frontend, we can better estimate the
898 * BER bit counters, in order to do the BER measure during a longer
899 * time. Use those data, if available, to update the bit count
903 if (state->estimated_rate[layer]
904 && state->estimated_rate[layer] != *count) {
905 dev_dbg(&state->i2c->dev,
906 "%s: updating layer %c preBER counter to %d.\n",
907 __func__, 'A' + layer, state->estimated_rate[layer]);
909 /* Turn off BER before Viterbi */
910 rc = mb86a20s_writereg(state, 0x52, 0x00);
912 /* Update counter for this layer */
913 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
916 rc = mb86a20s_writereg(state, 0x51,
917 state->estimated_rate[layer] >> 16);
920 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
923 rc = mb86a20s_writereg(state, 0x51,
924 state->estimated_rate[layer] >> 8);
927 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
930 rc = mb86a20s_writereg(state, 0x51,
931 state->estimated_rate[layer]);
935 /* Turn on BER before Viterbi */
936 rc = mb86a20s_writereg(state, 0x52, 0x01);
938 /* Reset all preBER counters */
939 rc = mb86a20s_writereg(state, 0x53, 0x00);
942 rc = mb86a20s_writereg(state, 0x53, 0x07);
944 /* Reset counter to collect new data */
945 rc = mb86a20s_readreg(state, 0x53);
949 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
952 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
958 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
960 u32 *error, u32 *count)
962 struct mb86a20s_state *state = fe->demodulator_priv;
963 u32 counter, collect_rate;
966 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
968 if (layer >= NUM_LAYERS)
971 /* Check if the BER measures are already available */
972 rc = mb86a20s_readreg(state, 0x60);
976 /* Check if data is available for that layer */
977 if (!(rc & (1 << layer))) {
978 dev_dbg(&state->i2c->dev,
979 "%s: post BER for layer %c is not available yet.\n",
980 __func__, 'A' + layer);
984 /* Read Bit Error Count */
985 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
989 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
993 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
998 dev_dbg(&state->i2c->dev,
999 "%s: post bit error for layer %c: %d.\n",
1000 __func__, 'A' + layer, *error);
1002 /* Read Bit Count */
1003 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1006 rc = mb86a20s_readreg(state, 0x51);
1010 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1013 rc = mb86a20s_readreg(state, 0x51);
1017 *count = counter * 204 * 8;
1019 dev_dbg(&state->i2c->dev,
1020 "%s: post bit count for layer %c: %d.\n",
1021 __func__, 'A' + layer, *count);
1024 * As we get TMCC data from the frontend, we can better estimate the
1025 * BER bit counters, in order to do the BER measure during a longer
1026 * time. Use those data, if available, to update the bit count
1030 if (!state->estimated_rate[layer])
1031 goto reset_measurement;
1033 collect_rate = state->estimated_rate[layer] / 204 / 8;
1034 if (collect_rate < 32)
1036 if (collect_rate > 65535)
1037 collect_rate = 65535;
1038 if (collect_rate != counter) {
1039 dev_dbg(&state->i2c->dev,
1040 "%s: updating postBER counter on layer %c to %d.\n",
1041 __func__, 'A' + layer, collect_rate);
1043 /* Turn off BER after Viterbi */
1044 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1046 /* Update counter for this layer */
1047 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1050 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1053 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1056 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1060 /* Turn on BER after Viterbi */
1061 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1063 /* Reset all preBER counters */
1064 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1067 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1073 /* Reset counter to collect new data */
1074 rc = mb86a20s_readreg(state, 0x5f);
1078 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1081 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1086 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1088 u32 *error, u32 *count)
1090 struct mb86a20s_state *state = fe->demodulator_priv;
1093 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1095 if (layer >= NUM_LAYERS)
1098 /* Check if the PER measures are already available */
1099 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1102 rc = mb86a20s_readreg(state, 0x51);
1106 /* Check if data is available for that layer */
1108 if (!(rc & (1 << layer))) {
1109 dev_dbg(&state->i2c->dev,
1110 "%s: block counts for layer %c aren't available yet.\n",
1111 __func__, 'A' + layer);
1115 /* Read Packet error Count */
1116 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1119 rc = mb86a20s_readreg(state, 0x51);
1123 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1126 rc = mb86a20s_readreg(state, 0x51);
1130 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1131 __func__, 'A' + layer, *error);
1133 /* Read Bit Count */
1134 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1137 rc = mb86a20s_readreg(state, 0x51);
1141 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1144 rc = mb86a20s_readreg(state, 0x51);
1149 dev_dbg(&state->i2c->dev,
1150 "%s: block count for layer %c: %d.\n",
1151 __func__, 'A' + layer, *count);
1154 * As we get TMCC data from the frontend, we can better estimate the
1155 * BER bit counters, in order to do the BER measure during a longer
1156 * time. Use those data, if available, to update the bit count
1160 if (!state->estimated_rate[layer])
1161 goto reset_measurement;
1163 collect_rate = state->estimated_rate[layer] / 204 / 8;
1164 if (collect_rate < 32)
1166 if (collect_rate > 65535)
1167 collect_rate = 65535;
1169 if (collect_rate != *count) {
1170 dev_dbg(&state->i2c->dev,
1171 "%s: updating PER counter on layer %c to %d.\n",
1172 __func__, 'A' + layer, collect_rate);
1174 /* Stop PER measurement */
1175 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1178 rc = mb86a20s_writereg(state, 0x51, 0x00);
1182 /* Update this layer's counter */
1183 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1186 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1189 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1192 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1196 /* start PER measurement */
1197 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1200 rc = mb86a20s_writereg(state, 0x51, 0x07);
1204 /* Reset all counters to collect new data */
1205 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1208 rc = mb86a20s_writereg(state, 0x51, 0x07);
1211 rc = mb86a20s_writereg(state, 0x51, 0x00);
1217 /* Reset counter to collect new data */
1218 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1221 rc = mb86a20s_readreg(state, 0x51);
1225 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1228 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1233 struct linear_segments {
1238 * All tables below return a dB/1000 measurement
1241 static struct linear_segments cnr_to_db_table[] = {
1275 static struct linear_segments cnr_64qam_table[] = {
1309 static struct linear_segments cnr_16qam_table[] = {
1343 struct linear_segments cnr_qpsk_table[] = {
1377 static u32 interpolate_value(u32 value, struct linear_segments *segments,
1384 if (value >= segments[0].x)
1385 return segments[0].y;
1386 if (value < segments[len-1].x)
1387 return segments[len-1].y;
1389 for (i = 1; i < len - 1; i++) {
1390 /* If value is identical, no need to interpolate */
1391 if (value == segments[i].x)
1392 return segments[i].y;
1393 if (value > segments[i].x)
1397 /* Linear interpolation between the two (x,y) points */
1398 dy = segments[i].y - segments[i - 1].y;
1399 dx = segments[i - 1].x - segments[i].x;
1400 tmp64 = value - segments[i].x;
1403 ret = segments[i].y - tmp64;
1408 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1410 struct mb86a20s_state *state = fe->demodulator_priv;
1411 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1412 u32 cnr_linear, cnr;
1415 /* Check if CNR is available */
1416 rc = mb86a20s_readreg(state, 0x45);
1421 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1427 rc = mb86a20s_readreg(state, 0x46);
1430 cnr_linear = rc << 8;
1432 rc = mb86a20s_readreg(state, 0x46);
1437 cnr = interpolate_value(cnr_linear,
1438 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1440 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1441 c->cnr.stat[0].svalue = cnr;
1443 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1444 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1446 /* CNR counter reset */
1447 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1450 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1455 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1457 struct mb86a20s_state *state = fe->demodulator_priv;
1458 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1461 struct linear_segments *segs;
1464 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1466 /* Check if the measures are already available */
1467 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1470 rc = mb86a20s_readreg(state, 0x51);
1474 /* Check if data is available */
1476 dev_dbg(&state->i2c->dev,
1477 "%s: MER measures aren't available yet.\n", __func__);
1481 /* Read all layers */
1482 for (layer = 0; layer < NUM_LAYERS; layer++) {
1483 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1484 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1488 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1491 rc = mb86a20s_readreg(state, 0x51);
1495 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1498 rc = mb86a20s_readreg(state, 0x51);
1502 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1505 rc = mb86a20s_readreg(state, 0x51);
1510 switch (c->layer[layer].modulation) {
1513 segs = cnr_qpsk_table;
1514 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1517 segs = cnr_16qam_table;
1518 segs_len = ARRAY_SIZE(cnr_16qam_table);
1522 segs = cnr_64qam_table;
1523 segs_len = ARRAY_SIZE(cnr_64qam_table);
1526 cnr = interpolate_value(mer, segs, segs_len);
1528 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1529 c->cnr.stat[1 + layer].svalue = cnr;
1531 dev_dbg(&state->i2c->dev,
1532 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1533 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1537 /* Start a new MER measurement */
1538 /* MER counter reset */
1539 rc = mb86a20s_writereg(state, 0x50, 0x50);
1542 rc = mb86a20s_readreg(state, 0x51);
1547 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1550 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1557 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1559 struct mb86a20s_state *state = fe->demodulator_priv;
1560 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1563 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1565 /* Fill the length of each status counter */
1567 /* Only global stats */
1568 c->strength.len = 1;
1570 /* Per-layer stats - 3 layers + global */
1571 c->cnr.len = NUM_LAYERS + 1;
1572 c->pre_bit_error.len = NUM_LAYERS + 1;
1573 c->pre_bit_count.len = NUM_LAYERS + 1;
1574 c->post_bit_error.len = NUM_LAYERS + 1;
1575 c->post_bit_count.len = NUM_LAYERS + 1;
1576 c->block_error.len = NUM_LAYERS + 1;
1577 c->block_count.len = NUM_LAYERS + 1;
1579 /* Signal is always available */
1580 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1581 c->strength.stat[0].uvalue = 0;
1583 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1584 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1585 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1586 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1587 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1588 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1589 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1590 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1591 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1595 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1597 struct mb86a20s_state *state = fe->demodulator_priv;
1598 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1600 u32 bit_error = 0, bit_count = 0;
1601 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1602 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1603 u32 block_error = 0, block_count = 0;
1604 u32 t_block_error = 0, t_block_count = 0;
1605 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1608 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1610 mb86a20s_get_main_CNR(fe);
1612 /* Get per-layer stats */
1613 mb86a20s_get_blk_error_layer_CNR(fe);
1616 * At state 7, only CNR is available
1617 * For BER measures, state=9 is required
1618 * FIXME: we may get MER measures with state=8
1623 for (layer = 0; layer < NUM_LAYERS; layer++) {
1624 if (c->isdbt_layer_enabled & (1 << layer)) {
1625 /* Layer is active and has rc segments */
1628 /* Handle BER before vterbi */
1629 rc = mb86a20s_get_pre_ber(fe, layer,
1630 &bit_error, &bit_count);
1632 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1633 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1634 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1635 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1636 } else if (rc != -EBUSY) {
1638 * If an I/O error happened,
1639 * measures are now unavailable
1641 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1642 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1643 dev_err(&state->i2c->dev,
1644 "%s: Can't get BER for layer %c (error %d).\n",
1645 __func__, 'A' + layer, rc);
1647 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1650 /* Handle BER post vterbi */
1651 rc = mb86a20s_get_post_ber(fe, layer,
1652 &bit_error, &bit_count);
1654 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1655 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1656 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1657 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1658 } else if (rc != -EBUSY) {
1660 * If an I/O error happened,
1661 * measures are now unavailable
1663 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1664 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1665 dev_err(&state->i2c->dev,
1666 "%s: Can't get BER for layer %c (error %d).\n",
1667 __func__, 'A' + layer, rc);
1669 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1672 /* Handle Block errors for PER/UCB reports */
1673 rc = mb86a20s_get_blk_error(fe, layer,
1677 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1678 c->block_error.stat[1 + layer].uvalue += block_error;
1679 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1680 c->block_count.stat[1 + layer].uvalue += block_count;
1681 } else if (rc != -EBUSY) {
1683 * If an I/O error happened,
1684 * measures are now unavailable
1686 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1687 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1688 dev_err(&state->i2c->dev,
1689 "%s: Can't get PER for layer %c (error %d).\n",
1690 __func__, 'A' + layer, rc);
1693 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1696 /* Update total preBER */
1697 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1698 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1700 /* Update total postBER */
1701 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1702 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1704 /* Update total PER */
1705 t_block_error += c->block_error.stat[1 + layer].uvalue;
1706 t_block_count += c->block_count.stat[1 + layer].uvalue;
1711 * Start showing global count if at least one error count is
1714 if (pre_ber_layers) {
1716 * At least one per-layer BER measure was read. We can now
1717 * calculate the total BER
1719 * Total Bit Error/Count is calculated as the sum of the
1720 * bit errors on all active layers.
1722 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1723 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1724 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1725 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1727 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1728 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1732 * Start showing global count if at least one error count is
1735 if (post_ber_layers) {
1737 * At least one per-layer BER measure was read. We can now
1738 * calculate the total BER
1740 * Total Bit Error/Count is calculated as the sum of the
1741 * bit errors on all active layers.
1743 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1744 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1745 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1746 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1748 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1749 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1754 * At least one per-layer UCB measure was read. We can now
1755 * calculate the total UCB
1757 * Total block Error/Count is calculated as the sum of the
1758 * block errors on all active layers.
1760 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1761 c->block_error.stat[0].uvalue = t_block_error;
1762 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1763 c->block_count.stat[0].uvalue = t_block_count;
1765 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1766 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1773 * The functions below are called via DVB callbacks, so they need to
1774 * properly use the I2C gate control
1777 static int mb86a20s_initfe(struct dvb_frontend *fe)
1779 struct mb86a20s_state *state = fe->demodulator_priv;
1783 u8 regD5 = 1, reg71, reg09 = 0x3a;
1785 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1787 if (fe->ops.i2c_gate_ctrl)
1788 fe->ops.i2c_gate_ctrl(fe, 0);
1790 /* Initialize the frontend */
1791 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1795 if (!state->inversion)
1797 rc = mb86a20s_writereg(state, 0x09, reg09);
1804 rc = mb86a20s_writereg(state, 0x39, reg71);
1807 rc = mb86a20s_writereg(state, 0x71, state->bw);
1810 if (state->subchannel) {
1811 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1816 fclk = state->config->fclk;
1820 /* Adjust IF frequency to match tuner */
1821 if (fe->ops.tuner_ops.get_if_frequency)
1822 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1824 if (!state->if_freq)
1825 state->if_freq = 3300000;
1827 pll = (((u64)1) << 34) * state->if_freq;
1828 do_div(pll, 63 * fclk);
1829 pll = (1 << 25) - pll;
1830 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1833 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1836 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1839 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1842 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1843 __func__, fclk, state->if_freq, (long long)pll);
1845 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1846 pll = state->if_freq * 1677721600L;
1847 do_div(pll, 1628571429L);
1848 rc = mb86a20s_writereg(state, 0x28, 0x20);
1851 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1854 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1857 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1860 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1861 __func__, state->if_freq, (long long)pll);
1863 if (!state->config->is_serial) {
1866 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1869 rc = mb86a20s_writereg(state, 0x51, regD5);
1874 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1880 if (fe->ops.i2c_gate_ctrl)
1881 fe->ops.i2c_gate_ctrl(fe, 1);
1884 state->need_init = true;
1885 dev_info(&state->i2c->dev,
1886 "mb86a20s: Init failed. Will try again later\n");
1888 state->need_init = false;
1889 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1894 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1896 struct mb86a20s_state *state = fe->demodulator_priv;
1897 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1899 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1901 if (!c->isdbt_layer_enabled)
1902 c->isdbt_layer_enabled = 7;
1904 if (c->isdbt_layer_enabled == 1)
1905 state->bw = MB86A20S_1SEG;
1906 else if (c->isdbt_partial_reception)
1907 state->bw = MB86A20S_13SEG_PARTIAL;
1909 state->bw = MB86A20S_13SEG;
1911 if (c->inversion == INVERSION_ON)
1912 state->inversion = true;
1914 state->inversion = false;
1916 if (!c->isdbt_sb_mode) {
1917 state->subchannel = 0;
1919 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1920 c->isdbt_sb_subchannel = 0;
1922 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1926 * Gate should already be opened, but it doesn't hurt to
1929 if (fe->ops.i2c_gate_ctrl)
1930 fe->ops.i2c_gate_ctrl(fe, 1);
1931 fe->ops.tuner_ops.set_params(fe);
1933 if (fe->ops.tuner_ops.get_if_frequency)
1934 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1937 * Make it more reliable: if, for some reason, the initial
1938 * device initialization doesn't happen, initialize it when
1939 * a SBTVD parameters are adjusted.
1941 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1942 * the agc callback logic is not called during DVB attach time,
1943 * causing mb86a20s to not be initialized with Kworld SBTVD.
1944 * So, this hack is needed, in order to make Kworld SBTVD to work.
1946 * It is also needed to change the IF after the initial init.
1948 * HACK: Always init the frontend when set_frontend is called:
1949 * it was noticed that, on some devices, it fails to lock on a
1950 * different channel. So, it is better to reset everything, even
1951 * wasting some time, than to loose channel lock.
1953 mb86a20s_initfe(fe);
1955 if (fe->ops.i2c_gate_ctrl)
1956 fe->ops.i2c_gate_ctrl(fe, 0);
1958 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1959 mb86a20s_reset_counters(fe);
1960 mb86a20s_stats_not_ready(fe);
1962 if (fe->ops.i2c_gate_ctrl)
1963 fe->ops.i2c_gate_ctrl(fe, 1);
1968 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1969 fe_status_t *status)
1971 struct mb86a20s_state *state = fe->demodulator_priv;
1974 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1976 if (fe->ops.i2c_gate_ctrl)
1977 fe->ops.i2c_gate_ctrl(fe, 0);
1980 status_nr = mb86a20s_read_status(fe, status);
1981 if (status_nr < 7) {
1982 mb86a20s_stats_not_ready(fe);
1983 mb86a20s_reset_frontend_cache(fe);
1985 if (status_nr < 0) {
1986 dev_err(&state->i2c->dev,
1987 "%s: Can't read frontend lock status\n", __func__);
1991 /* Get signal strength */
1992 rc = mb86a20s_read_signal_strength(fe);
1994 dev_err(&state->i2c->dev,
1995 "%s: Can't reset VBER registers.\n", __func__);
1996 mb86a20s_stats_not_ready(fe);
1997 mb86a20s_reset_frontend_cache(fe);
1999 rc = 0; /* Status is OK */
2003 if (status_nr >= 7) {
2005 rc = mb86a20s_get_frontend(fe);
2007 dev_err(&state->i2c->dev,
2008 "%s: Can't get FE TMCC data.\n", __func__);
2009 rc = 0; /* Status is OK */
2013 /* Get statistics */
2014 rc = mb86a20s_get_stats(fe, status_nr);
2015 if (rc < 0 && rc != -EBUSY) {
2016 dev_err(&state->i2c->dev,
2017 "%s: Can't get FE statistics.\n", __func__);
2021 rc = 0; /* Don't return EBUSY to userspace */
2026 mb86a20s_stats_not_ready(fe);
2029 if (fe->ops.i2c_gate_ctrl)
2030 fe->ops.i2c_gate_ctrl(fe, 1);
2035 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2038 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2041 *strength = c->strength.stat[0].uvalue;
2046 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2049 * get_frontend is now handled together with other stats
2050 * retrival, when read_status() is called, as some statistics
2051 * will depend on the layers detection.
2056 static int mb86a20s_tune(struct dvb_frontend *fe,
2058 unsigned int mode_flags,
2059 unsigned int *delay,
2060 fe_status_t *status)
2062 struct mb86a20s_state *state = fe->demodulator_priv;
2065 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2068 rc = mb86a20s_set_frontend(fe);
2070 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2071 mb86a20s_read_status_and_stats(fe, status);
2076 static void mb86a20s_release(struct dvb_frontend *fe)
2078 struct mb86a20s_state *state = fe->demodulator_priv;
2080 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2085 static struct dvb_frontend_ops mb86a20s_ops;
2087 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2088 struct i2c_adapter *i2c)
2090 struct mb86a20s_state *state;
2093 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2095 /* allocate memory for the internal state */
2096 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
2097 if (state == NULL) {
2099 "%s: unable to allocate memory for state\n", __func__);
2103 /* setup the state */
2104 state->config = config;
2107 /* create dvb_frontend */
2108 memcpy(&state->frontend.ops, &mb86a20s_ops,
2109 sizeof(struct dvb_frontend_ops));
2110 state->frontend.demodulator_priv = state;
2112 /* Check if it is a mb86a20s frontend */
2113 rev = mb86a20s_readreg(state, 0);
2117 "Detected a Fujitsu mb86a20s frontend\n");
2120 "Frontend revision %d is unknown - aborting.\n",
2125 return &state->frontend;
2131 EXPORT_SYMBOL(mb86a20s_attach);
2133 static struct dvb_frontend_ops mb86a20s_ops = {
2134 .delsys = { SYS_ISDBT },
2135 /* Use dib8000 values per default */
2137 .name = "Fujitsu mb86A20s",
2138 .caps = FE_CAN_RECOVER |
2139 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2140 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2141 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2142 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2143 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2144 /* Actually, those values depend on the used tuner */
2145 .frequency_min = 45000000,
2146 .frequency_max = 864000000,
2147 .frequency_stepsize = 62500,
2150 .release = mb86a20s_release,
2152 .init = mb86a20s_initfe,
2153 .set_frontend = mb86a20s_set_frontend,
2154 .get_frontend = mb86a20s_get_frontend_dummy,
2155 .read_status = mb86a20s_read_status_and_stats,
2156 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2157 .tune = mb86a20s_tune,
2160 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2161 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2162 MODULE_LICENSE("GPL");