2 * Montage Technology M88DS3103/M88RS6000 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include "m88ds3103_priv.h"
19 static const struct dvb_frontend_ops m88ds3103_ops;
21 /* write single register with mask */
22 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
23 u8 reg, u8 mask, u8 val)
28 /* no need for read if whole reg is written */
30 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
39 return regmap_bulk_write(dev->regmap, reg, &val, 1);
42 /* write reg val table using reg addr auto increment */
43 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
44 const struct m88ds3103_reg_val *tab, int tab_len)
46 struct i2c_client *client = dev->client;
50 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
57 for (i = 0, j = 0; i < tab_len; i++, j++) {
60 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
61 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
62 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
72 dev_dbg(&client->dev, "failed=%d\n", ret);
77 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
79 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
81 struct m88ds3103_dev *dev = fe->demodulator_priv;
85 ret = regmap_read(dev->regmap, 0x3f, &tmp);
90 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
92 static int m88ds3103_read_status(struct dvb_frontend *fe,
93 enum fe_status *status)
95 struct m88ds3103_dev *dev = fe->demodulator_priv;
96 struct i2c_client *client = dev->client;
97 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
109 switch (c->delivery_system) {
111 ret = regmap_read(dev->regmap, 0xd1, &utmp);
115 if ((utmp & 0x07) == 0x07)
116 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
117 FE_HAS_VITERBI | FE_HAS_SYNC |
121 ret = regmap_read(dev->regmap, 0x0d, &utmp);
125 if ((utmp & 0x8f) == 0x8f)
126 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
127 FE_HAS_VITERBI | FE_HAS_SYNC |
131 dev_dbg(&client->dev, "invalid delivery_system\n");
136 dev->fe_status = *status;
137 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
140 if (dev->fe_status & FE_HAS_VITERBI) {
141 unsigned int cnr, noise, signal, noise_tot, signal_tot;
144 /* more iterations for more accurate estimation */
145 #define M88DS3103_SNR_ITERATIONS 3
147 switch (c->delivery_system) {
151 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
152 ret = regmap_read(dev->regmap, 0xff, &utmp);
159 /* use of single register limits max value to 15 dB */
160 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
161 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
163 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
169 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
170 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
174 noise = buf[1] << 6; /* [13:6] */
175 noise |= buf[0] & 0x3f; /* [5:0] */
177 signal = buf[2] * buf[2];
181 signal_tot += signal;
184 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
185 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
187 /* SNR(X) dB = 10 * log10(X) dB */
188 if (signal > noise) {
189 itmp = signal / noise;
190 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
194 dev_dbg(&client->dev, "invalid delivery_system\n");
200 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
201 c->cnr.stat[0].svalue = cnr;
203 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
206 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
210 if (dev->fe_status & FE_HAS_LOCK) {
211 unsigned int utmp, post_bit_error, post_bit_count;
213 switch (c->delivery_system) {
215 ret = regmap_write(dev->regmap, 0xf9, 0x04);
219 ret = regmap_read(dev->regmap, 0xf8, &utmp);
223 /* measurement ready? */
224 if (!(utmp & 0x10)) {
225 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
229 post_bit_error = buf[1] << 8 | buf[0] << 0;
230 post_bit_count = 0x800000;
231 dev->post_bit_error += post_bit_error;
232 dev->post_bit_count += post_bit_count;
233 dev->dvbv3_ber = post_bit_error;
235 /* restart measurement */
237 ret = regmap_write(dev->regmap, 0xf8, utmp);
243 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
247 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
251 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
255 post_bit_error = buf[1] << 8 | buf[0] << 0;
256 post_bit_count = 32 * utmp; /* TODO: FEC */
257 dev->post_bit_error += post_bit_error;
258 dev->post_bit_count += post_bit_count;
259 dev->dvbv3_ber = post_bit_error;
261 /* restart measurement */
262 ret = regmap_write(dev->regmap, 0xd1, 0x01);
266 ret = regmap_write(dev->regmap, 0xf9, 0x01);
270 ret = regmap_write(dev->regmap, 0xf9, 0x00);
274 ret = regmap_write(dev->regmap, 0xd1, 0x00);
280 dev_dbg(&client->dev, "invalid delivery_system\n");
285 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
286 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
287 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
288 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
290 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
291 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
296 dev_dbg(&client->dev, "failed=%d\n", ret);
300 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
302 struct m88ds3103_dev *dev = fe->demodulator_priv;
303 struct i2c_client *client = dev->client;
304 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
306 const struct m88ds3103_reg_val *init;
307 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
310 u32 tuner_frequency_khz, target_mclk;
313 dev_dbg(&client->dev,
314 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
315 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
316 c->inversion, c->pilot, c->rolloff);
324 ret = regmap_write(dev->regmap, 0x07, 0x80);
328 ret = regmap_write(dev->regmap, 0x07, 0x00);
332 /* Disable demod clock path */
333 if (dev->chip_id == M88RS6000_CHIP_ID) {
334 ret = regmap_write(dev->regmap, 0x06, 0xe0);
340 if (fe->ops.tuner_ops.set_params) {
341 ret = fe->ops.tuner_ops.set_params(fe);
346 if (fe->ops.tuner_ops.get_frequency) {
347 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz);
352 * Use nominal target frequency as tuner driver does not provide
353 * actual frequency used. Carrier offset calculation is not
356 tuner_frequency_khz = c->frequency;
359 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
360 if (dev->chip_id == M88RS6000_CHIP_ID) {
361 if (c->symbol_rate > 45010000)
362 dev->mclk = 110250000;
364 dev->mclk = 96000000;
366 if (c->delivery_system == SYS_DVBS)
367 target_mclk = 96000000;
369 target_mclk = 144000000;
371 /* Enable demod clock path */
372 ret = regmap_write(dev->regmap, 0x06, 0x00);
375 usleep_range(10000, 20000);
377 /* set M88DS3103 mclk and ts mclk. */
378 dev->mclk = 96000000;
380 switch (dev->cfg->ts_mode) {
381 case M88DS3103_TS_SERIAL:
382 case M88DS3103_TS_SERIAL_D7:
383 target_mclk = dev->cfg->ts_clk;
385 case M88DS3103_TS_PARALLEL:
386 case M88DS3103_TS_CI:
387 if (c->delivery_system == SYS_DVBS)
388 target_mclk = 96000000;
390 if (c->symbol_rate < 18000000)
391 target_mclk = 96000000;
392 else if (c->symbol_rate < 28000000)
393 target_mclk = 144000000;
395 target_mclk = 192000000;
399 dev_dbg(&client->dev, "invalid ts_mode\n");
404 switch (target_mclk) {
406 u8tmp1 = 0x02; /* 0b10 */
407 u8tmp2 = 0x01; /* 0b01 */
410 u8tmp1 = 0x00; /* 0b00 */
411 u8tmp2 = 0x01; /* 0b01 */
414 u8tmp1 = 0x03; /* 0b11 */
415 u8tmp2 = 0x00; /* 0b00 */
418 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
421 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
426 ret = regmap_write(dev->regmap, 0xb2, 0x01);
430 ret = regmap_write(dev->regmap, 0x00, 0x01);
434 switch (c->delivery_system) {
436 if (dev->chip_id == M88RS6000_CHIP_ID) {
437 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
438 init = m88rs6000_dvbs_init_reg_vals;
440 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
441 init = m88ds3103_dvbs_init_reg_vals;
445 if (dev->chip_id == M88RS6000_CHIP_ID) {
446 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
447 init = m88rs6000_dvbs2_init_reg_vals;
449 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
450 init = m88ds3103_dvbs2_init_reg_vals;
454 dev_dbg(&client->dev, "invalid delivery_system\n");
459 /* program init table */
460 if (c->delivery_system != dev->delivery_system) {
461 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
466 if (dev->chip_id == M88RS6000_CHIP_ID) {
467 if (c->delivery_system == SYS_DVBS2 &&
468 c->symbol_rate <= 5000000) {
469 ret = regmap_write(dev->regmap, 0xc0, 0x04);
475 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
479 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
482 ret = regmap_write(dev->regmap, 0xf1, 0x01);
485 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
490 switch (dev->cfg->ts_mode) {
491 case M88DS3103_TS_SERIAL:
495 case M88DS3103_TS_SERIAL_D7:
499 case M88DS3103_TS_PARALLEL:
502 case M88DS3103_TS_CI:
506 dev_dbg(&client->dev, "invalid ts_mode\n");
511 if (dev->cfg->ts_clk_pol)
515 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
519 switch (dev->cfg->ts_mode) {
520 case M88DS3103_TS_SERIAL:
521 case M88DS3103_TS_SERIAL_D7:
522 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
530 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
531 u8tmp1 = u16tmp / 2 - 1;
532 u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1;
535 dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n",
536 target_mclk, dev->cfg->ts_clk, u16tmp);
538 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
539 /* u8tmp2[5:0] => ea[5:0] */
540 u8tmp = (u8tmp1 >> 2) & 0x0f;
541 ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp);
544 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
545 ret = regmap_write(dev->regmap, 0xea, u8tmp);
549 if (c->symbol_rate <= 3000000)
551 else if (c->symbol_rate <= 10000000)
556 ret = regmap_write(dev->regmap, 0xc3, 0x08);
560 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
564 ret = regmap_write(dev->regmap, 0xc4, 0x08);
568 ret = regmap_write(dev->regmap, 0xc7, 0x00);
572 u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk);
573 buf[0] = (u16tmp >> 0) & 0xff;
574 buf[1] = (u16tmp >> 8) & 0xff;
575 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
579 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
583 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
587 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
591 dev_dbg(&client->dev, "carrier offset=%d\n",
592 (tuner_frequency_khz - c->frequency));
594 /* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */
595 s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency);
596 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000);
597 buf[0] = (s32tmp >> 0) & 0xff;
598 buf[1] = (s32tmp >> 8) & 0xff;
599 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
603 ret = regmap_write(dev->regmap, 0x00, 0x00);
607 ret = regmap_write(dev->regmap, 0xb2, 0x00);
611 dev->delivery_system = c->delivery_system;
615 dev_dbg(&client->dev, "failed=%d\n", ret);
619 static int m88ds3103_init(struct dvb_frontend *fe)
621 struct m88ds3103_dev *dev = fe->demodulator_priv;
622 struct i2c_client *client = dev->client;
623 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
626 const struct firmware *firmware;
629 dev_dbg(&client->dev, "\n");
631 /* set cold state by default */
634 /* wake up device from sleep */
635 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
638 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
641 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
645 /* firmware status */
646 ret = regmap_read(dev->regmap, 0xb9, &utmp);
650 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
655 /* global reset, global diseqc reset, golbal fec reset */
656 ret = regmap_write(dev->regmap, 0x07, 0xe0);
659 ret = regmap_write(dev->regmap, 0x07, 0x00);
663 /* cold state - try to download firmware */
664 dev_info(&client->dev, "found a '%s' in cold state\n",
665 m88ds3103_ops.info.name);
667 if (dev->chip_id == M88RS6000_CHIP_ID)
668 name = M88RS6000_FIRMWARE;
670 name = M88DS3103_FIRMWARE;
671 /* request the firmware, this will block and timeout */
672 ret = request_firmware(&firmware, name, &client->dev);
674 dev_err(&client->dev, "firmware file '%s' not found\n", name);
678 dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
680 ret = regmap_write(dev->regmap, 0xb2, 0x01);
682 goto err_release_firmware;
684 for (rem = firmware->size; rem > 0; rem -= (dev->cfg->i2c_wr_max - 1)) {
685 len = min(dev->cfg->i2c_wr_max - 1, rem);
686 ret = regmap_bulk_write(dev->regmap, 0xb0,
687 &firmware->data[firmware->size - rem],
690 dev_err(&client->dev, "firmware download failed %d\n",
692 goto err_release_firmware;
696 ret = regmap_write(dev->regmap, 0xb2, 0x00);
698 goto err_release_firmware;
700 release_firmware(firmware);
702 ret = regmap_read(dev->regmap, 0xb9, &utmp);
708 dev_info(&client->dev, "firmware did not run\n");
712 dev_info(&client->dev, "found a '%s' in warm state\n",
713 m88ds3103_ops.info.name);
714 dev_info(&client->dev, "firmware version: %X.%X\n",
715 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
721 /* init stats here in order signal app which stats are supported */
723 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
724 c->post_bit_error.len = 1;
725 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
726 c->post_bit_count.len = 1;
727 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
730 err_release_firmware:
731 release_firmware(firmware);
733 dev_dbg(&client->dev, "failed=%d\n", ret);
737 static int m88ds3103_sleep(struct dvb_frontend *fe)
739 struct m88ds3103_dev *dev = fe->demodulator_priv;
740 struct i2c_client *client = dev->client;
744 dev_dbg(&client->dev, "\n");
747 dev->delivery_system = SYS_UNDEFINED;
750 if (dev->chip_id == M88RS6000_CHIP_ID)
754 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
759 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
762 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
765 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
771 dev_dbg(&client->dev, "failed=%d\n", ret);
775 static int m88ds3103_get_frontend(struct dvb_frontend *fe,
776 struct dtv_frontend_properties *c)
778 struct m88ds3103_dev *dev = fe->demodulator_priv;
779 struct i2c_client *client = dev->client;
783 dev_dbg(&client->dev, "\n");
785 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
790 switch (c->delivery_system) {
792 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
796 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
800 switch ((buf[0] >> 2) & 0x01) {
802 c->inversion = INVERSION_OFF;
805 c->inversion = INVERSION_ON;
809 switch ((buf[1] >> 5) & 0x07) {
811 c->fec_inner = FEC_7_8;
814 c->fec_inner = FEC_5_6;
817 c->fec_inner = FEC_3_4;
820 c->fec_inner = FEC_2_3;
823 c->fec_inner = FEC_1_2;
826 dev_dbg(&client->dev, "invalid fec_inner\n");
829 c->modulation = QPSK;
833 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
837 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
841 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
845 switch ((buf[0] >> 0) & 0x0f) {
847 c->fec_inner = FEC_2_5;
850 c->fec_inner = FEC_1_2;
853 c->fec_inner = FEC_3_5;
856 c->fec_inner = FEC_2_3;
859 c->fec_inner = FEC_3_4;
862 c->fec_inner = FEC_4_5;
865 c->fec_inner = FEC_5_6;
868 c->fec_inner = FEC_8_9;
871 c->fec_inner = FEC_9_10;
874 dev_dbg(&client->dev, "invalid fec_inner\n");
877 switch ((buf[0] >> 5) & 0x01) {
879 c->pilot = PILOT_OFF;
886 switch ((buf[0] >> 6) & 0x07) {
888 c->modulation = QPSK;
891 c->modulation = PSK_8;
894 c->modulation = APSK_16;
897 c->modulation = APSK_32;
900 dev_dbg(&client->dev, "invalid modulation\n");
903 switch ((buf[1] >> 7) & 0x01) {
905 c->inversion = INVERSION_OFF;
908 c->inversion = INVERSION_ON;
912 switch ((buf[2] >> 0) & 0x03) {
914 c->rolloff = ROLLOFF_35;
917 c->rolloff = ROLLOFF_25;
920 c->rolloff = ROLLOFF_20;
923 dev_dbg(&client->dev, "invalid rolloff\n");
927 dev_dbg(&client->dev, "invalid delivery_system\n");
932 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
936 c->symbol_rate = DIV_ROUND_CLOSEST_ULL((u64)(buf[1] << 8 | buf[0] << 0) * dev->mclk, 0x10000);
940 dev_dbg(&client->dev, "failed=%d\n", ret);
944 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
946 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
948 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
949 *snr = div_s64(c->cnr.stat[0].svalue, 100);
956 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
958 struct m88ds3103_dev *dev = fe->demodulator_priv;
960 *ber = dev->dvbv3_ber;
965 static int m88ds3103_set_tone(struct dvb_frontend *fe,
966 enum fe_sec_tone_mode fe_sec_tone_mode)
968 struct m88ds3103_dev *dev = fe->demodulator_priv;
969 struct i2c_client *client = dev->client;
971 unsigned int utmp, tone, reg_a1_mask;
973 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
980 switch (fe_sec_tone_mode) {
990 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
995 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
996 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1001 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
1007 dev_dbg(&client->dev, "failed=%d\n", ret);
1011 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1012 enum fe_sec_voltage fe_sec_voltage)
1014 struct m88ds3103_dev *dev = fe->demodulator_priv;
1015 struct i2c_client *client = dev->client;
1018 bool voltage_sel, voltage_dis;
1020 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1027 switch (fe_sec_voltage) {
1028 case SEC_VOLTAGE_18:
1030 voltage_dis = false;
1032 case SEC_VOLTAGE_13:
1033 voltage_sel = false;
1034 voltage_dis = false;
1036 case SEC_VOLTAGE_OFF:
1037 voltage_sel = false;
1041 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1046 /* output pin polarity */
1047 voltage_sel ^= dev->cfg->lnb_hv_pol;
1048 voltage_dis ^= dev->cfg->lnb_en_pol;
1050 utmp = voltage_dis << 1 | voltage_sel << 0;
1051 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1057 dev_dbg(&client->dev, "failed=%d\n", ret);
1061 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1062 struct dvb_diseqc_master_cmd *diseqc_cmd)
1064 struct m88ds3103_dev *dev = fe->demodulator_priv;
1065 struct i2c_client *client = dev->client;
1068 unsigned long timeout;
1070 dev_dbg(&client->dev, "msg=%*ph\n",
1071 diseqc_cmd->msg_len, diseqc_cmd->msg);
1078 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1083 utmp = dev->cfg->envelope_mode << 5;
1084 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1088 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1089 diseqc_cmd->msg_len);
1093 ret = regmap_write(dev->regmap, 0xa1,
1094 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1098 /* wait DiSEqC TX ready */
1099 #define SEND_MASTER_CMD_TIMEOUT 120
1100 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1102 /* DiSEqC message period is 13.5 ms per byte */
1103 utmp = diseqc_cmd->msg_len * 13500;
1104 usleep_range(utmp - 4000, utmp);
1106 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1107 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1110 utmp = (utmp >> 6) & 0x1;
1114 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1115 jiffies_to_msecs(jiffies) -
1116 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1118 dev_dbg(&client->dev, "diseqc tx timeout\n");
1120 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1125 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1136 dev_dbg(&client->dev, "failed=%d\n", ret);
1140 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1141 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1143 struct m88ds3103_dev *dev = fe->demodulator_priv;
1144 struct i2c_client *client = dev->client;
1146 unsigned int utmp, burst;
1147 unsigned long timeout;
1149 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1156 utmp = dev->cfg->envelope_mode << 5;
1157 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1161 switch (fe_sec_mini_cmd) {
1169 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1174 ret = regmap_write(dev->regmap, 0xa1, burst);
1178 /* wait DiSEqC TX ready */
1179 #define SEND_BURST_TIMEOUT 40
1180 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1182 /* DiSEqC ToneBurst period is 12.5 ms */
1183 usleep_range(8500, 12500);
1185 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1186 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1189 utmp = (utmp >> 6) & 0x1;
1193 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1194 jiffies_to_msecs(jiffies) -
1195 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1197 dev_dbg(&client->dev, "diseqc tx timeout\n");
1199 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1204 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1215 dev_dbg(&client->dev, "failed=%d\n", ret);
1219 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1220 struct dvb_frontend_tune_settings *s)
1222 s->min_delay_ms = 3000;
1227 static void m88ds3103_release(struct dvb_frontend *fe)
1229 struct m88ds3103_dev *dev = fe->demodulator_priv;
1230 struct i2c_client *client = dev->client;
1232 i2c_unregister_device(client);
1235 static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
1237 struct m88ds3103_dev *dev = i2c_mux_priv(muxc);
1238 struct i2c_client *client = dev->client;
1240 struct i2c_msg msg = {
1241 .addr = client->addr,
1247 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1248 ret = __i2c_transfer(client->adapter, &msg, 1);
1250 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1260 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1261 * proper I2C client for legacy media attach binding.
1262 * New users must use I2C client binding directly!
1264 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1265 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1267 struct i2c_client *client;
1268 struct i2c_board_info board_info;
1269 struct m88ds3103_platform_data pdata;
1271 pdata.clk = cfg->clock;
1272 pdata.i2c_wr_max = cfg->i2c_wr_max;
1273 pdata.ts_mode = cfg->ts_mode;
1274 pdata.ts_clk = cfg->ts_clk;
1275 pdata.ts_clk_pol = cfg->ts_clk_pol;
1276 pdata.spec_inv = cfg->spec_inv;
1277 pdata.agc = cfg->agc;
1278 pdata.agc_inv = cfg->agc_inv;
1279 pdata.clk_out = cfg->clock_out;
1280 pdata.envelope_mode = cfg->envelope_mode;
1281 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1282 pdata.lnb_en_pol = cfg->lnb_en_pol;
1283 pdata.attach_in_use = true;
1285 memset(&board_info, 0, sizeof(board_info));
1286 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1287 board_info.addr = cfg->i2c_addr;
1288 board_info.platform_data = &pdata;
1289 client = i2c_new_device(i2c, &board_info);
1290 if (!client || !client->dev.driver)
1293 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1294 return pdata.get_dvb_frontend(client);
1296 EXPORT_SYMBOL(m88ds3103_attach);
1298 static const struct dvb_frontend_ops m88ds3103_ops = {
1299 .delsys = {SYS_DVBS, SYS_DVBS2},
1301 .name = "Montage Technology M88DS3103",
1302 .frequency_min = 950000,
1303 .frequency_max = 2150000,
1304 .frequency_tolerance = 5000,
1305 .symbol_rate_min = 1000000,
1306 .symbol_rate_max = 45000000,
1307 .caps = FE_CAN_INVERSION_AUTO |
1319 FE_CAN_2G_MODULATION
1322 .release = m88ds3103_release,
1324 .get_tune_settings = m88ds3103_get_tune_settings,
1326 .init = m88ds3103_init,
1327 .sleep = m88ds3103_sleep,
1329 .set_frontend = m88ds3103_set_frontend,
1330 .get_frontend = m88ds3103_get_frontend,
1332 .read_status = m88ds3103_read_status,
1333 .read_snr = m88ds3103_read_snr,
1334 .read_ber = m88ds3103_read_ber,
1336 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1337 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1339 .set_tone = m88ds3103_set_tone,
1340 .set_voltage = m88ds3103_set_voltage,
1343 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1345 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1347 dev_dbg(&client->dev, "\n");
1352 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1354 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1356 dev_dbg(&client->dev, "\n");
1358 return dev->muxc->adapter[0];
1361 static int m88ds3103_probe(struct i2c_client *client,
1362 const struct i2c_device_id *id)
1364 struct m88ds3103_dev *dev;
1365 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1369 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1375 dev->client = client;
1376 dev->config.clock = pdata->clk;
1377 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1378 dev->config.ts_mode = pdata->ts_mode;
1379 dev->config.ts_clk = pdata->ts_clk * 1000;
1380 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1381 dev->config.spec_inv = pdata->spec_inv;
1382 dev->config.agc_inv = pdata->agc_inv;
1383 dev->config.clock_out = pdata->clk_out;
1384 dev->config.envelope_mode = pdata->envelope_mode;
1385 dev->config.agc = pdata->agc;
1386 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1387 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1388 dev->cfg = &dev->config;
1390 dev->regmap_config.reg_bits = 8,
1391 dev->regmap_config.val_bits = 8,
1392 dev->regmap_config.lock_arg = dev,
1393 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1394 if (IS_ERR(dev->regmap)) {
1395 ret = PTR_ERR(dev->regmap);
1399 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1400 ret = regmap_read(dev->regmap, 0x00, &utmp);
1404 dev->chip_id = utmp >> 1;
1405 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1407 switch (dev->chip_id) {
1408 case M88RS6000_CHIP_ID:
1409 case M88DS3103_CHIP_ID:
1415 switch (dev->cfg->clock_out) {
1416 case M88DS3103_CLOCK_OUT_DISABLED:
1419 case M88DS3103_CLOCK_OUT_ENABLED:
1422 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1430 if (!pdata->ts_clk) {
1435 /* 0x29 register is defined differently for m88rs6000. */
1436 /* set internal tuner address to 0x21 */
1437 if (dev->chip_id == M88RS6000_CHIP_ID)
1440 ret = regmap_write(dev->regmap, 0x29, utmp);
1445 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1448 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1451 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1455 /* create mux i2c adapter for tuner */
1456 dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
1457 m88ds3103_select, NULL);
1462 dev->muxc->priv = dev;
1463 ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1467 /* create dvb_frontend */
1468 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1469 if (dev->chip_id == M88RS6000_CHIP_ID)
1470 strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1471 sizeof(dev->fe.ops.info.name));
1472 if (!pdata->attach_in_use)
1473 dev->fe.ops.release = NULL;
1474 dev->fe.demodulator_priv = dev;
1475 i2c_set_clientdata(client, dev);
1477 /* setup callbacks */
1478 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1479 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1484 dev_dbg(&client->dev, "failed=%d\n", ret);
1488 static int m88ds3103_remove(struct i2c_client *client)
1490 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1492 dev_dbg(&client->dev, "\n");
1494 i2c_mux_del_adapters(dev->muxc);
1500 static const struct i2c_device_id m88ds3103_id_table[] = {
1504 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1506 static struct i2c_driver m88ds3103_driver = {
1508 .name = "m88ds3103",
1509 .suppress_bind_attrs = true,
1511 .probe = m88ds3103_probe,
1512 .remove = m88ds3103_remove,
1513 .id_table = m88ds3103_id_table,
1516 module_i2c_driver(m88ds3103_driver);
1518 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1519 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1520 MODULE_LICENSE("GPL");
1521 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1522 MODULE_FIRMWARE(M88RS6000_FIRMWARE);