1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Montage Technology M88DS3103/M88RS6000 demodulator driver
5 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
8 #include "m88ds3103_priv.h"
10 static const struct dvb_frontend_ops m88ds3103_ops;
12 /* write single register with mask */
13 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
14 u8 reg, u8 mask, u8 val)
19 /* no need for read if whole reg is written */
21 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
30 return regmap_bulk_write(dev->regmap, reg, &val, 1);
33 /* write reg val table using reg addr auto increment */
34 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
35 const struct m88ds3103_reg_val *tab, int tab_len)
37 struct i2c_client *client = dev->client;
41 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
48 for (i = 0, j = 0; i < tab_len; i++, j++) {
51 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
52 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
53 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
63 dev_dbg(&client->dev, "failed=%d\n", ret);
68 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
70 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
72 struct m88ds3103_dev *dev = fe->demodulator_priv;
76 ret = regmap_read(dev->regmap, 0x3f, &tmp);
81 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
83 static int m88ds3103_read_status(struct dvb_frontend *fe,
84 enum fe_status *status)
86 struct m88ds3103_dev *dev = fe->demodulator_priv;
87 struct i2c_client *client = dev->client;
88 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
100 switch (c->delivery_system) {
102 ret = regmap_read(dev->regmap, 0xd1, &utmp);
106 if ((utmp & 0x07) == 0x07)
107 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
108 FE_HAS_VITERBI | FE_HAS_SYNC |
112 ret = regmap_read(dev->regmap, 0x0d, &utmp);
116 if ((utmp & 0x8f) == 0x8f)
117 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
118 FE_HAS_VITERBI | FE_HAS_SYNC |
122 dev_dbg(&client->dev, "invalid delivery_system\n");
127 dev->fe_status = *status;
128 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
131 if (dev->fe_status & FE_HAS_VITERBI) {
132 unsigned int cnr, noise, signal, noise_tot, signal_tot;
135 /* more iterations for more accurate estimation */
136 #define M88DS3103_SNR_ITERATIONS 3
138 switch (c->delivery_system) {
142 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
143 ret = regmap_read(dev->regmap, 0xff, &utmp);
150 /* use of single register limits max value to 15 dB */
151 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
152 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
154 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
160 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
161 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
165 noise = buf[1] << 6; /* [13:6] */
166 noise |= buf[0] & 0x3f; /* [5:0] */
168 signal = buf[2] * buf[2];
172 signal_tot += signal;
175 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
176 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
178 /* SNR(X) dB = 10 * log10(X) dB */
179 if (signal > noise) {
180 itmp = signal / noise;
181 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
185 dev_dbg(&client->dev, "invalid delivery_system\n");
191 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
192 c->cnr.stat[0].svalue = cnr;
194 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
197 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
201 if (dev->fe_status & FE_HAS_LOCK) {
202 unsigned int utmp, post_bit_error, post_bit_count;
204 switch (c->delivery_system) {
206 ret = regmap_write(dev->regmap, 0xf9, 0x04);
210 ret = regmap_read(dev->regmap, 0xf8, &utmp);
214 /* measurement ready? */
215 if (!(utmp & 0x10)) {
216 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
220 post_bit_error = buf[1] << 8 | buf[0] << 0;
221 post_bit_count = 0x800000;
222 dev->post_bit_error += post_bit_error;
223 dev->post_bit_count += post_bit_count;
224 dev->dvbv3_ber = post_bit_error;
226 /* restart measurement */
228 ret = regmap_write(dev->regmap, 0xf8, utmp);
234 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
238 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
242 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
246 post_bit_error = buf[1] << 8 | buf[0] << 0;
247 post_bit_count = 32 * utmp; /* TODO: FEC */
248 dev->post_bit_error += post_bit_error;
249 dev->post_bit_count += post_bit_count;
250 dev->dvbv3_ber = post_bit_error;
252 /* restart measurement */
253 ret = regmap_write(dev->regmap, 0xd1, 0x01);
257 ret = regmap_write(dev->regmap, 0xf9, 0x01);
261 ret = regmap_write(dev->regmap, 0xf9, 0x00);
265 ret = regmap_write(dev->regmap, 0xd1, 0x00);
271 dev_dbg(&client->dev, "invalid delivery_system\n");
276 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
277 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
278 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
279 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
281 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
282 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
287 dev_dbg(&client->dev, "failed=%d\n", ret);
291 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
293 struct m88ds3103_dev *dev = fe->demodulator_priv;
294 struct i2c_client *client = dev->client;
295 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
297 const struct m88ds3103_reg_val *init;
298 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
301 u32 tuner_frequency_khz, target_mclk;
303 static const struct reg_sequence reset_buf[] = {
304 {0x07, 0x80}, {0x07, 0x00}
307 dev_dbg(&client->dev,
308 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
309 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
310 c->inversion, c->pilot, c->rolloff);
318 ret = regmap_multi_reg_write(dev->regmap, reset_buf, 2);
322 /* Disable demod clock path */
323 if (dev->chip_id == M88RS6000_CHIP_ID) {
324 ret = regmap_write(dev->regmap, 0x06, 0xe0);
330 if (fe->ops.tuner_ops.set_params) {
331 ret = fe->ops.tuner_ops.set_params(fe);
336 if (fe->ops.tuner_ops.get_frequency) {
337 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz);
342 * Use nominal target frequency as tuner driver does not provide
343 * actual frequency used. Carrier offset calculation is not
346 tuner_frequency_khz = c->frequency;
349 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
350 if (dev->chip_id == M88RS6000_CHIP_ID) {
351 if (c->symbol_rate > 45010000)
352 dev->mclk = 110250000;
354 dev->mclk = 96000000;
356 if (c->delivery_system == SYS_DVBS)
357 target_mclk = 96000000;
359 target_mclk = 144000000;
361 /* Enable demod clock path */
362 ret = regmap_write(dev->regmap, 0x06, 0x00);
365 usleep_range(10000, 20000);
367 /* set M88DS3103 mclk and ts mclk. */
368 dev->mclk = 96000000;
370 switch (dev->cfg->ts_mode) {
371 case M88DS3103_TS_SERIAL:
372 case M88DS3103_TS_SERIAL_D7:
373 target_mclk = dev->cfg->ts_clk;
375 case M88DS3103_TS_PARALLEL:
376 case M88DS3103_TS_CI:
377 if (c->delivery_system == SYS_DVBS)
378 target_mclk = 96000000;
380 if (c->symbol_rate < 18000000)
381 target_mclk = 96000000;
382 else if (c->symbol_rate < 28000000)
383 target_mclk = 144000000;
385 target_mclk = 192000000;
389 dev_dbg(&client->dev, "invalid ts_mode\n");
394 switch (target_mclk) {
396 u8tmp1 = 0x02; /* 0b10 */
397 u8tmp2 = 0x01; /* 0b01 */
400 u8tmp1 = 0x00; /* 0b00 */
401 u8tmp2 = 0x01; /* 0b01 */
404 u8tmp1 = 0x03; /* 0b11 */
405 u8tmp2 = 0x00; /* 0b00 */
408 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
411 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
416 ret = regmap_write(dev->regmap, 0xb2, 0x01);
420 ret = regmap_write(dev->regmap, 0x00, 0x01);
424 switch (c->delivery_system) {
426 if (dev->chip_id == M88RS6000_CHIP_ID) {
427 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
428 init = m88rs6000_dvbs_init_reg_vals;
430 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
431 init = m88ds3103_dvbs_init_reg_vals;
435 if (dev->chip_id == M88RS6000_CHIP_ID) {
436 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
437 init = m88rs6000_dvbs2_init_reg_vals;
439 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
440 init = m88ds3103_dvbs2_init_reg_vals;
444 dev_dbg(&client->dev, "invalid delivery_system\n");
449 /* program init table */
450 if (c->delivery_system != dev->delivery_system) {
451 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
456 if (dev->chip_id == M88RS6000_CHIP_ID) {
457 if (c->delivery_system == SYS_DVBS2 &&
458 c->symbol_rate <= 5000000) {
459 ret = regmap_write(dev->regmap, 0xc0, 0x04);
465 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
469 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
472 ret = regmap_write(dev->regmap, 0xf1, 0x01);
475 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
480 switch (dev->cfg->ts_mode) {
481 case M88DS3103_TS_SERIAL:
485 case M88DS3103_TS_SERIAL_D7:
489 case M88DS3103_TS_PARALLEL:
492 case M88DS3103_TS_CI:
496 dev_dbg(&client->dev, "invalid ts_mode\n");
501 if (dev->cfg->ts_clk_pol)
505 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
509 switch (dev->cfg->ts_mode) {
510 case M88DS3103_TS_SERIAL:
511 case M88DS3103_TS_SERIAL_D7:
512 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
520 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
521 u8tmp1 = u16tmp / 2 - 1;
522 u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1;
525 dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n",
526 target_mclk, dev->cfg->ts_clk, u16tmp);
528 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
529 /* u8tmp2[5:0] => ea[5:0] */
530 u8tmp = (u8tmp1 >> 2) & 0x0f;
531 ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp);
534 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
535 ret = regmap_write(dev->regmap, 0xea, u8tmp);
539 if (c->symbol_rate <= 3000000)
541 else if (c->symbol_rate <= 10000000)
546 ret = regmap_write(dev->regmap, 0xc3, 0x08);
550 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
554 ret = regmap_write(dev->regmap, 0xc4, 0x08);
558 ret = regmap_write(dev->regmap, 0xc7, 0x00);
562 u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk);
563 buf[0] = (u16tmp >> 0) & 0xff;
564 buf[1] = (u16tmp >> 8) & 0xff;
565 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
569 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
573 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
577 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
581 dev_dbg(&client->dev, "carrier offset=%d\n",
582 (tuner_frequency_khz - c->frequency));
584 /* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */
585 s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency);
586 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000);
587 buf[0] = (s32tmp >> 0) & 0xff;
588 buf[1] = (s32tmp >> 8) & 0xff;
589 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
593 ret = regmap_write(dev->regmap, 0x00, 0x00);
597 ret = regmap_write(dev->regmap, 0xb2, 0x00);
601 dev->delivery_system = c->delivery_system;
605 dev_dbg(&client->dev, "failed=%d\n", ret);
609 static int m88ds3103_init(struct dvb_frontend *fe)
611 struct m88ds3103_dev *dev = fe->demodulator_priv;
612 struct i2c_client *client = dev->client;
613 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
616 const struct firmware *firmware;
619 dev_dbg(&client->dev, "\n");
621 /* set cold state by default */
624 /* wake up device from sleep */
625 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
628 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
631 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
635 /* firmware status */
636 ret = regmap_read(dev->regmap, 0xb9, &utmp);
640 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
645 /* global reset, global diseqc reset, golbal fec reset */
646 ret = regmap_write(dev->regmap, 0x07, 0xe0);
649 ret = regmap_write(dev->regmap, 0x07, 0x00);
653 /* cold state - try to download firmware */
654 dev_info(&client->dev, "found a '%s' in cold state\n",
655 m88ds3103_ops.info.name);
657 if (dev->chip_id == M88RS6000_CHIP_ID)
658 name = M88RS6000_FIRMWARE;
660 name = M88DS3103_FIRMWARE;
661 /* request the firmware, this will block and timeout */
662 ret = request_firmware(&firmware, name, &client->dev);
664 dev_err(&client->dev, "firmware file '%s' not found\n", name);
668 dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
670 ret = regmap_write(dev->regmap, 0xb2, 0x01);
672 goto err_release_firmware;
674 for (rem = firmware->size; rem > 0; rem -= (dev->cfg->i2c_wr_max - 1)) {
675 len = min(dev->cfg->i2c_wr_max - 1, rem);
676 ret = regmap_bulk_write(dev->regmap, 0xb0,
677 &firmware->data[firmware->size - rem],
680 dev_err(&client->dev, "firmware download failed %d\n",
682 goto err_release_firmware;
686 ret = regmap_write(dev->regmap, 0xb2, 0x00);
688 goto err_release_firmware;
690 release_firmware(firmware);
692 ret = regmap_read(dev->regmap, 0xb9, &utmp);
698 dev_info(&client->dev, "firmware did not run\n");
702 dev_info(&client->dev, "found a '%s' in warm state\n",
703 m88ds3103_ops.info.name);
704 dev_info(&client->dev, "firmware version: %X.%X\n",
705 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
711 /* init stats here in order signal app which stats are supported */
713 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
714 c->post_bit_error.len = 1;
715 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
716 c->post_bit_count.len = 1;
717 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
720 err_release_firmware:
721 release_firmware(firmware);
723 dev_dbg(&client->dev, "failed=%d\n", ret);
727 static int m88ds3103_sleep(struct dvb_frontend *fe)
729 struct m88ds3103_dev *dev = fe->demodulator_priv;
730 struct i2c_client *client = dev->client;
734 dev_dbg(&client->dev, "\n");
737 dev->delivery_system = SYS_UNDEFINED;
740 if (dev->chip_id == M88RS6000_CHIP_ID)
744 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
749 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
752 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
755 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
761 dev_dbg(&client->dev, "failed=%d\n", ret);
765 static int m88ds3103_get_frontend(struct dvb_frontend *fe,
766 struct dtv_frontend_properties *c)
768 struct m88ds3103_dev *dev = fe->demodulator_priv;
769 struct i2c_client *client = dev->client;
773 dev_dbg(&client->dev, "\n");
775 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
780 switch (c->delivery_system) {
782 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
786 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
790 switch ((buf[0] >> 2) & 0x01) {
792 c->inversion = INVERSION_OFF;
795 c->inversion = INVERSION_ON;
799 switch ((buf[1] >> 5) & 0x07) {
801 c->fec_inner = FEC_7_8;
804 c->fec_inner = FEC_5_6;
807 c->fec_inner = FEC_3_4;
810 c->fec_inner = FEC_2_3;
813 c->fec_inner = FEC_1_2;
816 dev_dbg(&client->dev, "invalid fec_inner\n");
819 c->modulation = QPSK;
823 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
827 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
831 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
835 switch ((buf[0] >> 0) & 0x0f) {
837 c->fec_inner = FEC_2_5;
840 c->fec_inner = FEC_1_2;
843 c->fec_inner = FEC_3_5;
846 c->fec_inner = FEC_2_3;
849 c->fec_inner = FEC_3_4;
852 c->fec_inner = FEC_4_5;
855 c->fec_inner = FEC_5_6;
858 c->fec_inner = FEC_8_9;
861 c->fec_inner = FEC_9_10;
864 dev_dbg(&client->dev, "invalid fec_inner\n");
867 switch ((buf[0] >> 5) & 0x01) {
869 c->pilot = PILOT_OFF;
876 switch ((buf[0] >> 6) & 0x07) {
878 c->modulation = QPSK;
881 c->modulation = PSK_8;
884 c->modulation = APSK_16;
887 c->modulation = APSK_32;
890 dev_dbg(&client->dev, "invalid modulation\n");
893 switch ((buf[1] >> 7) & 0x01) {
895 c->inversion = INVERSION_OFF;
898 c->inversion = INVERSION_ON;
902 switch ((buf[2] >> 0) & 0x03) {
904 c->rolloff = ROLLOFF_35;
907 c->rolloff = ROLLOFF_25;
910 c->rolloff = ROLLOFF_20;
913 dev_dbg(&client->dev, "invalid rolloff\n");
917 dev_dbg(&client->dev, "invalid delivery_system\n");
922 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
926 c->symbol_rate = DIV_ROUND_CLOSEST_ULL((u64)(buf[1] << 8 | buf[0] << 0) * dev->mclk, 0x10000);
930 dev_dbg(&client->dev, "failed=%d\n", ret);
934 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
936 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
938 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
939 *snr = div_s64(c->cnr.stat[0].svalue, 100);
946 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
948 struct m88ds3103_dev *dev = fe->demodulator_priv;
950 *ber = dev->dvbv3_ber;
955 static int m88ds3103_set_tone(struct dvb_frontend *fe,
956 enum fe_sec_tone_mode fe_sec_tone_mode)
958 struct m88ds3103_dev *dev = fe->demodulator_priv;
959 struct i2c_client *client = dev->client;
961 unsigned int utmp, tone, reg_a1_mask;
963 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
970 switch (fe_sec_tone_mode) {
980 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
985 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
986 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
991 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
997 dev_dbg(&client->dev, "failed=%d\n", ret);
1001 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1002 enum fe_sec_voltage fe_sec_voltage)
1004 struct m88ds3103_dev *dev = fe->demodulator_priv;
1005 struct i2c_client *client = dev->client;
1008 bool voltage_sel, voltage_dis;
1010 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1017 switch (fe_sec_voltage) {
1018 case SEC_VOLTAGE_18:
1020 voltage_dis = false;
1022 case SEC_VOLTAGE_13:
1023 voltage_sel = false;
1024 voltage_dis = false;
1026 case SEC_VOLTAGE_OFF:
1027 voltage_sel = false;
1031 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1036 /* output pin polarity */
1037 voltage_sel ^= dev->cfg->lnb_hv_pol;
1038 voltage_dis ^= dev->cfg->lnb_en_pol;
1040 utmp = voltage_dis << 1 | voltage_sel << 0;
1041 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1047 dev_dbg(&client->dev, "failed=%d\n", ret);
1051 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1052 struct dvb_diseqc_master_cmd *diseqc_cmd)
1054 struct m88ds3103_dev *dev = fe->demodulator_priv;
1055 struct i2c_client *client = dev->client;
1058 unsigned long timeout;
1060 dev_dbg(&client->dev, "msg=%*ph\n",
1061 diseqc_cmd->msg_len, diseqc_cmd->msg);
1068 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1073 utmp = dev->cfg->envelope_mode << 5;
1074 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1078 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1079 diseqc_cmd->msg_len);
1083 ret = regmap_write(dev->regmap, 0xa1,
1084 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1088 /* wait DiSEqC TX ready */
1089 #define SEND_MASTER_CMD_TIMEOUT 120
1090 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1092 /* DiSEqC message period is 13.5 ms per byte */
1093 utmp = diseqc_cmd->msg_len * 13500;
1094 usleep_range(utmp - 4000, utmp);
1096 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1097 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1100 utmp = (utmp >> 6) & 0x1;
1104 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1105 jiffies_to_msecs(jiffies) -
1106 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1108 dev_dbg(&client->dev, "diseqc tx timeout\n");
1110 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1115 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1126 dev_dbg(&client->dev, "failed=%d\n", ret);
1130 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1131 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1133 struct m88ds3103_dev *dev = fe->demodulator_priv;
1134 struct i2c_client *client = dev->client;
1136 unsigned int utmp, burst;
1137 unsigned long timeout;
1139 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1146 utmp = dev->cfg->envelope_mode << 5;
1147 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1151 switch (fe_sec_mini_cmd) {
1159 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1164 ret = regmap_write(dev->regmap, 0xa1, burst);
1168 /* wait DiSEqC TX ready */
1169 #define SEND_BURST_TIMEOUT 40
1170 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1172 /* DiSEqC ToneBurst period is 12.5 ms */
1173 usleep_range(8500, 12500);
1175 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1176 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1179 utmp = (utmp >> 6) & 0x1;
1183 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1184 jiffies_to_msecs(jiffies) -
1185 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1187 dev_dbg(&client->dev, "diseqc tx timeout\n");
1189 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1194 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1205 dev_dbg(&client->dev, "failed=%d\n", ret);
1209 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1210 struct dvb_frontend_tune_settings *s)
1212 s->min_delay_ms = 3000;
1217 static void m88ds3103_release(struct dvb_frontend *fe)
1219 struct m88ds3103_dev *dev = fe->demodulator_priv;
1220 struct i2c_client *client = dev->client;
1222 i2c_unregister_device(client);
1225 static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
1227 struct m88ds3103_dev *dev = i2c_mux_priv(muxc);
1228 struct i2c_client *client = dev->client;
1230 struct i2c_msg msg = {
1231 .addr = client->addr,
1237 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1238 ret = __i2c_transfer(client->adapter, &msg, 1);
1240 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1250 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1251 * proper I2C client for legacy media attach binding.
1252 * New users must use I2C client binding directly!
1254 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1255 struct i2c_adapter *i2c,
1256 struct i2c_adapter **tuner_i2c_adapter)
1258 struct i2c_client *client;
1259 struct i2c_board_info board_info;
1260 struct m88ds3103_platform_data pdata = {};
1262 pdata.clk = cfg->clock;
1263 pdata.i2c_wr_max = cfg->i2c_wr_max;
1264 pdata.ts_mode = cfg->ts_mode;
1265 pdata.ts_clk = cfg->ts_clk;
1266 pdata.ts_clk_pol = cfg->ts_clk_pol;
1267 pdata.spec_inv = cfg->spec_inv;
1268 pdata.agc = cfg->agc;
1269 pdata.agc_inv = cfg->agc_inv;
1270 pdata.clk_out = cfg->clock_out;
1271 pdata.envelope_mode = cfg->envelope_mode;
1272 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1273 pdata.lnb_en_pol = cfg->lnb_en_pol;
1274 pdata.attach_in_use = true;
1276 memset(&board_info, 0, sizeof(board_info));
1277 strscpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1278 board_info.addr = cfg->i2c_addr;
1279 board_info.platform_data = &pdata;
1280 client = i2c_new_device(i2c, &board_info);
1281 if (!client || !client->dev.driver)
1284 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1285 return pdata.get_dvb_frontend(client);
1287 EXPORT_SYMBOL(m88ds3103_attach);
1289 static const struct dvb_frontend_ops m88ds3103_ops = {
1290 .delsys = {SYS_DVBS, SYS_DVBS2},
1292 .name = "Montage Technology M88DS3103",
1293 .frequency_min_hz = 950 * MHz,
1294 .frequency_max_hz = 2150 * MHz,
1295 .frequency_tolerance_hz = 5 * MHz,
1296 .symbol_rate_min = 1000000,
1297 .symbol_rate_max = 45000000,
1298 .caps = FE_CAN_INVERSION_AUTO |
1310 FE_CAN_2G_MODULATION
1313 .release = m88ds3103_release,
1315 .get_tune_settings = m88ds3103_get_tune_settings,
1317 .init = m88ds3103_init,
1318 .sleep = m88ds3103_sleep,
1320 .set_frontend = m88ds3103_set_frontend,
1321 .get_frontend = m88ds3103_get_frontend,
1323 .read_status = m88ds3103_read_status,
1324 .read_snr = m88ds3103_read_snr,
1325 .read_ber = m88ds3103_read_ber,
1327 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1328 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1330 .set_tone = m88ds3103_set_tone,
1331 .set_voltage = m88ds3103_set_voltage,
1334 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1336 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1338 dev_dbg(&client->dev, "\n");
1343 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1345 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1347 dev_dbg(&client->dev, "\n");
1349 return dev->muxc->adapter[0];
1352 static int m88ds3103_probe(struct i2c_client *client,
1353 const struct i2c_device_id *id)
1355 struct m88ds3103_dev *dev;
1356 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1360 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1366 dev->client = client;
1367 dev->config.clock = pdata->clk;
1368 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1369 dev->config.ts_mode = pdata->ts_mode;
1370 dev->config.ts_clk = pdata->ts_clk * 1000;
1371 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1372 dev->config.spec_inv = pdata->spec_inv;
1373 dev->config.agc_inv = pdata->agc_inv;
1374 dev->config.clock_out = pdata->clk_out;
1375 dev->config.envelope_mode = pdata->envelope_mode;
1376 dev->config.agc = pdata->agc;
1377 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1378 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1379 dev->cfg = &dev->config;
1381 dev->regmap_config.reg_bits = 8,
1382 dev->regmap_config.val_bits = 8,
1383 dev->regmap_config.lock_arg = dev,
1384 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1385 if (IS_ERR(dev->regmap)) {
1386 ret = PTR_ERR(dev->regmap);
1390 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1391 ret = regmap_read(dev->regmap, 0x00, &utmp);
1395 dev->chip_id = utmp >> 1;
1396 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1398 switch (dev->chip_id) {
1399 case M88RS6000_CHIP_ID:
1400 case M88DS3103_CHIP_ID:
1404 dev_err(&client->dev, "Unknown device. Chip_id=%02x\n", dev->chip_id);
1408 switch (dev->cfg->clock_out) {
1409 case M88DS3103_CLOCK_OUT_DISABLED:
1412 case M88DS3103_CLOCK_OUT_ENABLED:
1415 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1423 if (!pdata->ts_clk) {
1428 /* 0x29 register is defined differently for m88rs6000. */
1429 /* set internal tuner address to 0x21 */
1430 if (dev->chip_id == M88RS6000_CHIP_ID)
1433 ret = regmap_write(dev->regmap, 0x29, utmp);
1438 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1441 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1444 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1448 /* create mux i2c adapter for tuner */
1449 dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
1450 m88ds3103_select, NULL);
1455 dev->muxc->priv = dev;
1456 ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1460 /* create dvb_frontend */
1461 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1462 if (dev->chip_id == M88RS6000_CHIP_ID)
1463 strscpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1464 sizeof(dev->fe.ops.info.name));
1465 if (!pdata->attach_in_use)
1466 dev->fe.ops.release = NULL;
1467 dev->fe.demodulator_priv = dev;
1468 i2c_set_clientdata(client, dev);
1470 /* setup callbacks */
1471 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1472 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1477 dev_dbg(&client->dev, "failed=%d\n", ret);
1481 static int m88ds3103_remove(struct i2c_client *client)
1483 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1485 dev_dbg(&client->dev, "\n");
1487 i2c_mux_del_adapters(dev->muxc);
1493 static const struct i2c_device_id m88ds3103_id_table[] = {
1497 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1499 static struct i2c_driver m88ds3103_driver = {
1501 .name = "m88ds3103",
1502 .suppress_bind_attrs = true,
1504 .probe = m88ds3103_probe,
1505 .remove = m88ds3103_remove,
1506 .id_table = m88ds3103_id_table,
1509 module_i2c_driver(m88ds3103_driver);
1511 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1512 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1513 MODULE_LICENSE("GPL");
1514 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1515 MODULE_FIRMWARE(M88RS6000_FIRMWARE);