drivers/media/dvb-frontends/lgdt3306a.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *    Support for LGDT3306A - 8VSB/QAM-B
   4  *
   5  *    Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
   6  *    - driver structure based on lgdt3305.[ch] by Michael Krufky
   7  *    - code based on LG3306_V0.35 API by LG Electronics Inc.
   8  */
   9
  10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11
  12 #include <asm/div64.h>
  13 #include <linux/kernel.h>
  14 #include <linux/dvb/frontend.h>
  15 #include <media/dvb_math.h>
  16 #include "lgdt3306a.h"
  17 #include <linux/i2c-mux.h>
  18
  19
  20 static int debug;
  21 module_param(debug, int, 0644);
  22 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  23
  24 /*
  25  * Older drivers treated QAM64 and QAM256 the same; that is the HW always
  26  * used "Auto" mode during detection.  Setting "forced_manual"=1 allows
  27  * the user to treat these modes as separate.  For backwards compatibility,
  28  * it's off by default.  QAM_AUTO can now be specified to achive that
  29  * effect even if "forced_manual"=1
  30  */
  31 static int forced_manual;
  32 module_param(forced_manual, int, 0644);
  33 MODULE_PARM_DESC(forced_manual, "if set, QAM64 and QAM256 will only lock to modulation specified");
  34
  35 #define DBG_INFO 1
  36 #define DBG_REG  2
  37 #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
  38
  39 #define lg_debug(fmt, arg...) \
  40         printk(KERN_DEBUG pr_fmt(fmt), ## arg)
  41
  42 #define dbg_info(fmt, arg...)                                   \
  43         do {                                                    \
  44                 if (debug & DBG_INFO)                           \
  45                         lg_debug(fmt, ## arg);                  \
  46         } while (0)
  47
  48 #define dbg_reg(fmt, arg...)                                    \
  49         do {                                                    \
  50                 if (debug & DBG_REG)                            \
  51                         lg_debug(fmt, ## arg);                  \
  52         } while (0)
  53
  54 #define lg_chkerr(ret)                                                  \
  55 ({                                                                      \
  56         int __ret;                                                      \
  57         __ret = (ret < 0);                                              \
  58         if (__ret)                                                      \
  59                 pr_err("error %d on line %d\n", ret, __LINE__);         \
  60         __ret;                                                          \
  61 })
  62
  63 struct lgdt3306a_state {
  64         struct i2c_adapter *i2c_adap;
  65         const struct lgdt3306a_config *cfg;
  66
  67         struct dvb_frontend frontend;
  68
  69         enum fe_modulation current_modulation;
  70         u32 current_frequency;
  71         u32 snr;
  72
  73         struct i2c_mux_core *muxc;
  74 };
  75
  76 /*
  77  * LG3306A Register Usage
  78  *  (LG does not really name the registers, so this code does not either)
  79  *
  80  * 0000 -> 00FF Common control and status
  81  * 1000 -> 10FF Synchronizer control and status
  82  * 1F00 -> 1FFF Smart Antenna control and status
  83  * 2100 -> 21FF VSB Equalizer control and status
  84  * 2800 -> 28FF QAM Equalizer control and status
  85  * 3000 -> 30FF FEC control and status
  86  */
  87
  88 enum lgdt3306a_lock_status {
  89         LG3306_UNLOCK       = 0x00,
  90         LG3306_LOCK         = 0x01,
  91         LG3306_UNKNOWN_LOCK = 0xff
  92 };
  93
  94 enum lgdt3306a_neverlock_status {
  95         LG3306_NL_INIT    = 0x00,
  96         LG3306_NL_PROCESS = 0x01,
  97         LG3306_NL_LOCK    = 0x02,
  98         LG3306_NL_FAIL    = 0x03,
  99         LG3306_NL_UNKNOWN = 0xff
 100 };
 101
 102 enum lgdt3306a_modulation {
 103         LG3306_VSB          = 0x00,
 104         LG3306_QAM64        = 0x01,
 105         LG3306_QAM256       = 0x02,
 106         LG3306_UNKNOWN_MODE = 0xff
 107 };
 108
 109 enum lgdt3306a_lock_check {
 110         LG3306_SYNC_LOCK,
 111         LG3306_FEC_LOCK,
 112         LG3306_TR_LOCK,
 113         LG3306_AGC_LOCK,
 114 };
 115
 116
 117 #ifdef DBG_DUMP
 118 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
 119 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
 120 #endif
 121
 122
 123 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
 124 {
 125         int ret;
 126         u8 buf[] = { reg >> 8, reg & 0xff, val };
 127         struct i2c_msg msg = {
 128                 .addr = state->cfg->i2c_addr, .flags = 0,
 129                 .buf = buf, .len = 3,
 130         };
 131
 132         dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
 133
 134         ret = i2c_transfer(state->i2c_adap, &msg, 1);
 135
 136         if (ret != 1) {
 137                 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
 138                        msg.buf[0], msg.buf[1], msg.buf[2], ret);
 139                 if (ret < 0)
 140                         return ret;
 141                 else
 142                         return -EREMOTEIO;
 143         }
 144         return 0;
 145 }
 146
 147 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
 148 {
 149         int ret;
 150         u8 reg_buf[] = { reg >> 8, reg & 0xff };
 151         struct i2c_msg msg[] = {
 152                 { .addr = state->cfg->i2c_addr,
 153                   .flags = 0, .buf = reg_buf, .len = 2 },
 154                 { .addr = state->cfg->i2c_addr,
 155                   .flags = I2C_M_RD, .buf = val, .len = 1 },
 156         };
 157
 158         ret = i2c_transfer(state->i2c_adap, msg, 2);
 159
 160         if (ret != 2) {
 161                 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
 162                        state->cfg->i2c_addr, reg, ret);
 163                 if (ret < 0)
 164                         return ret;
 165                 else
 166                         return -EREMOTEIO;
 167         }
 168         dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
 169
 170         return 0;
 171 }
 172
 173 #define read_reg(state, reg)                                            \
 174 ({                                                                      \
 175         u8 __val;                                                       \
 176         int ret = lgdt3306a_read_reg(state, reg, &__val);               \
 177         if (lg_chkerr(ret))                                             \
 178                 __val = 0;                                              \
 179         __val;                                                          \
 180 })
 181
 182 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
 183                                 u16 reg, int bit, int onoff)
 184 {
 185         u8 val;
 186         int ret;
 187
 188         dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
 189
 190         ret = lgdt3306a_read_reg(state, reg, &val);
 191         if (lg_chkerr(ret))
 192                 goto fail;
 193
 194         val &= ~(1 << bit);
 195         val |= (onoff & 1) << bit;
 196
 197         ret = lgdt3306a_write_reg(state, reg, val);
 198         lg_chkerr(ret);
 199 fail:
 200         return ret;
 201 }
 202
 203 /* ------------------------------------------------------------------------ */
 204
 205 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
 206 {
 207         int ret;
 208
 209         dbg_info("\n");
 210
 211         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
 212         if (lg_chkerr(ret))
 213                 goto fail;
 214
 215         msleep(20);
 216         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
 217         lg_chkerr(ret);
 218
 219 fail:
 220         return ret;
 221 }
 222
 223 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
 224                                      enum lgdt3306a_mpeg_mode mode)
 225 {
 226         u8 val;
 227         int ret;
 228
 229         dbg_info("(%d)\n", mode);
 230         /* transport packet format - TPSENB=0x80 */
 231         ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
 232                                      mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
 233         if (lg_chkerr(ret))
 234                 goto fail;
 235
 236         /*
 237          * start of packet signal duration
 238          * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
 239          */
 240         ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
 241         if (lg_chkerr(ret))
 242                 goto fail;
 243
 244         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 245         if (lg_chkerr(ret))
 246                 goto fail;
 247
 248         val |= 0x10; /* TPCLKSUPB=0x10 */
 249
 250         if (mode == LGDT3306A_MPEG_PARALLEL)
 251                 val &= ~0x10;
 252
 253         ret = lgdt3306a_write_reg(state, 0x0070, val);
 254         lg_chkerr(ret);
 255
 256 fail:
 257         return ret;
 258 }
 259
 260 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
 261                                        enum lgdt3306a_tp_clock_edge edge,
 262                                        enum lgdt3306a_tp_valid_polarity valid)
 263 {
 264         u8 val;
 265         int ret;
 266
 267         dbg_info("edge=%d, valid=%d\n", edge, valid);
 268
 269         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 270         if (lg_chkerr(ret))
 271                 goto fail;
 272
 273         val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
 274
 275         if (edge == LGDT3306A_TPCLK_RISING_EDGE)
 276                 val |= 0x04;
 277         if (valid == LGDT3306A_TP_VALID_HIGH)
 278                 val |= 0x02;
 279
 280         ret = lgdt3306a_write_reg(state, 0x0070, val);
 281         lg_chkerr(ret);
 282
 283 fail:
 284         return ret;
 285 }
 286
 287 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
 288                                      int mode)
 289 {
 290         u8 val;
 291         int ret;
 292
 293         dbg_info("(%d)\n", mode);
 294
 295         if (mode) {
 296                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 297                 if (lg_chkerr(ret))
 298                         goto fail;
 299                 /*
 300                  * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
 301                  * TPDATAOUTEN=0x08
 302                  */
 303                 val &= ~0xa8;
 304                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 305                 if (lg_chkerr(ret))
 306                         goto fail;
 307
 308                 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
 309                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
 310                 if (lg_chkerr(ret))
 311                         goto fail;
 312
 313         } else {
 314                 /* enable IFAGC pin */
 315                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
 316                 if (lg_chkerr(ret))
 317                         goto fail;
 318
 319                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 320                 if (lg_chkerr(ret))
 321                         goto fail;
 322
 323                 val |= 0xa8; /* enable bus */
 324                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 325                 if (lg_chkerr(ret))
 326                         goto fail;
 327         }
 328
 329 fail:
 330         return ret;
 331 }
 332
 333 static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
 334 {
 335         struct lgdt3306a_state *state = fe->demodulator_priv;
 336
 337         dbg_info("acquire=%d\n", acquire);
 338
 339         return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
 340
 341 }
 342
 343 static int lgdt3306a_power(struct lgdt3306a_state *state,
 344                                      int mode)
 345 {
 346         int ret;
 347
 348         dbg_info("(%d)\n", mode);
 349
 350         if (mode == 0) {
 351                 /* into reset */
 352                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
 353                 if (lg_chkerr(ret))
 354                         goto fail;
 355
 356                 /* power down */
 357                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
 358                 if (lg_chkerr(ret))
 359                         goto fail;
 360
 361         } else {
 362                 /* out of reset */
 363                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
 364                 if (lg_chkerr(ret))
 365                         goto fail;
 366
 367                 /* power up */
 368                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
 369                 if (lg_chkerr(ret))
 370                         goto fail;
 371         }
 372
 373 #ifdef DBG_DUMP
 374         lgdt3306a_DumpAllRegs(state);
 375 #endif
 376 fail:
 377         return ret;
 378 }
 379
 380
 381 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
 382 {
 383         u8 val;
 384         int ret;
 385
 386         dbg_info("\n");
 387
 388         /* 0. Spectrum inversion detection manual; spectrum inverted */
 389         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 390         val &= 0xf7; /* SPECINVAUTO Off */
 391         val |= 0x04; /* SPECINV On */
 392         ret = lgdt3306a_write_reg(state, 0x0002, val);
 393         if (lg_chkerr(ret))
 394                 goto fail;
 395
 396         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 397         ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
 398         if (lg_chkerr(ret))
 399                 goto fail;
 400
 401         /* 2. Bandwidth mode for VSB(6MHz) */
 402         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 403         val &= 0xe3;
 404         val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
 405         ret = lgdt3306a_write_reg(state, 0x0009, val);
 406         if (lg_chkerr(ret))
 407                 goto fail;
 408
 409         /* 3. QAM mode detection mode(None) */
 410         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 411         val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
 412         ret = lgdt3306a_write_reg(state, 0x0009, val);
 413         if (lg_chkerr(ret))
 414                 goto fail;
 415
 416         /* 4. ADC sampling frequency rate(2x sampling) */
 417         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 418         val &= 0xbf; /* SAMPLING4XFEN=0 */
 419         ret = lgdt3306a_write_reg(state, 0x000d, val);
 420         if (lg_chkerr(ret))
 421                 goto fail;
 422
 423 #if 0
 424         /* FGR - disable any AICC filtering, testing only */
 425
 426         ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
 427         if (lg_chkerr(ret))
 428                 goto fail;
 429
 430         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 431         ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
 432         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 433         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 434
 435         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 436         ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
 437         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 438         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 439
 440         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 441         ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
 442         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 443         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 444
 445         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 446         ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
 447         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 448         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 449
 450 #else
 451         /* FGR - this works well for HVR-1955,1975 */
 452
 453         /* 5. AICCOPMODE  NT N-1 Adj. */
 454         ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
 455         if (lg_chkerr(ret))
 456                 goto fail;
 457
 458         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 459         ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
 460         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 461         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 462
 463         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 464         ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
 465         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 466         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 467
 468         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 469         ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
 470         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 471         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 472
 473         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 474         ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
 475         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 476         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 477 #endif
 478
 479         ret = lgdt3306a_read_reg(state, 0x001e, &val);
 480         val &= 0x0f;
 481         val |= 0xa0;
 482         ret = lgdt3306a_write_reg(state, 0x001e, val);
 483
 484         ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
 485
 486         ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
 487
 488         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 489         val &= 0xef;
 490         ret = lgdt3306a_write_reg(state, 0x211f, val);
 491
 492         ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
 493
 494         ret = lgdt3306a_read_reg(state, 0x1061, &val);
 495         val &= 0xf8;
 496         val |= 0x04;
 497         ret = lgdt3306a_write_reg(state, 0x1061, val);
 498
 499         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 500         val &= 0xcf;
 501         ret = lgdt3306a_write_reg(state, 0x103d, val);
 502
 503         ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
 504
 505         ret = lgdt3306a_read_reg(state, 0x2141, &val);
 506         val &= 0x3f;
 507         ret = lgdt3306a_write_reg(state, 0x2141, val);
 508
 509         ret = lgdt3306a_read_reg(state, 0x2135, &val);
 510         val &= 0x0f;
 511         val |= 0x70;
 512         ret = lgdt3306a_write_reg(state, 0x2135, val);
 513
 514         ret = lgdt3306a_read_reg(state, 0x0003, &val);
 515         val &= 0xf7;
 516         ret = lgdt3306a_write_reg(state, 0x0003, val);
 517
 518         ret = lgdt3306a_read_reg(state, 0x001c, &val);
 519         val &= 0x7f;
 520         ret = lgdt3306a_write_reg(state, 0x001c, val);
 521
 522         /* 6. EQ step size */
 523         ret = lgdt3306a_read_reg(state, 0x2179, &val);
 524         val &= 0xf8;
 525         ret = lgdt3306a_write_reg(state, 0x2179, val);
 526
 527         ret = lgdt3306a_read_reg(state, 0x217a, &val);
 528         val &= 0xf8;
 529         ret = lgdt3306a_write_reg(state, 0x217a, val);
 530
 531         /* 7. Reset */
 532         ret = lgdt3306a_soft_reset(state);
 533         if (lg_chkerr(ret))
 534                 goto fail;
 535
 536         dbg_info("complete\n");
 537 fail:
 538         return ret;
 539 }
 540
 541 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
 542 {
 543         u8 val;
 544         int ret;
 545
 546         dbg_info("modulation=%d\n", modulation);
 547
 548         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 549         ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
 550         if (lg_chkerr(ret))
 551                 goto fail;
 552
 553         /* 1a. Spectrum inversion detection to Auto */
 554         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 555         val &= 0xfb; /* SPECINV Off */
 556         val |= 0x08; /* SPECINVAUTO On */
 557         ret = lgdt3306a_write_reg(state, 0x0002, val);
 558         if (lg_chkerr(ret))
 559                 goto fail;
 560
 561         /* 2. Bandwidth mode for QAM */
 562         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 563         val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
 564         ret = lgdt3306a_write_reg(state, 0x0009, val);
 565         if (lg_chkerr(ret))
 566                 goto fail;
 567
 568         /* 3. : 64QAM/256QAM detection(manual, auto) */
 569         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 570         val &= 0xfc;
 571         /* Check for forced Manual modulation modes; otherwise always "auto" */
 572         if(forced_manual && (modulation != QAM_AUTO)){
 573                 val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */
 574         } else {
 575                 val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */
 576         }
 577         ret = lgdt3306a_write_reg(state, 0x0009, val);
 578         if (lg_chkerr(ret))
 579                 goto fail;
 580
 581         /* 3a. : 64QAM/256QAM selection for manual */
 582         ret = lgdt3306a_read_reg(state, 0x101a, &val);
 583         val &= 0xf8;
 584         if (modulation == QAM_64)
 585                 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
 586         else
 587                 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
 588
 589         ret = lgdt3306a_write_reg(state, 0x101a, val);
 590         if (lg_chkerr(ret))
 591                 goto fail;
 592
 593         /* 4. ADC sampling frequency rate(4x sampling) */
 594         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 595         val &= 0xbf;
 596         val |= 0x40; /* SAMPLING4XFEN=1 */
 597         ret = lgdt3306a_write_reg(state, 0x000d, val);
 598         if (lg_chkerr(ret))
 599                 goto fail;
 600
 601         /* 5. No AICC operation in QAM mode */
 602         ret = lgdt3306a_read_reg(state, 0x0024, &val);
 603         val &= 0x00;
 604         ret = lgdt3306a_write_reg(state, 0x0024, val);
 605         if (lg_chkerr(ret))
 606                 goto fail;
 607
 608         /* 5.1 V0.36 SRDCHKALWAYS : For better QAM detection */
 609         ret = lgdt3306a_read_reg(state, 0x000a, &val);
 610         val &= 0xfd;
 611         val |= 0x02;
 612         ret = lgdt3306a_write_reg(state, 0x000a, val);
 613         if (lg_chkerr(ret))
 614                 goto fail;
 615
 616         /* 5.2 V0.36 Control of "no signal" detector function */
 617         ret = lgdt3306a_read_reg(state, 0x2849, &val);
 618         val &= 0xdf;
 619         ret = lgdt3306a_write_reg(state, 0x2849, val);
 620         if (lg_chkerr(ret))
 621                 goto fail;
 622
 623         /* 5.3 Fix for Blonder Tongue HDE-2H-QAM and AQM modulators */
 624         ret = lgdt3306a_read_reg(state, 0x302b, &val);
 625         val &= 0x7f;  /* SELFSYNCFINDEN_CQS=0; disable auto reset */
 626         ret = lgdt3306a_write_reg(state, 0x302b, val);
 627         if (lg_chkerr(ret))
 628                 goto fail;
 629
 630         /* 6. Reset */
 631         ret = lgdt3306a_soft_reset(state);
 632         if (lg_chkerr(ret))
 633                 goto fail;
 634
 635         dbg_info("complete\n");
 636 fail:
 637         return ret;
 638 }
 639
 640 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
 641                                    struct dtv_frontend_properties *p)
 642 {
 643         int ret;
 644
 645         dbg_info("\n");
 646
 647         switch (p->modulation) {
 648         case VSB_8:
 649                 ret = lgdt3306a_set_vsb(state);
 650                 break;
 651         case QAM_64:
 652         case QAM_256:
 653         case QAM_AUTO:
 654                 ret = lgdt3306a_set_qam(state, p->modulation);
 655                 break;
 656         default:
 657                 return -EINVAL;
 658         }
 659         if (lg_chkerr(ret))
 660                 goto fail;
 661
 662         state->current_modulation = p->modulation;
 663
 664 fail:
 665         return ret;
 666 }
 667
 668 /* ------------------------------------------------------------------------ */
 669
 670 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
 671                               struct dtv_frontend_properties *p)
 672 {
 673         /* TODO: anything we want to do here??? */
 674         dbg_info("\n");
 675
 676         switch (p->modulation) {
 677         case VSB_8:
 678                 break;
 679         case QAM_64:
 680         case QAM_256:
 681         case QAM_AUTO:
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686         return 0;
 687 }
 688
 689 /* ------------------------------------------------------------------------ */
 690
 691 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
 692                                        int inversion)
 693 {
 694         int ret;
 695
 696         dbg_info("(%d)\n", inversion);
 697
 698         ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
 699         return ret;
 700 }
 701
 702 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
 703                                        int enabled)
 704 {
 705         int ret;
 706
 707         dbg_info("(%d)\n", enabled);
 708
 709         /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
 710         ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
 711         return ret;
 712 }
 713
 714 static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
 715                                        struct dtv_frontend_properties *p,
 716                                        int inversion)
 717 {
 718         int ret = 0;
 719
 720         dbg_info("(%d)\n", inversion);
 721 #if 0
 722         /*
 723          * FGR - spectral_inversion defaults already set for VSB and QAM;
 724          * can enable later if desired
 725          */
 726
 727         ret = lgdt3306a_set_inversion(state, inversion);
 728
 729         switch (p->modulation) {
 730         case VSB_8:
 731                 /* Manual only for VSB */
 732                 ret = lgdt3306a_set_inversion_auto(state, 0);
 733                 break;
 734         case QAM_64:
 735         case QAM_256:
 736         case QAM_AUTO:
 737                 /* Auto ok for QAM */
 738                 ret = lgdt3306a_set_inversion_auto(state, 1);
 739                 break;
 740         default:
 741                 ret = -EINVAL;
 742         }
 743 #endif
 744         return ret;
 745 }
 746
 747 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
 748                            struct dtv_frontend_properties *p)
 749 {
 750         int ret;
 751         u16 if_freq_khz;
 752         u8 nco1, nco2;
 753
 754         switch (p->modulation) {
 755         case VSB_8:
 756                 if_freq_khz = state->cfg->vsb_if_khz;
 757                 break;
 758         case QAM_64:
 759         case QAM_256:
 760         case QAM_AUTO:
 761                 if_freq_khz = state->cfg->qam_if_khz;
 762                 break;
 763         default:
 764                 return -EINVAL;
 765         }
 766
 767         switch (if_freq_khz) {
 768         default:
 769                 pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
 770                         if_freq_khz);
 771                 fallthrough;
 772         case 3250: /* 3.25Mhz */
 773                 nco1 = 0x34;
 774                 nco2 = 0x00;
 775                 break;
 776         case 3500: /* 3.50Mhz */
 777                 nco1 = 0x38;
 778                 nco2 = 0x00;
 779                 break;
 780         case 4000: /* 4.00Mhz */
 781                 nco1 = 0x40;
 782                 nco2 = 0x00;
 783                 break;
 784         case 5000: /* 5.00Mhz */
 785                 nco1 = 0x50;
 786                 nco2 = 0x00;
 787                 break;
 788         case 5380: /* 5.38Mhz */
 789                 nco1 = 0x56;
 790                 nco2 = 0x14;
 791                 break;
 792         }
 793         ret = lgdt3306a_write_reg(state, 0x0010, nco1);
 794         if (ret)
 795                 return ret;
 796         ret = lgdt3306a_write_reg(state, 0x0011, nco2);
 797         if (ret)
 798                 return ret;
 799
 800         dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
 801
 802         return 0;
 803 }
 804
 805 /* ------------------------------------------------------------------------ */
 806
 807 static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 808 {
 809         struct lgdt3306a_state *state = fe->demodulator_priv;
 810
 811         if (state->cfg->deny_i2c_rptr) {
 812                 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
 813                 return 0;
 814         }
 815         dbg_info("(%d)\n", enable);
 816
 817         /* NI2CRPTEN=0x80 */
 818         return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
 819 }
 820
 821 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
 822 {
 823         int ret;
 824
 825         dbg_info("\n");
 826         state->current_frequency = -1; /* force re-tune, when we wake */
 827
 828         ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
 829         if (lg_chkerr(ret))
 830                 goto fail;
 831
 832         ret = lgdt3306a_power(state, 0); /* power down */
 833         lg_chkerr(ret);
 834
 835 fail:
 836         return 0;
 837 }
 838
 839 static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
 840 {
 841         struct lgdt3306a_state *state = fe->demodulator_priv;
 842
 843         return lgdt3306a_sleep(state);
 844 }
 845
 846 static int lgdt3306a_init(struct dvb_frontend *fe)
 847 {
 848         struct lgdt3306a_state *state = fe->demodulator_priv;
 849         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 850         u8 val;
 851         int ret;
 852
 853         dbg_info("\n");
 854
 855         /* 1. Normal operation mode */
 856         ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
 857         if (lg_chkerr(ret))
 858                 goto fail;
 859
 860         /* 2. Spectrum inversion auto detection (Not valid for VSB) */
 861         ret = lgdt3306a_set_inversion_auto(state, 0);
 862         if (lg_chkerr(ret))
 863                 goto fail;
 864
 865         /* 3. Spectrum inversion(According to the tuner configuration) */
 866         ret = lgdt3306a_set_inversion(state, 1);
 867         if (lg_chkerr(ret))
 868                 goto fail;
 869
 870         /* 4. Peak-to-peak voltage of ADC input signal */
 871
 872         /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
 873         ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
 874         if (lg_chkerr(ret))
 875                 goto fail;
 876
 877         /* 5. ADC output data capture clock phase */
 878
 879         /* 0=same phase as ADC clock */
 880         ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
 881         if (lg_chkerr(ret))
 882                 goto fail;
 883
 884         /* 5a. ADC sampling clock source */
 885
 886         /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
 887         ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
 888         if (lg_chkerr(ret))
 889                 goto fail;
 890
 891         /* 6. Automatic PLL set */
 892
 893         /* PLLSETAUTO=0x40; 0=off */
 894         ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
 895         if (lg_chkerr(ret))
 896                 goto fail;
 897
 898         if (state->cfg->xtalMHz == 24) {        /* 24MHz */
 899                 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
 900                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 901                 if (lg_chkerr(ret))
 902                         goto fail;
 903                 val &= 0xc0;
 904                 val |= 0x25;
 905                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 906                 if (lg_chkerr(ret))
 907                         goto fail;
 908                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 909                 if (lg_chkerr(ret))
 910                         goto fail;
 911
 912                 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
 913                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 914                 if (lg_chkerr(ret))
 915                         goto fail;
 916                 val &= 0xc0;
 917                 val |= 0x18;
 918                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 919                 if (lg_chkerr(ret))
 920                         goto fail;
 921
 922         } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
 923                 /* 7. Frequency for PLL output */
 924                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 925                 if (lg_chkerr(ret))
 926                         goto fail;
 927                 val &= 0xc0;
 928                 val |= 0x25;
 929                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 930                 if (lg_chkerr(ret))
 931                         goto fail;
 932                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 933                 if (lg_chkerr(ret))
 934                         goto fail;
 935
 936                 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
 937                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 938                 if (lg_chkerr(ret))
 939                         goto fail;
 940                 val &= 0xc0;
 941                 val |= 0x19;
 942                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 943                 if (lg_chkerr(ret))
 944                         goto fail;
 945         } else {
 946                 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
 947         }
 948 #if 0
 949         ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
 950         ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
 951 #endif
 952
 953         /* 9. Center frequency of input signal of ADC */
 954         ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
 955         ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
 956
 957         /* 10. Fixed gain error value */
 958         ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
 959
 960         /* 10a. VSB TR BW gear shift initial step */
 961         ret = lgdt3306a_read_reg(state, 0x103c, &val);
 962         val &= 0x0f;
 963         val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
 964         ret = lgdt3306a_write_reg(state, 0x103c, val);
 965
 966         /* 10b. Timing offset calibration in low temperature for VSB */
 967         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 968         val &= 0xfc;
 969         val |= 0x03;
 970         ret = lgdt3306a_write_reg(state, 0x103d, val);
 971
 972         /* 10c. Timing offset calibration in low temperature for QAM */
 973         ret = lgdt3306a_read_reg(state, 0x1036, &val);
 974         val &= 0xf0;
 975         val |= 0x0c;
 976         ret = lgdt3306a_write_reg(state, 0x1036, val);
 977
 978         /* 11. Using the imaginary part of CIR in CIR loading */
 979         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 980         val &= 0xef; /* do not use imaginary of CIR */
 981         ret = lgdt3306a_write_reg(state, 0x211f, val);
 982
 983         /* 12. Control of no signal detector function */
 984         ret = lgdt3306a_read_reg(state, 0x2849, &val);
 985         val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
 986         ret = lgdt3306a_write_reg(state, 0x2849, val);
 987
 988         /* FGR - put demod in some known mode */
 989         ret = lgdt3306a_set_vsb(state);
 990
 991         /* 13. TP stream format */
 992         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
 993
 994         /* 14. disable output buses */
 995         ret = lgdt3306a_mpeg_tristate(state, 1);
 996
 997         /* 15. Sleep (in reset) */
 998         ret = lgdt3306a_sleep(state);
 999         lg_chkerr(ret);
1000
1001         c->cnr.len = 1;
1002         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1003
1004 fail:
1005         return ret;
1006 }
1007
1008 static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
1009 {
1010         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1011         struct lgdt3306a_state *state = fe->demodulator_priv;
1012         int ret;
1013
1014         dbg_info("(%d, %d)\n", p->frequency, p->modulation);
1015
1016         if (state->current_frequency  == p->frequency &&
1017            state->current_modulation == p->modulation) {
1018                 dbg_info(" (already set, skipping ...)\n");
1019                 return 0;
1020         }
1021         state->current_frequency = -1;
1022         state->current_modulation = -1;
1023
1024         ret = lgdt3306a_power(state, 1); /* power up */
1025         if (lg_chkerr(ret))
1026                 goto fail;
1027
1028         if (fe->ops.tuner_ops.set_params) {
1029                 ret = fe->ops.tuner_ops.set_params(fe);
1030                 if (fe->ops.i2c_gate_ctrl)
1031                         fe->ops.i2c_gate_ctrl(fe, 0);
1032 #if 0
1033                 if (lg_chkerr(ret))
1034                         goto fail;
1035                 state->current_frequency = p->frequency;
1036 #endif
1037         }
1038
1039         ret = lgdt3306a_set_modulation(state, p);
1040         if (lg_chkerr(ret))
1041                 goto fail;
1042
1043         ret = lgdt3306a_agc_setup(state, p);
1044         if (lg_chkerr(ret))
1045                 goto fail;
1046
1047         ret = lgdt3306a_set_if(state, p);
1048         if (lg_chkerr(ret))
1049                 goto fail;
1050
1051         ret = lgdt3306a_spectral_inversion(state, p,
1052                                         state->cfg->spectral_inversion ? 1 : 0);
1053         if (lg_chkerr(ret))
1054                 goto fail;
1055
1056         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1057         if (lg_chkerr(ret))
1058                 goto fail;
1059
1060         ret = lgdt3306a_mpeg_mode_polarity(state,
1061                                           state->cfg->tpclk_edge,
1062                                           state->cfg->tpvalid_polarity);
1063         if (lg_chkerr(ret))
1064                 goto fail;
1065
1066         ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1067         if (lg_chkerr(ret))
1068                 goto fail;
1069
1070         ret = lgdt3306a_soft_reset(state);
1071         if (lg_chkerr(ret))
1072                 goto fail;
1073
1074 #ifdef DBG_DUMP
1075         lgdt3306a_DumpAllRegs(state);
1076 #endif
1077         state->current_frequency = p->frequency;
1078 fail:
1079         return ret;
1080 }
1081
1082 static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1083                                   struct dtv_frontend_properties *p)
1084 {
1085         struct lgdt3306a_state *state = fe->demodulator_priv;
1086
1087         dbg_info("(%u, %d)\n",
1088                  state->current_frequency, state->current_modulation);
1089
1090         p->modulation = state->current_modulation;
1091         p->frequency = state->current_frequency;
1092         return 0;
1093 }
1094
1095 static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1096 {
1097 #if 1
1098         return DVBFE_ALGO_CUSTOM;
1099 #else
1100         return DVBFE_ALGO_HW;
1101 #endif
1102 }
1103
1104 /* ------------------------------------------------------------------------ */
1105 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1106 {
1107         u8 val;
1108         int ret;
1109         u8 snrRef, maxPowerMan, nCombDet;
1110         u16 fbDlyCir;
1111
1112         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1113         if (ret)
1114                 return ret;
1115         snrRef = val & 0x3f;
1116
1117         ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1118         if (ret)
1119                 return ret;
1120
1121         ret = lgdt3306a_read_reg(state, 0x2191, &val);
1122         if (ret)
1123                 return ret;
1124         nCombDet = (val & 0x80) >> 7;
1125
1126         ret = lgdt3306a_read_reg(state, 0x2180, &val);
1127         if (ret)
1128                 return ret;
1129         fbDlyCir = (val & 0x03) << 8;
1130
1131         ret = lgdt3306a_read_reg(state, 0x2181, &val);
1132         if (ret)
1133                 return ret;
1134         fbDlyCir |= val;
1135
1136         dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1137                 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1138
1139         /* Carrier offset sub loop bandwidth */
1140         ret = lgdt3306a_read_reg(state, 0x1061, &val);
1141         if (ret)
1142                 return ret;
1143         val &= 0xf8;
1144         if ((snrRef > 18) && (maxPowerMan > 0x68)
1145             && (nCombDet == 0x01)
1146             && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
1147                 /* SNR is over 18dB and no ghosting */
1148                 val |= 0x00; /* final bandwidth = 0 */
1149         } else {
1150                 val |= 0x04; /* final bandwidth = 4 */
1151         }
1152         ret = lgdt3306a_write_reg(state, 0x1061, val);
1153         if (ret)
1154                 return ret;
1155
1156         /* Adjust Notch Filter */
1157         ret = lgdt3306a_read_reg(state, 0x0024, &val);
1158         if (ret)
1159                 return ret;
1160         val &= 0x0f;
1161         if (nCombDet == 0) { /* Turn on the Notch Filter */
1162                 val |= 0x50;
1163         }
1164         ret = lgdt3306a_write_reg(state, 0x0024, val);
1165         if (ret)
1166                 return ret;
1167
1168         /* VSB Timing Recovery output normalization */
1169         ret = lgdt3306a_read_reg(state, 0x103d, &val);
1170         if (ret)
1171                 return ret;
1172         val &= 0xcf;
1173         val |= 0x20;
1174         ret = lgdt3306a_write_reg(state, 0x103d, val);
1175
1176         return ret;
1177 }
1178
1179 static enum lgdt3306a_modulation
1180 lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1181 {
1182         u8 val = 0;
1183         int ret;
1184
1185         ret = lgdt3306a_read_reg(state, 0x0081, &val);
1186         if (ret)
1187                 goto err;
1188
1189         if (val & 0x80) {
1190                 dbg_info("VSB\n");
1191                 return LG3306_VSB;
1192         }
1193         if (val & 0x08) {
1194                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1195                 if (ret)
1196                         goto err;
1197                 val = val >> 2;
1198                 if (val & 0x01) {
1199                         dbg_info("QAM256\n");
1200                         return LG3306_QAM256;
1201                 }
1202                 dbg_info("QAM64\n");
1203                 return LG3306_QAM64;
1204         }
1205 err:
1206         pr_warn("UNKNOWN\n");
1207         return LG3306_UNKNOWN_MODE;
1208 }
1209
1210 static enum lgdt3306a_lock_status
1211 lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1212                             enum lgdt3306a_lock_check whatLock)
1213 {
1214         u8 val = 0;
1215         int ret;
1216         enum lgdt3306a_modulation       modeOper;
1217         enum lgdt3306a_lock_status lockStatus;
1218
1219         modeOper = LG3306_UNKNOWN_MODE;
1220
1221         switch (whatLock) {
1222         case LG3306_SYNC_LOCK:
1223         {
1224                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1225                 if (ret)
1226                         return ret;
1227
1228                 if ((val & 0x80) == 0x80)
1229                         lockStatus = LG3306_LOCK;
1230                 else
1231                         lockStatus = LG3306_UNLOCK;
1232
1233                 dbg_info("SYNC_LOCK=%x\n", lockStatus);
1234                 break;
1235         }
1236         case LG3306_AGC_LOCK:
1237         {
1238                 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1239                 if (ret)
1240                         return ret;
1241
1242                 if ((val & 0x40) == 0x40)
1243                         lockStatus = LG3306_LOCK;
1244                 else
1245                         lockStatus = LG3306_UNLOCK;
1246
1247                 dbg_info("AGC_LOCK=%x\n", lockStatus);
1248                 break;
1249         }
1250         case LG3306_TR_LOCK:
1251         {
1252                 modeOper = lgdt3306a_check_oper_mode(state);
1253                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1254                         ret = lgdt3306a_read_reg(state, 0x1094, &val);
1255                         if (ret)
1256                                 return ret;
1257
1258                         if ((val & 0x80) == 0x80)
1259                                 lockStatus = LG3306_LOCK;
1260                         else
1261                                 lockStatus = LG3306_UNLOCK;
1262                 } else
1263                         lockStatus = LG3306_UNKNOWN_LOCK;
1264
1265                 dbg_info("TR_LOCK=%x\n", lockStatus);
1266                 break;
1267         }
1268         case LG3306_FEC_LOCK:
1269         {
1270                 modeOper = lgdt3306a_check_oper_mode(state);
1271                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1272                         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1273                         if (ret)
1274                                 return ret;
1275
1276                         if ((val & 0x10) == 0x10)
1277                                 lockStatus = LG3306_LOCK;
1278                         else
1279                                 lockStatus = LG3306_UNLOCK;
1280                 } else
1281                         lockStatus = LG3306_UNKNOWN_LOCK;
1282
1283                 dbg_info("FEC_LOCK=%x\n", lockStatus);
1284                 break;
1285         }
1286
1287         default:
1288                 lockStatus = LG3306_UNKNOWN_LOCK;
1289                 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
1290                 break;
1291         }
1292
1293         return lockStatus;
1294 }
1295
1296 static enum lgdt3306a_neverlock_status
1297 lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1298 {
1299         u8 val = 0;
1300         int ret;
1301         enum lgdt3306a_neverlock_status lockStatus;
1302
1303         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1304         if (ret)
1305                 return ret;
1306         lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1307
1308         dbg_info("NeverLock=%d", lockStatus);
1309
1310         return lockStatus;
1311 }
1312
1313 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1314 {
1315         u8 val = 0;
1316         int ret;
1317         u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1318
1319         /* Channel variation */
1320         ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1321         if (ret)
1322                 return ret;
1323
1324         /* SNR of Frame sync */
1325         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1326         if (ret)
1327                 return ret;
1328         snrRef = val & 0x3f;
1329
1330         /* Strong Main CIR */
1331         ret = lgdt3306a_read_reg(state, 0x2199, &val);
1332         if (ret)
1333                 return ret;
1334         mainStrong = (val & 0x40) >> 6;
1335
1336         ret = lgdt3306a_read_reg(state, 0x0090, &val);
1337         if (ret)
1338                 return ret;
1339         aiccrejStatus = (val & 0xf0) >> 4;
1340
1341         dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1342                 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1343
1344 #if 0
1345         /* Dynamic ghost exists */
1346         if ((mainStrong == 0) && (currChDiffACQ > 0x70))
1347 #endif
1348         if (mainStrong == 0) {
1349                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1350                 if (ret)
1351                         return ret;
1352                 val &= 0x0f;
1353                 val |= 0xa0;
1354                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1355                 if (ret)
1356                         return ret;
1357
1358                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1359                 if (ret)
1360                         return ret;
1361                 val &= 0x3f;
1362                 val |= 0x80;
1363                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1364                 if (ret)
1365                         return ret;
1366
1367                 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1368                 if (ret)
1369                         return ret;
1370         } else { /* Weak ghost or static channel */
1371                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1372                 if (ret)
1373                         return ret;
1374                 val &= 0x0f;
1375                 val |= 0x70;
1376                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1377                 if (ret)
1378                         return ret;
1379
1380                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1381                 if (ret)
1382                         return ret;
1383                 val &= 0x3f;
1384                 val |= 0x40;
1385                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1386                 if (ret)
1387                         return ret;
1388
1389                 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1390                 if (ret)
1391                         return ret;
1392         }
1393         return 0;
1394 }
1395
1396 static enum lgdt3306a_lock_status
1397 lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1398 {
1399         enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
1400         int     i;
1401
1402         for (i = 0; i < 2; i++) {
1403                 msleep(30);
1404
1405                 syncLockStatus = lgdt3306a_check_lock_status(state,
1406                                                              LG3306_SYNC_LOCK);
1407
1408                 if (syncLockStatus == LG3306_LOCK) {
1409                         dbg_info("locked(%d)\n", i);
1410                         return LG3306_LOCK;
1411                 }
1412         }
1413         dbg_info("not locked\n");
1414         return LG3306_UNLOCK;
1415 }
1416
1417 static enum lgdt3306a_lock_status
1418 lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1419 {
1420         enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
1421         int     i;
1422
1423         for (i = 0; i < 2; i++) {
1424                 msleep(30);
1425
1426                 FECLockStatus = lgdt3306a_check_lock_status(state,
1427                                                             LG3306_FEC_LOCK);
1428
1429                 if (FECLockStatus == LG3306_LOCK) {
1430                         dbg_info("locked(%d)\n", i);
1431                         return FECLockStatus;
1432                 }
1433         }
1434         dbg_info("not locked\n");
1435         return FECLockStatus;
1436 }
1437
1438 static enum lgdt3306a_neverlock_status
1439 lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1440 {
1441         enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
1442         int     i;
1443
1444         for (i = 0; i < 5; i++) {
1445                 msleep(30);
1446
1447                 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1448
1449                 if (NLLockStatus == LG3306_NL_LOCK) {
1450                         dbg_info("NL_LOCK(%d)\n", i);
1451                         return NLLockStatus;
1452                 }
1453         }
1454         dbg_info("NLLockStatus=%d\n", NLLockStatus);
1455         return NLLockStatus;
1456 }
1457
1458 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1459 {
1460         u8 val;
1461         int ret;
1462
1463         ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1464         if (ret)
1465                 return ret;
1466
1467         return val;
1468 }
1469
1470 static const u32 valx_x10[] = {
1471         10,  11,  13,  15,  17,  20,  25,  33,  41,  50,  59,  73,  87,  100
1472 };
1473 static const u32 log10x_x1000[] = {
1474         0,   41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
1475 };
1476
1477 static u32 log10_x1000(u32 x)
1478 {
1479         u32 diff_val, step_val, step_log10;
1480         u32 log_val = 0;
1481         u32 i;
1482
1483         if (x <= 0)
1484                 return -1000000; /* signal error */
1485
1486         if (x == 10)
1487                 return 0; /* log(1)=0 */
1488
1489         if (x < 10) {
1490                 while (x < 10) {
1491                         x = x * 10;
1492                         log_val--;
1493                 }
1494         } else {        /* x > 10 */
1495                 while (x >= 100) {
1496                         x = x / 10;
1497                         log_val++;
1498                 }
1499         }
1500         log_val *= 1000;
1501
1502         if (x == 10) /* was our input an exact multiple of 10 */
1503                 return log_val; /* don't need to interpolate */
1504
1505         /* find our place on the log curve */
1506         for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
1507                 if (valx_x10[i] >= x)
1508                         break;
1509         }
1510         if (i == ARRAY_SIZE(valx_x10))
1511                 return log_val + log10x_x1000[i - 1];
1512
1513         diff_val   = x - valx_x10[i-1];
1514         step_val   = valx_x10[i] - valx_x10[i - 1];
1515         step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1516
1517         /* do a linear interpolation to get in-between values */
1518         return log_val + log10x_x1000[i - 1] +
1519                 ((diff_val*step_log10) / step_val);
1520 }
1521
1522 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1523 {
1524         u32 mse; /* Mean-Square Error */
1525         u32 pwr; /* Constelation power */
1526         u32 snr_x100;
1527
1528         mse = (read_reg(state, 0x00ec) << 8) |
1529               (read_reg(state, 0x00ed));
1530         pwr = (read_reg(state, 0x00e8) << 8) |
1531               (read_reg(state, 0x00e9));
1532
1533         if (mse == 0) /* no signal */
1534                 return 0;
1535
1536         snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
1537         dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1538
1539         return snr_x100;
1540 }
1541
1542 static enum lgdt3306a_lock_status
1543 lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1544 {
1545         int ret;
1546         u8 cnt = 0;
1547         u8 packet_error;
1548         u32 snr;
1549
1550         for (cnt = 0; cnt < 10; cnt++) {
1551                 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1552                         dbg_info("no sync lock!\n");
1553                         return LG3306_UNLOCK;
1554                 }
1555
1556                 msleep(20);
1557                 ret = lgdt3306a_pre_monitoring(state);
1558                 if (ret)
1559                         break;
1560
1561                 packet_error = lgdt3306a_get_packet_error(state);
1562                 snr = lgdt3306a_calculate_snr_x100(state);
1563                 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1564
1565                 if ((snr >= 1500) && (packet_error < 0xff))
1566                         return LG3306_LOCK;
1567         }
1568
1569         dbg_info("not locked!\n");
1570         return LG3306_UNLOCK;
1571 }
1572
1573 static enum lgdt3306a_lock_status
1574 lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1575 {
1576         u8 cnt;
1577         u8 packet_error;
1578         u32     snr;
1579
1580         for (cnt = 0; cnt < 10; cnt++) {
1581                 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1582                         dbg_info("no fec lock!\n");
1583                         return LG3306_UNLOCK;
1584                 }
1585
1586                 msleep(20);
1587
1588                 packet_error = lgdt3306a_get_packet_error(state);
1589                 snr = lgdt3306a_calculate_snr_x100(state);
1590                 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1591
1592                 if ((snr >= 1500) && (packet_error < 0xff))
1593                         return LG3306_LOCK;
1594         }
1595
1596         dbg_info("not locked!\n");
1597         return LG3306_UNLOCK;
1598 }
1599
1600 static int lgdt3306a_read_status(struct dvb_frontend *fe,
1601                                  enum fe_status *status)
1602 {
1603         struct lgdt3306a_state *state = fe->demodulator_priv;
1604         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1605         u16 strength = 0;
1606         int ret = 0;
1607
1608         if (fe->ops.tuner_ops.get_rf_strength) {
1609                 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1610                 if (ret == 0)
1611                         dbg_info("strength=%d\n", strength);
1612                 else
1613                         dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
1614         }
1615
1616         *status = 0;
1617         if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1618                 *status |= FE_HAS_SIGNAL;
1619                 *status |= FE_HAS_CARRIER;
1620
1621                 switch (state->current_modulation) {
1622                 case QAM_256:
1623                 case QAM_64:
1624                 case QAM_AUTO:
1625                         if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1626                                 *status |= FE_HAS_VITERBI;
1627                                 *status |= FE_HAS_SYNC;
1628
1629                                 *status |= FE_HAS_LOCK;
1630                         }
1631                         break;
1632                 case VSB_8:
1633                         if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1634                                 *status |= FE_HAS_VITERBI;
1635                                 *status |= FE_HAS_SYNC;
1636
1637                                 *status |= FE_HAS_LOCK;
1638
1639                                 ret = lgdt3306a_monitor_vsb(state);
1640                         }
1641                         break;
1642                 default:
1643                         ret = -EINVAL;
1644                 }
1645
1646                 if (*status & FE_HAS_SYNC) {
1647                         c->cnr.len = 1;
1648                         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1649                         c->cnr.stat[0].svalue = lgdt3306a_calculate_snr_x100(state) * 10;
1650                 } else {
1651                         c->cnr.len = 1;
1652                         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1653                 }
1654         }
1655         return ret;
1656 }
1657
1658
1659 static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1660 {
1661         struct lgdt3306a_state *state = fe->demodulator_priv;
1662
1663         state->snr = lgdt3306a_calculate_snr_x100(state);
1664         /* report SNR in dB * 10 */
1665         *snr = state->snr/10;
1666
1667         return 0;
1668 }
1669
1670 static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1671                                          u16 *strength)
1672 {
1673         /*
1674          * Calculate some sort of "strength" from SNR
1675          */
1676         struct lgdt3306a_state *state = fe->demodulator_priv;
1677         u8 val;
1678         u16 snr; /* snr_x10 */
1679         int ret;
1680         u32 ref_snr; /* snr*100 */
1681         u32 str;
1682
1683         *strength = 0;
1684
1685         switch (state->current_modulation) {
1686         case VSB_8:
1687                  ref_snr = 1600; /* 16dB */
1688                  break;
1689         case QAM_64:
1690         case QAM_256:
1691         case QAM_AUTO:
1692                 /* need to know actual modulation to set proper SNR baseline */
1693                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1694                 if (lg_chkerr(ret))
1695                         goto fail;
1696
1697                 if(val & 0x04)
1698                         ref_snr = 2800; /* QAM-256 28dB */
1699                 else
1700                         ref_snr = 2200; /* QAM-64  22dB */
1701                 break;
1702         default:
1703                 return -EINVAL;
1704         }
1705
1706         ret = fe->ops.read_snr(fe, &snr);
1707         if (lg_chkerr(ret))
1708                 goto fail;
1709
1710         if (state->snr <= (ref_snr - 100))
1711                 str = 0;
1712         else if (state->snr <= ref_snr)
1713                 str = (0xffff * 65) / 100; /* 65% */
1714         else {
1715                 str = state->snr - ref_snr;
1716                 str /= 50;
1717                 str += 78; /* 78%-100% */
1718                 if (str > 100)
1719                         str = 100;
1720                 str = (0xffff * str) / 100;
1721         }
1722         *strength = (u16)str;
1723         dbg_info("strength=%u\n", *strength);
1724
1725 fail:
1726         return ret;
1727 }
1728
1729 /* ------------------------------------------------------------------------ */
1730
1731 static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1732 {
1733         struct lgdt3306a_state *state = fe->demodulator_priv;
1734         u32 tmp;
1735
1736         *ber = 0;
1737 #if 1
1738         /* FGR - FIXME - I don't know what value is expected by dvb_core
1739          * what is the scale of the value?? */
1740         tmp =              read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1741         tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1742         tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1743         tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
1744         *ber = tmp;
1745         dbg_info("ber=%u\n", tmp);
1746 #endif
1747         return 0;
1748 }
1749
1750 static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1751 {
1752         struct lgdt3306a_state *state = fe->demodulator_priv;
1753
1754         *ucblocks = 0;
1755 #if 1
1756         /* FGR - FIXME - I don't know what value is expected by dvb_core
1757          * what happens when value wraps? */
1758         *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
1759         dbg_info("ucblocks=%u\n", *ucblocks);
1760 #endif
1761
1762         return 0;
1763 }
1764
1765 static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1766                           unsigned int mode_flags, unsigned int *delay,
1767                           enum fe_status *status)
1768 {
1769         int ret = 0;
1770         struct lgdt3306a_state *state = fe->demodulator_priv;
1771
1772         dbg_info("re_tune=%u\n", re_tune);
1773
1774         if (re_tune) {
1775                 state->current_frequency = -1; /* force re-tune */
1776                 ret = lgdt3306a_set_parameters(fe);
1777                 if (ret != 0)
1778                         return ret;
1779         }
1780         *delay = 125;
1781         ret = lgdt3306a_read_status(fe, status);
1782
1783         return ret;
1784 }
1785
1786 static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
1787                                        struct dvb_frontend_tune_settings
1788                                        *fe_tune_settings)
1789 {
1790         fe_tune_settings->min_delay_ms = 100;
1791         dbg_info("\n");
1792         return 0;
1793 }
1794
1795 static enum dvbfe_search lgdt3306a_search(struct dvb_frontend *fe)
1796 {
1797         enum fe_status status = 0;
1798         int ret;
1799
1800         /* set frontend */
1801         ret = lgdt3306a_set_parameters(fe);
1802         if (ret)
1803                 goto error;
1804
1805         ret = lgdt3306a_read_status(fe, &status);
1806         if (ret)
1807                 goto error;
1808
1809         /* check if we have a valid signal */
1810         if (status & FE_HAS_LOCK)
1811                 return DVBFE_ALGO_SEARCH_SUCCESS;
1812         else
1813                 return DVBFE_ALGO_SEARCH_AGAIN;
1814
1815 error:
1816         dbg_info("failed (%d)\n", ret);
1817         return DVBFE_ALGO_SEARCH_ERROR;
1818 }
1819
1820 static void lgdt3306a_release(struct dvb_frontend *fe)
1821 {
1822         struct lgdt3306a_state *state = fe->demodulator_priv;
1823
1824         dbg_info("\n");
1825         kfree(state);
1826 }
1827
1828 static const struct dvb_frontend_ops lgdt3306a_ops;
1829
1830 struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
1831                                       struct i2c_adapter *i2c_adap)
1832 {
1833         struct lgdt3306a_state *state = NULL;
1834         int ret;
1835         u8 val;
1836
1837         dbg_info("(%d-%04x)\n",
1838                i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1839                config ? config->i2c_addr : 0);
1840
1841         state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1842         if (state == NULL)
1843                 goto fail;
1844
1845         state->cfg = config;
1846         state->i2c_adap = i2c_adap;
1847
1848         memcpy(&state->frontend.ops, &lgdt3306a_ops,
1849                sizeof(struct dvb_frontend_ops));
1850         state->frontend.demodulator_priv = state;
1851
1852         /* verify that we're talking to a lg3306a */
1853         /* FGR - NOTE - there is no obvious ChipId to check; we check
1854          * some "known" bits after reset, but it's still just a guess */
1855         ret = lgdt3306a_read_reg(state, 0x0000, &val);
1856         if (lg_chkerr(ret))
1857                 goto fail;
1858         if ((val & 0x74) != 0x74) {
1859                 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1860 #if 0
1861                 /* FIXME - re-enable when we know this is right */
1862                 goto fail;
1863 #endif
1864         }
1865         ret = lgdt3306a_read_reg(state, 0x0001, &val);
1866         if (lg_chkerr(ret))
1867                 goto fail;
1868         if ((val & 0xf6) != 0xc6) {
1869                 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
1870 #if 0
1871                 /* FIXME - re-enable when we know this is right */
1872                 goto fail;
1873 #endif
1874         }
1875         ret = lgdt3306a_read_reg(state, 0x0002, &val);
1876         if (lg_chkerr(ret))
1877                 goto fail;
1878         if ((val & 0x73) != 0x03) {
1879                 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
1880 #if 0
1881                 /* FIXME - re-enable when we know this is right */
1882                 goto fail;
1883 #endif
1884         }
1885
1886         state->current_frequency = -1;
1887         state->current_modulation = -1;
1888
1889         lgdt3306a_sleep(state);
1890
1891         return &state->frontend;
1892
1893 fail:
1894         pr_warn("unable to detect LGDT3306A hardware\n");
1895         kfree(state);
1896         return NULL;
1897 }
1898 EXPORT_SYMBOL(lgdt3306a_attach);
1899
1900 #ifdef DBG_DUMP
1901
1902 static const short regtab[] = {
1903         0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1904         0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1905         0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1906         0x0003, /* AGCRFOUT */
1907         0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1908         0x0005, /* PLLINDIVSE */
1909         0x0006, /* PLLCTRL[7:0] 11100001 */
1910         0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1911         0x0008, /* STDOPMODE[7:0] 10000000 */
1912         0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1913         0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1914         0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1915         0x000d, /* x SAMPLING4 */
1916         0x000e, /* SAMFREQ[15:8] 00000000 */
1917         0x000f, /* SAMFREQ[7:0] 00000000 */
1918         0x0010, /* IFFREQ[15:8] 01100000 */
1919         0x0011, /* IFFREQ[7:0] 00000000 */
1920         0x0012, /* AGCEN AGCREFMO */
1921         0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1922         0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1923         0x0015, /* AGCREF[15:8] 00001010 */
1924         0x0016, /* AGCREF[7:0] 11100100 */
1925         0x0017, /* AGCDELAY[7:0] 00100000 */
1926         0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1927         0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1928         0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1929         0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1930         0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1931         0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1932         0x0020, /* AICCDETTH[15:8] 01111100 */
1933         0x0021, /* AICCDETTH[7:0] 00000000 */
1934         0x0022, /* AICCOFFTH[15:8] 00000101 */
1935         0x0023, /* AICCOFFTH[7:0] 11100000 */
1936         0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1937         0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1938         0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1939         0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1940         0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1941         0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1942         0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1943         0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1944         0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1945         0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1946         0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1947         0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
1948         0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1949         0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1950         0x0032, /* DAGC1STEN DAGC1STER */
1951         0x0033, /* DAGC1STREF[15:8] 00001010 */
1952         0x0034, /* DAGC1STREF[7:0] 11100100 */
1953         0x0035, /* DAGC2NDE */
1954         0x0036, /* DAGC2NDREF[15:8] 00001010 */
1955         0x0037, /* DAGC2NDREF[7:0] 10000000 */
1956         0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1957         0x003d, /* 1'b1 SAMGEARS */
1958         0x0040, /* SAMLFGMA */
1959         0x0041, /* SAMLFBWM */
1960         0x0044, /* 1'b1 CRGEARSHE */
1961         0x0045, /* CRLFGMAN */
1962         0x0046, /* CFLFBWMA */
1963         0x0047, /* CRLFGMAN */
1964         0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1965         0x0049, /* CRLFBWMA */
1966         0x004a, /* CRLFBWMA */
1967         0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1968         0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1969         0x0071, /* TPSENB TPSSOPBITE */
1970         0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1971         0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1972         0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1973         0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1974         0x0078, /* NBERPOLY[31:24] 00000000 */
1975         0x0079, /* NBERPOLY[23:16] 00000000 */
1976         0x007a, /* NBERPOLY[15:8] 00000000 */
1977         0x007b, /* NBERPOLY[7:0] 00000000 */
1978         0x007c, /* NBERPED[31:24] 00000000 */
1979         0x007d, /* NBERPED[23:16] 00000000 */
1980         0x007e, /* NBERPED[15:8] 00000000 */
1981         0x007f, /* NBERPED[7:0] 00000000 */
1982         0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1983         0x0085, /* SPECINVST */
1984         0x0088, /* SYSLOCKTIME[15:8] */
1985         0x0089, /* SYSLOCKTIME[7:0] */
1986         0x008c, /* FECLOCKTIME[15:8] */
1987         0x008d, /* FECLOCKTIME[7:0] */
1988         0x008e, /* AGCACCOUT[15:8] */
1989         0x008f, /* AGCACCOUT[7:0] */
1990         0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1991         0x0091, /* AICCVSYNC */
1992         0x009c, /* CARRFREQOFFSET[15:8] */
1993         0x009d, /* CARRFREQOFFSET[7:0] */
1994         0x00a1, /* SAMFREQOFFSET[23:16] */
1995         0x00a2, /* SAMFREQOFFSET[15:8] */
1996         0x00a3, /* SAMFREQOFFSET[7:0] */
1997         0x00a6, /* SYNCLOCK SYNCLOCKH */
1998 #if 0 /* covered elsewhere */
1999         0x00e8, /* CONSTPWR[15:8] */
2000         0x00e9, /* CONSTPWR[7:0] */
2001         0x00ea, /* BMSE[15:8] */
2002         0x00eb, /* BMSE[7:0] */
2003         0x00ec, /* MSE[15:8] */
2004         0x00ed, /* MSE[7:0] */
2005         0x00ee, /* CONSTI[7:0] */
2006         0x00ef, /* CONSTQ[7:0] */
2007 #endif
2008         0x00f4, /* TPIFTPERRCNT[7:0] */
2009         0x00f5, /* TPCORREC */
2010         0x00f6, /* VBBER[15:8] */
2011         0x00f7, /* VBBER[7:0] */
2012         0x00f8, /* VABER[15:8] */
2013         0x00f9, /* VABER[7:0] */
2014         0x00fa, /* TPERRCNT[7:0] */
2015         0x00fb, /* NBERLOCK x x x x x x x */
2016         0x00fc, /* NBERVALUE[31:24] */
2017         0x00fd, /* NBERVALUE[23:16] */
2018         0x00fe, /* NBERVALUE[15:8] */
2019         0x00ff, /* NBERVALUE[7:0] */
2020         0x1000, /* 1'b0 WODAGCOU */
2021         0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
2022         0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
2023         0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
2024         0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
2025         0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
2026         0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
2027         0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
2028         0x103f, /* SAMZTEDSE */
2029         0x105d, /* EQSTATUSE */
2030         0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
2031         0x1060, /* 1'b1 EQSTATUSE */
2032         0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
2033         0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
2034         0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
2035         0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
2036         0x106e, /* x x x x x CREPHNEN_ */
2037         0x106f, /* CREPHNTH_V[7:0] 00010101 */
2038         0x1072, /* CRSWEEPN */
2039         0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
2040         0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
2041         0x1080, /* DAFTSTATUS[1:0] x x x x x x */
2042         0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
2043         0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
2044         0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
2045 #if 0 /* SMART_ANT */
2046         0x1f00, /* MODEDETE */
2047         0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
2048         0x1f03, /* NUMOFANT[7:0] 10000000 */
2049         0x1f04, /* x SELMASK[6:0] x0000000 */
2050         0x1f05, /* x SETMASK[6:0] x0000000 */
2051         0x1f06, /* x TXDATA[6:0] x0000000 */
2052         0x1f07, /* x CHNUMBER[6:0] x0000000 */
2053         0x1f09, /* AGCTIME[23:16] 10011000 */
2054         0x1f0a, /* AGCTIME[15:8] 10010110 */
2055         0x1f0b, /* AGCTIME[7:0] 10000000 */
2056         0x1f0c, /* ANTTIME[31:24] 00000000 */
2057         0x1f0d, /* ANTTIME[23:16] 00000011 */
2058         0x1f0e, /* ANTTIME[15:8] 10010000 */
2059         0x1f0f, /* ANTTIME[7:0] 10010000 */
2060         0x1f11, /* SYNCTIME[23:16] 10011000 */
2061         0x1f12, /* SYNCTIME[15:8] 10010110 */
2062         0x1f13, /* SYNCTIME[7:0] 10000000 */
2063         0x1f14, /* SNRTIME[31:24] 00000001 */
2064         0x1f15, /* SNRTIME[23:16] 01111101 */
2065         0x1f16, /* SNRTIME[15:8] 01111000 */
2066         0x1f17, /* SNRTIME[7:0] 01000000 */
2067         0x1f19, /* FECTIME[23:16] 00000000 */
2068         0x1f1a, /* FECTIME[15:8] 01110010 */
2069         0x1f1b, /* FECTIME[7:0] 01110000 */
2070         0x1f1d, /* FECTHD[7:0] 00000011 */
2071         0x1f1f, /* SNRTHD[23:16] 00001000 */
2072         0x1f20, /* SNRTHD[15:8] 01111111 */
2073         0x1f21, /* SNRTHD[7:0] 10000101 */
2074         0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2075         0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2076         0x1f82, /* x x x SCANOPCD[4:0] */
2077         0x1f83, /* x x x x MAINOPCD[3:0] */
2078         0x1f84, /* x x RXDATA[13:8] */
2079         0x1f85, /* RXDATA[7:0] */
2080         0x1f86, /* x x SDTDATA[13:8] */
2081         0x1f87, /* SDTDATA[7:0] */
2082         0x1f89, /* ANTSNR[23:16] */
2083         0x1f8a, /* ANTSNR[15:8] */
2084         0x1f8b, /* ANTSNR[7:0] */
2085         0x1f8c, /* x x x x ANTFEC[13:8] */
2086         0x1f8d, /* ANTFEC[7:0] */
2087         0x1f8e, /* MAXCNT[7:0] */
2088         0x1f8f, /* SCANCNT[7:0] */
2089         0x1f91, /* MAXPW[23:16] */
2090         0x1f92, /* MAXPW[15:8] */
2091         0x1f93, /* MAXPW[7:0] */
2092         0x1f95, /* CURPWMSE[23:16] */
2093         0x1f96, /* CURPWMSE[15:8] */
2094         0x1f97, /* CURPWMSE[7:0] */
2095 #endif /* SMART_ANT */
2096         0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2097         0x212a, /* EQAUTOST */
2098         0x2122, /* CHFAST[7:0] 01100000 */
2099         0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2100         0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2101         0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
2102         0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2103         0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2104         0x2162, /* AICCCTRLE */
2105         0x2173, /* PHNCNFCNT[7:0] 00000100 */
2106         0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
2107         0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2108         0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2109         0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
2110         0x2180, /* x x x x x x FBDLYCIR[9:8] */
2111         0x2181, /* FBDLYCIR[7:0] */
2112         0x2185, /* MAXPWRMAIN[7:0] */
2113         0x2191, /* NCOMBDET x x x x x x x */
2114         0x2199, /* x MAINSTRON */
2115         0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2116         0x21a1, /* x x SNRREF[5:0] */
2117         0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2118         0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2119         0x2847, /* ENNOSIGDE */
2120         0x2849, /* 1'b1 1'b1 NOUSENOSI */
2121         0x284a, /* EQINITWAITTIME[7:0] 01100100 */
2122         0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2123         0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2124         0x3031, /* FRAMELOC */
2125         0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
2126         0x30a9, /* VDLOCK_Q FRAMELOCK */
2127         0x30aa, /* MPEGLOCK */
2128 };
2129
2130 #define numDumpRegs (ARRAY_SIZE(regtab))
2131 static u8 regval1[numDumpRegs] = {0, };
2132 static u8 regval2[numDumpRegs] = {0, };
2133
2134 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2135 {
2136                 memset(regval2, 0xff, sizeof(regval2));
2137                 lgdt3306a_DumpRegs(state);
2138 }
2139
2140 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2141 {
2142         int i;
2143         int sav_debug = debug;
2144
2145         if ((debug & DBG_DUMP) == 0)
2146                 return;
2147         debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
2148
2149         lg_debug("\n");
2150
2151         for (i = 0; i < numDumpRegs; i++) {
2152                 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
2153                 if (regval1[i] != regval2[i]) {
2154                         lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
2155                         regval2[i] = regval1[i];
2156                 }
2157         }
2158         debug = sav_debug;
2159 }
2160 #endif /* DBG_DUMP */
2161
2162
2163
2164 static const struct dvb_frontend_ops lgdt3306a_ops = {
2165         .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2166         .info = {
2167                 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
2168                 .frequency_min_hz      =  54 * MHz,
2169                 .frequency_max_hz      = 858 * MHz,
2170                 .frequency_stepsize_hz = 62500,
2171                 .caps = FE_CAN_QAM_AUTO | FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2172         },
2173         .i2c_gate_ctrl        = lgdt3306a_i2c_gate_ctrl,
2174         .init                 = lgdt3306a_init,
2175         .sleep                = lgdt3306a_fe_sleep,
2176         /* if this is set, it overrides the default swzigzag */
2177         .tune                 = lgdt3306a_tune,
2178         .set_frontend         = lgdt3306a_set_parameters,
2179         .get_frontend         = lgdt3306a_get_frontend,
2180         .get_frontend_algo    = lgdt3306a_get_frontend_algo,
2181         .get_tune_settings    = lgdt3306a_get_tune_settings,
2182         .read_status          = lgdt3306a_read_status,
2183         .read_ber             = lgdt3306a_read_ber,
2184         .read_signal_strength = lgdt3306a_read_signal_strength,
2185         .read_snr             = lgdt3306a_read_snr,
2186         .read_ucblocks        = lgdt3306a_read_ucblocks,
2187         .release              = lgdt3306a_release,
2188         .ts_bus_ctrl          = lgdt3306a_ts_bus_ctrl,
2189         .search               = lgdt3306a_search,
2190 };
2191
2192 static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2193 {
2194         struct i2c_client *client = i2c_mux_priv(muxc);
2195         struct lgdt3306a_state *state = i2c_get_clientdata(client);
2196
2197         return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2198 }
2199
2200 static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2201 {
2202         struct i2c_client *client = i2c_mux_priv(muxc);
2203         struct lgdt3306a_state *state = i2c_get_clientdata(client);
2204
2205         return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2206 }
2207
2208 static int lgdt3306a_probe(struct i2c_client *client,
2209                 const struct i2c_device_id *id)
2210 {
2211         struct lgdt3306a_config *config;
2212         struct lgdt3306a_state *state;
2213         struct dvb_frontend *fe;
2214         int ret;
2215
2216         config = kmemdup(client->dev.platform_data,
2217                          sizeof(struct lgdt3306a_config), GFP_KERNEL);
2218         if (config == NULL) {
2219                 ret = -ENOMEM;
2220                 goto fail;
2221         }
2222
2223         config->i2c_addr = client->addr;
2224         fe = lgdt3306a_attach(config, client->adapter);
2225         if (fe == NULL) {
2226                 ret = -ENODEV;
2227                 goto err_fe;
2228         }
2229
2230         i2c_set_clientdata(client, fe->demodulator_priv);
2231         state = fe->demodulator_priv;
2232         state->frontend.ops.release = NULL;
2233
2234         /* create mux i2c adapter for tuner */
2235         state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2236                                   1, 0, I2C_MUX_LOCKED,
2237                                   lgdt3306a_select, lgdt3306a_deselect);
2238         if (!state->muxc) {
2239                 ret = -ENOMEM;
2240                 goto err_kfree;
2241         }
2242         state->muxc->priv = client;
2243         ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2244         if (ret)
2245                 goto err_kfree;
2246
2247         /* create dvb_frontend */
2248         fe->ops.i2c_gate_ctrl = NULL;
2249         *config->i2c_adapter = state->muxc->adapter[0];
2250         *config->fe = fe;
2251
2252         dev_info(&client->dev, "LG Electronics LGDT3306A successfully identified\n");
2253
2254         return 0;
2255
2256 err_kfree:
2257         kfree(state);
2258 err_fe:
2259         kfree(config);
2260 fail:
2261         dev_warn(&client->dev, "probe failed = %d\n", ret);
2262         return ret;
2263 }
2264
2265 static int lgdt3306a_remove(struct i2c_client *client)
2266 {
2267         struct lgdt3306a_state *state = i2c_get_clientdata(client);
2268
2269         i2c_mux_del_adapters(state->muxc);
2270
2271         state->frontend.ops.release = NULL;
2272         state->frontend.demodulator_priv = NULL;
2273
2274         kfree(state->cfg);
2275         kfree(state);
2276
2277         return 0;
2278 }
2279
2280 static const struct i2c_device_id lgdt3306a_id_table[] = {
2281         {"lgdt3306a", 0},
2282         {}
2283 };
2284 MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2285
2286 static struct i2c_driver lgdt3306a_driver = {
2287         .driver = {
2288                 .name                = "lgdt3306a",
2289                 .suppress_bind_attrs = true,
2290         },
2291         .probe          = lgdt3306a_probe,
2292         .remove         = lgdt3306a_remove,
2293         .id_table       = lgdt3306a_id_table,
2294 };
2295
2296 module_i2c_driver(lgdt3306a_driver);
2297
2298 MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2299 MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2300 MODULE_LICENSE("GPL");
2301 MODULE_VERSION("0.2");