drivers/media/dvb-frontends/drxk_hard.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drxk_hard: DRX-K DVB-C/T demodulator driver
   4  *
   5  * Copyright (C) 2010-2011 Digital Devices GmbH
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/delay.h>
  15 #include <linux/firmware.h>
  16 #include <linux/i2c.h>
  17 #include <linux/hardirq.h>
  18 #include <asm/div64.h>
  19
  20 #include <media/dvb_frontend.h>
  21 #include "drxk.h"
  22 #include "drxk_hard.h"
  23 #include <media/dvb_math.h>
  24
  25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
  26 static int power_down_qam(struct drxk_state *state);
  27 static int set_dvbt_standard(struct drxk_state *state,
  28                            enum operation_mode o_mode);
  29 static int set_qam_standard(struct drxk_state *state,
  30                           enum operation_mode o_mode);
  31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
  32                   s32 tuner_freq_offset);
  33 static int set_dvbt_standard(struct drxk_state *state,
  34                            enum operation_mode o_mode);
  35 static int dvbt_start(struct drxk_state *state);
  36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
  37                    s32 tuner_freq_offset);
  38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
  39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
  40 static int switch_antenna_to_qam(struct drxk_state *state);
  41 static int switch_antenna_to_dvbt(struct drxk_state *state);
  42
  43 static bool is_dvbt(struct drxk_state *state)
  44 {
  45         return state->m_operation_mode == OM_DVBT;
  46 }
  47
  48 static bool is_qam(struct drxk_state *state)
  49 {
  50         return state->m_operation_mode == OM_QAM_ITU_A ||
  51             state->m_operation_mode == OM_QAM_ITU_B ||
  52             state->m_operation_mode == OM_QAM_ITU_C;
  53 }
  54
  55 #define NOA1ROM 0
  56
  57 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
  58 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
  59
  60 #define DEFAULT_MER_83  165
  61 #define DEFAULT_MER_93  250
  62
  63 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
  64 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
  65 #endif
  66
  67 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
  68 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
  69 #endif
  70
  71 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
  72 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
  73
  74 #ifndef DRXK_KI_RAGC_ATV
  75 #define DRXK_KI_RAGC_ATV   4
  76 #endif
  77 #ifndef DRXK_KI_IAGC_ATV
  78 #define DRXK_KI_IAGC_ATV   6
  79 #endif
  80 #ifndef DRXK_KI_DAGC_ATV
  81 #define DRXK_KI_DAGC_ATV   7
  82 #endif
  83
  84 #ifndef DRXK_KI_RAGC_QAM
  85 #define DRXK_KI_RAGC_QAM   3
  86 #endif
  87 #ifndef DRXK_KI_IAGC_QAM
  88 #define DRXK_KI_IAGC_QAM   4
  89 #endif
  90 #ifndef DRXK_KI_DAGC_QAM
  91 #define DRXK_KI_DAGC_QAM   7
  92 #endif
  93 #ifndef DRXK_KI_RAGC_DVBT
  94 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
  95 #endif
  96 #ifndef DRXK_KI_IAGC_DVBT
  97 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
  98 #endif
  99 #ifndef DRXK_KI_DAGC_DVBT
 100 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
 101 #endif
 102
 103 #ifndef DRXK_AGC_DAC_OFFSET
 104 #define DRXK_AGC_DAC_OFFSET (0x800)
 105 #endif
 106
 107 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
 108 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
 109 #endif
 110
 111 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
 112 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
 113 #endif
 114
 115 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
 116 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
 117 #endif
 118
 119 #ifndef DRXK_QAM_SYMBOLRATE_MAX
 120 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
 121 #endif
 122
 123 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
 124 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
 125 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
 126 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
 127 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
 128 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
 129 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
 130 #define DRXK_BL_ROM_OFFSET_UCODE        0
 131
 132 #define DRXK_BLC_TIMEOUT                100
 133
 134 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
 135 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
 136
 137 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
 138
 139 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
 140 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
 141 #endif
 142
 143 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
 144 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
 145 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
 146 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
 147 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
 148
 149 static unsigned int debug;
 150 module_param(debug, int, 0644);
 151 MODULE_PARM_DESC(debug, "enable debug messages");
 152
 153 #define dprintk(level, fmt, arg...) do {                                \
 154 if (debug >= level)                                                     \
 155         printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
 156 } while (0)
 157
 158
 159 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 160 {
 161         u64 tmp64;
 162
 163         tmp64 = (u64) a * (u64) b;
 164         do_div(tmp64, c);
 165
 166         return (u32) tmp64;
 167 }
 168
 169 static inline u32 Frac28a(u32 a, u32 c)
 170 {
 171         int i = 0;
 172         u32 Q1 = 0;
 173         u32 R0 = 0;
 174
 175         R0 = (a % c) << 4;      /* 32-28 == 4 shifts possible at max */
 176         Q1 = a / c;             /*
 177                                  * integer part, only the 4 least significant
 178                                  * bits will be visible in the result
 179                                  */
 180
 181         /* division using radix 16, 7 nibbles in the result */
 182         for (i = 0; i < 7; i++) {
 183                 Q1 = (Q1 << 4) | (R0 / c);
 184                 R0 = (R0 % c) << 4;
 185         }
 186         /* rounding */
 187         if ((R0 >> 3) >= c)
 188                 Q1++;
 189
 190         return Q1;
 191 }
 192
 193 static inline u32 log10times100(u32 value)
 194 {
 195         return (100L * intlog10(value)) >> 24;
 196 }
 197
 198 /***************************************************************************/
 199 /* I2C **********************************************************************/
 200 /***************************************************************************/
 201
 202 static int drxk_i2c_lock(struct drxk_state *state)
 203 {
 204         i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
 205         state->drxk_i2c_exclusive_lock = true;
 206
 207         return 0;
 208 }
 209
 210 static void drxk_i2c_unlock(struct drxk_state *state)
 211 {
 212         if (!state->drxk_i2c_exclusive_lock)
 213                 return;
 214
 215         i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
 216         state->drxk_i2c_exclusive_lock = false;
 217 }
 218
 219 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
 220                              unsigned len)
 221 {
 222         if (state->drxk_i2c_exclusive_lock)
 223                 return __i2c_transfer(state->i2c, msgs, len);
 224         else
 225                 return i2c_transfer(state->i2c, msgs, len);
 226 }
 227
 228 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
 229 {
 230         struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
 231                                     .buf = val, .len = 1}
 232         };
 233
 234         return drxk_i2c_transfer(state, msgs, 1);
 235 }
 236
 237 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
 238 {
 239         int status;
 240         struct i2c_msg msg = {
 241             .addr = adr, .flags = 0, .buf = data, .len = len };
 242
 243         dprintk(3, ":");
 244         if (debug > 2) {
 245                 int i;
 246                 for (i = 0; i < len; i++)
 247                         pr_cont(" %02x", data[i]);
 248                 pr_cont("\n");
 249         }
 250         status = drxk_i2c_transfer(state, &msg, 1);
 251         if (status >= 0 && status != 1)
 252                 status = -EIO;
 253
 254         if (status < 0)
 255                 pr_err("i2c write error at addr 0x%02x\n", adr);
 256
 257         return status;
 258 }
 259
 260 static int i2c_read(struct drxk_state *state,
 261                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 262 {
 263         int status;
 264         struct i2c_msg msgs[2] = {
 265                 {.addr = adr, .flags = 0,
 266                                     .buf = msg, .len = len},
 267                 {.addr = adr, .flags = I2C_M_RD,
 268                  .buf = answ, .len = alen}
 269         };
 270
 271         status = drxk_i2c_transfer(state, msgs, 2);
 272         if (status != 2) {
 273                 if (debug > 2)
 274                         pr_cont(": ERROR!\n");
 275                 if (status >= 0)
 276                         status = -EIO;
 277
 278                 pr_err("i2c read error at addr 0x%02x\n", adr);
 279                 return status;
 280         }
 281         if (debug > 2) {
 282                 int i;
 283                 dprintk(2, ": read from");
 284                 for (i = 0; i < len; i++)
 285                         pr_cont(" %02x", msg[i]);
 286                 pr_cont(", value = ");
 287                 for (i = 0; i < alen; i++)
 288                         pr_cont(" %02x", answ[i]);
 289                 pr_cont("\n");
 290         }
 291         return 0;
 292 }
 293
 294 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
 295 {
 296         int status;
 297         u8 adr = state->demod_address, mm1[4], mm2[2], len;
 298
 299         if (state->single_master)
 300                 flags |= 0xC0;
 301
 302         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 303                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 304                 mm1[1] = ((reg >> 16) & 0xFF);
 305                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 306                 mm1[3] = ((reg >> 7) & 0xFF);
 307                 len = 4;
 308         } else {
 309                 mm1[0] = ((reg << 1) & 0xFF);
 310                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 311                 len = 2;
 312         }
 313         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 314         status = i2c_read(state, adr, mm1, len, mm2, 2);
 315         if (status < 0)
 316                 return status;
 317         if (data)
 318                 *data = mm2[0] | (mm2[1] << 8);
 319
 320         return 0;
 321 }
 322
 323 static int read16(struct drxk_state *state, u32 reg, u16 *data)
 324 {
 325         return read16_flags(state, reg, data, 0);
 326 }
 327
 328 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
 329 {
 330         int status;
 331         u8 adr = state->demod_address, mm1[4], mm2[4], len;
 332
 333         if (state->single_master)
 334                 flags |= 0xC0;
 335
 336         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 337                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 338                 mm1[1] = ((reg >> 16) & 0xFF);
 339                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 340                 mm1[3] = ((reg >> 7) & 0xFF);
 341                 len = 4;
 342         } else {
 343                 mm1[0] = ((reg << 1) & 0xFF);
 344                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 345                 len = 2;
 346         }
 347         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 348         status = i2c_read(state, adr, mm1, len, mm2, 4);
 349         if (status < 0)
 350                 return status;
 351         if (data)
 352                 *data = mm2[0] | (mm2[1] << 8) |
 353                     (mm2[2] << 16) | (mm2[3] << 24);
 354
 355         return 0;
 356 }
 357
 358 static int read32(struct drxk_state *state, u32 reg, u32 *data)
 359 {
 360         return read32_flags(state, reg, data, 0);
 361 }
 362
 363 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
 364 {
 365         u8 adr = state->demod_address, mm[6], len;
 366
 367         if (state->single_master)
 368                 flags |= 0xC0;
 369         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 370                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 371                 mm[1] = ((reg >> 16) & 0xFF);
 372                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 373                 mm[3] = ((reg >> 7) & 0xFF);
 374                 len = 4;
 375         } else {
 376                 mm[0] = ((reg << 1) & 0xFF);
 377                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 378                 len = 2;
 379         }
 380         mm[len] = data & 0xff;
 381         mm[len + 1] = (data >> 8) & 0xff;
 382
 383         dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
 384         return i2c_write(state, adr, mm, len + 2);
 385 }
 386
 387 static int write16(struct drxk_state *state, u32 reg, u16 data)
 388 {
 389         return write16_flags(state, reg, data, 0);
 390 }
 391
 392 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
 393 {
 394         u8 adr = state->demod_address, mm[8], len;
 395
 396         if (state->single_master)
 397                 flags |= 0xC0;
 398         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 399                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 400                 mm[1] = ((reg >> 16) & 0xFF);
 401                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 402                 mm[3] = ((reg >> 7) & 0xFF);
 403                 len = 4;
 404         } else {
 405                 mm[0] = ((reg << 1) & 0xFF);
 406                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 407                 len = 2;
 408         }
 409         mm[len] = data & 0xff;
 410         mm[len + 1] = (data >> 8) & 0xff;
 411         mm[len + 2] = (data >> 16) & 0xff;
 412         mm[len + 3] = (data >> 24) & 0xff;
 413         dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
 414
 415         return i2c_write(state, adr, mm, len + 4);
 416 }
 417
 418 static int write32(struct drxk_state *state, u32 reg, u32 data)
 419 {
 420         return write32_flags(state, reg, data, 0);
 421 }
 422
 423 static int write_block(struct drxk_state *state, u32 address,
 424                       const int block_size, const u8 p_block[])
 425 {
 426         int status = 0, blk_size = block_size;
 427         u8 flags = 0;
 428
 429         if (state->single_master)
 430                 flags |= 0xC0;
 431
 432         while (blk_size > 0) {
 433                 int chunk = blk_size > state->m_chunk_size ?
 434                     state->m_chunk_size : blk_size;
 435                 u8 *adr_buf = &state->chunk[0];
 436                 u32 adr_length = 0;
 437
 438                 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
 439                         adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
 440                         adr_buf[1] = ((address >> 16) & 0xFF);
 441                         adr_buf[2] = ((address >> 24) & 0xFF);
 442                         adr_buf[3] = ((address >> 7) & 0xFF);
 443                         adr_buf[2] |= flags;
 444                         adr_length = 4;
 445                         if (chunk == state->m_chunk_size)
 446                                 chunk -= 2;
 447                 } else {
 448                         adr_buf[0] = ((address << 1) & 0xFF);
 449                         adr_buf[1] = (((address >> 16) & 0x0F) |
 450                                      ((address >> 18) & 0xF0));
 451                         adr_length = 2;
 452                 }
 453                 memcpy(&state->chunk[adr_length], p_block, chunk);
 454                 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
 455                 if (debug > 1) {
 456                         int i;
 457                         if (p_block)
 458                                 for (i = 0; i < chunk; i++)
 459                                         pr_cont(" %02x", p_block[i]);
 460                         pr_cont("\n");
 461                 }
 462                 status = i2c_write(state, state->demod_address,
 463                                    &state->chunk[0], chunk + adr_length);
 464                 if (status < 0) {
 465                         pr_err("%s: i2c write error at addr 0x%02x\n",
 466                                __func__, address);
 467                         break;
 468                 }
 469                 p_block += chunk;
 470                 address += (chunk >> 1);
 471                 blk_size -= chunk;
 472         }
 473         return status;
 474 }
 475
 476 #ifndef DRXK_MAX_RETRIES_POWERUP
 477 #define DRXK_MAX_RETRIES_POWERUP 20
 478 #endif
 479
 480 static int power_up_device(struct drxk_state *state)
 481 {
 482         int status;
 483         u8 data = 0;
 484         u16 retry_count = 0;
 485
 486         dprintk(1, "\n");
 487
 488         status = i2c_read1(state, state->demod_address, &data);
 489         if (status < 0) {
 490                 do {
 491                         data = 0;
 492                         status = i2c_write(state, state->demod_address,
 493                                            &data, 1);
 494                         usleep_range(10000, 11000);
 495                         retry_count++;
 496                         if (status < 0)
 497                                 continue;
 498                         status = i2c_read1(state, state->demod_address,
 499                                            &data);
 500                 } while (status < 0 &&
 501                          (retry_count < DRXK_MAX_RETRIES_POWERUP));
 502                 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
 503                         goto error;
 504         }
 505
 506         /* Make sure all clk domains are active */
 507         status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
 508         if (status < 0)
 509                 goto error;
 510         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
 511         if (status < 0)
 512                 goto error;
 513         /* Enable pll lock tests */
 514         status = write16(state, SIO_CC_PLL_LOCK__A, 1);
 515         if (status < 0)
 516                 goto error;
 517
 518         state->m_current_power_mode = DRX_POWER_UP;
 519
 520 error:
 521         if (status < 0)
 522                 pr_err("Error %d on %s\n", status, __func__);
 523
 524         return status;
 525 }
 526
 527
 528 static int init_state(struct drxk_state *state)
 529 {
 530         /*
 531          * FIXME: most (all?) of the values below should be moved into
 532          * struct drxk_config, as they are probably board-specific
 533          */
 534         u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
 535         u32 ul_vsb_if_agc_output_level = 0;
 536         u32 ul_vsb_if_agc_min_level = 0;
 537         u32 ul_vsb_if_agc_max_level = 0x7FFF;
 538         u32 ul_vsb_if_agc_speed = 3;
 539
 540         u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
 541         u32 ul_vsb_rf_agc_output_level = 0;
 542         u32 ul_vsb_rf_agc_min_level = 0;
 543         u32 ul_vsb_rf_agc_max_level = 0x7FFF;
 544         u32 ul_vsb_rf_agc_speed = 3;
 545         u32 ul_vsb_rf_agc_top = 9500;
 546         u32 ul_vsb_rf_agc_cut_off_current = 4000;
 547
 548         u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
 549         u32 ul_atv_if_agc_output_level = 0;
 550         u32 ul_atv_if_agc_min_level = 0;
 551         u32 ul_atv_if_agc_max_level = 0;
 552         u32 ul_atv_if_agc_speed = 3;
 553
 554         u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
 555         u32 ul_atv_rf_agc_output_level = 0;
 556         u32 ul_atv_rf_agc_min_level = 0;
 557         u32 ul_atv_rf_agc_max_level = 0;
 558         u32 ul_atv_rf_agc_top = 9500;
 559         u32 ul_atv_rf_agc_cut_off_current = 4000;
 560         u32 ul_atv_rf_agc_speed = 3;
 561
 562         u32 ulQual83 = DEFAULT_MER_83;
 563         u32 ulQual93 = DEFAULT_MER_93;
 564
 565         u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 566         u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 567
 568         /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
 569         /* io_pad_cfg_mode output mode is drive always */
 570         /* io_pad_cfg_drive is set to power 2 (23 mA) */
 571         u32 ul_gpio_cfg = 0x0113;
 572         u32 ul_invert_ts_clock = 0;
 573         u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
 574         u32 ul_dvbt_bitrate = 50000000;
 575         u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
 576
 577         u32 ul_insert_rs_byte = 0;
 578
 579         u32 ul_rf_mirror = 1;
 580         u32 ul_power_down = 0;
 581
 582         dprintk(1, "\n");
 583
 584         state->m_has_lna = false;
 585         state->m_has_dvbt = false;
 586         state->m_has_dvbc = false;
 587         state->m_has_atv = false;
 588         state->m_has_oob = false;
 589         state->m_has_audio = false;
 590
 591         if (!state->m_chunk_size)
 592                 state->m_chunk_size = 124;
 593
 594         state->m_osc_clock_freq = 0;
 595         state->m_smart_ant_inverted = false;
 596         state->m_b_p_down_open_bridge = false;
 597
 598         /* real system clock frequency in kHz */
 599         state->m_sys_clock_freq = 151875;
 600         /* Timing div, 250ns/Psys */
 601         /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
 602         state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
 603                                    HI_I2C_DELAY) / 1000;
 604         /* Clipping */
 605         if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
 606                 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
 607         state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
 608         /* port/bridge/power down ctrl */
 609         state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
 610
 611         state->m_b_power_down = (ul_power_down != 0);
 612
 613         state->m_drxk_a3_patch_code = false;
 614
 615         /* Init AGC and PGA parameters */
 616         /* VSB IF */
 617         state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
 618         state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
 619         state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
 620         state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
 621         state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
 622         state->m_vsb_pga_cfg = 140;
 623
 624         /* VSB RF */
 625         state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
 626         state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
 627         state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
 628         state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
 629         state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
 630         state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
 631         state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
 632         state->m_vsb_pre_saw_cfg.reference = 0x07;
 633         state->m_vsb_pre_saw_cfg.use_pre_saw = true;
 634
 635         state->m_Quality83percent = DEFAULT_MER_83;
 636         state->m_Quality93percent = DEFAULT_MER_93;
 637         if (ulQual93 <= 500 && ulQual83 < ulQual93) {
 638                 state->m_Quality83percent = ulQual83;
 639                 state->m_Quality93percent = ulQual93;
 640         }
 641
 642         /* ATV IF */
 643         state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
 644         state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
 645         state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
 646         state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
 647         state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
 648
 649         /* ATV RF */
 650         state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
 651         state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
 652         state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
 653         state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
 654         state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
 655         state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
 656         state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
 657         state->m_atv_pre_saw_cfg.reference = 0x04;
 658         state->m_atv_pre_saw_cfg.use_pre_saw = true;
 659
 660
 661         /* DVBT RF */
 662         state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
 663         state->m_dvbt_rf_agc_cfg.output_level = 0;
 664         state->m_dvbt_rf_agc_cfg.min_output_level = 0;
 665         state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
 666         state->m_dvbt_rf_agc_cfg.top = 0x2100;
 667         state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
 668         state->m_dvbt_rf_agc_cfg.speed = 1;
 669
 670
 671         /* DVBT IF */
 672         state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
 673         state->m_dvbt_if_agc_cfg.output_level = 0;
 674         state->m_dvbt_if_agc_cfg.min_output_level = 0;
 675         state->m_dvbt_if_agc_cfg.max_output_level = 9000;
 676         state->m_dvbt_if_agc_cfg.top = 13424;
 677         state->m_dvbt_if_agc_cfg.cut_off_current = 0;
 678         state->m_dvbt_if_agc_cfg.speed = 3;
 679         state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
 680         state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
 681         /* state->m_dvbtPgaCfg = 140; */
 682
 683         state->m_dvbt_pre_saw_cfg.reference = 4;
 684         state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
 685
 686         /* QAM RF */
 687         state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
 688         state->m_qam_rf_agc_cfg.output_level = 0;
 689         state->m_qam_rf_agc_cfg.min_output_level = 6023;
 690         state->m_qam_rf_agc_cfg.max_output_level = 27000;
 691         state->m_qam_rf_agc_cfg.top = 0x2380;
 692         state->m_qam_rf_agc_cfg.cut_off_current = 4000;
 693         state->m_qam_rf_agc_cfg.speed = 3;
 694
 695         /* QAM IF */
 696         state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
 697         state->m_qam_if_agc_cfg.output_level = 0;
 698         state->m_qam_if_agc_cfg.min_output_level = 0;
 699         state->m_qam_if_agc_cfg.max_output_level = 9000;
 700         state->m_qam_if_agc_cfg.top = 0x0511;
 701         state->m_qam_if_agc_cfg.cut_off_current = 0;
 702         state->m_qam_if_agc_cfg.speed = 3;
 703         state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
 704         state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
 705
 706         state->m_qam_pga_cfg = 140;
 707         state->m_qam_pre_saw_cfg.reference = 4;
 708         state->m_qam_pre_saw_cfg.use_pre_saw = false;
 709
 710         state->m_operation_mode = OM_NONE;
 711         state->m_drxk_state = DRXK_UNINITIALIZED;
 712
 713         /* MPEG output configuration */
 714         state->m_enable_mpeg_output = true;     /* If TRUE; enable MPEG output */
 715         state->m_insert_rs_byte = false;        /* If TRUE; insert RS byte */
 716         state->m_invert_data = false;   /* If TRUE; invert DATA signals */
 717         state->m_invert_err = false;    /* If TRUE; invert ERR signal */
 718         state->m_invert_str = false;    /* If TRUE; invert STR signals */
 719         state->m_invert_val = false;    /* If TRUE; invert VAL signals */
 720         state->m_invert_clk = (ul_invert_ts_clock != 0);        /* If TRUE; invert CLK signals */
 721
 722         /* If TRUE; static MPEG clockrate will be used;
 723            otherwise clockrate will adapt to the bitrate of the TS */
 724
 725         state->m_dvbt_bitrate = ul_dvbt_bitrate;
 726         state->m_dvbc_bitrate = ul_dvbc_bitrate;
 727
 728         state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
 729
 730         /* Maximum bitrate in b/s in case static clockrate is selected */
 731         state->m_mpeg_ts_static_bitrate = 19392658;
 732         state->m_disable_te_ihandling = false;
 733
 734         if (ul_insert_rs_byte)
 735                 state->m_insert_rs_byte = true;
 736
 737         state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 738         if (ul_mpeg_lock_time_out < 10000)
 739                 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
 740         state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 741         if (ul_demod_lock_time_out < 10000)
 742                 state->m_demod_lock_time_out = ul_demod_lock_time_out;
 743
 744         /* QAM defaults */
 745         state->m_constellation = DRX_CONSTELLATION_AUTO;
 746         state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
 747         state->m_fec_rs_plen = 204 * 8; /* fecRsPlen  annex A */
 748         state->m_fec_rs_prescale = 1;
 749
 750         state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
 751         state->m_agcfast_clip_ctrl_delay = 0;
 752
 753         state->m_gpio_cfg = ul_gpio_cfg;
 754
 755         state->m_b_power_down = false;
 756         state->m_current_power_mode = DRX_POWER_DOWN;
 757
 758         state->m_rfmirror = (ul_rf_mirror == 0);
 759         state->m_if_agc_pol = false;
 760         return 0;
 761 }
 762
 763 static int drxx_open(struct drxk_state *state)
 764 {
 765         int status = 0;
 766         u32 jtag = 0;
 767         u16 bid = 0;
 768         u16 key = 0;
 769
 770         dprintk(1, "\n");
 771         /* stop lock indicator process */
 772         status = write16(state, SCU_RAM_GPIO__A,
 773                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 774         if (status < 0)
 775                 goto error;
 776         /* Check device id */
 777         status = read16(state, SIO_TOP_COMM_KEY__A, &key);
 778         if (status < 0)
 779                 goto error;
 780         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 781         if (status < 0)
 782                 goto error;
 783         status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
 784         if (status < 0)
 785                 goto error;
 786         status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
 787         if (status < 0)
 788                 goto error;
 789         status = write16(state, SIO_TOP_COMM_KEY__A, key);
 790 error:
 791         if (status < 0)
 792                 pr_err("Error %d on %s\n", status, __func__);
 793         return status;
 794 }
 795
 796 static int get_device_capabilities(struct drxk_state *state)
 797 {
 798         u16 sio_pdr_ohw_cfg = 0;
 799         u32 sio_top_jtagid_lo = 0;
 800         int status;
 801         const char *spin = "";
 802
 803         dprintk(1, "\n");
 804
 805         /* driver 0.9.0 */
 806         /* stop lock indicator process */
 807         status = write16(state, SCU_RAM_GPIO__A,
 808                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 809         if (status < 0)
 810                 goto error;
 811         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 812         if (status < 0)
 813                 goto error;
 814         status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
 815         if (status < 0)
 816                 goto error;
 817         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
 818         if (status < 0)
 819                 goto error;
 820
 821         switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
 822         case 0:
 823                 /* ignore (bypass ?) */
 824                 break;
 825         case 1:
 826                 /* 27 MHz */
 827                 state->m_osc_clock_freq = 27000;
 828                 break;
 829         case 2:
 830                 /* 20.25 MHz */
 831                 state->m_osc_clock_freq = 20250;
 832                 break;
 833         case 3:
 834                 /* 4 MHz */
 835                 state->m_osc_clock_freq = 20250;
 836                 break;
 837         default:
 838                 pr_err("Clock Frequency is unknown\n");
 839                 return -EINVAL;
 840         }
 841         /*
 842                 Determine device capabilities
 843                 Based on pinning v14
 844                 */
 845         status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
 846         if (status < 0)
 847                 goto error;
 848
 849         pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
 850
 851         /* driver 0.9.0 */
 852         switch ((sio_top_jtagid_lo >> 29) & 0xF) {
 853         case 0:
 854                 state->m_device_spin = DRXK_SPIN_A1;
 855                 spin = "A1";
 856                 break;
 857         case 2:
 858                 state->m_device_spin = DRXK_SPIN_A2;
 859                 spin = "A2";
 860                 break;
 861         case 3:
 862                 state->m_device_spin = DRXK_SPIN_A3;
 863                 spin = "A3";
 864                 break;
 865         default:
 866                 state->m_device_spin = DRXK_SPIN_UNKNOWN;
 867                 status = -EINVAL;
 868                 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
 869                 goto error2;
 870         }
 871         switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
 872         case 0x13:
 873                 /* typeId = DRX3913K_TYPE_ID */
 874                 state->m_has_lna = false;
 875                 state->m_has_oob = false;
 876                 state->m_has_atv = false;
 877                 state->m_has_audio = false;
 878                 state->m_has_dvbt = true;
 879                 state->m_has_dvbc = true;
 880                 state->m_has_sawsw = true;
 881                 state->m_has_gpio2 = false;
 882                 state->m_has_gpio1 = false;
 883                 state->m_has_irqn = false;
 884                 break;
 885         case 0x15:
 886                 /* typeId = DRX3915K_TYPE_ID */
 887                 state->m_has_lna = false;
 888                 state->m_has_oob = false;
 889                 state->m_has_atv = true;
 890                 state->m_has_audio = false;
 891                 state->m_has_dvbt = true;
 892                 state->m_has_dvbc = false;
 893                 state->m_has_sawsw = true;
 894                 state->m_has_gpio2 = true;
 895                 state->m_has_gpio1 = true;
 896                 state->m_has_irqn = false;
 897                 break;
 898         case 0x16:
 899                 /* typeId = DRX3916K_TYPE_ID */
 900                 state->m_has_lna = false;
 901                 state->m_has_oob = false;
 902                 state->m_has_atv = true;
 903                 state->m_has_audio = false;
 904                 state->m_has_dvbt = true;
 905                 state->m_has_dvbc = false;
 906                 state->m_has_sawsw = true;
 907                 state->m_has_gpio2 = true;
 908                 state->m_has_gpio1 = true;
 909                 state->m_has_irqn = false;
 910                 break;
 911         case 0x18:
 912                 /* typeId = DRX3918K_TYPE_ID */
 913                 state->m_has_lna = false;
 914                 state->m_has_oob = false;
 915                 state->m_has_atv = true;
 916                 state->m_has_audio = true;
 917                 state->m_has_dvbt = true;
 918                 state->m_has_dvbc = false;
 919                 state->m_has_sawsw = true;
 920                 state->m_has_gpio2 = true;
 921                 state->m_has_gpio1 = true;
 922                 state->m_has_irqn = false;
 923                 break;
 924         case 0x21:
 925                 /* typeId = DRX3921K_TYPE_ID */
 926                 state->m_has_lna = false;
 927                 state->m_has_oob = false;
 928                 state->m_has_atv = true;
 929                 state->m_has_audio = true;
 930                 state->m_has_dvbt = true;
 931                 state->m_has_dvbc = true;
 932                 state->m_has_sawsw = true;
 933                 state->m_has_gpio2 = true;
 934                 state->m_has_gpio1 = true;
 935                 state->m_has_irqn = false;
 936                 break;
 937         case 0x23:
 938                 /* typeId = DRX3923K_TYPE_ID */
 939                 state->m_has_lna = false;
 940                 state->m_has_oob = false;
 941                 state->m_has_atv = true;
 942                 state->m_has_audio = true;
 943                 state->m_has_dvbt = true;
 944                 state->m_has_dvbc = true;
 945                 state->m_has_sawsw = true;
 946                 state->m_has_gpio2 = true;
 947                 state->m_has_gpio1 = true;
 948                 state->m_has_irqn = false;
 949                 break;
 950         case 0x25:
 951                 /* typeId = DRX3925K_TYPE_ID */
 952                 state->m_has_lna = false;
 953                 state->m_has_oob = false;
 954                 state->m_has_atv = true;
 955                 state->m_has_audio = true;
 956                 state->m_has_dvbt = true;
 957                 state->m_has_dvbc = true;
 958                 state->m_has_sawsw = true;
 959                 state->m_has_gpio2 = true;
 960                 state->m_has_gpio1 = true;
 961                 state->m_has_irqn = false;
 962                 break;
 963         case 0x26:
 964                 /* typeId = DRX3926K_TYPE_ID */
 965                 state->m_has_lna = false;
 966                 state->m_has_oob = false;
 967                 state->m_has_atv = true;
 968                 state->m_has_audio = false;
 969                 state->m_has_dvbt = true;
 970                 state->m_has_dvbc = true;
 971                 state->m_has_sawsw = true;
 972                 state->m_has_gpio2 = true;
 973                 state->m_has_gpio1 = true;
 974                 state->m_has_irqn = false;
 975                 break;
 976         default:
 977                 pr_err("DeviceID 0x%02x not supported\n",
 978                         ((sio_top_jtagid_lo >> 12) & 0xFF));
 979                 status = -EINVAL;
 980                 goto error2;
 981         }
 982
 983         pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
 984                ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
 985                state->m_osc_clock_freq / 1000,
 986                state->m_osc_clock_freq % 1000);
 987
 988 error:
 989         if (status < 0)
 990                 pr_err("Error %d on %s\n", status, __func__);
 991
 992 error2:
 993         return status;
 994 }
 995
 996 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
 997 {
 998         int status;
 999         bool powerdown_cmd;
1000
1001         dprintk(1, "\n");
1002
1003         /* Write command */
1004         status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1005         if (status < 0)
1006                 goto error;
1007         if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1008                 usleep_range(1000, 2000);
1009
1010         powerdown_cmd =
1011             (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1012                     ((state->m_hi_cfg_ctrl) &
1013                      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1014                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1015         if (!powerdown_cmd) {
1016                 /* Wait until command rdy */
1017                 u32 retry_count = 0;
1018                 u16 wait_cmd;
1019
1020                 do {
1021                         usleep_range(1000, 2000);
1022                         retry_count += 1;
1023                         status = read16(state, SIO_HI_RA_RAM_CMD__A,
1024                                           &wait_cmd);
1025                 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1026                          && (wait_cmd != 0));
1027                 if (status < 0)
1028                         goto error;
1029                 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1030         }
1031 error:
1032         if (status < 0)
1033                 pr_err("Error %d on %s\n", status, __func__);
1034
1035         return status;
1036 }
1037
1038 static int hi_cfg_command(struct drxk_state *state)
1039 {
1040         int status;
1041
1042         dprintk(1, "\n");
1043
1044         mutex_lock(&state->mutex);
1045
1046         status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1047                          state->m_hi_cfg_timeout);
1048         if (status < 0)
1049                 goto error;
1050         status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1051                          state->m_hi_cfg_ctrl);
1052         if (status < 0)
1053                 goto error;
1054         status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1055                          state->m_hi_cfg_wake_up_key);
1056         if (status < 0)
1057                 goto error;
1058         status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1059                          state->m_hi_cfg_bridge_delay);
1060         if (status < 0)
1061                 goto error;
1062         status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1063                          state->m_hi_cfg_timing_div);
1064         if (status < 0)
1065                 goto error;
1066         status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1067                          SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1068         if (status < 0)
1069                 goto error;
1070         status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1071         if (status < 0)
1072                 goto error;
1073
1074         state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1075 error:
1076         mutex_unlock(&state->mutex);
1077         if (status < 0)
1078                 pr_err("Error %d on %s\n", status, __func__);
1079         return status;
1080 }
1081
1082 static int init_hi(struct drxk_state *state)
1083 {
1084         dprintk(1, "\n");
1085
1086         state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1087         state->m_hi_cfg_timeout = 0x96FF;
1088         /* port/bridge/power down ctrl */
1089         state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1090
1091         return hi_cfg_command(state);
1092 }
1093
1094 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1095 {
1096         int status = -1;
1097         u16 sio_pdr_mclk_cfg = 0;
1098         u16 sio_pdr_mdx_cfg = 0;
1099         u16 err_cfg = 0;
1100
1101         dprintk(1, ": mpeg %s, %s mode\n",
1102                 mpeg_enable ? "enable" : "disable",
1103                 state->m_enable_parallel ? "parallel" : "serial");
1104
1105         /* stop lock indicator process */
1106         status = write16(state, SCU_RAM_GPIO__A,
1107                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1108         if (status < 0)
1109                 goto error;
1110
1111         /*  MPEG TS pad configuration */
1112         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1113         if (status < 0)
1114                 goto error;
1115
1116         if (!mpeg_enable) {
1117                 /*  Set MPEG TS pads to inputmode */
1118                 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1119                 if (status < 0)
1120                         goto error;
1121                 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1122                 if (status < 0)
1123                         goto error;
1124                 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1125                 if (status < 0)
1126                         goto error;
1127                 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1128                 if (status < 0)
1129                         goto error;
1130                 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1131                 if (status < 0)
1132                         goto error;
1133                 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1134                 if (status < 0)
1135                         goto error;
1136                 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1137                 if (status < 0)
1138                         goto error;
1139                 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1140                 if (status < 0)
1141                         goto error;
1142                 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1143                 if (status < 0)
1144                         goto error;
1145                 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1146                 if (status < 0)
1147                         goto error;
1148                 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1149                 if (status < 0)
1150                         goto error;
1151                 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1152                 if (status < 0)
1153                         goto error;
1154         } else {
1155                 /* Enable MPEG output */
1156                 sio_pdr_mdx_cfg =
1157                         ((state->m_ts_data_strength <<
1158                         SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1159                 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1160                                         SIO_PDR_MCLK_CFG_DRIVE__B) |
1161                                         0x0003);
1162
1163                 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1164                 if (status < 0)
1165                         goto error;
1166
1167                 if (state->enable_merr_cfg)
1168                         err_cfg = sio_pdr_mdx_cfg;
1169
1170                 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1171                 if (status < 0)
1172                         goto error;
1173                 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1174                 if (status < 0)
1175                         goto error;
1176
1177                 if (state->m_enable_parallel) {
1178                         /* parallel -> enable MD1 to MD7 */
1179                         status = write16(state, SIO_PDR_MD1_CFG__A,
1180                                          sio_pdr_mdx_cfg);
1181                         if (status < 0)
1182                                 goto error;
1183                         status = write16(state, SIO_PDR_MD2_CFG__A,
1184                                          sio_pdr_mdx_cfg);
1185                         if (status < 0)
1186                                 goto error;
1187                         status = write16(state, SIO_PDR_MD3_CFG__A,
1188                                          sio_pdr_mdx_cfg);
1189                         if (status < 0)
1190                                 goto error;
1191                         status = write16(state, SIO_PDR_MD4_CFG__A,
1192                                          sio_pdr_mdx_cfg);
1193                         if (status < 0)
1194                                 goto error;
1195                         status = write16(state, SIO_PDR_MD5_CFG__A,
1196                                          sio_pdr_mdx_cfg);
1197                         if (status < 0)
1198                                 goto error;
1199                         status = write16(state, SIO_PDR_MD6_CFG__A,
1200                                          sio_pdr_mdx_cfg);
1201                         if (status < 0)
1202                                 goto error;
1203                         status = write16(state, SIO_PDR_MD7_CFG__A,
1204                                          sio_pdr_mdx_cfg);
1205                         if (status < 0)
1206                                 goto error;
1207                 } else {
1208                         sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1209                                                 SIO_PDR_MD0_CFG_DRIVE__B)
1210                                         | 0x0003);
1211                         /* serial -> disable MD1 to MD7 */
1212                         status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1213                         if (status < 0)
1214                                 goto error;
1215                         status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1216                         if (status < 0)
1217                                 goto error;
1218                         status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1219                         if (status < 0)
1220                                 goto error;
1221                         status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1222                         if (status < 0)
1223                                 goto error;
1224                         status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1225                         if (status < 0)
1226                                 goto error;
1227                         status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1228                         if (status < 0)
1229                                 goto error;
1230                         status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1231                         if (status < 0)
1232                                 goto error;
1233                 }
1234                 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1235                 if (status < 0)
1236                         goto error;
1237                 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1238                 if (status < 0)
1239                         goto error;
1240         }
1241         /*  Enable MB output over MPEG pads and ctl input */
1242         status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1243         if (status < 0)
1244                 goto error;
1245         /*  Write nomagic word to enable pdr reg write */
1246         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1247 error:
1248         if (status < 0)
1249                 pr_err("Error %d on %s\n", status, __func__);
1250         return status;
1251 }
1252
1253 static int mpegts_disable(struct drxk_state *state)
1254 {
1255         dprintk(1, "\n");
1256
1257         return mpegts_configure_pins(state, false);
1258 }
1259
1260 static int bl_chain_cmd(struct drxk_state *state,
1261                       u16 rom_offset, u16 nr_of_elements, u32 time_out)
1262 {
1263         u16 bl_status = 0;
1264         int status;
1265         unsigned long end;
1266
1267         dprintk(1, "\n");
1268         mutex_lock(&state->mutex);
1269         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1270         if (status < 0)
1271                 goto error;
1272         status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1273         if (status < 0)
1274                 goto error;
1275         status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1276         if (status < 0)
1277                 goto error;
1278         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1279         if (status < 0)
1280                 goto error;
1281
1282         end = jiffies + msecs_to_jiffies(time_out);
1283         do {
1284                 usleep_range(1000, 2000);
1285                 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1286                 if (status < 0)
1287                         goto error;
1288         } while ((bl_status == 0x1) &&
1289                         ((time_is_after_jiffies(end))));
1290
1291         if (bl_status == 0x1) {
1292                 pr_err("SIO not ready\n");
1293                 status = -EINVAL;
1294                 goto error2;
1295         }
1296 error:
1297         if (status < 0)
1298                 pr_err("Error %d on %s\n", status, __func__);
1299 error2:
1300         mutex_unlock(&state->mutex);
1301         return status;
1302 }
1303
1304
1305 static int download_microcode(struct drxk_state *state,
1306                              const u8 p_mc_image[], u32 length)
1307 {
1308         const u8 *p_src = p_mc_image;
1309         u32 address;
1310         u16 n_blocks;
1311         u16 block_size;
1312         u32 offset = 0;
1313         u32 i;
1314         int status = 0;
1315
1316         dprintk(1, "\n");
1317
1318         /* down the drain (we don't care about MAGIC_WORD) */
1319 #if 0
1320         /* For future reference */
1321         drain = (p_src[0] << 8) | p_src[1];
1322 #endif
1323         p_src += sizeof(u16);
1324         offset += sizeof(u16);
1325         n_blocks = (p_src[0] << 8) | p_src[1];
1326         p_src += sizeof(u16);
1327         offset += sizeof(u16);
1328
1329         for (i = 0; i < n_blocks; i += 1) {
1330                 address = (p_src[0] << 24) | (p_src[1] << 16) |
1331                     (p_src[2] << 8) | p_src[3];
1332                 p_src += sizeof(u32);
1333                 offset += sizeof(u32);
1334
1335                 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1336                 p_src += sizeof(u16);
1337                 offset += sizeof(u16);
1338
1339 #if 0
1340                 /* For future reference */
1341                 flags = (p_src[0] << 8) | p_src[1];
1342 #endif
1343                 p_src += sizeof(u16);
1344                 offset += sizeof(u16);
1345
1346 #if 0
1347                 /* For future reference */
1348                 block_crc = (p_src[0] << 8) | p_src[1];
1349 #endif
1350                 p_src += sizeof(u16);
1351                 offset += sizeof(u16);
1352
1353                 if (offset + block_size > length) {
1354                         pr_err("Firmware is corrupted.\n");
1355                         return -EINVAL;
1356                 }
1357
1358                 status = write_block(state, address, block_size, p_src);
1359                 if (status < 0) {
1360                         pr_err("Error %d while loading firmware\n", status);
1361                         break;
1362                 }
1363                 p_src += block_size;
1364                 offset += block_size;
1365         }
1366         return status;
1367 }
1368
1369 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1370 {
1371         int status;
1372         u16 data = 0;
1373         u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1374         u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1375         unsigned long end;
1376
1377         dprintk(1, "\n");
1378
1379         if (!enable) {
1380                 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1381                 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1382         }
1383
1384         status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1385         if (status >= 0 && data == desired_status) {
1386                 /* tokenring already has correct status */
1387                 return status;
1388         }
1389         /* Disable/enable dvbt tokenring bridge   */
1390         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1391
1392         end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1393         do {
1394                 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1395                 if ((status >= 0 && data == desired_status)
1396                     || time_is_after_jiffies(end))
1397                         break;
1398                 usleep_range(1000, 2000);
1399         } while (1);
1400         if (data != desired_status) {
1401                 pr_err("SIO not ready\n");
1402                 return -EINVAL;
1403         }
1404         return status;
1405 }
1406
1407 static int mpegts_stop(struct drxk_state *state)
1408 {
1409         int status = 0;
1410         u16 fec_oc_snc_mode = 0;
1411         u16 fec_oc_ipr_mode = 0;
1412
1413         dprintk(1, "\n");
1414
1415         /* Graceful shutdown (byte boundaries) */
1416         status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1417         if (status < 0)
1418                 goto error;
1419         fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1420         status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1421         if (status < 0)
1422                 goto error;
1423
1424         /* Suppress MCLK during absence of data */
1425         status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1426         if (status < 0)
1427                 goto error;
1428         fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1429         status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1430
1431 error:
1432         if (status < 0)
1433                 pr_err("Error %d on %s\n", status, __func__);
1434
1435         return status;
1436 }
1437
1438 static int scu_command(struct drxk_state *state,
1439                        u16 cmd, u8 parameter_len,
1440                        u16 *parameter, u8 result_len, u16 *result)
1441 {
1442 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1443 #error DRXK register mapping no longer compatible with this routine!
1444 #endif
1445         u16 cur_cmd = 0;
1446         int status = -EINVAL;
1447         unsigned long end;
1448         u8 buffer[34];
1449         int cnt = 0, ii;
1450         const char *p;
1451         char errname[30];
1452
1453         dprintk(1, "\n");
1454
1455         if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1456             ((result_len > 0) && (result == NULL))) {
1457                 pr_err("Error %d on %s\n", status, __func__);
1458                 return status;
1459         }
1460
1461         mutex_lock(&state->mutex);
1462
1463         /* assume that the command register is ready
1464                 since it is checked afterwards */
1465         if (parameter) {
1466                 for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1467                         buffer[cnt++] = (parameter[ii] & 0xFF);
1468                         buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1469                 }
1470         }
1471         buffer[cnt++] = (cmd & 0xFF);
1472         buffer[cnt++] = ((cmd >> 8) & 0xFF);
1473
1474         write_block(state, SCU_RAM_PARAM_0__A -
1475                         (parameter_len - 1), cnt, buffer);
1476         /* Wait until SCU has processed command */
1477         end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1478         do {
1479                 usleep_range(1000, 2000);
1480                 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1481                 if (status < 0)
1482                         goto error;
1483         } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1484         if (cur_cmd != DRX_SCU_READY) {
1485                 pr_err("SCU not ready\n");
1486                 status = -EIO;
1487                 goto error2;
1488         }
1489         /* read results */
1490         if ((result_len > 0) && (result != NULL)) {
1491                 s16 err;
1492                 int ii;
1493
1494                 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1495                         status = read16(state, SCU_RAM_PARAM_0__A - ii,
1496                                         &result[ii]);
1497                         if (status < 0)
1498                                 goto error;
1499                 }
1500
1501                 /* Check if an error was reported by SCU */
1502                 err = (s16)result[0];
1503                 if (err >= 0)
1504                         goto error;
1505
1506                 /* check for the known error codes */
1507                 switch (err) {
1508                 case SCU_RESULT_UNKCMD:
1509                         p = "SCU_RESULT_UNKCMD";
1510                         break;
1511                 case SCU_RESULT_UNKSTD:
1512                         p = "SCU_RESULT_UNKSTD";
1513                         break;
1514                 case SCU_RESULT_SIZE:
1515                         p = "SCU_RESULT_SIZE";
1516                         break;
1517                 case SCU_RESULT_INVPAR:
1518                         p = "SCU_RESULT_INVPAR";
1519                         break;
1520                 default: /* Other negative values are errors */
1521                         sprintf(errname, "ERROR: %d\n", err);
1522                         p = errname;
1523                 }
1524                 pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1525                 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1526                 status = -EINVAL;
1527                 goto error2;
1528         }
1529
1530 error:
1531         if (status < 0)
1532                 pr_err("Error %d on %s\n", status, __func__);
1533 error2:
1534         mutex_unlock(&state->mutex);
1535         return status;
1536 }
1537
1538 static int set_iqm_af(struct drxk_state *state, bool active)
1539 {
1540         u16 data = 0;
1541         int status;
1542
1543         dprintk(1, "\n");
1544
1545         /* Configure IQM */
1546         status = read16(state, IQM_AF_STDBY__A, &data);
1547         if (status < 0)
1548                 goto error;
1549
1550         if (!active) {
1551                 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1552                                 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1553                                 | IQM_AF_STDBY_STDBY_PD_STANDBY
1554                                 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1555                                 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1556         } else {
1557                 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1558                                 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1559                                 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1560                                 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1561                                 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1562                         );
1563         }
1564         status = write16(state, IQM_AF_STDBY__A, data);
1565
1566 error:
1567         if (status < 0)
1568                 pr_err("Error %d on %s\n", status, __func__);
1569         return status;
1570 }
1571
1572 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1573 {
1574         int status = 0;
1575         u16 sio_cc_pwd_mode = 0;
1576
1577         dprintk(1, "\n");
1578
1579         /* Check arguments */
1580         if (mode == NULL)
1581                 return -EINVAL;
1582
1583         switch (*mode) {
1584         case DRX_POWER_UP:
1585                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1586                 break;
1587         case DRXK_POWER_DOWN_OFDM:
1588                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1589                 break;
1590         case DRXK_POWER_DOWN_CORE:
1591                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1592                 break;
1593         case DRXK_POWER_DOWN_PLL:
1594                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1595                 break;
1596         case DRX_POWER_DOWN:
1597                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1598                 break;
1599         default:
1600                 /* Unknow sleep mode */
1601                 return -EINVAL;
1602         }
1603
1604         /* If already in requested power mode, do nothing */
1605         if (state->m_current_power_mode == *mode)
1606                 return 0;
1607
1608         /* For next steps make sure to start from DRX_POWER_UP mode */
1609         if (state->m_current_power_mode != DRX_POWER_UP) {
1610                 status = power_up_device(state);
1611                 if (status < 0)
1612                         goto error;
1613                 status = dvbt_enable_ofdm_token_ring(state, true);
1614                 if (status < 0)
1615                         goto error;
1616         }
1617
1618         if (*mode == DRX_POWER_UP) {
1619                 /* Restore analog & pin configuration */
1620         } else {
1621                 /* Power down to requested mode */
1622                 /* Backup some register settings */
1623                 /* Set pins with possible pull-ups connected
1624                    to them in input mode */
1625                 /* Analog power down */
1626                 /* ADC power down */
1627                 /* Power down device */
1628                 /* stop all comm_exec */
1629                 /* Stop and power down previous standard */
1630                 switch (state->m_operation_mode) {
1631                 case OM_DVBT:
1632                         status = mpegts_stop(state);
1633                         if (status < 0)
1634                                 goto error;
1635                         status = power_down_dvbt(state, false);
1636                         if (status < 0)
1637                                 goto error;
1638                         break;
1639                 case OM_QAM_ITU_A:
1640                 case OM_QAM_ITU_C:
1641                         status = mpegts_stop(state);
1642                         if (status < 0)
1643                                 goto error;
1644                         status = power_down_qam(state);
1645                         if (status < 0)
1646                                 goto error;
1647                         break;
1648                 default:
1649                         break;
1650                 }
1651                 status = dvbt_enable_ofdm_token_ring(state, false);
1652                 if (status < 0)
1653                         goto error;
1654                 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1655                 if (status < 0)
1656                         goto error;
1657                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1658                 if (status < 0)
1659                         goto error;
1660
1661                 if (*mode != DRXK_POWER_DOWN_OFDM) {
1662                         state->m_hi_cfg_ctrl |=
1663                                 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1664                         status = hi_cfg_command(state);
1665                         if (status < 0)
1666                                 goto error;
1667                 }
1668         }
1669         state->m_current_power_mode = *mode;
1670
1671 error:
1672         if (status < 0)
1673                 pr_err("Error %d on %s\n", status, __func__);
1674
1675         return status;
1676 }
1677
1678 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1679 {
1680         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1681         u16 cmd_result = 0;
1682         u16 data = 0;
1683         int status;
1684
1685         dprintk(1, "\n");
1686
1687         status = read16(state, SCU_COMM_EXEC__A, &data);
1688         if (status < 0)
1689                 goto error;
1690         if (data == SCU_COMM_EXEC_ACTIVE) {
1691                 /* Send OFDM stop command */
1692                 status = scu_command(state,
1693                                      SCU_RAM_COMMAND_STANDARD_OFDM
1694                                      | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1695                                      0, NULL, 1, &cmd_result);
1696                 if (status < 0)
1697                         goto error;
1698                 /* Send OFDM reset command */
1699                 status = scu_command(state,
1700                                      SCU_RAM_COMMAND_STANDARD_OFDM
1701                                      | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1702                                      0, NULL, 1, &cmd_result);
1703                 if (status < 0)
1704                         goto error;
1705         }
1706
1707         /* Reset datapath for OFDM, processors first */
1708         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1709         if (status < 0)
1710                 goto error;
1711         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1712         if (status < 0)
1713                 goto error;
1714         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1715         if (status < 0)
1716                 goto error;
1717
1718         /* powerdown AFE                   */
1719         status = set_iqm_af(state, false);
1720         if (status < 0)
1721                 goto error;
1722
1723         /* powerdown to OFDM mode          */
1724         if (set_power_mode) {
1725                 status = ctrl_power_mode(state, &power_mode);
1726                 if (status < 0)
1727                         goto error;
1728         }
1729 error:
1730         if (status < 0)
1731                 pr_err("Error %d on %s\n", status, __func__);
1732         return status;
1733 }
1734
1735 static int setoperation_mode(struct drxk_state *state,
1736                             enum operation_mode o_mode)
1737 {
1738         int status = 0;
1739
1740         dprintk(1, "\n");
1741         /*
1742            Stop and power down previous standard
1743            TODO investigate total power down instead of partial
1744            power down depending on "previous" standard.
1745          */
1746
1747         /* disable HW lock indicator */
1748         status = write16(state, SCU_RAM_GPIO__A,
1749                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1750         if (status < 0)
1751                 goto error;
1752
1753         /* Device is already at the required mode */
1754         if (state->m_operation_mode == o_mode)
1755                 return 0;
1756
1757         switch (state->m_operation_mode) {
1758                 /* OM_NONE was added for start up */
1759         case OM_NONE:
1760                 break;
1761         case OM_DVBT:
1762                 status = mpegts_stop(state);
1763                 if (status < 0)
1764                         goto error;
1765                 status = power_down_dvbt(state, true);
1766                 if (status < 0)
1767                         goto error;
1768                 state->m_operation_mode = OM_NONE;
1769                 break;
1770         case OM_QAM_ITU_A:      /* fallthrough */
1771         case OM_QAM_ITU_C:
1772                 status = mpegts_stop(state);
1773                 if (status < 0)
1774                         goto error;
1775                 status = power_down_qam(state);
1776                 if (status < 0)
1777                         goto error;
1778                 state->m_operation_mode = OM_NONE;
1779                 break;
1780         case OM_QAM_ITU_B:
1781         default:
1782                 status = -EINVAL;
1783                 goto error;
1784         }
1785
1786         /*
1787                 Power up new standard
1788                 */
1789         switch (o_mode) {
1790         case OM_DVBT:
1791                 dprintk(1, ": DVB-T\n");
1792                 state->m_operation_mode = o_mode;
1793                 status = set_dvbt_standard(state, o_mode);
1794                 if (status < 0)
1795                         goto error;
1796                 break;
1797         case OM_QAM_ITU_A:      /* fallthrough */
1798         case OM_QAM_ITU_C:
1799                 dprintk(1, ": DVB-C Annex %c\n",
1800                         (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1801                 state->m_operation_mode = o_mode;
1802                 status = set_qam_standard(state, o_mode);
1803                 if (status < 0)
1804                         goto error;
1805                 break;
1806         case OM_QAM_ITU_B:
1807         default:
1808                 status = -EINVAL;
1809         }
1810 error:
1811         if (status < 0)
1812                 pr_err("Error %d on %s\n", status, __func__);
1813         return status;
1814 }
1815
1816 static int start(struct drxk_state *state, s32 offset_freq,
1817                  s32 intermediate_frequency)
1818 {
1819         int status = -EINVAL;
1820
1821         u16 i_freqk_hz;
1822         s32 offsetk_hz = offset_freq / 1000;
1823
1824         dprintk(1, "\n");
1825         if (state->m_drxk_state != DRXK_STOPPED &&
1826                 state->m_drxk_state != DRXK_DTV_STARTED)
1827                 goto error;
1828
1829         state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1830
1831         if (intermediate_frequency < 0) {
1832                 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1833                 intermediate_frequency = -intermediate_frequency;
1834         }
1835
1836         switch (state->m_operation_mode) {
1837         case OM_QAM_ITU_A:
1838         case OM_QAM_ITU_C:
1839                 i_freqk_hz = (intermediate_frequency / 1000);
1840                 status = set_qam(state, i_freqk_hz, offsetk_hz);
1841                 if (status < 0)
1842                         goto error;
1843                 state->m_drxk_state = DRXK_DTV_STARTED;
1844                 break;
1845         case OM_DVBT:
1846                 i_freqk_hz = (intermediate_frequency / 1000);
1847                 status = mpegts_stop(state);
1848                 if (status < 0)
1849                         goto error;
1850                 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1851                 if (status < 0)
1852                         goto error;
1853                 status = dvbt_start(state);
1854                 if (status < 0)
1855                         goto error;
1856                 state->m_drxk_state = DRXK_DTV_STARTED;
1857                 break;
1858         default:
1859                 break;
1860         }
1861 error:
1862         if (status < 0)
1863                 pr_err("Error %d on %s\n", status, __func__);
1864         return status;
1865 }
1866
1867 static int shut_down(struct drxk_state *state)
1868 {
1869         dprintk(1, "\n");
1870
1871         mpegts_stop(state);
1872         return 0;
1873 }
1874
1875 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1876 {
1877         int status = -EINVAL;
1878
1879         dprintk(1, "\n");
1880
1881         if (p_lock_status == NULL)
1882                 goto error;
1883
1884         *p_lock_status = NOT_LOCKED;
1885
1886         /* define the SCU command code */
1887         switch (state->m_operation_mode) {
1888         case OM_QAM_ITU_A:
1889         case OM_QAM_ITU_B:
1890         case OM_QAM_ITU_C:
1891                 status = get_qam_lock_status(state, p_lock_status);
1892                 break;
1893         case OM_DVBT:
1894                 status = get_dvbt_lock_status(state, p_lock_status);
1895                 break;
1896         default:
1897                 pr_debug("Unsupported operation mode %d in %s\n",
1898                         state->m_operation_mode, __func__);
1899                 return 0;
1900         }
1901 error:
1902         if (status < 0)
1903                 pr_err("Error %d on %s\n", status, __func__);
1904         return status;
1905 }
1906
1907 static int mpegts_start(struct drxk_state *state)
1908 {
1909         int status;
1910
1911         u16 fec_oc_snc_mode = 0;
1912
1913         /* Allow OC to sync again */
1914         status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1915         if (status < 0)
1916                 goto error;
1917         fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1918         status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1919         if (status < 0)
1920                 goto error;
1921         status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1922 error:
1923         if (status < 0)
1924                 pr_err("Error %d on %s\n", status, __func__);
1925         return status;
1926 }
1927
1928 static int mpegts_dto_init(struct drxk_state *state)
1929 {
1930         int status;
1931
1932         dprintk(1, "\n");
1933
1934         /* Rate integration settings */
1935         status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1936         if (status < 0)
1937                 goto error;
1938         status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1939         if (status < 0)
1940                 goto error;
1941         status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1942         if (status < 0)
1943                 goto error;
1944         status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1945         if (status < 0)
1946                 goto error;
1947         status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1948         if (status < 0)
1949                 goto error;
1950         status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1951         if (status < 0)
1952                 goto error;
1953         status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1954         if (status < 0)
1955                 goto error;
1956         status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1957         if (status < 0)
1958                 goto error;
1959
1960         /* Additional configuration */
1961         status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1962         if (status < 0)
1963                 goto error;
1964         status = write16(state, FEC_OC_SNC_LWM__A, 2);
1965         if (status < 0)
1966                 goto error;
1967         status = write16(state, FEC_OC_SNC_HWM__A, 12);
1968 error:
1969         if (status < 0)
1970                 pr_err("Error %d on %s\n", status, __func__);
1971
1972         return status;
1973 }
1974
1975 static int mpegts_dto_setup(struct drxk_state *state,
1976                           enum operation_mode o_mode)
1977 {
1978         int status;
1979
1980         u16 fec_oc_reg_mode = 0;        /* FEC_OC_MODE       register value */
1981         u16 fec_oc_reg_ipr_mode = 0;    /* FEC_OC_IPR_MODE   register value */
1982         u16 fec_oc_dto_mode = 0;        /* FEC_OC_IPR_INVERT register value */
1983         u16 fec_oc_fct_mode = 0;        /* FEC_OC_IPR_INVERT register value */
1984         u16 fec_oc_dto_period = 2;      /* FEC_OC_IPR_INVERT register value */
1985         u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1986         u32 fec_oc_rcn_ctl_rate = 0;    /* FEC_OC_IPR_INVERT register value */
1987         u16 fec_oc_tmd_mode = 0;
1988         u16 fec_oc_tmd_int_upd_rate = 0;
1989         u32 max_bit_rate = 0;
1990         bool static_clk = false;
1991
1992         dprintk(1, "\n");
1993
1994         /* Check insertion of the Reed-Solomon parity bytes */
1995         status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1996         if (status < 0)
1997                 goto error;
1998         status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1999         if (status < 0)
2000                 goto error;
2001         fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2002         fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2003         if (state->m_insert_rs_byte) {
2004                 /* enable parity symbol forward */
2005                 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2006                 /* MVAL disable during parity bytes */
2007                 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2008                 /* TS burst length to 204 */
2009                 fec_oc_dto_burst_len = 204;
2010         }
2011
2012         /* Check serial or parallel output */
2013         fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2014         if (!state->m_enable_parallel) {
2015                 /* MPEG data output is serial -> set ipr_mode[0] */
2016                 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2017         }
2018
2019         switch (o_mode) {
2020         case OM_DVBT:
2021                 max_bit_rate = state->m_dvbt_bitrate;
2022                 fec_oc_tmd_mode = 3;
2023                 fec_oc_rcn_ctl_rate = 0xC00000;
2024                 static_clk = state->m_dvbt_static_clk;
2025                 break;
2026         case OM_QAM_ITU_A:      /* fallthrough */
2027         case OM_QAM_ITU_C:
2028                 fec_oc_tmd_mode = 0x0004;
2029                 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
2030                 max_bit_rate = state->m_dvbc_bitrate;
2031                 static_clk = state->m_dvbc_static_clk;
2032                 break;
2033         default:
2034                 status = -EINVAL;
2035         }               /* switch (standard) */
2036         if (status < 0)
2037                 goto error;
2038
2039         /* Configure DTO's */
2040         if (static_clk) {
2041                 u32 bit_rate = 0;
2042
2043                 /* Rational DTO for MCLK source (static MCLK rate),
2044                         Dynamic DTO for optimal grouping
2045                         (avoid intra-packet gaps),
2046                         DTO offset enable to sync TS burst with MSTRT */
2047                 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2048                                 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2049                 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2050                                 FEC_OC_FCT_MODE_VIRT_ENA__M);
2051
2052                 /* Check user defined bitrate */
2053                 bit_rate = max_bit_rate;
2054                 if (bit_rate > 75900000UL) {    /* max is 75.9 Mb/s */
2055                         bit_rate = 75900000UL;
2056                 }
2057                 /* Rational DTO period:
2058                         dto_period = (Fsys / bitrate) - 2
2059
2060                         result should be floored,
2061                         to make sure >= requested bitrate
2062                         */
2063                 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2064                                                 * 1000) / bit_rate);
2065                 if (fec_oc_dto_period <= 2)
2066                         fec_oc_dto_period = 0;
2067                 else
2068                         fec_oc_dto_period -= 2;
2069                 fec_oc_tmd_int_upd_rate = 8;
2070         } else {
2071                 /* (commonAttr->static_clk == false) => dynamic mode */
2072                 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2073                 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2074                 fec_oc_tmd_int_upd_rate = 5;
2075         }
2076
2077         /* Write appropriate registers with requested configuration */
2078         status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2079         if (status < 0)
2080                 goto error;
2081         status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2082         if (status < 0)
2083                 goto error;
2084         status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2085         if (status < 0)
2086                 goto error;
2087         status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2088         if (status < 0)
2089                 goto error;
2090         status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2091         if (status < 0)
2092                 goto error;
2093         status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2094         if (status < 0)
2095                 goto error;
2096
2097         /* Rate integration settings */
2098         status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2099         if (status < 0)
2100                 goto error;
2101         status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2102                          fec_oc_tmd_int_upd_rate);
2103         if (status < 0)
2104                 goto error;
2105         status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2106 error:
2107         if (status < 0)
2108                 pr_err("Error %d on %s\n", status, __func__);
2109         return status;
2110 }
2111
2112 static int mpegts_configure_polarity(struct drxk_state *state)
2113 {
2114         u16 fec_oc_reg_ipr_invert = 0;
2115
2116         /* Data mask for the output data byte */
2117         u16 invert_data_mask =
2118             FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2119             FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2120             FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2121             FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2122
2123         dprintk(1, "\n");
2124
2125         /* Control selective inversion of output bits */
2126         fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2127         if (state->m_invert_data)
2128                 fec_oc_reg_ipr_invert |= invert_data_mask;
2129         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2130         if (state->m_invert_err)
2131                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2132         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2133         if (state->m_invert_str)
2134                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2135         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2136         if (state->m_invert_val)
2137                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2138         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2139         if (state->m_invert_clk)
2140                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2141
2142         return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2143 }
2144
2145 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2146
2147 static int set_agc_rf(struct drxk_state *state,
2148                     struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2149 {
2150         int status = -EINVAL;
2151         u16 data = 0;
2152         struct s_cfg_agc *p_if_agc_settings;
2153
2154         dprintk(1, "\n");
2155
2156         if (p_agc_cfg == NULL)
2157                 goto error;
2158
2159         switch (p_agc_cfg->ctrl_mode) {
2160         case DRXK_AGC_CTRL_AUTO:
2161                 /* Enable RF AGC DAC */
2162                 status = read16(state, IQM_AF_STDBY__A, &data);
2163                 if (status < 0)
2164                         goto error;
2165                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2166                 status = write16(state, IQM_AF_STDBY__A, data);
2167                 if (status < 0)
2168                         goto error;
2169                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2170                 if (status < 0)
2171                         goto error;
2172
2173                 /* Enable SCU RF AGC loop */
2174                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2175
2176                 /* Polarity */
2177                 if (state->m_rf_agc_pol)
2178                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2179                 else
2180                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2181                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2182                 if (status < 0)
2183                         goto error;
2184
2185                 /* Set speed (using complementary reduction value) */
2186                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2187                 if (status < 0)
2188                         goto error;
2189
2190                 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2191                 data |= (~(p_agc_cfg->speed <<
2192                                 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2193                                 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2194
2195                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2196                 if (status < 0)
2197                         goto error;
2198
2199                 if (is_dvbt(state))
2200                         p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2201                 else if (is_qam(state))
2202                         p_if_agc_settings = &state->m_qam_if_agc_cfg;
2203                 else
2204                         p_if_agc_settings = &state->m_atv_if_agc_cfg;
2205                 if (p_if_agc_settings == NULL) {
2206                         status = -EINVAL;
2207                         goto error;
2208                 }
2209
2210                 /* Set TOP, only if IF-AGC is in AUTO mode */
2211                 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
2212                         status = write16(state,
2213                                          SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2214                                          p_agc_cfg->top);
2215                         if (status < 0)
2216                                 goto error;
2217                 }
2218
2219                 /* Cut-Off current */
2220                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2221                                  p_agc_cfg->cut_off_current);
2222                 if (status < 0)
2223                         goto error;
2224
2225                 /* Max. output level */
2226                 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2227                                  p_agc_cfg->max_output_level);
2228                 if (status < 0)
2229                         goto error;
2230
2231                 break;
2232
2233         case DRXK_AGC_CTRL_USER:
2234                 /* Enable RF AGC DAC */
2235                 status = read16(state, IQM_AF_STDBY__A, &data);
2236                 if (status < 0)
2237                         goto error;
2238                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2239                 status = write16(state, IQM_AF_STDBY__A, data);
2240                 if (status < 0)
2241                         goto error;
2242
2243                 /* Disable SCU RF AGC loop */
2244                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2245                 if (status < 0)
2246                         goto error;
2247                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2248                 if (state->m_rf_agc_pol)
2249                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2250                 else
2251                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2252                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2253                 if (status < 0)
2254                         goto error;
2255
2256                 /* SCU c.o.c. to 0, enabling full control range */
2257                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2258                 if (status < 0)
2259                         goto error;
2260
2261                 /* Write value to output pin */
2262                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2263                                  p_agc_cfg->output_level);
2264                 if (status < 0)
2265                         goto error;
2266                 break;
2267
2268         case DRXK_AGC_CTRL_OFF:
2269                 /* Disable RF AGC DAC */
2270                 status = read16(state, IQM_AF_STDBY__A, &data);
2271                 if (status < 0)
2272                         goto error;
2273                 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2274                 status = write16(state, IQM_AF_STDBY__A, data);
2275                 if (status < 0)
2276                         goto error;
2277
2278                 /* Disable SCU RF AGC loop */
2279                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2280                 if (status < 0)
2281                         goto error;
2282                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2283                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2284                 if (status < 0)
2285                         goto error;
2286                 break;
2287
2288         default:
2289                 status = -EINVAL;
2290
2291         }
2292 error:
2293         if (status < 0)
2294                 pr_err("Error %d on %s\n", status, __func__);
2295         return status;
2296 }
2297
2298 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2299
2300 static int set_agc_if(struct drxk_state *state,
2301                     struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2302 {
2303         u16 data = 0;
2304         int status = 0;
2305         struct s_cfg_agc *p_rf_agc_settings;
2306
2307         dprintk(1, "\n");
2308
2309         switch (p_agc_cfg->ctrl_mode) {
2310         case DRXK_AGC_CTRL_AUTO:
2311
2312                 /* Enable IF AGC DAC */
2313                 status = read16(state, IQM_AF_STDBY__A, &data);
2314                 if (status < 0)
2315                         goto error;
2316                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2317                 status = write16(state, IQM_AF_STDBY__A, data);
2318                 if (status < 0)
2319                         goto error;
2320
2321                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2322                 if (status < 0)
2323                         goto error;
2324
2325                 /* Enable SCU IF AGC loop */
2326                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2327
2328                 /* Polarity */
2329                 if (state->m_if_agc_pol)
2330                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2331                 else
2332                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2333                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2334                 if (status < 0)
2335                         goto error;
2336
2337                 /* Set speed (using complementary reduction value) */
2338                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2339                 if (status < 0)
2340                         goto error;
2341                 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2342                 data |= (~(p_agc_cfg->speed <<
2343                                 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2344                                 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2345
2346                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2347                 if (status < 0)
2348                         goto error;
2349
2350                 if (is_qam(state))
2351                         p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2352                 else
2353                         p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2354                 if (p_rf_agc_settings == NULL)
2355                         return -1;
2356                 /* Restore TOP */
2357                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2358                                  p_rf_agc_settings->top);
2359                 if (status < 0)
2360                         goto error;
2361                 break;
2362
2363         case DRXK_AGC_CTRL_USER:
2364
2365                 /* Enable IF AGC DAC */
2366                 status = read16(state, IQM_AF_STDBY__A, &data);
2367                 if (status < 0)
2368                         goto error;
2369                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2370                 status = write16(state, IQM_AF_STDBY__A, data);
2371                 if (status < 0)
2372                         goto error;
2373
2374                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2375                 if (status < 0)
2376                         goto error;
2377
2378                 /* Disable SCU IF AGC loop */
2379                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2380
2381                 /* Polarity */
2382                 if (state->m_if_agc_pol)
2383                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2384                 else
2385                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2386                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2387                 if (status < 0)
2388                         goto error;
2389
2390                 /* Write value to output pin */
2391                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2392                                  p_agc_cfg->output_level);
2393                 if (status < 0)
2394                         goto error;
2395                 break;
2396
2397         case DRXK_AGC_CTRL_OFF:
2398
2399                 /* Disable If AGC DAC */
2400                 status = read16(state, IQM_AF_STDBY__A, &data);
2401                 if (status < 0)
2402                         goto error;
2403                 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2404                 status = write16(state, IQM_AF_STDBY__A, data);
2405                 if (status < 0)
2406                         goto error;
2407
2408                 /* Disable SCU IF AGC loop */
2409                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2410                 if (status < 0)
2411                         goto error;
2412                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2413                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2414                 if (status < 0)
2415                         goto error;
2416                 break;
2417         }               /* switch (agcSettingsIf->ctrl_mode) */
2418
2419         /* always set the top to support
2420                 configurations without if-loop */
2421         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2422 error:
2423         if (status < 0)
2424                 pr_err("Error %d on %s\n", status, __func__);
2425         return status;
2426 }
2427
2428 static int get_qam_signal_to_noise(struct drxk_state *state,
2429                                s32 *p_signal_to_noise)
2430 {
2431         int status = 0;
2432         u16 qam_sl_err_power = 0;       /* accum. error between
2433                                         raw and sliced symbols */
2434         u32 qam_sl_sig_power = 0;       /* used for MER, depends of
2435                                         QAM modulation */
2436         u32 qam_sl_mer = 0;     /* QAM MER */
2437
2438         dprintk(1, "\n");
2439
2440         /* MER calculation */
2441
2442         /* get the register value needed for MER */
2443         status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2444         if (status < 0) {
2445                 pr_err("Error %d on %s\n", status, __func__);
2446                 return -EINVAL;
2447         }
2448
2449         switch (state->props.modulation) {
2450         case QAM_16:
2451                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2452                 break;
2453         case QAM_32:
2454                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2455                 break;
2456         case QAM_64:
2457                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2458                 break;
2459         case QAM_128:
2460                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2461                 break;
2462         default:
2463         case QAM_256:
2464                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2465                 break;
2466         }
2467
2468         if (qam_sl_err_power > 0) {
2469                 qam_sl_mer = log10times100(qam_sl_sig_power) -
2470                         log10times100((u32) qam_sl_err_power);
2471         }
2472         *p_signal_to_noise = qam_sl_mer;
2473
2474         return status;
2475 }
2476
2477 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2478                                 s32 *p_signal_to_noise)
2479 {
2480         int status;
2481         u16 reg_data = 0;
2482         u32 eq_reg_td_sqr_err_i = 0;
2483         u32 eq_reg_td_sqr_err_q = 0;
2484         u16 eq_reg_td_sqr_err_exp = 0;
2485         u16 eq_reg_td_tps_pwr_ofs = 0;
2486         u16 eq_reg_td_req_smb_cnt = 0;
2487         u32 tps_cnt = 0;
2488         u32 sqr_err_iq = 0;
2489         u32 a = 0;
2490         u32 b = 0;
2491         u32 c = 0;
2492         u32 i_mer = 0;
2493         u16 transmission_params = 0;
2494
2495         dprintk(1, "\n");
2496
2497         status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2498                         &eq_reg_td_tps_pwr_ofs);
2499         if (status < 0)
2500                 goto error;
2501         status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2502                         &eq_reg_td_req_smb_cnt);
2503         if (status < 0)
2504                 goto error;
2505         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2506                         &eq_reg_td_sqr_err_exp);
2507         if (status < 0)
2508                 goto error;
2509         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2510                         &reg_data);
2511         if (status < 0)
2512                 goto error;
2513         /* Extend SQR_ERR_I operational range */
2514         eq_reg_td_sqr_err_i = (u32) reg_data;
2515         if ((eq_reg_td_sqr_err_exp > 11) &&
2516                 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2517                 eq_reg_td_sqr_err_i += 0x00010000UL;
2518         }
2519         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);
2520         if (status < 0)
2521                 goto error;
2522         /* Extend SQR_ERR_Q operational range */
2523         eq_reg_td_sqr_err_q = (u32) reg_data;
2524         if ((eq_reg_td_sqr_err_exp > 11) &&
2525                 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2526                 eq_reg_td_sqr_err_q += 0x00010000UL;
2527
2528         status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2529                         &transmission_params);
2530         if (status < 0)
2531                 goto error;
2532
2533         /* Check input data for MER */
2534
2535         /* MER calculation (in 0.1 dB) without math.h */
2536         if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2537                 i_mer = 0;
2538         else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2539                 /* No error at all, this must be the HW reset value
2540                         * Apparently no first measurement yet
2541                         * Set MER to 0.0 */
2542                 i_mer = 0;
2543         } else {
2544                 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2545                         eq_reg_td_sqr_err_exp;
2546                 if ((transmission_params &
2547                         OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2548                         == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2549                         tps_cnt = 17;
2550                 else
2551                         tps_cnt = 68;
2552
2553                 /* IMER = 100 * log10 (x)
2554                         where x = (eq_reg_td_tps_pwr_ofs^2 *
2555                         eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2556
2557                         => IMER = a + b -c
2558                         where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2559                         b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2560                         c = 100 * log10 (sqr_err_iq)
2561                         */
2562
2563                 /* log(x) x = 9bits * 9bits->18 bits  */
2564                 a = log10times100(eq_reg_td_tps_pwr_ofs *
2565                                         eq_reg_td_tps_pwr_ofs);
2566                 /* log(x) x = 16bits * 7bits->23 bits  */
2567                 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2568                 /* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2569                 c = log10times100(sqr_err_iq);
2570
2571                 i_mer = a + b - c;
2572         }
2573         *p_signal_to_noise = i_mer;
2574
2575 error:
2576         if (status < 0)
2577                 pr_err("Error %d on %s\n", status, __func__);
2578         return status;
2579 }
2580
2581 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2582 {
2583         dprintk(1, "\n");
2584
2585         *p_signal_to_noise = 0;
2586         switch (state->m_operation_mode) {
2587         case OM_DVBT:
2588                 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2589         case OM_QAM_ITU_A:
2590         case OM_QAM_ITU_C:
2591                 return get_qam_signal_to_noise(state, p_signal_to_noise);
2592         default:
2593                 break;
2594         }
2595         return 0;
2596 }
2597
2598 #if 0
2599 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2600 {
2601         /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2602         int status = 0;
2603
2604         dprintk(1, "\n");
2605
2606         static s32 QE_SN[] = {
2607                 51,             /* QPSK 1/2 */
2608                 69,             /* QPSK 2/3 */
2609                 79,             /* QPSK 3/4 */
2610                 89,             /* QPSK 5/6 */
2611                 97,             /* QPSK 7/8 */
2612                 108,            /* 16-QAM 1/2 */
2613                 131,            /* 16-QAM 2/3 */
2614                 146,            /* 16-QAM 3/4 */
2615                 156,            /* 16-QAM 5/6 */
2616                 160,            /* 16-QAM 7/8 */
2617                 165,            /* 64-QAM 1/2 */
2618                 187,            /* 64-QAM 2/3 */
2619                 202,            /* 64-QAM 3/4 */
2620                 216,            /* 64-QAM 5/6 */
2621                 225,            /* 64-QAM 7/8 */
2622         };
2623
2624         *p_quality = 0;
2625
2626         do {
2627                 s32 signal_to_noise = 0;
2628                 u16 constellation = 0;
2629                 u16 code_rate = 0;
2630                 u32 signal_to_noise_rel;
2631                 u32 ber_quality;
2632
2633                 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2634                 if (status < 0)
2635                         break;
2636                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2637                                 &constellation);
2638                 if (status < 0)
2639                         break;
2640                 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2641
2642                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2643                                 &code_rate);
2644                 if (status < 0)
2645                         break;
2646                 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2647
2648                 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2649                     code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2650                         break;
2651                 signal_to_noise_rel = signal_to_noise -
2652                     QE_SN[constellation * 5 + code_rate];
2653                 ber_quality = 100;
2654
2655                 if (signal_to_noise_rel < -70)
2656                         *p_quality = 0;
2657                 else if (signal_to_noise_rel < 30)
2658                         *p_quality = ((signal_to_noise_rel + 70) *
2659                                      ber_quality) / 100;
2660                 else
2661                         *p_quality = ber_quality;
2662         } while (0);
2663         return 0;
2664 };
2665
2666 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2667 {
2668         int status = 0;
2669         *p_quality = 0;
2670
2671         dprintk(1, "\n");
2672
2673         do {
2674                 u32 signal_to_noise = 0;
2675                 u32 ber_quality = 100;
2676                 u32 signal_to_noise_rel = 0;
2677
2678                 status = get_qam_signal_to_noise(state, &signal_to_noise);
2679                 if (status < 0)
2680                         break;
2681
2682                 switch (state->props.modulation) {
2683                 case QAM_16:
2684                         signal_to_noise_rel = signal_to_noise - 200;
2685                         break;
2686                 case QAM_32:
2687                         signal_to_noise_rel = signal_to_noise - 230;
2688                         break;  /* Not in NorDig */
2689                 case QAM_64:
2690                         signal_to_noise_rel = signal_to_noise - 260;
2691                         break;
2692                 case QAM_128:
2693                         signal_to_noise_rel = signal_to_noise - 290;
2694                         break;
2695                 default:
2696                 case QAM_256:
2697                         signal_to_noise_rel = signal_to_noise - 320;
2698                         break;
2699                 }
2700
2701                 if (signal_to_noise_rel < -70)
2702                         *p_quality = 0;
2703                 else if (signal_to_noise_rel < 30)
2704                         *p_quality = ((signal_to_noise_rel + 70) *
2705                                      ber_quality) / 100;
2706                 else
2707                         *p_quality = ber_quality;
2708         } while (0);
2709
2710         return status;
2711 }
2712
2713 static int get_quality(struct drxk_state *state, s32 *p_quality)
2714 {
2715         dprintk(1, "\n");
2716
2717         switch (state->m_operation_mode) {
2718         case OM_DVBT:
2719                 return get_dvbt_quality(state, p_quality);
2720         case OM_QAM_ITU_A:
2721                 return get_dvbc_quality(state, p_quality);
2722         default:
2723                 break;
2724         }
2725
2726         return 0;
2727 }
2728 #endif
2729
2730 /* Free data ram in SIO HI */
2731 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2732 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2733
2734 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2735 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2736 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2737 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2738
2739 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2740 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2741 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2742
2743 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2744 {
2745         int status = -EINVAL;
2746
2747         dprintk(1, "\n");
2748
2749         if (state->m_drxk_state == DRXK_UNINITIALIZED)
2750                 return 0;
2751         if (state->m_drxk_state == DRXK_POWERED_DOWN)
2752                 goto error;
2753
2754         if (state->no_i2c_bridge)
2755                 return 0;
2756
2757         status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2758                          SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2759         if (status < 0)
2760                 goto error;
2761         if (b_enable_bridge) {
2762                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2763                                  SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2764                 if (status < 0)
2765                         goto error;
2766         } else {
2767                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2768                                  SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2769                 if (status < 0)
2770                         goto error;
2771         }
2772
2773         status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2774
2775 error:
2776         if (status < 0)
2777                 pr_err("Error %d on %s\n", status, __func__);
2778         return status;
2779 }
2780
2781 static int set_pre_saw(struct drxk_state *state,
2782                      struct s_cfg_pre_saw *p_pre_saw_cfg)
2783 {
2784         int status = -EINVAL;
2785
2786         dprintk(1, "\n");
2787
2788         if ((p_pre_saw_cfg == NULL)
2789             || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2790                 goto error;
2791
2792         status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2793 error:
2794         if (status < 0)
2795                 pr_err("Error %d on %s\n", status, __func__);
2796         return status;
2797 }
2798
2799 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2800                        u16 rom_offset, u16 nr_of_elements, u32 time_out)
2801 {
2802         u16 bl_status = 0;
2803         u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2804         u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2805         int status;
2806         unsigned long end;
2807
2808         dprintk(1, "\n");
2809
2810         mutex_lock(&state->mutex);
2811         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2812         if (status < 0)
2813                 goto error;
2814         status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2815         if (status < 0)
2816                 goto error;
2817         status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2818         if (status < 0)
2819                 goto error;
2820         status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2821         if (status < 0)
2822                 goto error;
2823         status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2824         if (status < 0)
2825                 goto error;
2826         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2827         if (status < 0)
2828                 goto error;
2829
2830         end = jiffies + msecs_to_jiffies(time_out);
2831         do {
2832                 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2833                 if (status < 0)
2834                         goto error;
2835         } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2836         if (bl_status == 0x1) {
2837                 pr_err("SIO not ready\n");
2838                 status = -EINVAL;
2839                 goto error2;
2840         }
2841 error:
2842         if (status < 0)
2843                 pr_err("Error %d on %s\n", status, __func__);
2844 error2:
2845         mutex_unlock(&state->mutex);
2846         return status;
2847
2848 }
2849
2850 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2851 {
2852         u16 data = 0;
2853         int status;
2854
2855         dprintk(1, "\n");
2856
2857         /* start measurement */
2858         status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2859         if (status < 0)
2860                 goto error;
2861         status = write16(state, IQM_AF_START_LOCK__A, 1);
2862         if (status < 0)
2863                 goto error;
2864
2865         *count = 0;
2866         status = read16(state, IQM_AF_PHASE0__A, &data);
2867         if (status < 0)
2868                 goto error;
2869         if (data == 127)
2870                 *count = *count + 1;
2871         status = read16(state, IQM_AF_PHASE1__A, &data);
2872         if (status < 0)
2873                 goto error;
2874         if (data == 127)
2875                 *count = *count + 1;
2876         status = read16(state, IQM_AF_PHASE2__A, &data);
2877         if (status < 0)
2878                 goto error;
2879         if (data == 127)
2880                 *count = *count + 1;
2881
2882 error:
2883         if (status < 0)
2884                 pr_err("Error %d on %s\n", status, __func__);
2885         return status;
2886 }
2887
2888 static int adc_synchronization(struct drxk_state *state)
2889 {
2890         u16 count = 0;
2891         int status;
2892
2893         dprintk(1, "\n");
2894
2895         status = adc_sync_measurement(state, &count);
2896         if (status < 0)
2897                 goto error;
2898
2899         if (count == 1) {
2900                 /* Try sampling on a different edge */
2901                 u16 clk_neg = 0;
2902
2903                 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2904                 if (status < 0)
2905                         goto error;
2906                 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2907                         IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2908                         clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2909                         clk_neg |=
2910                                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2911                 } else {
2912                         clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2913                         clk_neg |=
2914                                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2915                 }
2916                 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2917                 if (status < 0)
2918                         goto error;
2919                 status = adc_sync_measurement(state, &count);
2920                 if (status < 0)
2921                         goto error;
2922         }
2923
2924         if (count < 2)
2925                 status = -EINVAL;
2926 error:
2927         if (status < 0)
2928                 pr_err("Error %d on %s\n", status, __func__);
2929         return status;
2930 }
2931
2932 static int set_frequency_shifter(struct drxk_state *state,
2933                                u16 intermediate_freqk_hz,
2934                                s32 tuner_freq_offset, bool is_dtv)
2935 {
2936         bool select_pos_image = false;
2937         u32 rf_freq_residual = tuner_freq_offset;
2938         u32 fm_frequency_shift = 0;
2939         bool tuner_mirror = !state->m_b_mirror_freq_spect;
2940         u32 adc_freq;
2941         bool adc_flip;
2942         int status;
2943         u32 if_freq_actual;
2944         u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2945         u32 frequency_shift;
2946         bool image_to_select;
2947
2948         dprintk(1, "\n");
2949
2950         /*
2951            Program frequency shifter
2952            No need to account for mirroring on RF
2953          */
2954         if (is_dtv) {
2955                 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2956                     (state->m_operation_mode == OM_QAM_ITU_C) ||
2957                     (state->m_operation_mode == OM_DVBT))
2958                         select_pos_image = true;
2959                 else
2960                         select_pos_image = false;
2961         }
2962         if (tuner_mirror)
2963                 /* tuner doesn't mirror */
2964                 if_freq_actual = intermediate_freqk_hz +
2965                     rf_freq_residual + fm_frequency_shift;
2966         else
2967                 /* tuner mirrors */
2968                 if_freq_actual = intermediate_freqk_hz -
2969                     rf_freq_residual - fm_frequency_shift;
2970         if (if_freq_actual > sampling_frequency / 2) {
2971                 /* adc mirrors */
2972                 adc_freq = sampling_frequency - if_freq_actual;
2973                 adc_flip = true;
2974         } else {
2975                 /* adc doesn't mirror */
2976                 adc_freq = if_freq_actual;
2977                 adc_flip = false;
2978         }
2979
2980         frequency_shift = adc_freq;
2981         image_to_select = state->m_rfmirror ^ tuner_mirror ^
2982             adc_flip ^ select_pos_image;
2983         state->m_iqm_fs_rate_ofs =
2984             Frac28a((frequency_shift), sampling_frequency);
2985
2986         if (image_to_select)
2987                 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2988
2989         /* Program frequency shifter with tuner offset compensation */
2990         /* frequency_shift += tuner_freq_offset; TODO */
2991         status = write32(state, IQM_FS_RATE_OFS_LO__A,
2992                          state->m_iqm_fs_rate_ofs);
2993         if (status < 0)
2994                 pr_err("Error %d on %s\n", status, __func__);
2995         return status;
2996 }
2997
2998 static int init_agc(struct drxk_state *state, bool is_dtv)
2999 {
3000         u16 ingain_tgt = 0;
3001         u16 ingain_tgt_min = 0;
3002         u16 ingain_tgt_max = 0;
3003         u16 clp_cyclen = 0;
3004         u16 clp_sum_min = 0;
3005         u16 clp_dir_to = 0;
3006         u16 sns_sum_min = 0;
3007         u16 sns_sum_max = 0;
3008         u16 clp_sum_max = 0;
3009         u16 sns_dir_to = 0;
3010         u16 ki_innergain_min = 0;
3011         u16 if_iaccu_hi_tgt = 0;
3012         u16 if_iaccu_hi_tgt_min = 0;
3013         u16 if_iaccu_hi_tgt_max = 0;
3014         u16 data = 0;
3015         u16 fast_clp_ctrl_delay = 0;
3016         u16 clp_ctrl_mode = 0;
3017         int status = 0;
3018
3019         dprintk(1, "\n");
3020
3021         /* Common settings */
3022         sns_sum_max = 1023;
3023         if_iaccu_hi_tgt_min = 2047;
3024         clp_cyclen = 500;
3025         clp_sum_max = 1023;
3026
3027         /* AGCInit() not available for DVBT; init done in microcode */
3028         if (!is_qam(state)) {
3029                 pr_err("%s: mode %d is not DVB-C\n",
3030                        __func__, state->m_operation_mode);
3031                 return -EINVAL;
3032         }
3033
3034         /* FIXME: Analog TV AGC require different settings */
3035
3036         /* Standard specific settings */
3037         clp_sum_min = 8;
3038         clp_dir_to = (u16) -9;
3039         clp_ctrl_mode = 0;
3040         sns_sum_min = 8;
3041         sns_dir_to = (u16) -9;
3042         ki_innergain_min = (u16) -1030;
3043         if_iaccu_hi_tgt_max = 0x2380;
3044         if_iaccu_hi_tgt = 0x2380;
3045         ingain_tgt_min = 0x0511;
3046         ingain_tgt = 0x0511;
3047         ingain_tgt_max = 5119;
3048         fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3049
3050         status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3051                          fast_clp_ctrl_delay);
3052         if (status < 0)
3053                 goto error;
3054
3055         status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3056         if (status < 0)
3057                 goto error;
3058         status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3059         if (status < 0)
3060                 goto error;
3061         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3062         if (status < 0)
3063                 goto error;
3064         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3065         if (status < 0)
3066                 goto error;
3067         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3068                          if_iaccu_hi_tgt_min);
3069         if (status < 0)
3070                 goto error;
3071         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3072                          if_iaccu_hi_tgt_max);
3073         if (status < 0)
3074                 goto error;
3075         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3076         if (status < 0)
3077                 goto error;
3078         status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3079         if (status < 0)
3080                 goto error;
3081         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3082         if (status < 0)
3083                 goto error;
3084         status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3085         if (status < 0)
3086                 goto error;
3087         status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3088         if (status < 0)
3089                 goto error;
3090         status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3091         if (status < 0)
3092                 goto error;
3093
3094         status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3095                          ki_innergain_min);
3096         if (status < 0)
3097                 goto error;
3098         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3099                          if_iaccu_hi_tgt);
3100         if (status < 0)
3101                 goto error;
3102         status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3103         if (status < 0)
3104                 goto error;
3105
3106         status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3107         if (status < 0)
3108                 goto error;
3109         status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3110         if (status < 0)
3111                 goto error;
3112         status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3113         if (status < 0)
3114                 goto error;
3115
3116         status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3117         if (status < 0)
3118                 goto error;
3119         status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3120         if (status < 0)
3121                 goto error;
3122         status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3123         if (status < 0)
3124                 goto error;
3125         status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3126         if (status < 0)
3127                 goto error;
3128         status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3129         if (status < 0)
3130                 goto error;
3131         status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3132         if (status < 0)
3133                 goto error;
3134         status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3135         if (status < 0)
3136                 goto error;
3137         status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3138         if (status < 0)
3139                 goto error;
3140         status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3141         if (status < 0)
3142                 goto error;
3143         status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3144         if (status < 0)
3145                 goto error;
3146         status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3147         if (status < 0)
3148                 goto error;
3149         status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3150         if (status < 0)
3151                 goto error;
3152         status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3153         if (status < 0)
3154                 goto error;
3155         status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3156         if (status < 0)
3157                 goto error;
3158         status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3159         if (status < 0)
3160                 goto error;
3161         status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3162         if (status < 0)
3163                 goto error;
3164         status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3165         if (status < 0)
3166                 goto error;
3167         status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3168         if (status < 0)
3169                 goto error;
3170         status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3171         if (status < 0)
3172                 goto error;
3173
3174         /* Initialize inner-loop KI gain factors */
3175         status = read16(state, SCU_RAM_AGC_KI__A, &data);
3176         if (status < 0)
3177                 goto error;
3178
3179         data = 0x0657;
3180         data &= ~SCU_RAM_AGC_KI_RF__M;
3181         data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3182         data &= ~SCU_RAM_AGC_KI_IF__M;
3183         data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3184
3185         status = write16(state, SCU_RAM_AGC_KI__A, data);
3186 error:
3187         if (status < 0)
3188                 pr_err("Error %d on %s\n", status, __func__);
3189         return status;
3190 }
3191
3192 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3193 {
3194         int status;
3195
3196         dprintk(1, "\n");
3197         if (packet_err == NULL)
3198                 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3199         else
3200                 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3201                                 packet_err);
3202         if (status < 0)
3203                 pr_err("Error %d on %s\n", status, __func__);
3204         return status;
3205 }
3206
3207 static int dvbt_sc_command(struct drxk_state *state,
3208                          u16 cmd, u16 subcmd,
3209                          u16 param0, u16 param1, u16 param2,
3210                          u16 param3, u16 param4)
3211 {
3212         u16 cur_cmd = 0;
3213         u16 err_code = 0;
3214         u16 retry_cnt = 0;
3215         u16 sc_exec = 0;
3216         int status;
3217
3218         dprintk(1, "\n");
3219         status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3220         if (sc_exec != 1) {
3221                 /* SC is not running */
3222                 status = -EINVAL;
3223         }
3224         if (status < 0)
3225                 goto error;
3226
3227         /* Wait until sc is ready to receive command */
3228         retry_cnt = 0;
3229         do {
3230                 usleep_range(1000, 2000);
3231                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3232                 retry_cnt++;
3233         } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3234         if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3235                 goto error;
3236
3237         /* Write sub-command */
3238         switch (cmd) {
3239                 /* All commands using sub-cmd */
3240         case OFDM_SC_RA_RAM_CMD_PROC_START:
3241         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3242         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3243                 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3244                 if (status < 0)
3245                         goto error;
3246                 break;
3247         default:
3248                 /* Do nothing */
3249                 break;
3250         }
3251
3252         /* Write needed parameters and the command */
3253         status = 0;
3254         switch (cmd) {
3255                 /* All commands using 5 parameters */
3256                 /* All commands using 4 parameters */
3257                 /* All commands using 3 parameters */
3258                 /* All commands using 2 parameters */
3259         case OFDM_SC_RA_RAM_CMD_PROC_START:
3260         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3261         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3262                 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3263                 /* fall through - All commands using 1 parameters */
3264         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3265         case OFDM_SC_RA_RAM_CMD_USER_IO:
3266                 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3267                 /* fall through - All commands using 0 parameters */
3268         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3269         case OFDM_SC_RA_RAM_CMD_NULL:
3270                 /* Write command */
3271                 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3272                 break;
3273         default:
3274                 /* Unknown command */
3275                 status = -EINVAL;
3276         }
3277         if (status < 0)
3278                 goto error;
3279
3280         /* Wait until sc is ready processing command */
3281         retry_cnt = 0;
3282         do {
3283                 usleep_range(1000, 2000);
3284                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3285                 retry_cnt++;
3286         } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3287         if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3288                 goto error;
3289
3290         /* Check for illegal cmd */
3291         status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3292         if (err_code == 0xFFFF) {
3293                 /* illegal command */
3294                 status = -EINVAL;
3295         }
3296         if (status < 0)
3297                 goto error;
3298
3299         /* Retrieve results parameters from SC */
3300         switch (cmd) {
3301                 /* All commands yielding 5 results */
3302                 /* All commands yielding 4 results */
3303                 /* All commands yielding 3 results */
3304                 /* All commands yielding 2 results */
3305                 /* All commands yielding 1 result */
3306         case OFDM_SC_RA_RAM_CMD_USER_IO:
3307         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3308                 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3309                 /* All commands yielding 0 results */
3310         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3311         case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3312         case OFDM_SC_RA_RAM_CMD_PROC_START:
3313         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3314         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3315         case OFDM_SC_RA_RAM_CMD_NULL:
3316                 break;
3317         default:
3318                 /* Unknown command */
3319                 status = -EINVAL;
3320                 break;
3321         }                       /* switch (cmd->cmd) */
3322 error:
3323         if (status < 0)
3324                 pr_err("Error %d on %s\n", status, __func__);
3325         return status;
3326 }
3327
3328 static int power_up_dvbt(struct drxk_state *state)
3329 {
3330         enum drx_power_mode power_mode = DRX_POWER_UP;
3331         int status;
3332
3333         dprintk(1, "\n");
3334         status = ctrl_power_mode(state, &power_mode);
3335         if (status < 0)
3336                 pr_err("Error %d on %s\n", status, __func__);
3337         return status;
3338 }
3339
3340 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3341 {
3342         int status;
3343
3344         dprintk(1, "\n");
3345         if (*enabled)
3346                 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3347         else
3348                 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3349         if (status < 0)
3350                 pr_err("Error %d on %s\n", status, __func__);
3351         return status;
3352 }
3353
3354 #define DEFAULT_FR_THRES_8K     4000
3355 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3356 {
3357
3358         int status;
3359
3360         dprintk(1, "\n");
3361         if (*enabled) {
3362                 /* write mask to 1 */
3363                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3364                                    DEFAULT_FR_THRES_8K);
3365         } else {
3366                 /* write mask to 0 */
3367                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3368         }
3369         if (status < 0)
3370                 pr_err("Error %d on %s\n", status, __func__);
3371
3372         return status;
3373 }
3374
3375 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3376                                 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3377 {
3378         u16 data = 0;
3379         int status;
3380
3381         dprintk(1, "\n");
3382         status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3383         if (status < 0)
3384                 goto error;
3385
3386         switch (echo_thres->fft_mode) {
3387         case DRX_FFTMODE_2K:
3388                 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3389                 data |= ((echo_thres->threshold <<
3390                         OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3391                         & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3392                 break;
3393         case DRX_FFTMODE_8K:
3394                 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3395                 data |= ((echo_thres->threshold <<
3396                         OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3397                         & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3398                 break;
3399         default:
3400                 return -EINVAL;
3401         }
3402
3403         status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3404 error:
3405         if (status < 0)
3406                 pr_err("Error %d on %s\n", status, __func__);
3407         return status;
3408 }
3409
3410 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3411                                enum drxk_cfg_dvbt_sqi_speed *speed)
3412 {
3413         int status = -EINVAL;
3414
3415         dprintk(1, "\n");
3416
3417         switch (*speed) {
3418         case DRXK_DVBT_SQI_SPEED_FAST:
3419         case DRXK_DVBT_SQI_SPEED_MEDIUM:
3420         case DRXK_DVBT_SQI_SPEED_SLOW:
3421                 break;
3422         default:
3423                 goto error;
3424         }
3425         status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3426                            (u16) *speed);
3427 error:
3428         if (status < 0)
3429                 pr_err("Error %d on %s\n", status, __func__);
3430         return status;
3431 }
3432
3433 /*============================================================================*/
3434
3435 /*
3436 * \brief Activate DVBT specific presets
3437 * \param demod instance of demodulator.
3438 * \return DRXStatus_t.
3439 *
3440 * Called in DVBTSetStandard
3441 *
3442 */
3443 static int dvbt_activate_presets(struct drxk_state *state)
3444 {
3445         int status;
3446         bool setincenable = false;
3447         bool setfrenable = true;
3448
3449         struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3450         struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3451
3452         dprintk(1, "\n");
3453         status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3454         if (status < 0)
3455                 goto error;
3456         status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3457         if (status < 0)
3458                 goto error;
3459         status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3460         if (status < 0)
3461                 goto error;
3462         status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3463         if (status < 0)
3464                 goto error;
3465         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3466                          state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3467 error:
3468         if (status < 0)
3469                 pr_err("Error %d on %s\n", status, __func__);
3470         return status;
3471 }
3472
3473 /*============================================================================*/
3474
3475 /*
3476 * \brief Initialize channelswitch-independent settings for DVBT.
3477 * \param demod instance of demodulator.
3478 * \return DRXStatus_t.
3479 *
3480 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3481 * the DVB-T taps from the drxk_filters.h are used.
3482 */
3483 static int set_dvbt_standard(struct drxk_state *state,
3484                            enum operation_mode o_mode)
3485 {
3486         u16 cmd_result = 0;
3487         u16 data = 0;
3488         int status;
3489
3490         dprintk(1, "\n");
3491
3492         power_up_dvbt(state);
3493         /* added antenna switch */
3494         switch_antenna_to_dvbt(state);
3495         /* send OFDM reset command */
3496         status = scu_command(state,
3497                              SCU_RAM_COMMAND_STANDARD_OFDM
3498                              | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3499                              0, NULL, 1, &cmd_result);
3500         if (status < 0)
3501                 goto error;
3502
3503         /* send OFDM setenv command */
3504         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3505                              | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3506                              0, NULL, 1, &cmd_result);
3507         if (status < 0)
3508                 goto error;
3509
3510         /* reset datapath for OFDM, processors first */
3511         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3512         if (status < 0)
3513                 goto error;
3514         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3515         if (status < 0)
3516                 goto error;
3517         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3518         if (status < 0)
3519                 goto error;
3520
3521         /* IQM setup */
3522         /* synchronize on ofdstate->m_festart */
3523         status = write16(state, IQM_AF_UPD_SEL__A, 1);
3524         if (status < 0)
3525                 goto error;
3526         /* window size for clipping ADC detection */
3527         status = write16(state, IQM_AF_CLP_LEN__A, 0);
3528         if (status < 0)
3529                 goto error;
3530         /* window size for for sense pre-SAW detection */
3531         status = write16(state, IQM_AF_SNS_LEN__A, 0);
3532         if (status < 0)
3533                 goto error;
3534         /* sense threshold for sense pre-SAW detection */
3535         status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3536         if (status < 0)
3537                 goto error;
3538         status = set_iqm_af(state, true);
3539         if (status < 0)
3540                 goto error;
3541
3542         status = write16(state, IQM_AF_AGC_RF__A, 0);
3543         if (status < 0)
3544                 goto error;
3545
3546         /* Impulse noise cruncher setup */
3547         status = write16(state, IQM_AF_INC_LCT__A, 0);  /* crunch in IQM_CF */
3548         if (status < 0)
3549                 goto error;
3550         status = write16(state, IQM_CF_DET_LCT__A, 0);  /* detect in IQM_CF */
3551         if (status < 0)
3552                 goto error;
3553         status = write16(state, IQM_CF_WND_LEN__A, 3);  /* peak detector window length */
3554         if (status < 0)
3555                 goto error;
3556
3557         status = write16(state, IQM_RC_STRETCH__A, 16);
3558         if (status < 0)
3559                 goto error;
3560         status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3561         if (status < 0)
3562                 goto error;
3563         status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3564         if (status < 0)
3565                 goto error;
3566         status = write16(state, IQM_CF_SCALE__A, 1600);
3567         if (status < 0)
3568                 goto error;
3569         status = write16(state, IQM_CF_SCALE_SH__A, 0);
3570         if (status < 0)
3571                 goto error;
3572
3573         /* virtual clipping threshold for clipping ADC detection */
3574         status = write16(state, IQM_AF_CLP_TH__A, 448);
3575         if (status < 0)
3576                 goto error;
3577         status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3578         if (status < 0)
3579                 goto error;
3580
3581         status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3582                               DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3583         if (status < 0)
3584                 goto error;
3585
3586         status = write16(state, IQM_CF_PKDTH__A, 2);    /* peak detector threshold */
3587         if (status < 0)
3588                 goto error;
3589         status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3590         if (status < 0)
3591                 goto error;
3592         /* enable power measurement interrupt */
3593         status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3594         if (status < 0)
3595                 goto error;
3596         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3597         if (status < 0)
3598                 goto error;
3599
3600         /* IQM will not be reset from here, sync ADC and update/init AGC */
3601         status = adc_synchronization(state);
3602         if (status < 0)
3603                 goto error;
3604         status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3605         if (status < 0)
3606                 goto error;
3607
3608         /* Halt SCU to enable safe non-atomic accesses */
3609         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3610         if (status < 0)
3611                 goto error;
3612
3613         status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3614         if (status < 0)
3615                 goto error;
3616         status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3617         if (status < 0)
3618                 goto error;
3619
3620         /* Set Noise Estimation notch width and enable DC fix */
3621         status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3622         if (status < 0)
3623                 goto error;
3624         data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3625         status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3626         if (status < 0)
3627                 goto error;
3628
3629         /* Activate SCU to enable SCU commands */
3630         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3631         if (status < 0)
3632                 goto error;
3633
3634         if (!state->m_drxk_a3_rom_code) {
3635                 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay  */
3636                 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3637                                  state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3638                 if (status < 0)
3639                         goto error;
3640         }
3641
3642         /* OFDM_SC setup */
3643 #ifdef COMPILE_FOR_NONRT
3644         status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3645         if (status < 0)
3646                 goto error;
3647         status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3648         if (status < 0)
3649                 goto error;
3650 #endif
3651
3652         /* FEC setup */
3653         status = write16(state, FEC_DI_INPUT_CTL__A, 1);        /* OFDM input */
3654         if (status < 0)
3655                 goto error;
3656
3657
3658 #ifdef COMPILE_FOR_NONRT
3659         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3660         if (status < 0)
3661                 goto error;
3662 #else
3663         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3664         if (status < 0)
3665                 goto error;
3666 #endif
3667         status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3668         if (status < 0)
3669                 goto error;
3670
3671         /* Setup MPEG bus */
3672         status = mpegts_dto_setup(state, OM_DVBT);
3673         if (status < 0)
3674                 goto error;
3675         /* Set DVBT Presets */
3676         status = dvbt_activate_presets(state);
3677         if (status < 0)
3678                 goto error;
3679
3680 error:
3681         if (status < 0)
3682                 pr_err("Error %d on %s\n", status, __func__);
3683         return status;
3684 }
3685
3686 /*============================================================================*/
3687 /*
3688 * \brief start dvbt demodulating for channel.
3689 * \param demod instance of demodulator.
3690 * \return DRXStatus_t.
3691 */
3692 static int dvbt_start(struct drxk_state *state)
3693 {
3694         u16 param1;
3695         int status;
3696         /* drxk_ofdm_sc_cmd_t scCmd; */
3697
3698         dprintk(1, "\n");
3699         /* start correct processes to get in lock */
3700         /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3701         param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3702         status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3703                                  OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3704                                  0, 0, 0);
3705         if (status < 0)
3706                 goto error;
3707         /* start FEC OC */
3708         status = mpegts_start(state);
3709         if (status < 0)
3710                 goto error;
3711         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3712         if (status < 0)
3713                 goto error;
3714 error:
3715         if (status < 0)
3716                 pr_err("Error %d on %s\n", status, __func__);
3717         return status;
3718 }
3719
3720
3721 /*============================================================================*/
3722
3723 /*
3724 * \brief Set up dvbt demodulator for channel.
3725 * \param demod instance of demodulator.
3726 * \return DRXStatus_t.
3727 * // original DVBTSetChannel()
3728 */
3729 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3730                    s32 tuner_freq_offset)
3731 {
3732         u16 cmd_result = 0;
3733         u16 transmission_params = 0;
3734         u16 operation_mode = 0;
3735         u32 iqm_rc_rate_ofs = 0;
3736         u32 bandwidth = 0;
3737         u16 param1;
3738         int status;
3739
3740         dprintk(1, "IF =%d, TFO = %d\n",
3741                 intermediate_freqk_hz, tuner_freq_offset);
3742
3743         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3744                             | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3745                             0, NULL, 1, &cmd_result);
3746         if (status < 0)
3747                 goto error;
3748
3749         /* Halt SCU to enable safe non-atomic accesses */
3750         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3751         if (status < 0)
3752                 goto error;
3753
3754         /* Stop processors */
3755         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3756         if (status < 0)
3757                 goto error;
3758         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3759         if (status < 0)
3760                 goto error;
3761
3762         /* Mandatory fix, always stop CP, required to set spl offset back to
3763                 hardware default (is set to 0 by ucode during pilot detection */
3764         status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3765         if (status < 0)
3766                 goto error;
3767
3768         /*== Write channel settings to device ================================*/
3769
3770         /* mode */
3771         switch (state->props.transmission_mode) {
3772         case TRANSMISSION_MODE_AUTO:
3773         default:
3774                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3775                 /* fall through - try first guess DRX_FFTMODE_8K */
3776         case TRANSMISSION_MODE_8K:
3777                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3778                 break;
3779         case TRANSMISSION_MODE_2K:
3780                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3781                 break;
3782         }
3783
3784         /* guard */
3785         switch (state->props.guard_interval) {
3786         default:
3787         case GUARD_INTERVAL_AUTO:
3788                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3789                 /* fall through - try first guess DRX_GUARD_1DIV4 */
3790         case GUARD_INTERVAL_1_4:
3791                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3792                 break;
3793         case GUARD_INTERVAL_1_32:
3794                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3795                 break;
3796         case GUARD_INTERVAL_1_16:
3797                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3798                 break;
3799         case GUARD_INTERVAL_1_8:
3800                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3801                 break;
3802         }
3803
3804         /* hierarchy */
3805         switch (state->props.hierarchy) {
3806         case HIERARCHY_AUTO:
3807         case HIERARCHY_NONE:
3808         default:
3809                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3810                 /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3811                 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3812                 /* fall through */
3813         case HIERARCHY_1:
3814                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3815                 break;
3816         case HIERARCHY_2:
3817                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3818                 break;
3819         case HIERARCHY_4:
3820                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3821                 break;
3822         }
3823
3824
3825         /* modulation */
3826         switch (state->props.modulation) {
3827         case QAM_AUTO:
3828         default:
3829                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3830                 /* fall through - try first guess DRX_CONSTELLATION_QAM64 */
3831         case QAM_64:
3832                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3833                 break;
3834         case QPSK:
3835                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3836                 break;
3837         case QAM_16:
3838                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3839                 break;
3840         }
3841 #if 0
3842         /* No hierarchical channels support in BDA */
3843         /* Priority (only for hierarchical channels) */
3844         switch (channel->priority) {
3845         case DRX_PRIORITY_LOW:
3846                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3847                 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3848                         OFDM_EC_SB_PRIOR_LO);
3849                 break;
3850         case DRX_PRIORITY_HIGH:
3851                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3852                 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3853                         OFDM_EC_SB_PRIOR_HI));
3854                 break;
3855         case DRX_PRIORITY_UNKNOWN:      /* fall through */
3856         default:
3857                 status = -EINVAL;
3858                 goto error;
3859         }
3860 #else
3861         /* Set Priority high */
3862         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3863         status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3864         if (status < 0)
3865                 goto error;
3866 #endif
3867
3868         /* coderate */
3869         switch (state->props.code_rate_HP) {
3870         case FEC_AUTO:
3871         default:
3872                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3873                 /* fall through - try first guess DRX_CODERATE_2DIV3 */
3874         case FEC_2_3:
3875                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3876                 break;
3877         case FEC_1_2:
3878                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3879                 break;
3880         case FEC_3_4:
3881                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3882                 break;
3883         case FEC_5_6:
3884                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3885                 break;
3886         case FEC_7_8:
3887                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3888                 break;
3889         }
3890
3891         /*
3892          * SAW filter selection: normally not necessary, but if wanted
3893          * the application can select a SAW filter via the driver by
3894          * using UIOs
3895          */
3896
3897         /* First determine real bandwidth (Hz) */
3898         /* Also set delay for impulse noise cruncher */
3899         /*
3900          * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3901          * changed by SC for fix for some 8K,1/8 guard but is restored by
3902          * InitEC and ResetEC functions
3903          */
3904         switch (state->props.bandwidth_hz) {
3905         case 0:
3906                 state->props.bandwidth_hz = 8000000;
3907                 /* fall through */
3908         case 8000000:
3909                 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3910                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3911                                  3052);
3912                 if (status < 0)
3913                         goto error;
3914                 /* cochannel protection for PAL 8 MHz */
3915                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3916                                  7);
3917                 if (status < 0)
3918                         goto error;
3919                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3920                                  7);
3921                 if (status < 0)
3922                         goto error;
3923                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3924                                  7);
3925                 if (status < 0)
3926                         goto error;
3927                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3928                                  1);
3929                 if (status < 0)
3930                         goto error;
3931                 break;
3932         case 7000000:
3933                 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3934                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3935                                  3491);
3936                 if (status < 0)
3937                         goto error;
3938                 /* cochannel protection for PAL 7 MHz */
3939                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3940                                  8);
3941                 if (status < 0)
3942                         goto error;
3943                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3944                                  8);
3945                 if (status < 0)
3946                         goto error;
3947                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3948                                  4);
3949                 if (status < 0)
3950                         goto error;
3951                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3952                                  1);
3953                 if (status < 0)
3954                         goto error;
3955                 break;
3956         case 6000000:
3957                 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3958                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3959                                  4073);
3960                 if (status < 0)
3961                         goto error;
3962                 /* cochannel protection for NTSC 6 MHz */
3963                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3964                                  19);
3965                 if (status < 0)
3966                         goto error;
3967                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3968                                  19);
3969                 if (status < 0)
3970                         goto error;
3971                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3972                                  14);
3973                 if (status < 0)
3974                         goto error;
3975                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3976                                  1);
3977                 if (status < 0)
3978                         goto error;
3979                 break;
3980         default:
3981                 status = -EINVAL;
3982                 goto error;
3983         }
3984
3985         if (iqm_rc_rate_ofs == 0) {
3986                 /* Now compute IQM_RC_RATE_OFS
3987                         (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3988                         =>
3989                         ((SysFreq / BandWidth) * (2^21)) - (2^23)
3990                         */
3991                 /* (SysFreq / BandWidth) * (2^28)  */
3992                 /*
3993                  * assert (MAX(sysClk)/MIN(bandwidth) < 16)
3994                  *      => assert(MAX(sysClk) < 16*MIN(bandwidth))
3995                  *      => assert(109714272 > 48000000) = true
3996                  * so Frac 28 can be used
3997                  */
3998                 iqm_rc_rate_ofs = Frac28a((u32)
3999                                         ((state->m_sys_clock_freq *
4000                                                 1000) / 3), bandwidth);
4001                 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4002                 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
4003                         iqm_rc_rate_ofs += 0x80L;
4004                 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
4005                 /* ((SysFreq / BandWidth) * (2^21)) - (2^23)  */
4006                 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
4007         }
4008
4009         iqm_rc_rate_ofs &=
4010                 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4011                 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4012         status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4013         if (status < 0)
4014                 goto error;
4015
4016         /* Bandwidth setting done */
4017
4018 #if 0
4019         status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4020         if (status < 0)
4021                 goto error;
4022 #endif
4023         status = set_frequency_shifter(state, intermediate_freqk_hz,
4024                                        tuner_freq_offset, true);
4025         if (status < 0)
4026                 goto error;
4027
4028         /*== start SC, write channel settings to SC ==========================*/
4029
4030         /* Activate SCU to enable SCU commands */
4031         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4032         if (status < 0)
4033                 goto error;
4034
4035         /* Enable SC after setting all other parameters */
4036         status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4037         if (status < 0)
4038                 goto error;
4039         status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4040         if (status < 0)
4041                 goto error;
4042
4043
4044         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4045                              | SCU_RAM_COMMAND_CMD_DEMOD_START,
4046                              0, NULL, 1, &cmd_result);
4047         if (status < 0)
4048                 goto error;
4049
4050         /* Write SC parameter registers, set all AUTO flags in operation mode */
4051         param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4052                         OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4053                         OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4054                         OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4055                         OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4056         status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4057                                 0, transmission_params, param1, 0, 0, 0);
4058         if (status < 0)
4059                 goto error;
4060
4061         if (!state->m_drxk_a3_rom_code)
4062                 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4063 error:
4064         if (status < 0)
4065                 pr_err("Error %d on %s\n", status, __func__);
4066
4067         return status;
4068 }
4069
4070
4071 /*============================================================================*/
4072
4073 /*
4074 * \brief Retrieve lock status .
4075 * \param demod    Pointer to demodulator instance.
4076 * \param lockStat Pointer to lock status structure.
4077 * \return DRXStatus_t.
4078 *
4079 */
4080 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4081 {
4082         int status;
4083         const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4084                                     OFDM_SC_RA_RAM_LOCK_FEC__M);
4085         const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4086         const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4087
4088         u16 sc_ra_ram_lock = 0;
4089         u16 sc_comm_exec = 0;
4090
4091         dprintk(1, "\n");
4092
4093         *p_lock_status = NOT_LOCKED;
4094         /* driver 0.9.0 */
4095         /* Check if SC is running */
4096         status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4097         if (status < 0)
4098                 goto end;
4099         if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4100                 goto end;
4101
4102         status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4103         if (status < 0)
4104                 goto end;
4105
4106         if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4107                 *p_lock_status = MPEG_LOCK;
4108         else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4109                 *p_lock_status = FEC_LOCK;
4110         else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4111                 *p_lock_status = DEMOD_LOCK;
4112         else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4113                 *p_lock_status = NEVER_LOCK;
4114 end:
4115         if (status < 0)
4116                 pr_err("Error %d on %s\n", status, __func__);
4117
4118         return status;
4119 }
4120
4121 static int power_up_qam(struct drxk_state *state)
4122 {
4123         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4124         int status;
4125
4126         dprintk(1, "\n");
4127         status = ctrl_power_mode(state, &power_mode);
4128         if (status < 0)
4129                 pr_err("Error %d on %s\n", status, __func__);
4130
4131         return status;
4132 }
4133
4134
4135 /* Power Down QAM */
4136 static int power_down_qam(struct drxk_state *state)
4137 {
4138         u16 data = 0;
4139         u16 cmd_result;
4140         int status = 0;
4141
4142         dprintk(1, "\n");
4143         status = read16(state, SCU_COMM_EXEC__A, &data);
4144         if (status < 0)
4145                 goto error;
4146         if (data == SCU_COMM_EXEC_ACTIVE) {
4147                 /*
4148                         STOP demodulator
4149                         QAM and HW blocks
4150                         */
4151                 /* stop all comstate->m_exec */
4152                 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4153                 if (status < 0)
4154                         goto error;
4155                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4156                                      | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4157                                      0, NULL, 1, &cmd_result);
4158                 if (status < 0)
4159                         goto error;
4160         }
4161         /* powerdown AFE                   */
4162         status = set_iqm_af(state, false);
4163
4164 error:
4165         if (status < 0)
4166                 pr_err("Error %d on %s\n", status, __func__);
4167
4168         return status;
4169 }
4170
4171 /*============================================================================*/
4172
4173 /*
4174 * \brief Setup of the QAM Measurement intervals for signal quality
4175 * \param demod instance of demod.
4176 * \param modulation current modulation.
4177 * \return DRXStatus_t.
4178 *
4179 *  NOTE:
4180 *  Take into account that for certain settings the errorcounters can overflow.
4181 *  The implementation does not check this.
4182 *
4183 */
4184 static int set_qam_measurement(struct drxk_state *state,
4185                              enum e_drxk_constellation modulation,
4186                              u32 symbol_rate)
4187 {
4188         u32 fec_bits_desired = 0;       /* BER accounting period */
4189         u32 fec_rs_period_total = 0;    /* Total period */
4190         u16 fec_rs_prescale = 0;        /* ReedSolomon Measurement Prescale */
4191         u16 fec_rs_period = 0;  /* Value for corresponding I2C register */
4192         int status = 0;
4193
4194         dprintk(1, "\n");
4195
4196         fec_rs_prescale = 1;
4197         /* fec_bits_desired = symbol_rate [kHz] *
4198                 FrameLenght [ms] *
4199                 (modulation + 1) *
4200                 SyncLoss (== 1) *
4201                 ViterbiLoss (==1)
4202                 */
4203         switch (modulation) {
4204         case DRX_CONSTELLATION_QAM16:
4205                 fec_bits_desired = 4 * symbol_rate;
4206                 break;
4207         case DRX_CONSTELLATION_QAM32:
4208                 fec_bits_desired = 5 * symbol_rate;
4209                 break;
4210         case DRX_CONSTELLATION_QAM64:
4211                 fec_bits_desired = 6 * symbol_rate;
4212                 break;
4213         case DRX_CONSTELLATION_QAM128:
4214                 fec_bits_desired = 7 * symbol_rate;
4215                 break;
4216         case DRX_CONSTELLATION_QAM256:
4217                 fec_bits_desired = 8 * symbol_rate;
4218                 break;
4219         default:
4220                 status = -EINVAL;
4221         }
4222         if (status < 0)
4223                 goto error;
4224
4225         fec_bits_desired /= 1000;       /* symbol_rate [Hz] -> symbol_rate [kHz] */
4226         fec_bits_desired *= 500;        /* meas. period [ms] */
4227
4228         /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4229         /* fec_rs_period_total = fec_bits_desired / 1632 */
4230         fec_rs_period_total = (fec_bits_desired / 1632UL) + 1;  /* roughly ceil */
4231
4232         /* fec_rs_period_total =  fec_rs_prescale * fec_rs_period  */
4233         fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4234         if (fec_rs_prescale == 0) {
4235                 /* Divide by zero (though impossible) */
4236                 status = -EINVAL;
4237                 if (status < 0)
4238                         goto error;
4239         }
4240         fec_rs_period =
4241                 ((u16) fec_rs_period_total +
4242                 (fec_rs_prescale >> 1)) / fec_rs_prescale;
4243
4244         /* write corresponding registers */
4245         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4246         if (status < 0)
4247                 goto error;
4248         status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4249                          fec_rs_prescale);
4250         if (status < 0)
4251                 goto error;
4252         status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4253 error:
4254         if (status < 0)
4255                 pr_err("Error %d on %s\n", status, __func__);
4256         return status;
4257 }
4258
4259 static int set_qam16(struct drxk_state *state)
4260 {
4261         int status = 0;
4262
4263         dprintk(1, "\n");
4264         /* QAM Equalizer Setup */
4265         /* Equalizer */
4266         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4267         if (status < 0)
4268                 goto error;
4269         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4270         if (status < 0)
4271                 goto error;
4272         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4273         if (status < 0)
4274                 goto error;
4275         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4276         if (status < 0)
4277                 goto error;
4278         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4279         if (status < 0)
4280                 goto error;
4281         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4282         if (status < 0)
4283                 goto error;
4284         /* Decision Feedback Equalizer */
4285         status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4286         if (status < 0)
4287                 goto error;
4288         status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4289         if (status < 0)
4290                 goto error;
4291         status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4292         if (status < 0)
4293                 goto error;
4294         status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4295         if (status < 0)
4296                 goto error;
4297         status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4298         if (status < 0)
4299                 goto error;
4300         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4301         if (status < 0)
4302                 goto error;
4303
4304         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4305         if (status < 0)
4306                 goto error;
4307         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4308         if (status < 0)
4309                 goto error;
4310         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4311         if (status < 0)
4312                 goto error;
4313
4314         /* QAM Slicer Settings */
4315         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4316                          DRXK_QAM_SL_SIG_POWER_QAM16);
4317         if (status < 0)
4318                 goto error;
4319
4320         /* QAM Loop Controller Coeficients */
4321         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4322         if (status < 0)
4323                 goto error;
4324         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4325         if (status < 0)
4326                 goto error;
4327         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4328         if (status < 0)
4329                 goto error;
4330         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4331         if (status < 0)
4332                 goto error;
4333         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4334         if (status < 0)
4335                 goto error;
4336         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4337         if (status < 0)
4338                 goto error;
4339         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4340         if (status < 0)
4341                 goto error;
4342         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4343         if (status < 0)
4344                 goto error;
4345
4346         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4347         if (status < 0)
4348                 goto error;
4349         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4350         if (status < 0)
4351                 goto error;
4352         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4353         if (status < 0)
4354                 goto error;
4355         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4356         if (status < 0)
4357                 goto error;
4358         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4359         if (status < 0)
4360                 goto error;
4361         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4362         if (status < 0)
4363                 goto error;
4364         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4365         if (status < 0)
4366                 goto error;
4367         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4368         if (status < 0)
4369                 goto error;
4370         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4371         if (status < 0)
4372                 goto error;
4373         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4374         if (status < 0)
4375                 goto error;
4376         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4377         if (status < 0)
4378                 goto error;
4379         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4380         if (status < 0)
4381                 goto error;
4382
4383
4384         /* QAM State Machine (FSM) Thresholds */
4385
4386         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4387         if (status < 0)
4388                 goto error;
4389         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4390         if (status < 0)
4391                 goto error;
4392         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4393         if (status < 0)
4394                 goto error;
4395         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4396         if (status < 0)
4397                 goto error;
4398         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4399         if (status < 0)
4400                 goto error;
4401         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4402         if (status < 0)
4403                 goto error;
4404
4405         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4406         if (status < 0)
4407                 goto error;
4408         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4409         if (status < 0)
4410                 goto error;
4411         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4412         if (status < 0)
4413                 goto error;
4414
4415
4416         /* QAM FSM Tracking Parameters */
4417
4418         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4419         if (status < 0)
4420                 goto error;
4421         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4422         if (status < 0)
4423                 goto error;
4424         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4425         if (status < 0)
4426                 goto error;
4427         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4428         if (status < 0)
4429                 goto error;
4430         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4431         if (status < 0)
4432                 goto error;
4433         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4434         if (status < 0)
4435                 goto error;
4436         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4437         if (status < 0)
4438                 goto error;
4439
4440 error:
4441         if (status < 0)
4442                 pr_err("Error %d on %s\n", status, __func__);
4443         return status;
4444 }
4445
4446 /*============================================================================*/
4447
4448 /*
4449 * \brief QAM32 specific setup
4450 * \param demod instance of demod.
4451 * \return DRXStatus_t.
4452 */
4453 static int set_qam32(struct drxk_state *state)
4454 {
4455         int status = 0;
4456
4457         dprintk(1, "\n");
4458
4459         /* QAM Equalizer Setup */
4460         /* Equalizer */
4461         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4462         if (status < 0)
4463                 goto error;
4464         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4465         if (status < 0)
4466                 goto error;
4467         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4468         if (status < 0)
4469                 goto error;
4470         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4471         if (status < 0)
4472                 goto error;
4473         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4474         if (status < 0)
4475                 goto error;
4476         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4477         if (status < 0)
4478                 goto error;
4479
4480         /* Decision Feedback Equalizer */
4481         status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4482         if (status < 0)
4483                 goto error;
4484         status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4485         if (status < 0)
4486                 goto error;
4487         status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4488         if (status < 0)
4489                 goto error;
4490         status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4491         if (status < 0)
4492                 goto error;
4493         status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4494         if (status < 0)
4495                 goto error;
4496         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4497         if (status < 0)
4498                 goto error;
4499
4500         status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4501         if (status < 0)
4502                 goto error;
4503         status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4504         if (status < 0)
4505                 goto error;
4506         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4507         if (status < 0)
4508                 goto error;
4509
4510         /* QAM Slicer Settings */
4511
4512         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4513                          DRXK_QAM_SL_SIG_POWER_QAM32);
4514         if (status < 0)
4515                 goto error;
4516
4517
4518         /* QAM Loop Controller Coeficients */
4519
4520         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4521         if (status < 0)
4522                 goto error;
4523         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4524         if (status < 0)
4525                 goto error;
4526         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4527         if (status < 0)
4528                 goto error;
4529         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4530         if (status < 0)
4531                 goto error;
4532         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4533         if (status < 0)
4534                 goto error;
4535         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4536         if (status < 0)
4537                 goto error;
4538         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4539         if (status < 0)
4540                 goto error;
4541         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4542         if (status < 0)
4543                 goto error;
4544
4545         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4546         if (status < 0)
4547                 goto error;
4548         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4549         if (status < 0)
4550                 goto error;
4551         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4552         if (status < 0)
4553                 goto error;
4554         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4555         if (status < 0)
4556                 goto error;
4557         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4558         if (status < 0)
4559                 goto error;
4560         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4561         if (status < 0)
4562                 goto error;
4563         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4564         if (status < 0)
4565                 goto error;
4566         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4567         if (status < 0)
4568                 goto error;
4569         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4570         if (status < 0)
4571                 goto error;
4572         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4573         if (status < 0)
4574                 goto error;
4575         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4576         if (status < 0)
4577                 goto error;
4578         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4579         if (status < 0)
4580                 goto error;
4581
4582
4583         /* QAM State Machine (FSM) Thresholds */
4584
4585         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4586         if (status < 0)
4587                 goto error;
4588         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4589         if (status < 0)
4590                 goto error;
4591         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4592         if (status < 0)
4593                 goto error;
4594         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4595         if (status < 0)
4596                 goto error;
4597         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4598         if (status < 0)
4599                 goto error;
4600         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4601         if (status < 0)
4602                 goto error;
4603
4604         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4605         if (status < 0)
4606                 goto error;
4607         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4608         if (status < 0)
4609                 goto error;
4610         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4611         if (status < 0)
4612                 goto error;
4613
4614
4615         /* QAM FSM Tracking Parameters */
4616
4617         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4618         if (status < 0)
4619                 goto error;
4620         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4621         if (status < 0)
4622                 goto error;
4623         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4624         if (status < 0)
4625                 goto error;
4626         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4627         if (status < 0)
4628                 goto error;
4629         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4630         if (status < 0)
4631                 goto error;
4632         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4633         if (status < 0)
4634                 goto error;
4635         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4636 error:
4637         if (status < 0)
4638                 pr_err("Error %d on %s\n", status, __func__);
4639         return status;
4640 }
4641
4642 /*============================================================================*/
4643
4644 /*
4645 * \brief QAM64 specific setup
4646 * \param demod instance of demod.
4647 * \return DRXStatus_t.
4648 */
4649 static int set_qam64(struct drxk_state *state)
4650 {
4651         int status = 0;
4652
4653         dprintk(1, "\n");
4654         /* QAM Equalizer Setup */
4655         /* Equalizer */
4656         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4657         if (status < 0)
4658                 goto error;
4659         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4660         if (status < 0)
4661                 goto error;
4662         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4663         if (status < 0)
4664                 goto error;
4665         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4666         if (status < 0)
4667                 goto error;
4668         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4669         if (status < 0)
4670                 goto error;
4671         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4672         if (status < 0)
4673                 goto error;
4674
4675         /* Decision Feedback Equalizer */
4676         status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4677         if (status < 0)
4678                 goto error;
4679         status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4680         if (status < 0)
4681                 goto error;
4682         status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4683         if (status < 0)
4684                 goto error;
4685         status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4686         if (status < 0)
4687                 goto error;
4688         status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4689         if (status < 0)
4690                 goto error;
4691         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4692         if (status < 0)
4693                 goto error;
4694
4695         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4696         if (status < 0)
4697                 goto error;
4698         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4699         if (status < 0)
4700                 goto error;
4701         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4702         if (status < 0)
4703                 goto error;
4704
4705         /* QAM Slicer Settings */
4706         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4707                          DRXK_QAM_SL_SIG_POWER_QAM64);
4708         if (status < 0)
4709                 goto error;
4710
4711
4712         /* QAM Loop Controller Coeficients */
4713
4714         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4715         if (status < 0)
4716                 goto error;
4717         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4718         if (status < 0)
4719                 goto error;
4720         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4721         if (status < 0)
4722                 goto error;
4723         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4724         if (status < 0)
4725                 goto error;
4726         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4727         if (status < 0)
4728                 goto error;
4729         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4730         if (status < 0)
4731                 goto error;
4732         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4733         if (status < 0)
4734                 goto error;
4735         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4736         if (status < 0)
4737                 goto error;
4738
4739         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4740         if (status < 0)
4741                 goto error;
4742         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4743         if (status < 0)
4744                 goto error;
4745         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4746         if (status < 0)
4747                 goto error;
4748         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4749         if (status < 0)
4750                 goto error;
4751         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4752         if (status < 0)
4753                 goto error;
4754         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4755         if (status < 0)
4756                 goto error;
4757         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4758         if (status < 0)
4759                 goto error;
4760         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4761         if (status < 0)
4762                 goto error;
4763         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4764         if (status < 0)
4765                 goto error;
4766         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4767         if (status < 0)
4768                 goto error;
4769         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4770         if (status < 0)
4771                 goto error;
4772         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4773         if (status < 0)
4774                 goto error;
4775
4776
4777         /* QAM State Machine (FSM) Thresholds */
4778
4779         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4780         if (status < 0)
4781                 goto error;
4782         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4783         if (status < 0)
4784                 goto error;
4785         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4786         if (status < 0)
4787                 goto error;
4788         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4789         if (status < 0)
4790                 goto error;
4791         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4792         if (status < 0)
4793                 goto error;
4794         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4795         if (status < 0)
4796                 goto error;
4797
4798         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4799         if (status < 0)
4800                 goto error;
4801         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4802         if (status < 0)
4803                 goto error;
4804         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4805         if (status < 0)
4806                 goto error;
4807
4808
4809         /* QAM FSM Tracking Parameters */
4810
4811         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4812         if (status < 0)
4813                 goto error;
4814         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4815         if (status < 0)
4816                 goto error;
4817         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4818         if (status < 0)
4819                 goto error;
4820         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4821         if (status < 0)
4822                 goto error;
4823         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4824         if (status < 0)
4825                 goto error;
4826         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4827         if (status < 0)
4828                 goto error;
4829         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4830 error:
4831         if (status < 0)
4832                 pr_err("Error %d on %s\n", status, __func__);
4833
4834         return status;
4835 }
4836
4837 /*============================================================================*/
4838
4839 /*
4840 * \brief QAM128 specific setup
4841 * \param demod: instance of demod.
4842 * \return DRXStatus_t.
4843 */
4844 static int set_qam128(struct drxk_state *state)
4845 {
4846         int status = 0;
4847
4848         dprintk(1, "\n");
4849         /* QAM Equalizer Setup */
4850         /* Equalizer */
4851         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4852         if (status < 0)
4853                 goto error;
4854         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4855         if (status < 0)
4856                 goto error;
4857         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4858         if (status < 0)
4859                 goto error;
4860         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4861         if (status < 0)
4862                 goto error;
4863         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4864         if (status < 0)
4865                 goto error;
4866         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4867         if (status < 0)
4868                 goto error;
4869
4870         /* Decision Feedback Equalizer */
4871         status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4872         if (status < 0)
4873                 goto error;
4874         status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4875         if (status < 0)
4876                 goto error;
4877         status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4878         if (status < 0)
4879                 goto error;
4880         status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4881         if (status < 0)
4882                 goto error;
4883         status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4884         if (status < 0)
4885                 goto error;
4886         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4887         if (status < 0)
4888                 goto error;
4889
4890         status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4891         if (status < 0)
4892                 goto error;
4893         status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4894         if (status < 0)
4895                 goto error;
4896         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4897         if (status < 0)
4898                 goto error;
4899
4900
4901         /* QAM Slicer Settings */
4902
4903         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4904                          DRXK_QAM_SL_SIG_POWER_QAM128);
4905         if (status < 0)
4906                 goto error;
4907
4908
4909         /* QAM Loop Controller Coeficients */
4910
4911         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4912         if (status < 0)
4913                 goto error;
4914         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4915         if (status < 0)
4916                 goto error;
4917         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4918         if (status < 0)
4919                 goto error;
4920         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4921         if (status < 0)
4922                 goto error;
4923         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4924         if (status < 0)
4925                 goto error;
4926         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4927         if (status < 0)
4928                 goto error;
4929         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4930         if (status < 0)
4931                 goto error;
4932         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4933         if (status < 0)
4934                 goto error;
4935
4936         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4937         if (status < 0)
4938                 goto error;
4939         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4940         if (status < 0)
4941                 goto error;
4942         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4943         if (status < 0)
4944                 goto error;
4945         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4946         if (status < 0)
4947                 goto error;
4948         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4949         if (status < 0)
4950                 goto error;
4951         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4952         if (status < 0)
4953                 goto error;
4954         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4955         if (status < 0)
4956                 goto error;
4957         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4958         if (status < 0)
4959                 goto error;
4960         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4961         if (status < 0)
4962                 goto error;
4963         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4964         if (status < 0)
4965                 goto error;
4966         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4967         if (status < 0)
4968                 goto error;
4969         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4970         if (status < 0)
4971                 goto error;
4972
4973
4974         /* QAM State Machine (FSM) Thresholds */
4975
4976         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4977         if (status < 0)
4978                 goto error;
4979         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4980         if (status < 0)
4981                 goto error;
4982         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4983         if (status < 0)
4984                 goto error;
4985         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4986         if (status < 0)
4987                 goto error;
4988         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4989         if (status < 0)
4990                 goto error;
4991         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4992         if (status < 0)
4993                 goto error;
4994
4995         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4996         if (status < 0)
4997                 goto error;
4998         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4999         if (status < 0)
5000                 goto error;
5001
5002         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5003         if (status < 0)
5004                 goto error;
5005
5006         /* QAM FSM Tracking Parameters */
5007
5008         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5009         if (status < 0)
5010                 goto error;
5011         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5012         if (status < 0)
5013                 goto error;
5014         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5015         if (status < 0)
5016                 goto error;
5017         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5018         if (status < 0)
5019                 goto error;
5020         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5021         if (status < 0)
5022                 goto error;
5023         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5024         if (status < 0)
5025                 goto error;
5026         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5027 error:
5028         if (status < 0)
5029                 pr_err("Error %d on %s\n", status, __func__);
5030
5031         return status;
5032 }
5033
5034 /*============================================================================*/
5035
5036 /*
5037 * \brief QAM256 specific setup
5038 * \param demod: instance of demod.
5039 * \return DRXStatus_t.
5040 */
5041 static int set_qam256(struct drxk_state *state)
5042 {
5043         int status = 0;
5044
5045         dprintk(1, "\n");
5046         /* QAM Equalizer Setup */
5047         /* Equalizer */
5048         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5049         if (status < 0)
5050                 goto error;
5051         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5052         if (status < 0)
5053                 goto error;
5054         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5055         if (status < 0)
5056                 goto error;
5057         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5058         if (status < 0)
5059                 goto error;
5060         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5061         if (status < 0)
5062                 goto error;
5063         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5064         if (status < 0)
5065                 goto error;
5066
5067         /* Decision Feedback Equalizer */
5068         status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5069         if (status < 0)
5070                 goto error;
5071         status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5072         if (status < 0)
5073                 goto error;
5074         status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5075         if (status < 0)
5076                 goto error;
5077         status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5078         if (status < 0)
5079                 goto error;
5080         status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5081         if (status < 0)
5082                 goto error;
5083         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5084         if (status < 0)
5085                 goto error;
5086
5087         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5088         if (status < 0)
5089                 goto error;
5090         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5091         if (status < 0)
5092                 goto error;
5093         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5094         if (status < 0)
5095                 goto error;
5096
5097         /* QAM Slicer Settings */
5098
5099         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5100                          DRXK_QAM_SL_SIG_POWER_QAM256);
5101         if (status < 0)
5102                 goto error;
5103
5104
5105         /* QAM Loop Controller Coeficients */
5106
5107         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5108         if (status < 0)
5109                 goto error;
5110         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5111         if (status < 0)
5112                 goto error;
5113         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5114         if (status < 0)
5115                 goto error;
5116         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5117         if (status < 0)
5118                 goto error;
5119         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5120         if (status < 0)
5121                 goto error;
5122         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5123         if (status < 0)
5124                 goto error;
5125         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5126         if (status < 0)
5127                 goto error;
5128         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5129         if (status < 0)
5130                 goto error;
5131
5132         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5133         if (status < 0)
5134                 goto error;
5135         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5136         if (status < 0)
5137                 goto error;
5138         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5139         if (status < 0)
5140                 goto error;
5141         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5142         if (status < 0)
5143                 goto error;
5144         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5145         if (status < 0)
5146                 goto error;
5147         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5148         if (status < 0)
5149                 goto error;
5150         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5151         if (status < 0)
5152                 goto error;
5153         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5154         if (status < 0)
5155                 goto error;
5156         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5157         if (status < 0)
5158                 goto error;
5159         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5160         if (status < 0)
5161                 goto error;
5162         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5163         if (status < 0)
5164                 goto error;
5165         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5166         if (status < 0)
5167                 goto error;
5168
5169
5170         /* QAM State Machine (FSM) Thresholds */
5171
5172         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5173         if (status < 0)
5174                 goto error;
5175         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5176         if (status < 0)
5177                 goto error;
5178         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5179         if (status < 0)
5180                 goto error;
5181         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5182         if (status < 0)
5183                 goto error;
5184         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5185         if (status < 0)
5186                 goto error;
5187         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5188         if (status < 0)
5189                 goto error;
5190
5191         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5192         if (status < 0)
5193                 goto error;
5194         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5195         if (status < 0)
5196                 goto error;
5197         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5198         if (status < 0)
5199                 goto error;
5200
5201
5202         /* QAM FSM Tracking Parameters */
5203
5204         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5205         if (status < 0)
5206                 goto error;
5207         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5208         if (status < 0)
5209                 goto error;
5210         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5211         if (status < 0)
5212                 goto error;
5213         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5214         if (status < 0)
5215                 goto error;
5216         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5217         if (status < 0)
5218                 goto error;
5219         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5220         if (status < 0)
5221                 goto error;
5222         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5223 error:
5224         if (status < 0)
5225                 pr_err("Error %d on %s\n", status, __func__);
5226         return status;
5227 }
5228
5229
5230 /*============================================================================*/
5231 /*
5232 * \brief Reset QAM block.
5233 * \param demod:   instance of demod.
5234 * \param channel: pointer to channel data.
5235 * \return DRXStatus_t.
5236 */
5237 static int qam_reset_qam(struct drxk_state *state)
5238 {
5239         int status;
5240         u16 cmd_result;
5241
5242         dprintk(1, "\n");
5243         /* Stop QAM comstate->m_exec */
5244         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5245         if (status < 0)
5246                 goto error;
5247
5248         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5249                              | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5250                              0, NULL, 1, &cmd_result);
5251 error:
5252         if (status < 0)
5253                 pr_err("Error %d on %s\n", status, __func__);
5254         return status;
5255 }
5256
5257 /*============================================================================*/
5258
5259 /*
5260 * \brief Set QAM symbolrate.
5261 * \param demod:   instance of demod.
5262 * \param channel: pointer to channel data.
5263 * \return DRXStatus_t.
5264 */
5265 static int qam_set_symbolrate(struct drxk_state *state)
5266 {
5267         u32 adc_frequency = 0;
5268         u32 symb_freq = 0;
5269         u32 iqm_rc_rate = 0;
5270         u16 ratesel = 0;
5271         u32 lc_symb_rate = 0;
5272         int status;
5273
5274         dprintk(1, "\n");
5275         /* Select & calculate correct IQM rate */
5276         adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5277         ratesel = 0;
5278         if (state->props.symbol_rate <= 1188750)
5279                 ratesel = 3;
5280         else if (state->props.symbol_rate <= 2377500)
5281                 ratesel = 2;
5282         else if (state->props.symbol_rate <= 4755000)
5283                 ratesel = 1;
5284         status = write16(state, IQM_FD_RATESEL__A, ratesel);
5285         if (status < 0)
5286                 goto error;
5287
5288         /*
5289                 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5290                 */
5291         symb_freq = state->props.symbol_rate * (1 << ratesel);
5292         if (symb_freq == 0) {
5293                 /* Divide by zero */
5294                 status = -EINVAL;
5295                 goto error;
5296         }
5297         iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5298                 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5299                 (1 << 23);
5300         status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5301         if (status < 0)
5302                 goto error;
5303         state->m_iqm_rc_rate = iqm_rc_rate;
5304         /*
5305                 LcSymbFreq = round (.125 *  symbolrate / adc_freq * (1<<15))
5306                 */
5307         symb_freq = state->props.symbol_rate;
5308         if (adc_frequency == 0) {
5309                 /* Divide by zero */
5310                 status = -EINVAL;
5311                 goto error;
5312         }
5313         lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5314                 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5315                 16);
5316         if (lc_symb_rate > 511)
5317                 lc_symb_rate = 511;
5318         status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5319
5320 error:
5321         if (status < 0)
5322                 pr_err("Error %d on %s\n", status, __func__);
5323         return status;
5324 }
5325
5326 /*============================================================================*/
5327
5328 /*
5329 * \brief Get QAM lock status.
5330 * \param demod:   instance of demod.
5331 * \param channel: pointer to channel data.
5332 * \return DRXStatus_t.
5333 */
5334
5335 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5336 {
5337         int status;
5338         u16 result[2] = { 0, 0 };
5339
5340         dprintk(1, "\n");
5341         *p_lock_status = NOT_LOCKED;
5342         status = scu_command(state,
5343                         SCU_RAM_COMMAND_STANDARD_QAM |
5344                         SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5345                         result);
5346         if (status < 0)
5347                 pr_err("Error %d on %s\n", status, __func__);
5348
5349         if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5350                 /* 0x0000 NOT LOCKED */
5351         } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5352                 /* 0x4000 DEMOD LOCKED */
5353                 *p_lock_status = DEMOD_LOCK;
5354         } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5355                 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5356                 *p_lock_status = MPEG_LOCK;
5357         } else {
5358                 /* 0xC000 NEVER LOCKED */
5359                 /* (system will never be able to lock to the signal) */
5360                 /*
5361                  * TODO: check this, intermediate & standard specific lock
5362                  * states are not taken into account here
5363                  */
5364                 *p_lock_status = NEVER_LOCK;
5365         }
5366         return status;
5367 }
5368
5369 #define QAM_MIRROR__M         0x03
5370 #define QAM_MIRROR_NORMAL     0x00
5371 #define QAM_MIRRORED          0x01
5372 #define QAM_MIRROR_AUTO_ON    0x02
5373 #define QAM_LOCKRANGE__M      0x10
5374 #define QAM_LOCKRANGE_NORMAL  0x10
5375
5376 static int qam_demodulator_command(struct drxk_state *state,
5377                                  int number_of_parameters)
5378 {
5379         int status;
5380         u16 cmd_result;
5381         u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5382
5383         set_param_parameters[0] = state->m_constellation;       /* modulation     */
5384         set_param_parameters[1] = DRXK_QAM_I12_J17;     /* interleave mode   */
5385
5386         if (number_of_parameters == 2) {
5387                 u16 set_env_parameters[1] = { 0 };
5388
5389                 if (state->m_operation_mode == OM_QAM_ITU_C)
5390                         set_env_parameters[0] = QAM_TOP_ANNEX_C;
5391                 else
5392                         set_env_parameters[0] = QAM_TOP_ANNEX_A;
5393
5394                 status = scu_command(state,
5395                                      SCU_RAM_COMMAND_STANDARD_QAM
5396                                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5397                                      1, set_env_parameters, 1, &cmd_result);
5398                 if (status < 0)
5399                         goto error;
5400
5401                 status = scu_command(state,
5402                                      SCU_RAM_COMMAND_STANDARD_QAM
5403                                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5404                                      number_of_parameters, set_param_parameters,
5405                                      1, &cmd_result);
5406         } else if (number_of_parameters == 4) {
5407                 if (state->m_operation_mode == OM_QAM_ITU_C)
5408                         set_param_parameters[2] = QAM_TOP_ANNEX_C;
5409                 else
5410                         set_param_parameters[2] = QAM_TOP_ANNEX_A;
5411
5412                 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5413                 /* Env parameters */
5414                 /* check for LOCKRANGE Extended */
5415                 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5416
5417                 status = scu_command(state,
5418                                      SCU_RAM_COMMAND_STANDARD_QAM
5419                                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5420                                      number_of_parameters, set_param_parameters,
5421                                      1, &cmd_result);
5422         } else {
5423                 pr_warn("Unknown QAM demodulator parameter count %d\n",
5424                         number_of_parameters);
5425                 status = -EINVAL;
5426         }
5427
5428 error:
5429         if (status < 0)
5430                 pr_warn("Warning %d on %s\n", status, __func__);
5431         return status;
5432 }
5433
5434 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5435                   s32 tuner_freq_offset)
5436 {
5437         int status;
5438         u16 cmd_result;
5439         int qam_demod_param_count = state->qam_demod_parameter_count;
5440
5441         dprintk(1, "\n");
5442         /*
5443          * STEP 1: reset demodulator
5444          *      resets FEC DI and FEC RS
5445          *      resets QAM block
5446          *      resets SCU variables
5447          */
5448         status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5449         if (status < 0)
5450                 goto error;
5451         status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5452         if (status < 0)
5453                 goto error;
5454         status = qam_reset_qam(state);
5455         if (status < 0)
5456                 goto error;
5457
5458         /*
5459          * STEP 2: configure demodulator
5460          *      -set params; resets IQM,QAM,FEC HW; initializes some
5461          *       SCU variables
5462          */
5463         status = qam_set_symbolrate(state);
5464         if (status < 0)
5465                 goto error;
5466
5467         /* Set params */
5468         switch (state->props.modulation) {
5469         case QAM_256:
5470                 state->m_constellation = DRX_CONSTELLATION_QAM256;
5471                 break;
5472         case QAM_AUTO:
5473         case QAM_64:
5474                 state->m_constellation = DRX_CONSTELLATION_QAM64;
5475                 break;
5476         case QAM_16:
5477                 state->m_constellation = DRX_CONSTELLATION_QAM16;
5478                 break;
5479         case QAM_32:
5480                 state->m_constellation = DRX_CONSTELLATION_QAM32;
5481                 break;
5482         case QAM_128:
5483                 state->m_constellation = DRX_CONSTELLATION_QAM128;
5484                 break;
5485         default:
5486                 status = -EINVAL;
5487                 break;
5488         }
5489         if (status < 0)
5490                 goto error;
5491
5492         /* Use the 4-parameter if it's requested or we're probing for
5493          * the correct command. */
5494         if (state->qam_demod_parameter_count == 4
5495                 || !state->qam_demod_parameter_count) {
5496                 qam_demod_param_count = 4;
5497                 status = qam_demodulator_command(state, qam_demod_param_count);
5498         }
5499
5500         /* Use the 2-parameter command if it was requested or if we're
5501          * probing for the correct command and the 4-parameter command
5502          * failed. */
5503         if (state->qam_demod_parameter_count == 2
5504                 || (!state->qam_demod_parameter_count && status < 0)) {
5505                 qam_demod_param_count = 2;
5506                 status = qam_demodulator_command(state, qam_demod_param_count);
5507         }
5508
5509         if (status < 0) {
5510                 dprintk(1, "Could not set demodulator parameters.\n");
5511                 dprintk(1,
5512                         "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5513                         state->qam_demod_parameter_count,
5514                         state->microcode_name);
5515                 goto error;
5516         } else if (!state->qam_demod_parameter_count) {
5517                 dprintk(1,
5518                         "Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5519                         qam_demod_param_count);
5520
5521                 /*
5522                  * One of our commands was successful. We don't need to
5523                  * auto-probe anymore, now that we got the correct command.
5524                  */
5525                 state->qam_demod_parameter_count = qam_demod_param_count;
5526         }
5527
5528         /*
5529          * STEP 3: enable the system in a mode where the ADC provides valid
5530          * signal setup modulation independent registers
5531          */
5532 #if 0
5533         status = set_frequency(channel, tuner_freq_offset));
5534         if (status < 0)
5535                 goto error;
5536 #endif
5537         status = set_frequency_shifter(state, intermediate_freqk_hz,
5538                                        tuner_freq_offset, true);
5539         if (status < 0)
5540                 goto error;
5541
5542         /* Setup BER measurement */
5543         status = set_qam_measurement(state, state->m_constellation,
5544                                      state->props.symbol_rate);
5545         if (status < 0)
5546                 goto error;
5547
5548         /* Reset default values */
5549         status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5550         if (status < 0)
5551                 goto error;
5552         status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5553         if (status < 0)
5554                 goto error;
5555
5556         /* Reset default LC values */
5557         status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5558         if (status < 0)
5559                 goto error;
5560         status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5561         if (status < 0)
5562                 goto error;
5563         status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5564         if (status < 0)
5565                 goto error;
5566         status = write16(state, QAM_LC_MODE__A, 7);
5567         if (status < 0)
5568                 goto error;
5569
5570         status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5571         if (status < 0)
5572                 goto error;
5573         status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5574         if (status < 0)
5575                 goto error;
5576         status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5577         if (status < 0)
5578                 goto error;
5579         status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5580         if (status < 0)
5581                 goto error;
5582         status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5583         if (status < 0)
5584                 goto error;
5585         status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5586         if (status < 0)
5587                 goto error;
5588         status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5589         if (status < 0)
5590                 goto error;
5591         status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5592         if (status < 0)
5593                 goto error;
5594         status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5595         if (status < 0)
5596                 goto error;
5597         status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5598         if (status < 0)
5599                 goto error;
5600         status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5601         if (status < 0)
5602                 goto error;
5603         status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5604         if (status < 0)
5605                 goto error;
5606         status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5607         if (status < 0)
5608                 goto error;
5609         status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5610         if (status < 0)
5611                 goto error;
5612         status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5613         if (status < 0)
5614                 goto error;
5615
5616         /* Mirroring, QAM-block starting point not inverted */
5617         status = write16(state, QAM_SY_SP_INV__A,
5618                          QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5619         if (status < 0)
5620                 goto error;
5621
5622         /* Halt SCU to enable safe non-atomic accesses */
5623         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5624         if (status < 0)
5625                 goto error;
5626
5627         /* STEP 4: modulation specific setup */
5628         switch (state->props.modulation) {
5629         case QAM_16:
5630                 status = set_qam16(state);
5631                 break;
5632         case QAM_32:
5633                 status = set_qam32(state);
5634                 break;
5635         case QAM_AUTO:
5636         case QAM_64:
5637                 status = set_qam64(state);
5638                 break;
5639         case QAM_128:
5640                 status = set_qam128(state);
5641                 break;
5642         case QAM_256:
5643                 status = set_qam256(state);
5644                 break;
5645         default:
5646                 status = -EINVAL;
5647                 break;
5648         }
5649         if (status < 0)
5650                 goto error;
5651
5652         /* Activate SCU to enable SCU commands */
5653         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5654         if (status < 0)
5655                 goto error;
5656
5657         /* Re-configure MPEG output, requires knowledge of channel bitrate */
5658         /* extAttr->currentChannel.modulation = channel->modulation; */
5659         /* extAttr->currentChannel.symbolrate    = channel->symbolrate; */
5660         status = mpegts_dto_setup(state, state->m_operation_mode);
5661         if (status < 0)
5662                 goto error;
5663
5664         /* start processes */
5665         status = mpegts_start(state);
5666         if (status < 0)
5667                 goto error;
5668         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5669         if (status < 0)
5670                 goto error;
5671         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5672         if (status < 0)
5673                 goto error;
5674         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5675         if (status < 0)
5676                 goto error;
5677
5678         /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5679         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5680                              | SCU_RAM_COMMAND_CMD_DEMOD_START,
5681                              0, NULL, 1, &cmd_result);
5682         if (status < 0)
5683                 goto error;
5684
5685         /* update global DRXK data container */
5686 /*?     extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5687
5688 error:
5689         if (status < 0)
5690                 pr_err("Error %d on %s\n", status, __func__);
5691         return status;
5692 }
5693
5694 static int set_qam_standard(struct drxk_state *state,
5695                           enum operation_mode o_mode)
5696 {
5697         int status;
5698 #ifdef DRXK_QAM_TAPS
5699 #define DRXK_QAMA_TAPS_SELECT
5700 #include "drxk_filters.h"
5701 #undef DRXK_QAMA_TAPS_SELECT
5702 #endif
5703
5704         dprintk(1, "\n");
5705
5706         /* added antenna switch */
5707         switch_antenna_to_qam(state);
5708
5709         /* Ensure correct power-up mode */
5710         status = power_up_qam(state);
5711         if (status < 0)
5712                 goto error;
5713         /* Reset QAM block */
5714         status = qam_reset_qam(state);
5715         if (status < 0)
5716                 goto error;
5717
5718         /* Setup IQM */
5719
5720         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5721         if (status < 0)
5722                 goto error;
5723         status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5724         if (status < 0)
5725                 goto error;
5726
5727         /* Upload IQM Channel Filter settings by
5728                 boot loader from ROM table */
5729         switch (o_mode) {
5730         case OM_QAM_ITU_A:
5731                 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5732                                       DRXK_BLCC_NR_ELEMENTS_TAPS,
5733                         DRXK_BLC_TIMEOUT);
5734                 break;
5735         case OM_QAM_ITU_C:
5736                 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5737                                        DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5738                                        DRXK_BLDC_NR_ELEMENTS_TAPS,
5739                                        DRXK_BLC_TIMEOUT);
5740                 if (status < 0)
5741                         goto error;
5742                 status = bl_direct_cmd(state,
5743                                        IQM_CF_TAP_IM0__A,
5744                                        DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5745                                        DRXK_BLDC_NR_ELEMENTS_TAPS,
5746                                        DRXK_BLC_TIMEOUT);
5747                 break;
5748         default:
5749                 status = -EINVAL;
5750         }
5751         if (status < 0)
5752                 goto error;
5753
5754         status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5755         if (status < 0)
5756                 goto error;
5757         status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5758         if (status < 0)
5759                 goto error;
5760         status = write16(state, IQM_CF_MIDTAP__A,
5761                      ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5762         if (status < 0)
5763                 goto error;
5764
5765         status = write16(state, IQM_RC_STRETCH__A, 21);
5766         if (status < 0)
5767                 goto error;
5768         status = write16(state, IQM_AF_CLP_LEN__A, 0);
5769         if (status < 0)
5770                 goto error;
5771         status = write16(state, IQM_AF_CLP_TH__A, 448);
5772         if (status < 0)
5773                 goto error;
5774         status = write16(state, IQM_AF_SNS_LEN__A, 0);
5775         if (status < 0)
5776                 goto error;
5777         status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5778         if (status < 0)
5779                 goto error;
5780
5781         status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5782         if (status < 0)
5783                 goto error;
5784         status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5785         if (status < 0)
5786                 goto error;
5787         status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5788         if (status < 0)
5789                 goto error;
5790         status = write16(state, IQM_AF_UPD_SEL__A, 0);
5791         if (status < 0)
5792                 goto error;
5793
5794         /* IQM Impulse Noise Processing Unit */
5795         status = write16(state, IQM_CF_CLP_VAL__A, 500);
5796         if (status < 0)
5797                 goto error;
5798         status = write16(state, IQM_CF_DATATH__A, 1000);
5799         if (status < 0)
5800                 goto error;
5801         status = write16(state, IQM_CF_BYPASSDET__A, 1);
5802         if (status < 0)
5803                 goto error;
5804         status = write16(state, IQM_CF_DET_LCT__A, 0);
5805         if (status < 0)
5806                 goto error;
5807         status = write16(state, IQM_CF_WND_LEN__A, 1);
5808         if (status < 0)
5809                 goto error;
5810         status = write16(state, IQM_CF_PKDTH__A, 1);
5811         if (status < 0)
5812                 goto error;
5813         status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5814         if (status < 0)
5815                 goto error;
5816
5817         /* turn on IQMAF. Must be done before setAgc**() */
5818         status = set_iqm_af(state, true);
5819         if (status < 0)
5820                 goto error;
5821         status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5822         if (status < 0)
5823                 goto error;
5824
5825         /* IQM will not be reset from here, sync ADC and update/init AGC */
5826         status = adc_synchronization(state);
5827         if (status < 0)
5828                 goto error;
5829
5830         /* Set the FSM step period */
5831         status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5832         if (status < 0)
5833                 goto error;
5834
5835         /* Halt SCU to enable safe non-atomic accesses */
5836         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5837         if (status < 0)
5838                 goto error;
5839
5840         /* No more resets of the IQM, current standard correctly set =>
5841                 now AGCs can be configured. */
5842
5843         status = init_agc(state, true);
5844         if (status < 0)
5845                 goto error;
5846         status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5847         if (status < 0)
5848                 goto error;
5849
5850         /* Configure AGC's */
5851         status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5852         if (status < 0)
5853                 goto error;
5854         status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5855         if (status < 0)
5856                 goto error;
5857
5858         /* Activate SCU to enable SCU commands */
5859         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5860 error:
5861         if (status < 0)
5862                 pr_err("Error %d on %s\n", status, __func__);
5863         return status;
5864 }
5865
5866 static int write_gpio(struct drxk_state *state)
5867 {
5868         int status;
5869         u16 value = 0;
5870
5871         dprintk(1, "\n");
5872         /* stop lock indicator process */
5873         status = write16(state, SCU_RAM_GPIO__A,
5874                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5875         if (status < 0)
5876                 goto error;
5877
5878         /*  Write magic word to enable pdr reg write               */
5879         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5880         if (status < 0)
5881                 goto error;
5882
5883         if (state->m_has_sawsw) {
5884                 if (state->uio_mask & 0x0001) { /* UIO-1 */
5885                         /* write to io pad configuration register - output mode */
5886                         status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5887                                          state->m_gpio_cfg);
5888                         if (status < 0)
5889                                 goto error;
5890
5891                         /* use corresponding bit in io data output registar */
5892                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5893                         if (status < 0)
5894                                 goto error;
5895                         if ((state->m_gpio & 0x0001) == 0)
5896                                 value &= 0x7FFF;        /* write zero to 15th bit - 1st UIO */
5897                         else
5898                                 value |= 0x8000;        /* write one to 15th bit - 1st UIO */
5899                         /* write back to io data output register */
5900                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5901                         if (status < 0)
5902                                 goto error;
5903                 }
5904                 if (state->uio_mask & 0x0002) { /* UIO-2 */
5905                         /* write to io pad configuration register - output mode */
5906                         status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5907                                          state->m_gpio_cfg);
5908                         if (status < 0)
5909                                 goto error;
5910
5911                         /* use corresponding bit in io data output registar */
5912                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5913                         if (status < 0)
5914                                 goto error;
5915                         if ((state->m_gpio & 0x0002) == 0)
5916                                 value &= 0xBFFF;        /* write zero to 14th bit - 2st UIO */
5917                         else
5918                                 value |= 0x4000;        /* write one to 14th bit - 2st UIO */
5919                         /* write back to io data output register */
5920                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5921                         if (status < 0)
5922                                 goto error;
5923                 }
5924                 if (state->uio_mask & 0x0004) { /* UIO-3 */
5925                         /* write to io pad configuration register - output mode */
5926                         status = write16(state, SIO_PDR_GPIO_CFG__A,
5927                                          state->m_gpio_cfg);
5928                         if (status < 0)
5929                                 goto error;
5930
5931                         /* use corresponding bit in io data output registar */
5932                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5933                         if (status < 0)
5934                                 goto error;
5935                         if ((state->m_gpio & 0x0004) == 0)
5936                                 value &= 0xFFFB;            /* write zero to 2nd bit - 3rd UIO */
5937                         else
5938                                 value |= 0x0004;            /* write one to 2nd bit - 3rd UIO */
5939                         /* write back to io data output register */
5940                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5941                         if (status < 0)
5942                                 goto error;
5943                 }
5944         }
5945         /*  Write magic word to disable pdr reg write               */
5946         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5947 error:
5948         if (status < 0)
5949                 pr_err("Error %d on %s\n", status, __func__);
5950         return status;
5951 }
5952
5953 static int switch_antenna_to_qam(struct drxk_state *state)
5954 {
5955         int status = 0;
5956         bool gpio_state;
5957
5958         dprintk(1, "\n");
5959
5960         if (!state->antenna_gpio)
5961                 return 0;
5962
5963         gpio_state = state->m_gpio & state->antenna_gpio;
5964
5965         if (state->antenna_dvbt ^ gpio_state) {
5966                 /* Antenna is on DVB-T mode. Switch */
5967                 if (state->antenna_dvbt)
5968                         state->m_gpio &= ~state->antenna_gpio;
5969                 else
5970                         state->m_gpio |= state->antenna_gpio;
5971                 status = write_gpio(state);
5972         }
5973         if (status < 0)
5974                 pr_err("Error %d on %s\n", status, __func__);
5975         return status;
5976 }
5977
5978 static int switch_antenna_to_dvbt(struct drxk_state *state)
5979 {
5980         int status = 0;
5981         bool gpio_state;
5982
5983         dprintk(1, "\n");
5984
5985         if (!state->antenna_gpio)
5986                 return 0;
5987
5988         gpio_state = state->m_gpio & state->antenna_gpio;
5989
5990         if (!(state->antenna_dvbt ^ gpio_state)) {
5991                 /* Antenna is on DVB-C mode. Switch */
5992                 if (state->antenna_dvbt)
5993                         state->m_gpio |= state->antenna_gpio;
5994                 else
5995                         state->m_gpio &= ~state->antenna_gpio;
5996                 status = write_gpio(state);
5997         }
5998         if (status < 0)
5999                 pr_err("Error %d on %s\n", status, __func__);
6000         return status;
6001 }
6002
6003
6004 static int power_down_device(struct drxk_state *state)
6005 {
6006         /* Power down to requested mode */
6007         /* Backup some register settings */
6008         /* Set pins with possible pull-ups connected to them in input mode */
6009         /* Analog power down */
6010         /* ADC power down */
6011         /* Power down device */
6012         int status;
6013
6014         dprintk(1, "\n");
6015         if (state->m_b_p_down_open_bridge) {
6016                 /* Open I2C bridge before power down of DRXK */
6017                 status = ConfigureI2CBridge(state, true);
6018                 if (status < 0)
6019                         goto error;
6020         }
6021         /* driver 0.9.0 */
6022         status = dvbt_enable_ofdm_token_ring(state, false);
6023         if (status < 0)
6024                 goto error;
6025
6026         status = write16(state, SIO_CC_PWD_MODE__A,
6027                          SIO_CC_PWD_MODE_LEVEL_CLOCK);
6028         if (status < 0)
6029                 goto error;
6030         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6031         if (status < 0)
6032                 goto error;
6033         state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6034         status = hi_cfg_command(state);
6035 error:
6036         if (status < 0)
6037                 pr_err("Error %d on %s\n", status, __func__);
6038
6039         return status;
6040 }
6041
6042 static int init_drxk(struct drxk_state *state)
6043 {
6044         int status = 0, n = 0;
6045         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6046         u16 driver_version;
6047
6048         dprintk(1, "\n");
6049         if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6050                 drxk_i2c_lock(state);
6051                 status = power_up_device(state);
6052                 if (status < 0)
6053                         goto error;
6054                 status = drxx_open(state);
6055                 if (status < 0)
6056                         goto error;
6057                 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6058                 status = write16(state, SIO_CC_SOFT_RST__A,
6059                                  SIO_CC_SOFT_RST_OFDM__M
6060                                  | SIO_CC_SOFT_RST_SYS__M
6061                                  | SIO_CC_SOFT_RST_OSC__M);
6062                 if (status < 0)
6063                         goto error;
6064                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6065                 if (status < 0)
6066                         goto error;
6067                 /*
6068                  * TODO is this needed? If yes, how much delay in
6069                  * worst case scenario
6070                  */
6071                 usleep_range(1000, 2000);
6072                 state->m_drxk_a3_patch_code = true;
6073                 status = get_device_capabilities(state);
6074                 if (status < 0)
6075                         goto error;
6076
6077                 /* Bridge delay, uses oscilator clock */
6078                 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6079                 /* SDA brdige delay */
6080                 state->m_hi_cfg_bridge_delay =
6081                         (u16) ((state->m_osc_clock_freq / 1000) *
6082                                 HI_I2C_BRIDGE_DELAY) / 1000;
6083                 /* Clipping */
6084                 if (state->m_hi_cfg_bridge_delay >
6085                         SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6086                         state->m_hi_cfg_bridge_delay =
6087                                 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6088                 }
6089                 /* SCL bridge delay, same as SDA for now */
6090                 state->m_hi_cfg_bridge_delay +=
6091                         state->m_hi_cfg_bridge_delay <<
6092                         SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6093
6094                 status = init_hi(state);
6095                 if (status < 0)
6096                         goto error;
6097                 /* disable various processes */
6098 #if NOA1ROM
6099                 if (!(state->m_DRXK_A1_ROM_CODE)
6100                         && !(state->m_DRXK_A2_ROM_CODE))
6101 #endif
6102                 {
6103                         status = write16(state, SCU_RAM_GPIO__A,
6104                                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6105                         if (status < 0)
6106                                 goto error;
6107                 }
6108
6109                 /* disable MPEG port */
6110                 status = mpegts_disable(state);
6111                 if (status < 0)
6112                         goto error;
6113
6114                 /* Stop AUD and SCU */
6115                 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6116                 if (status < 0)
6117                         goto error;
6118                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6119                 if (status < 0)
6120                         goto error;
6121
6122                 /* enable token-ring bus through OFDM block for possible ucode upload */
6123                 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6124                                  SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6125                 if (status < 0)
6126                         goto error;
6127
6128                 /* include boot loader section */
6129                 status = write16(state, SIO_BL_COMM_EXEC__A,
6130                                  SIO_BL_COMM_EXEC_ACTIVE);
6131                 if (status < 0)
6132                         goto error;
6133                 status = bl_chain_cmd(state, 0, 6, 100);
6134                 if (status < 0)
6135                         goto error;
6136
6137                 if (state->fw) {
6138                         status = download_microcode(state, state->fw->data,
6139                                                    state->fw->size);
6140                         if (status < 0)
6141                                 goto error;
6142                 }
6143
6144                 /* disable token-ring bus through OFDM block for possible ucode upload */
6145                 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6146                                  SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6147                 if (status < 0)
6148                         goto error;
6149
6150                 /* Run SCU for a little while to initialize microcode version numbers */
6151                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6152                 if (status < 0)
6153                         goto error;
6154                 status = drxx_open(state);
6155                 if (status < 0)
6156                         goto error;
6157                 /* added for test */
6158                 msleep(30);
6159
6160                 power_mode = DRXK_POWER_DOWN_OFDM;
6161                 status = ctrl_power_mode(state, &power_mode);
6162                 if (status < 0)
6163                         goto error;
6164
6165                 /* Stamp driver version number in SCU data RAM in BCD code
6166                         Done to enable field application engineers to retrieve drxdriver version
6167                         via I2C from SCU RAM.
6168                         Not using SCU command interface for SCU register access since no
6169                         microcode may be present.
6170                         */
6171                 driver_version =
6172                         (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6173                         (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6174                         ((DRXK_VERSION_MAJOR % 10) << 4) +
6175                         (DRXK_VERSION_MINOR % 10);
6176                 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6177                                  driver_version);
6178                 if (status < 0)
6179                         goto error;
6180                 driver_version =
6181                         (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6182                         (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6183                         (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6184                         (DRXK_VERSION_PATCH % 10);
6185                 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6186                                  driver_version);
6187                 if (status < 0)
6188                         goto error;
6189
6190                 pr_info("DRXK driver version %d.%d.%d\n",
6191                         DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6192                         DRXK_VERSION_PATCH);
6193
6194                 /*
6195                  * Dirty fix of default values for ROM/PATCH microcode
6196                  * Dirty because this fix makes it impossible to setup
6197                  * suitable values before calling DRX_Open. This solution
6198                  * requires changes to RF AGC speed to be done via the CTRL
6199                  * function after calling DRX_Open
6200                  */
6201
6202                 /* m_dvbt_rf_agc_cfg.speed = 3; */
6203
6204                 /* Reset driver debug flags to 0 */
6205                 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6206                 if (status < 0)
6207                         goto error;
6208                 /* driver 0.9.0 */
6209                 /* Setup FEC OC:
6210                         NOTE: No more full FEC resets allowed afterwards!! */
6211                 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6212                 if (status < 0)
6213                         goto error;
6214                 /* MPEGTS functions are still the same */
6215                 status = mpegts_dto_init(state);
6216                 if (status < 0)
6217                         goto error;
6218                 status = mpegts_stop(state);
6219                 if (status < 0)
6220                         goto error;
6221                 status = mpegts_configure_polarity(state);
6222                 if (status < 0)
6223                         goto error;
6224                 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6225                 if (status < 0)
6226                         goto error;
6227                 /* added: configure GPIO */
6228                 status = write_gpio(state);
6229                 if (status < 0)
6230                         goto error;
6231
6232                 state->m_drxk_state = DRXK_STOPPED;
6233
6234                 if (state->m_b_power_down) {
6235                         status = power_down_device(state);
6236                         if (status < 0)
6237                                 goto error;
6238                         state->m_drxk_state = DRXK_POWERED_DOWN;
6239                 } else
6240                         state->m_drxk_state = DRXK_STOPPED;
6241
6242                 /* Initialize the supported delivery systems */
6243                 n = 0;
6244                 if (state->m_has_dvbc) {
6245                         state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6246                         state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6247                         strlcat(state->frontend.ops.info.name, " DVB-C",
6248                                 sizeof(state->frontend.ops.info.name));
6249                 }
6250                 if (state->m_has_dvbt) {
6251                         state->frontend.ops.delsys[n++] = SYS_DVBT;
6252                         strlcat(state->frontend.ops.info.name, " DVB-T",
6253                                 sizeof(state->frontend.ops.info.name));
6254                 }
6255                 drxk_i2c_unlock(state);
6256         }
6257 error:
6258         if (status < 0) {
6259                 state->m_drxk_state = DRXK_NO_DEV;
6260                 drxk_i2c_unlock(state);
6261                 pr_err("Error %d on %s\n", status, __func__);
6262         }
6263
6264         return status;
6265 }
6266
6267 static void load_firmware_cb(const struct firmware *fw,
6268                              void *context)
6269 {
6270         struct drxk_state *state = context;
6271
6272         dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6273         if (!fw) {
6274                 pr_err("Could not load firmware file %s.\n",
6275                         state->microcode_name);
6276                 pr_info("Copy %s to your hotplug directory!\n",
6277                         state->microcode_name);
6278                 state->microcode_name = NULL;
6279
6280                 /*
6281                  * As firmware is now load asynchronous, it is not possible
6282                  * anymore to fail at frontend attach. We might silently
6283                  * return here, and hope that the driver won't crash.
6284                  * We might also change all DVB callbacks to return -ENODEV
6285                  * if the device is not initialized.
6286                  * As the DRX-K devices have their own internal firmware,
6287                  * let's just hope that it will match a firmware revision
6288                  * compatible with this driver and proceed.
6289                  */
6290         }
6291         state->fw = fw;
6292
6293         init_drxk(state);
6294 }
6295
6296 static void drxk_release(struct dvb_frontend *fe)
6297 {
6298         struct drxk_state *state = fe->demodulator_priv;
6299
6300         dprintk(1, "\n");
6301         release_firmware(state->fw);
6302
6303         kfree(state);
6304 }
6305
6306 static int drxk_sleep(struct dvb_frontend *fe)
6307 {
6308         struct drxk_state *state = fe->demodulator_priv;
6309
6310         dprintk(1, "\n");
6311
6312         if (state->m_drxk_state == DRXK_NO_DEV)
6313                 return -ENODEV;
6314         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6315                 return 0;
6316
6317         shut_down(state);
6318         return 0;
6319 }
6320
6321 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6322 {
6323         struct drxk_state *state = fe->demodulator_priv;
6324
6325         dprintk(1, ": %s\n", enable ? "enable" : "disable");
6326
6327         if (state->m_drxk_state == DRXK_NO_DEV)
6328                 return -ENODEV;
6329
6330         return ConfigureI2CBridge(state, enable ? true : false);
6331 }
6332
6333 static int drxk_set_parameters(struct dvb_frontend *fe)
6334 {
6335         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6336         u32 delsys  = p->delivery_system, old_delsys;
6337         struct drxk_state *state = fe->demodulator_priv;
6338         u32 IF;
6339
6340         dprintk(1, "\n");
6341
6342         if (state->m_drxk_state == DRXK_NO_DEV)
6343                 return -ENODEV;
6344
6345         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6346                 return -EAGAIN;
6347
6348         if (!fe->ops.tuner_ops.get_if_frequency) {
6349                 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6350                 return -EINVAL;
6351         }
6352
6353         if (fe->ops.i2c_gate_ctrl)
6354                 fe->ops.i2c_gate_ctrl(fe, 1);
6355         if (fe->ops.tuner_ops.set_params)
6356                 fe->ops.tuner_ops.set_params(fe);
6357         if (fe->ops.i2c_gate_ctrl)
6358                 fe->ops.i2c_gate_ctrl(fe, 0);
6359
6360         old_delsys = state->props.delivery_system;
6361         state->props = *p;
6362
6363         if (old_delsys != delsys) {
6364                 shut_down(state);
6365                 switch (delsys) {
6366                 case SYS_DVBC_ANNEX_A:
6367                 case SYS_DVBC_ANNEX_C:
6368                         if (!state->m_has_dvbc)
6369                                 return -EINVAL;
6370                         state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6371                                                 true : false;
6372                         if (state->m_itut_annex_c)
6373                                 setoperation_mode(state, OM_QAM_ITU_C);
6374                         else
6375                                 setoperation_mode(state, OM_QAM_ITU_A);
6376                         break;
6377                 case SYS_DVBT:
6378                         if (!state->m_has_dvbt)
6379                                 return -EINVAL;
6380                         setoperation_mode(state, OM_DVBT);
6381                         break;
6382                 default:
6383                         return -EINVAL;
6384                 }
6385         }
6386
6387         fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6388         start(state, 0, IF);
6389
6390         /* After set_frontend, stats aren't available */
6391         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6392         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6393         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6394         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6395         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6396         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6397         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6398         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6399
6400         /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6401
6402         return 0;
6403 }
6404
6405 static int get_strength(struct drxk_state *state, u64 *strength)
6406 {
6407         int status;
6408         struct s_cfg_agc   rf_agc, if_agc;
6409         u32          total_gain  = 0;
6410         u32          atten      = 0;
6411         u32          agc_range   = 0;
6412         u16            scu_lvl  = 0;
6413         u16            scu_coc  = 0;
6414         /* FIXME: those are part of the tuner presets */
6415         u16 tuner_rf_gain         = 50; /* Default value on az6007 driver */
6416         u16 tuner_if_gain         = 40; /* Default value on az6007 driver */
6417
6418         *strength = 0;
6419
6420         if (is_dvbt(state)) {
6421                 rf_agc = state->m_dvbt_rf_agc_cfg;
6422                 if_agc = state->m_dvbt_if_agc_cfg;
6423         } else if (is_qam(state)) {
6424                 rf_agc = state->m_qam_rf_agc_cfg;
6425                 if_agc = state->m_qam_if_agc_cfg;
6426         } else {
6427                 rf_agc = state->m_atv_rf_agc_cfg;
6428                 if_agc = state->m_atv_if_agc_cfg;
6429         }
6430
6431         if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6432                 /* SCU output_level */
6433                 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6434                 if (status < 0)
6435                         return status;
6436
6437                 /* SCU c.o.c. */
6438                 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6439                 if (status < 0)
6440                         return status;
6441
6442                 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6443                         rf_agc.output_level = scu_lvl + scu_coc;
6444                 else
6445                         rf_agc.output_level = 0xffff;
6446
6447                 /* Take RF gain into account */
6448                 total_gain += tuner_rf_gain;
6449
6450                 /* clip output value */
6451                 if (rf_agc.output_level < rf_agc.min_output_level)
6452                         rf_agc.output_level = rf_agc.min_output_level;
6453                 if (rf_agc.output_level > rf_agc.max_output_level)
6454                         rf_agc.output_level = rf_agc.max_output_level;
6455
6456                 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6457                 if (agc_range > 0) {
6458                         atten += 100UL *
6459                                 ((u32)(tuner_rf_gain)) *
6460                                 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6461                                 / agc_range;
6462                 }
6463         }
6464
6465         if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6466                 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6467                                 &if_agc.output_level);
6468                 if (status < 0)
6469                         return status;
6470
6471                 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6472                                 &if_agc.top);
6473                 if (status < 0)
6474                         return status;
6475
6476                 /* Take IF gain into account */
6477                 total_gain += (u32) tuner_if_gain;
6478
6479                 /* clip output value */
6480                 if (if_agc.output_level < if_agc.min_output_level)
6481                         if_agc.output_level = if_agc.min_output_level;
6482                 if (if_agc.output_level > if_agc.max_output_level)
6483                         if_agc.output_level = if_agc.max_output_level;
6484
6485                 agc_range  = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6486                 if (agc_range > 0) {
6487                         atten += 100UL *
6488                                 ((u32)(tuner_if_gain)) *
6489                                 ((u32)(if_agc.output_level - if_agc.min_output_level))
6490                                 / agc_range;
6491                 }
6492         }
6493
6494         /*
6495          * Convert to 0..65535 scale.
6496          * If it can't be measured (AGC is disabled), just show 100%.
6497          */
6498         if (total_gain > 0)
6499                 *strength = (65535UL * atten / total_gain / 100);
6500         else
6501                 *strength = 65535;
6502
6503         return 0;
6504 }
6505
6506 static int drxk_get_stats(struct dvb_frontend *fe)
6507 {
6508         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6509         struct drxk_state *state = fe->demodulator_priv;
6510         int status;
6511         u32 stat;
6512         u16 reg16;
6513         u32 post_bit_count;
6514         u32 post_bit_err_count;
6515         u32 post_bit_error_scale;
6516         u32 pre_bit_err_count;
6517         u32 pre_bit_count;
6518         u32 pkt_count;
6519         u32 pkt_error_count;
6520         s32 cnr;
6521
6522         if (state->m_drxk_state == DRXK_NO_DEV)
6523                 return -ENODEV;
6524         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6525                 return -EAGAIN;
6526
6527         /* get status */
6528         state->fe_status = 0;
6529         get_lock_status(state, &stat);
6530         if (stat == MPEG_LOCK)
6531                 state->fe_status |= 0x1f;
6532         if (stat == FEC_LOCK)
6533                 state->fe_status |= 0x0f;
6534         if (stat == DEMOD_LOCK)
6535                 state->fe_status |= 0x07;
6536
6537         /*
6538          * Estimate signal strength from AGC
6539          */
6540         get_strength(state, &c->strength.stat[0].uvalue);
6541         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6542
6543
6544         if (stat >= DEMOD_LOCK) {
6545                 get_signal_to_noise(state, &cnr);
6546                 c->cnr.stat[0].svalue = cnr * 100;
6547                 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6548         } else {
6549                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6550         }
6551
6552         if (stat < FEC_LOCK) {
6553                 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6554                 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6555                 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6556                 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6557                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6558                 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6559                 return 0;
6560         }
6561
6562         /* Get post BER */
6563
6564         /* BER measurement is valid if at least FEC lock is achieved */
6565
6566         /*
6567          * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6568          * written to set nr of symbols or bits over which to measure
6569          * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6570          */
6571
6572         /* Read registers for post/preViterbi BER calculation */
6573         status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);
6574         if (status < 0)
6575                 goto error;
6576         pre_bit_err_count = reg16;
6577
6578         status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);
6579         if (status < 0)
6580                 goto error;
6581         pre_bit_count = reg16;
6582
6583         /* Number of bit-errors */
6584         status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);
6585         if (status < 0)
6586                 goto error;
6587         post_bit_err_count = reg16;
6588
6589         status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);
6590         if (status < 0)
6591                 goto error;
6592         post_bit_error_scale = reg16;
6593
6594         status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);
6595         if (status < 0)
6596                 goto error;
6597         pkt_count = reg16;
6598
6599         status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);
6600         if (status < 0)
6601                 goto error;
6602         pkt_error_count = reg16;
6603         write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6604
6605         post_bit_err_count *= post_bit_error_scale;
6606
6607         post_bit_count = pkt_count * 204 * 8;
6608
6609         /* Store the results */
6610         c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6611         c->block_error.stat[0].uvalue += pkt_error_count;
6612         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6613         c->block_count.stat[0].uvalue += pkt_count;
6614
6615         c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6616         c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6617         c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6618         c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6619
6620         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6621         c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6622         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6623         c->post_bit_count.stat[0].uvalue += post_bit_count;
6624
6625 error:
6626         return status;
6627 }
6628
6629
6630 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6631 {
6632         struct drxk_state *state = fe->demodulator_priv;
6633         int rc;
6634
6635         dprintk(1, "\n");
6636
6637         rc = drxk_get_stats(fe);
6638         if (rc < 0)
6639                 return rc;
6640
6641         *status = state->fe_status;
6642
6643         return 0;
6644 }
6645
6646 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6647                                      u16 *strength)
6648 {
6649         struct drxk_state *state = fe->demodulator_priv;
6650         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6651
6652         dprintk(1, "\n");
6653
6654         if (state->m_drxk_state == DRXK_NO_DEV)
6655                 return -ENODEV;
6656         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6657                 return -EAGAIN;
6658
6659         *strength = c->strength.stat[0].uvalue;
6660         return 0;
6661 }
6662
6663 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6664 {
6665         struct drxk_state *state = fe->demodulator_priv;
6666         s32 snr2;
6667
6668         dprintk(1, "\n");
6669
6670         if (state->m_drxk_state == DRXK_NO_DEV)
6671                 return -ENODEV;
6672         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6673                 return -EAGAIN;
6674
6675         get_signal_to_noise(state, &snr2);
6676
6677         /* No negative SNR, clip to zero */
6678         if (snr2 < 0)
6679                 snr2 = 0;
6680         *snr = snr2 & 0xffff;
6681         return 0;
6682 }
6683
6684 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6685 {
6686         struct drxk_state *state = fe->demodulator_priv;
6687         u16 err;
6688
6689         dprintk(1, "\n");
6690
6691         if (state->m_drxk_state == DRXK_NO_DEV)
6692                 return -ENODEV;
6693         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6694                 return -EAGAIN;
6695
6696         dvbtqam_get_acc_pkt_err(state, &err);
6697         *ucblocks = (u32) err;
6698         return 0;
6699 }
6700
6701 static int drxk_get_tune_settings(struct dvb_frontend *fe,
6702                                   struct dvb_frontend_tune_settings *sets)
6703 {
6704         struct drxk_state *state = fe->demodulator_priv;
6705         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6706
6707         dprintk(1, "\n");
6708
6709         if (state->m_drxk_state == DRXK_NO_DEV)
6710                 return -ENODEV;
6711         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6712                 return -EAGAIN;
6713
6714         switch (p->delivery_system) {
6715         case SYS_DVBC_ANNEX_A:
6716         case SYS_DVBC_ANNEX_C:
6717         case SYS_DVBT:
6718                 sets->min_delay_ms = 3000;
6719                 sets->max_drift = 0;
6720                 sets->step_size = 0;
6721                 return 0;
6722         default:
6723                 return -EINVAL;
6724         }
6725 }
6726
6727 static const struct dvb_frontend_ops drxk_ops = {
6728         /* .delsys will be filled dynamically */
6729         .info = {
6730                 .name = "DRXK",
6731                 .frequency_min_hz =  47 * MHz,
6732                 .frequency_max_hz = 865 * MHz,
6733                  /* For DVB-C */
6734                 .symbol_rate_min =   870000,
6735                 .symbol_rate_max = 11700000,
6736                 /* For DVB-T */
6737                 .frequency_stepsize_hz = 166667,
6738
6739                 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6740                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6741                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6742                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6743                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6744                         FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6745         },
6746
6747         .release = drxk_release,
6748         .sleep = drxk_sleep,
6749         .i2c_gate_ctrl = drxk_gate_ctrl,
6750
6751         .set_frontend = drxk_set_parameters,
6752         .get_tune_settings = drxk_get_tune_settings,
6753
6754         .read_status = drxk_read_status,
6755         .read_signal_strength = drxk_read_signal_strength,
6756         .read_snr = drxk_read_snr,
6757         .read_ucblocks = drxk_read_ucblocks,
6758 };
6759
6760 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6761                                  struct i2c_adapter *i2c)
6762 {
6763         struct dtv_frontend_properties *p;
6764         struct drxk_state *state = NULL;
6765         u8 adr = config->adr;
6766         int status;
6767
6768         dprintk(1, "\n");
6769         state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6770         if (!state)
6771                 return NULL;
6772
6773         state->i2c = i2c;
6774         state->demod_address = adr;
6775         state->single_master = config->single_master;
6776         state->microcode_name = config->microcode_name;
6777         state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6778         state->no_i2c_bridge = config->no_i2c_bridge;
6779         state->antenna_gpio = config->antenna_gpio;
6780         state->antenna_dvbt = config->antenna_dvbt;
6781         state->m_chunk_size = config->chunk_size;
6782         state->enable_merr_cfg = config->enable_merr_cfg;
6783
6784         if (config->dynamic_clk) {
6785                 state->m_dvbt_static_clk = false;
6786                 state->m_dvbc_static_clk = false;
6787         } else {
6788                 state->m_dvbt_static_clk = true;
6789                 state->m_dvbc_static_clk = true;
6790         }
6791
6792
6793         if (config->mpeg_out_clk_strength)
6794                 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6795         else
6796                 state->m_ts_clockk_strength = 0x06;
6797
6798         if (config->parallel_ts)
6799                 state->m_enable_parallel = true;
6800         else
6801                 state->m_enable_parallel = false;
6802
6803         /* NOTE: as more UIO bits will be used, add them to the mask */
6804         state->uio_mask = config->antenna_gpio;
6805
6806         /* Default gpio to DVB-C */
6807         if (!state->antenna_dvbt && state->antenna_gpio)
6808                 state->m_gpio |= state->antenna_gpio;
6809         else
6810                 state->m_gpio &= ~state->antenna_gpio;
6811
6812         mutex_init(&state->mutex);
6813
6814         memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6815         state->frontend.demodulator_priv = state;
6816
6817         init_state(state);
6818
6819         /* Load firmware and initialize DRX-K */
6820         if (state->microcode_name) {
6821                 const struct firmware *fw = NULL;
6822
6823                 status = request_firmware(&fw, state->microcode_name,
6824                                           state->i2c->dev.parent);
6825                 if (status < 0)
6826                         fw = NULL;
6827                 load_firmware_cb(fw, state);
6828         } else if (init_drxk(state) < 0)
6829                 goto error;
6830
6831
6832         /* Initialize stats */
6833         p = &state->frontend.dtv_property_cache;
6834         p->strength.len = 1;
6835         p->cnr.len = 1;
6836         p->block_error.len = 1;
6837         p->block_count.len = 1;
6838         p->pre_bit_error.len = 1;
6839         p->pre_bit_count.len = 1;
6840         p->post_bit_error.len = 1;
6841         p->post_bit_count.len = 1;
6842
6843         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6844         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6845         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6846         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6847         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6848         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6849         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6850         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6851
6852         pr_info("frontend initialized.\n");
6853         return &state->frontend;
6854
6855 error:
6856         pr_err("not found\n");
6857         kfree(state);
6858         return NULL;
6859 }
6860 EXPORT_SYMBOL(drxk_attach);
6861
6862 MODULE_DESCRIPTION("DRX-K driver");
6863 MODULE_AUTHOR("Ralph Metzler");
6864 MODULE_LICENSE("GPL");