1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux-DVB Driver for DiBcom's DiB0070 base-band RF Tuner.
5 * Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
7 * This code is more or less generated from another driver, please
8 * excuse some codingstyle oddities.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/i2c.h>
16 #include <linux/mutex.h>
18 #include <media/dvb_frontend.h>
21 #include "dibx000_common.h"
24 module_param(debug, int, 0644);
25 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
27 #define dprintk(fmt, arg...) do { \
29 printk(KERN_DEBUG pr_fmt("%s: " fmt), \
33 #define DIB0070_P1D 0x00
34 #define DIB0070_P1F 0x01
35 #define DIB0070_P1G 0x03
36 #define DIB0070S_P1A 0x02
38 struct dib0070_state {
39 struct i2c_adapter *i2c;
40 struct dvb_frontend *fe;
41 const struct dib0070_config *cfg;
45 enum frontend_tune_state tune_state;
48 /* for the captrim binary search */
56 const struct dib0070_tuning *current_tune_table_index;
57 const struct dib0070_lna_match *lna_match;
60 u16 wbd_offset_3_3[2];
62 /* for the I2C transfer */
63 struct i2c_msg msg[2];
64 u8 i2c_write_buffer[3];
65 u8 i2c_read_buffer[2];
66 struct mutex i2c_buffer_lock;
69 static u16 dib0070_read_reg(struct dib0070_state *state, u8 reg)
73 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
74 dprintk("could not acquire lock\n");
78 state->i2c_write_buffer[0] = reg;
80 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
81 state->msg[0].addr = state->cfg->i2c_address;
82 state->msg[0].flags = 0;
83 state->msg[0].buf = state->i2c_write_buffer;
84 state->msg[0].len = 1;
85 state->msg[1].addr = state->cfg->i2c_address;
86 state->msg[1].flags = I2C_M_RD;
87 state->msg[1].buf = state->i2c_read_buffer;
88 state->msg[1].len = 2;
90 if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
91 pr_warn("DiB0070 I2C read failed\n");
94 ret = (state->i2c_read_buffer[0] << 8)
95 | state->i2c_read_buffer[1];
97 mutex_unlock(&state->i2c_buffer_lock);
101 static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
105 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
106 dprintk("could not acquire lock\n");
109 state->i2c_write_buffer[0] = reg;
110 state->i2c_write_buffer[1] = val >> 8;
111 state->i2c_write_buffer[2] = val & 0xff;
113 memset(state->msg, 0, sizeof(struct i2c_msg));
114 state->msg[0].addr = state->cfg->i2c_address;
115 state->msg[0].flags = 0;
116 state->msg[0].buf = state->i2c_write_buffer;
117 state->msg[0].len = 3;
119 if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
120 pr_warn("DiB0070 I2C write failed\n");
125 mutex_unlock(&state->i2c_buffer_lock);
129 #define HARD_RESET(state) do { \
130 state->cfg->sleep(state->fe, 0); \
131 if (state->cfg->reset) { \
132 state->cfg->reset(state->fe,1); msleep(10); \
133 state->cfg->reset(state->fe,0); msleep(10); \
137 static int dib0070_set_bandwidth(struct dvb_frontend *fe)
139 struct dib0070_state *state = fe->tuner_priv;
140 u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
142 if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
144 else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
146 else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
151 dib0070_write_reg(state, 0x02, tmp);
153 /* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
154 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
155 u16 value = dib0070_read_reg(state, 0x17);
157 dib0070_write_reg(state, 0x17, value & 0xfffc);
158 tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
159 dib0070_write_reg(state, 0x01, tmp | (60 << 9));
161 dib0070_write_reg(state, 0x17, value);
166 static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state)
172 if (*tune_state == CT_TUNER_STEP_0) {
173 dib0070_write_reg(state, 0x0f, 0xed10);
174 dib0070_write_reg(state, 0x17, 0x0034);
176 dib0070_write_reg(state, 0x18, 0x0032);
177 state->step = state->captrim = state->fcaptrim = 64;
178 state->adc_diff = 3000;
181 *tune_state = CT_TUNER_STEP_1;
182 } else if (*tune_state == CT_TUNER_STEP_1) {
184 dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
187 *tune_state = CT_TUNER_STEP_2;
188 } else if (*tune_state == CT_TUNER_STEP_2) {
190 adc = dib0070_read_reg(state, 0x19);
192 dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV\n", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
202 if (adc < state->adc_diff) {
203 dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)\n", state->captrim, adc, state->adc_diff);
204 state->adc_diff = adc;
205 state->fcaptrim = state->captrim;
207 state->captrim += (step_sign * state->step);
209 if (state->step >= 1)
210 *tune_state = CT_TUNER_STEP_1;
212 *tune_state = CT_TUNER_STEP_3;
214 } else if (*tune_state == CT_TUNER_STEP_3) {
215 dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
216 dib0070_write_reg(state, 0x18, 0x07ff);
217 *tune_state = CT_TUNER_STEP_4;
223 static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
225 struct dib0070_state *state = fe->tuner_priv;
226 u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
228 dprintk("CTRL_LO5: 0x%x\n", lo5);
229 return dib0070_write_reg(state, 0x15, lo5);
232 void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
234 struct dib0070_state *state = fe->tuner_priv;
237 dib0070_write_reg(state, 0x1b, 0xff00);
238 dib0070_write_reg(state, 0x1a, 0x0000);
240 dib0070_write_reg(state, 0x1b, 0x4112);
241 if (state->cfg->vga_filter != 0) {
242 dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
243 dprintk("vga filter register is set to %x\n", state->cfg->vga_filter);
245 dib0070_write_reg(state, 0x1a, 0x0009);
249 EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
250 struct dib0070_tuning {
251 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
261 struct dib0070_lna_match {
262 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
266 static const struct dib0070_tuning dib0070s_tuning_table[] = {
267 { 570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */
268 { 700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 },
269 { 863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 },
270 { 1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */
271 { 1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
272 { 2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
273 { 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */
276 static const struct dib0070_tuning dib0070_tuning_table[] = {
277 { 115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
278 { 179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
279 { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
280 { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
281 { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
282 { 699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800 },
283 { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
284 { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
287 static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
288 { 180000, 0 }, /* VHF */
292 { 550000, 0 }, /* UHF */
296 { 1500000, 0 }, /* LBAND or everything higher than UHF */
302 static const struct dib0070_lna_match dib0070_lna[] = {
303 { 180000, 0 }, /* VHF */
307 { 550000, 2 }, /* UHF */
312 { 1500000, 0 }, /* LBAND or everything higher than UHF */
319 static int dib0070_tune_digital(struct dvb_frontend *fe)
321 struct dib0070_state *state = fe->tuner_priv;
323 const struct dib0070_tuning *tune;
324 const struct dib0070_lna_match *lna_match;
326 enum frontend_tune_state *tune_state = &state->tune_state;
327 int ret = 10; /* 1ms is the default delay most of the time */
329 u8 band = (u8)BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency/1000);
330 u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
332 #ifdef CONFIG_SYS_ISDBT
333 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
334 if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
335 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
336 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
337 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
338 || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
339 && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
342 if (state->current_rf != freq) {
344 switch (state->revision) {
346 tune = dib0070s_tuning_table;
347 lna_match = dib0070_lna;
350 tune = dib0070_tuning_table;
351 if (state->cfg->flip_chip)
352 lna_match = dib0070_lna_flip_chip;
354 lna_match = dib0070_lna;
357 while (freq > tune->max_freq) /* find the right one */
359 while (freq > lna_match->max_freq) /* find the right one */
362 state->current_tune_table_index = tune;
363 state->lna_match = lna_match;
366 if (*tune_state == CT_TUNER_START) {
367 dprintk("Tuning for Band: %hd (%d kHz)\n", band, freq);
368 if (state->current_rf != freq) {
370 u32 FBDiv, Rest, FREF, VCOF_kHz;
373 state->current_rf = freq;
374 state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
377 dib0070_write_reg(state, 0x17, 0x30);
380 VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
384 REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
387 REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
390 REFDIV = (u8) (state->cfg->clock_khz / 10000);
393 FREF = state->cfg->clock_khz / REFDIV;
397 switch (state->revision) {
399 FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
400 Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
406 FBDiv = (freq / (FREF / 2));
407 Rest = 2 * freq - FBDiv * FREF;
413 else if (Rest < 2 * LPF)
415 else if (Rest > (FREF - LPF)) {
418 } else if (Rest > (FREF - 2 * LPF))
419 Rest = FREF - 2 * LPF;
420 Rest = (Rest * 6528) / (FREF / 10);
424 state->lo4 |= (1 << 14) | (1 << 12);
429 dib0070_write_reg(state, 0x11, (u16)FBDiv);
430 dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
431 dib0070_write_reg(state, 0x13, (u16) Rest);
433 if (state->revision == DIB0070S_P1A) {
435 if (band == BAND_SBAND) {
436 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
437 dib0070_write_reg(state, 0x1d, 0xFFFF);
439 dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
442 dib0070_write_reg(state, 0x20,
443 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
445 dprintk("REFDIV: %hd, FREF: %d\n", REFDIV, FREF);
446 dprintk("FBDIV: %d, Rest: %d\n", FBDiv, Rest);
447 dprintk("Num: %hd, Den: %hd, SD: %hd\n", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
448 dprintk("HFDIV code: %hd\n", state->current_tune_table_index->hfdiv);
449 dprintk("VCO = %hd\n", state->current_tune_table_index->vco_band);
450 dprintk("VCOF: ((%hd*%d) << 1))\n", state->current_tune_table_index->vco_multi, freq);
452 *tune_state = CT_TUNER_STEP_0;
453 } else { /* we are already tuned to this frequency - the configuration is correct */
454 ret = 50; /* wakeup time */
455 *tune_state = CT_TUNER_STEP_5;
457 } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
459 ret = dib0070_captrim(state, tune_state);
461 } else if (*tune_state == CT_TUNER_STEP_4) {
462 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
464 while (freq/1000 > tmp->freq) /* find the right one */
466 dib0070_write_reg(state, 0x0f,
467 (0 << 15) | (1 << 14) | (3 << 12)
468 | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
469 | (state->current_tune_table_index->wbdmux << 0));
470 state->wbd_gain_current = tmp->wbd_gain_val;
472 dib0070_write_reg(state, 0x0f,
473 (0 << 15) | (1 << 14) | (3 << 12)
474 | (6 << 9) | (0 << 8) | (1 << 7)
475 | (state->current_tune_table_index->wbdmux << 0));
476 state->wbd_gain_current = 6;
479 dib0070_write_reg(state, 0x06, 0x3fff);
480 dib0070_write_reg(state, 0x07,
481 (state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
482 dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
483 dib0070_write_reg(state, 0x0d, 0x0d80);
486 dib0070_write_reg(state, 0x18, 0x07ff);
487 dib0070_write_reg(state, 0x17, 0x0033);
490 *tune_state = CT_TUNER_STEP_5;
491 } else if (*tune_state == CT_TUNER_STEP_5) {
492 dib0070_set_bandwidth(fe);
493 *tune_state = CT_TUNER_STOP;
495 ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
501 static int dib0070_tune(struct dvb_frontend *fe)
503 struct dib0070_state *state = fe->tuner_priv;
506 state->tune_state = CT_TUNER_START;
509 ret = dib0070_tune_digital(fe);
510 if (ret != FE_CALLBACK_TIME_NEVER)
514 } while (state->tune_state != CT_TUNER_STOP);
519 static int dib0070_wakeup(struct dvb_frontend *fe)
521 struct dib0070_state *state = fe->tuner_priv;
522 if (state->cfg->sleep)
523 state->cfg->sleep(fe, 0);
527 static int dib0070_sleep(struct dvb_frontend *fe)
529 struct dib0070_state *state = fe->tuner_priv;
530 if (state->cfg->sleep)
531 state->cfg->sleep(fe, 1);
535 u8 dib0070_get_rf_output(struct dvb_frontend *fe)
537 struct dib0070_state *state = fe->tuner_priv;
538 return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
540 EXPORT_SYMBOL(dib0070_get_rf_output);
542 int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
544 struct dib0070_state *state = fe->tuner_priv;
545 u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
550 return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
552 EXPORT_SYMBOL(dib0070_set_rf_output);
554 static const u16 dib0070_p1f_defaults[] =
588 0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
593 static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
595 u16 tuner_en = dib0070_read_reg(state, 0x20);
598 dib0070_write_reg(state, 0x18, 0x07ff);
599 dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
600 dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
602 offset = dib0070_read_reg(state, 0x19);
603 dib0070_write_reg(state, 0x20, tuner_en);
607 static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
610 for (gain = 6; gain < 8; gain++) {
611 state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
612 dprintk("Gain: %d, WBDOffset (3.3V) = %hd\n", gain, state->wbd_offset_3_3[gain-6]);
616 u16 dib0070_wbd_offset(struct dvb_frontend *fe)
618 struct dib0070_state *state = fe->tuner_priv;
619 const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
620 u32 freq = fe->dtv_property_cache.frequency/1000;
623 while (freq/1000 > tmp->freq) /* find the right one */
625 state->wbd_gain_current = tmp->wbd_gain_val;
627 state->wbd_gain_current = 6;
629 return state->wbd_offset_3_3[state->wbd_gain_current - 6];
631 EXPORT_SYMBOL(dib0070_wbd_offset);
633 #define pgm_read_word(w) (*w)
634 static int dib0070_reset(struct dvb_frontend *fe)
636 struct dib0070_state *state = fe->tuner_priv;
642 #ifndef FORCE_SBAND_TUNER
643 if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
644 state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
647 #warning forcing SBAND
649 state->revision = DIB0070S_P1A;
652 dprintk("Revision: %x\n", state->revision);
654 if (state->revision == DIB0070_P1D) {
655 dprintk("Error: this driver is not to be used meant for P1D or earlier\n");
659 n = (u16 *) dib0070_p1f_defaults;
660 l = pgm_read_word(n++);
662 r = pgm_read_word(n++);
664 dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
667 l = pgm_read_word(n++);
670 if (state->cfg->force_crystal_mode != 0)
671 r = state->cfg->force_crystal_mode;
672 else if (state->cfg->clock_khz >= 24000)
678 r |= state->cfg->osc_buffer_state << 3;
680 dib0070_write_reg(state, 0x10, r);
681 dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5));
683 if (state->cfg->invert_iq) {
684 r = dib0070_read_reg(state, 0x02) & 0xffdf;
685 dib0070_write_reg(state, 0x02, r | (1 << 5));
688 if (state->revision == DIB0070S_P1A)
689 dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
691 dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump,
692 state->cfg->enable_third_order_filter);
694 dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
696 dib0070_wbd_offset_calibration(state);
701 static int dib0070_get_frequency(struct dvb_frontend *fe, u32 *frequency)
703 struct dib0070_state *state = fe->tuner_priv;
705 *frequency = 1000 * state->current_rf;
709 static void dib0070_release(struct dvb_frontend *fe)
711 kfree(fe->tuner_priv);
712 fe->tuner_priv = NULL;
715 static const struct dvb_tuner_ops dib0070_ops = {
717 .name = "DiBcom DiB0070",
718 .frequency_min_hz = 45 * MHz,
719 .frequency_max_hz = 860 * MHz,
720 .frequency_step_hz = 1 * kHz,
722 .release = dib0070_release,
724 .init = dib0070_wakeup,
725 .sleep = dib0070_sleep,
726 .set_params = dib0070_tune,
728 .get_frequency = dib0070_get_frequency,
729 // .get_bandwidth = dib0070_get_bandwidth
732 struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
734 struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
741 mutex_init(&state->i2c_buffer_lock);
742 fe->tuner_priv = state;
744 if (dib0070_reset(fe) != 0)
747 pr_info("DiB0070: successfully identified\n");
748 memcpy(&fe->ops.tuner_ops, &dib0070_ops, sizeof(struct dvb_tuner_ops));
750 fe->tuner_priv = state;
755 fe->tuner_priv = NULL;
758 EXPORT_SYMBOL(dib0070_attach);
760 MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>");
761 MODULE_DESCRIPTION("Driver for the DiBcom 0070 base-band RF Tuner");
762 MODULE_LICENSE("GPL");