1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/delay.h>
7 #include <linux/interrupt.h>
9 #include <linux/mailbox_controller.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <linux/slab.h>
16 #include <soc/tegra/fuse.h>
18 #include <dt-bindings/mailbox/tegra186-hsp.h>
22 #define HSP_INT_IE(x) (0x100 + ((x) * 4))
23 #define HSP_INT_IV 0x300
24 #define HSP_INT_IR 0x304
26 #define HSP_INT_EMPTY_SHIFT 0
27 #define HSP_INT_EMPTY_MASK 0xff
28 #define HSP_INT_FULL_SHIFT 8
29 #define HSP_INT_FULL_MASK 0xff
31 #define HSP_INT_DIMENSIONING 0x380
32 #define HSP_nSM_SHIFT 0
33 #define HSP_nSS_SHIFT 4
34 #define HSP_nAS_SHIFT 8
35 #define HSP_nDB_SHIFT 12
36 #define HSP_nSI_SHIFT 16
37 #define HSP_nINT_MASK 0xf
39 #define HSP_DB_TRIGGER 0x0
40 #define HSP_DB_ENABLE 0x4
41 #define HSP_DB_RAW 0x8
42 #define HSP_DB_PENDING 0xc
44 #define HSP_SM_SHRD_MBOX 0x0
45 #define HSP_SM_SHRD_MBOX_FULL BIT(31)
46 #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
47 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
49 #define HSP_DB_CCPLEX 1
53 struct tegra_hsp_channel;
56 struct tegra_hsp_channel {
57 struct tegra_hsp *hsp;
58 struct mbox_chan *chan;
62 struct tegra_hsp_doorbell {
63 struct tegra_hsp_channel channel;
64 struct list_head list;
70 struct tegra_hsp_mailbox {
71 struct tegra_hsp_channel channel;
76 struct tegra_hsp_db_map {
82 struct tegra_hsp_soc {
83 const struct tegra_hsp_db_map *map;
89 const struct tegra_hsp_soc *soc;
90 struct mbox_controller mbox_db;
91 struct mbox_controller mbox_sm;
93 unsigned int doorbell_irq;
94 unsigned int *shared_irqs;
95 unsigned int shared_irq;
103 struct lock_class_key lock_key;
105 struct list_head doorbells;
106 struct tegra_hsp_mailbox *mailboxes;
111 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
113 return readl(hsp->regs + offset);
116 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
119 writel(value, hsp->regs + offset);
122 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
125 return readl(channel->regs + offset);
128 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
129 u32 value, unsigned int offset)
131 writel(value, channel->regs + offset);
134 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
138 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
140 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
143 static struct tegra_hsp_doorbell *
144 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
146 struct tegra_hsp_doorbell *entry;
148 list_for_each_entry(entry, &hsp->doorbells, list)
149 if (entry->master == master)
155 static struct tegra_hsp_doorbell *
156 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
158 struct tegra_hsp_doorbell *db;
161 spin_lock_irqsave(&hsp->lock, flags);
162 db = __tegra_hsp_doorbell_get(hsp, master);
163 spin_unlock_irqrestore(&hsp->lock, flags);
168 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
170 struct tegra_hsp *hsp = data;
171 struct tegra_hsp_doorbell *db;
172 unsigned long master, value;
174 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
178 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
179 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
181 spin_lock(&hsp->lock);
183 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
184 struct tegra_hsp_doorbell *db;
186 db = __tegra_hsp_doorbell_get(hsp, master);
188 * Depending on the bootloader chain, the CCPLEX doorbell will
189 * have some doorbells enabled, which means that requesting an
190 * interrupt will immediately fire.
192 * In that case, db->channel.chan will still be NULL here and
193 * cause a crash if not properly guarded.
195 * It remains to be seen if ignoring the doorbell in that case
196 * is the correct solution.
198 if (db && db->channel.chan)
199 mbox_chan_received_data(db->channel.chan, NULL);
202 spin_unlock(&hsp->lock);
207 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
209 struct tegra_hsp *hsp = data;
210 unsigned long bit, mask;
214 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
216 /* process EMPTY interrupts first */
217 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
219 for_each_set_bit(bit, &mask, hsp->num_sm) {
220 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
224 * Disable EMPTY interrupts until data is sent with
225 * the next message. These interrupts are level-
226 * triggered, so if we kept them enabled they would
227 * constantly trigger until we next write data into
230 spin_lock(&hsp->lock);
232 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
233 tegra_hsp_writel(hsp, hsp->mask,
234 HSP_INT_IE(hsp->shared_irq));
236 spin_unlock(&hsp->lock);
238 mbox_chan_txdone(mb->channel.chan, 0);
242 /* process FULL interrupts */
243 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
245 for_each_set_bit(bit, &mask, hsp->num_sm) {
246 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
249 value = tegra_hsp_channel_readl(&mb->channel,
251 value &= ~HSP_SM_SHRD_MBOX_FULL;
252 msg = (void *)(unsigned long)value;
253 mbox_chan_received_data(mb->channel.chan, msg);
256 * Need to clear all bits here since some producers,
257 * such as TCU, depend on fields in the register
258 * getting cleared by the consumer.
260 * The mailbox API doesn't give the consumers a way
261 * of doing that explicitly, so we have to make sure
262 * we cover all possible cases.
264 tegra_hsp_channel_writel(&mb->channel, 0x0,
272 static struct tegra_hsp_channel *
273 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
274 unsigned int master, unsigned int index)
276 struct tegra_hsp_doorbell *db;
280 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
282 return ERR_PTR(-ENOMEM);
284 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
285 offset += index * 0x100;
287 db->channel.regs = hsp->regs + offset;
288 db->channel.hsp = hsp;
290 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
294 spin_lock_irqsave(&hsp->lock, flags);
295 list_add_tail(&db->list, &hsp->doorbells);
296 spin_unlock_irqrestore(&hsp->lock, flags);
301 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
303 struct tegra_hsp_doorbell *db = chan->con_priv;
305 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
310 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
312 struct tegra_hsp_doorbell *db = chan->con_priv;
313 struct tegra_hsp *hsp = db->channel.hsp;
314 struct tegra_hsp_doorbell *ccplex;
318 if (db->master >= chan->mbox->num_chans) {
319 dev_err(chan->mbox->dev,
320 "invalid master ID %u for HSP channel\n",
325 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
330 * On simulation platforms the BPMP hasn't had a chance yet to mark
331 * the doorbell as ringable by the CCPLEX, so we want to skip extra
334 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
337 spin_lock_irqsave(&hsp->lock, flags);
339 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
340 value |= BIT(db->master);
341 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
343 spin_unlock_irqrestore(&hsp->lock, flags);
348 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
350 struct tegra_hsp_doorbell *db = chan->con_priv;
351 struct tegra_hsp *hsp = db->channel.hsp;
352 struct tegra_hsp_doorbell *ccplex;
356 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
360 spin_lock_irqsave(&hsp->lock, flags);
362 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
363 value &= ~BIT(db->master);
364 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
366 spin_unlock_irqrestore(&hsp->lock, flags);
369 static const struct mbox_chan_ops tegra_hsp_db_ops = {
370 .send_data = tegra_hsp_doorbell_send_data,
371 .startup = tegra_hsp_doorbell_startup,
372 .shutdown = tegra_hsp_doorbell_shutdown,
375 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
377 struct tegra_hsp_mailbox *mb = chan->con_priv;
378 struct tegra_hsp *hsp = mb->channel.hsp;
382 if (WARN_ON(!mb->producer))
385 /* copy data and mark mailbox full */
386 value = (u32)(unsigned long)data;
387 value |= HSP_SM_SHRD_MBOX_FULL;
389 tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
391 /* enable EMPTY interrupt for the shared mailbox */
392 spin_lock_irqsave(&hsp->lock, flags);
394 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
395 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
397 spin_unlock_irqrestore(&hsp->lock, flags);
402 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
403 unsigned long timeout)
405 struct tegra_hsp_mailbox *mb = chan->con_priv;
406 struct tegra_hsp_channel *ch = &mb->channel;
409 timeout = jiffies + msecs_to_jiffies(timeout);
411 while (time_before(jiffies, timeout)) {
412 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
413 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
414 mbox_chan_txdone(chan, 0);
424 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
426 struct tegra_hsp_mailbox *mb = chan->con_priv;
427 struct tegra_hsp_channel *ch = &mb->channel;
428 struct tegra_hsp *hsp = mb->channel.hsp;
431 chan->txdone_method = TXDONE_BY_IRQ;
434 * Shared mailboxes start out as consumers by default. FULL and EMPTY
435 * interrupts are coalesced at the same shared interrupt.
437 * Keep EMPTY interrupts disabled at startup and only enable them when
438 * the mailbox is actually full. This is required because the FULL and
439 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
440 * enabled all the time would cause an interrupt storm while mailboxes
444 spin_lock_irqsave(&hsp->lock, flags);
447 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
449 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
451 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
453 spin_unlock_irqrestore(&hsp->lock, flags);
455 if (hsp->soc->has_per_mb_ie) {
457 tegra_hsp_channel_writel(ch, 0x0,
458 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
460 tegra_hsp_channel_writel(ch, 0x1,
461 HSP_SM_SHRD_MBOX_FULL_INT_IE);
467 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
469 struct tegra_hsp_mailbox *mb = chan->con_priv;
470 struct tegra_hsp_channel *ch = &mb->channel;
471 struct tegra_hsp *hsp = mb->channel.hsp;
474 if (hsp->soc->has_per_mb_ie) {
476 tegra_hsp_channel_writel(ch, 0x0,
477 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
479 tegra_hsp_channel_writel(ch, 0x0,
480 HSP_SM_SHRD_MBOX_FULL_INT_IE);
483 spin_lock_irqsave(&hsp->lock, flags);
486 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
488 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
490 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
492 spin_unlock_irqrestore(&hsp->lock, flags);
495 static const struct mbox_chan_ops tegra_hsp_sm_ops = {
496 .send_data = tegra_hsp_mailbox_send_data,
497 .flush = tegra_hsp_mailbox_flush,
498 .startup = tegra_hsp_mailbox_startup,
499 .shutdown = tegra_hsp_mailbox_shutdown,
502 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
503 const struct of_phandle_args *args)
505 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
506 unsigned int type = args->args[0], master = args->args[1];
507 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
508 struct tegra_hsp_doorbell *db;
509 struct mbox_chan *chan;
513 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
514 return ERR_PTR(-ENODEV);
516 db = tegra_hsp_doorbell_get(hsp, master);
518 channel = &db->channel;
521 return ERR_CAST(channel);
523 spin_lock_irqsave(&hsp->lock, flags);
525 for (i = 0; i < mbox->num_chans; i++) {
526 chan = &mbox->chans[i];
527 if (!chan->con_priv) {
528 channel->chan = chan;
536 spin_unlock_irqrestore(&hsp->lock, flags);
538 return chan ?: ERR_PTR(-EBUSY);
541 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
542 const struct of_phandle_args *args)
544 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
545 unsigned int type = args->args[0], index;
546 struct tegra_hsp_mailbox *mb;
548 index = args->args[1] & TEGRA_HSP_SM_MASK;
550 if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
551 index >= hsp->num_sm)
552 return ERR_PTR(-ENODEV);
554 mb = &hsp->mailboxes[index];
556 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
557 mb->producer = false;
561 return mb->channel.chan;
564 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
566 const struct tegra_hsp_db_map *map = hsp->soc->map;
567 struct tegra_hsp_channel *channel;
570 channel = tegra_hsp_doorbell_create(hsp, map->name,
571 map->master, map->index);
573 return PTR_ERR(channel);
581 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
585 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
590 for (i = 0; i < hsp->num_sm; i++) {
591 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
595 mb->channel.hsp = hsp;
596 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
597 mb->channel.chan = &hsp->mbox_sm.chans[i];
598 mb->channel.chan->con_priv = mb;
604 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
606 unsigned int i, irq = 0;
609 for (i = 0; i < hsp->num_si; i++) {
610 irq = hsp->shared_irqs[i];
614 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
615 dev_name(hsp->dev), hsp);
617 dev_err(hsp->dev, "failed to request interrupt: %d\n",
624 /* disable all interrupts */
625 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
627 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
632 if (i == hsp->num_si) {
633 dev_err(hsp->dev, "failed to find available interrupt\n");
640 static int tegra_hsp_probe(struct platform_device *pdev)
642 struct tegra_hsp *hsp;
643 struct resource *res;
648 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
652 hsp->dev = &pdev->dev;
653 hsp->soc = of_device_get_match_data(&pdev->dev);
654 INIT_LIST_HEAD(&hsp->doorbells);
655 spin_lock_init(&hsp->lock);
657 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
658 hsp->regs = devm_ioremap_resource(&pdev->dev, res);
659 if (IS_ERR(hsp->regs))
660 return PTR_ERR(hsp->regs);
662 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
663 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
664 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
665 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
666 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
667 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
669 err = platform_get_irq_byname_optional(pdev, "doorbell");
671 hsp->doorbell_irq = err;
673 if (hsp->num_si > 0) {
674 unsigned int count = 0;
676 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
677 sizeof(*hsp->shared_irqs),
679 if (!hsp->shared_irqs)
682 for (i = 0; i < hsp->num_si; i++) {
685 name = kasprintf(GFP_KERNEL, "shared%u", i);
689 err = platform_get_irq_byname_optional(pdev, name);
691 hsp->shared_irqs[i] = err;
699 devm_kfree(&pdev->dev, hsp->shared_irqs);
700 hsp->shared_irqs = NULL;
704 /* setup the doorbell controller */
705 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
706 hsp->mbox_db.num_chans = 32;
707 hsp->mbox_db.dev = &pdev->dev;
708 hsp->mbox_db.ops = &tegra_hsp_db_ops;
710 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
711 sizeof(*hsp->mbox_db.chans),
713 if (!hsp->mbox_db.chans)
716 if (hsp->doorbell_irq) {
717 err = tegra_hsp_add_doorbells(hsp);
719 dev_err(&pdev->dev, "failed to add doorbells: %d\n",
725 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
727 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
732 /* setup the shared mailbox controller */
733 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
734 hsp->mbox_sm.num_chans = hsp->num_sm;
735 hsp->mbox_sm.dev = &pdev->dev;
736 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
738 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
739 sizeof(*hsp->mbox_sm.chans),
741 if (!hsp->mbox_sm.chans)
744 if (hsp->shared_irqs) {
745 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
747 dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
753 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
755 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
760 platform_set_drvdata(pdev, hsp);
762 if (hsp->doorbell_irq) {
763 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
764 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
765 dev_name(&pdev->dev), hsp);
768 "failed to request doorbell IRQ#%u: %d\n",
769 hsp->doorbell_irq, err);
774 if (hsp->shared_irqs) {
775 err = tegra_hsp_request_shared_irq(hsp);
780 lockdep_register_key(&hsp->lock_key);
781 lockdep_set_class(&hsp->lock, &hsp->lock_key);
786 static int tegra_hsp_remove(struct platform_device *pdev)
788 struct tegra_hsp *hsp = platform_get_drvdata(pdev);
790 lockdep_unregister_key(&hsp->lock_key);
795 static int __maybe_unused tegra_hsp_resume(struct device *dev)
797 struct tegra_hsp *hsp = dev_get_drvdata(dev);
799 struct tegra_hsp_doorbell *db;
801 list_for_each_entry(db, &hsp->doorbells, list) {
802 if (db && db->channel.chan)
803 tegra_hsp_doorbell_startup(db->channel.chan);
806 if (hsp->mailboxes) {
807 for (i = 0; i < hsp->num_sm; i++) {
808 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
810 if (mb->channel.chan->cl)
811 tegra_hsp_mailbox_startup(mb->channel.chan);
818 static const struct dev_pm_ops tegra_hsp_pm_ops = {
819 .resume_noirq = tegra_hsp_resume,
822 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
823 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
824 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
828 static const struct tegra_hsp_soc tegra186_hsp_soc = {
829 .map = tegra186_hsp_db_map,
830 .has_per_mb_ie = false,
833 static const struct tegra_hsp_soc tegra194_hsp_soc = {
834 .map = tegra186_hsp_db_map,
835 .has_per_mb_ie = true,
838 static const struct of_device_id tegra_hsp_match[] = {
839 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
840 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
844 static struct platform_driver tegra_hsp_driver = {
847 .of_match_table = tegra_hsp_match,
848 .pm = &tegra_hsp_pm_ops,
850 .probe = tegra_hsp_probe,
851 .remove = tegra_hsp_remove,
854 static int __init tegra_hsp_init(void)
856 return platform_driver_register(&tegra_hsp_driver);
858 core_initcall(tegra_hsp_init);