drivers/mailbox/imx-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/firmware/imx/ipc.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mailbox_controller.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/slab.h>
  17
  18 #define IMX_MU_xSR_GIPn(x)      BIT(28 + (3 - (x)))
  19 #define IMX_MU_xSR_RFn(x)       BIT(24 + (3 - (x)))
  20 #define IMX_MU_xSR_TEn(x)       BIT(20 + (3 - (x)))
  21 #define IMX_MU_xSR_BRDIP        BIT(9)
  22
  23 /* General Purpose Interrupt Enable */
  24 #define IMX_MU_xCR_GIEn(x)      BIT(28 + (3 - (x)))
  25 /* Receive Interrupt Enable */
  26 #define IMX_MU_xCR_RIEn(x)      BIT(24 + (3 - (x)))
  27 /* Transmit Interrupt Enable */
  28 #define IMX_MU_xCR_TIEn(x)      BIT(20 + (3 - (x)))
  29 /* General Purpose Interrupt Request */
  30 #define IMX_MU_xCR_GIRn(x)      BIT(16 + (3 - (x)))
  31
  32 #define IMX_MU_CHANS            16
  33 /* TX0/RX0/RXDB[0-3] */
  34 #define IMX_MU_SCU_CHANS        6
  35 #define IMX_MU_CHAN_NAME_SIZE   20
  36
  37 enum imx_mu_chan_type {
  38         IMX_MU_TYPE_TX,         /* Tx */
  39         IMX_MU_TYPE_RX,         /* Rx */
  40         IMX_MU_TYPE_TXDB,       /* Tx doorbell */
  41         IMX_MU_TYPE_RXDB,       /* Rx doorbell */
  42 };
  43
  44 enum imx_mu_xcr {
  45         IMX_MU_CR,
  46         IMX_MU_GCR,
  47         IMX_MU_TCR,
  48         IMX_MU_RCR,
  49         IMX_MU_xCR_MAX,
  50 };
  51
  52 enum imx_mu_xsr {
  53         IMX_MU_SR,
  54         IMX_MU_GSR,
  55         IMX_MU_TSR,
  56         IMX_MU_RSR,
  57 };
  58
  59 struct imx_sc_rpc_msg_max {
  60         struct imx_sc_rpc_msg hdr;
  61         u32 data[7];
  62 };
  63
  64 struct imx_mu_con_priv {
  65         unsigned int            idx;
  66         char                    irq_desc[IMX_MU_CHAN_NAME_SIZE];
  67         enum imx_mu_chan_type   type;
  68         struct mbox_chan        *chan;
  69         struct tasklet_struct   txdb_tasklet;
  70 };
  71
  72 struct imx_mu_priv {
  73         struct device           *dev;
  74         void __iomem            *base;
  75         spinlock_t              xcr_lock; /* control register lock */
  76
  77         struct mbox_controller  mbox;
  78         struct mbox_chan        mbox_chans[IMX_MU_CHANS];
  79
  80         struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
  81         const struct imx_mu_dcfg        *dcfg;
  82         struct clk              *clk;
  83         int                     irq;
  84
  85         u32 xcr[4];
  86
  87         bool                    side_b;
  88 };
  89
  90 struct imx_mu_dcfg {
  91         int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
  92         int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
  93         void (*init)(struct imx_mu_priv *priv);
  94         u32     xTR;            /* Transmit Register0 */
  95         u32     xRR;            /* Receive Register0 */
  96         u32     xSR[4];         /* Status Registers */
  97         u32     xCR[4];         /* Control Registers */
  98 };
  99
 100 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
 101 {
 102         return container_of(mbox, struct imx_mu_priv, mbox);
 103 }
 104
 105 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
 106 {
 107         iowrite32(val, priv->base + offs);
 108 }
 109
 110 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
 111 {
 112         return ioread32(priv->base + offs);
 113 }
 114
 115 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
 116 {
 117         unsigned long flags;
 118         u32 val;
 119
 120         spin_lock_irqsave(&priv->xcr_lock, flags);
 121         val = imx_mu_read(priv, priv->dcfg->xCR[type]);
 122         val &= ~clr;
 123         val |= set;
 124         imx_mu_write(priv, val, priv->dcfg->xCR[type]);
 125         spin_unlock_irqrestore(&priv->xcr_lock, flags);
 126
 127         return val;
 128 }
 129
 130 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
 131                              struct imx_mu_con_priv *cp,
 132                              void *data)
 133 {
 134         u32 *arg = data;
 135
 136         switch (cp->type) {
 137         case IMX_MU_TYPE_TX:
 138                 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
 139                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
 140                 break;
 141         case IMX_MU_TYPE_TXDB:
 142                 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(cp->idx), 0);
 143                 tasklet_schedule(&cp->txdb_tasklet);
 144                 break;
 145         default:
 146                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 147                 return -EINVAL;
 148         }
 149
 150         return 0;
 151 }
 152
 153 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
 154                              struct imx_mu_con_priv *cp)
 155 {
 156         u32 dat;
 157
 158         dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
 159         mbox_chan_received_data(cp->chan, (void *)&dat);
 160
 161         return 0;
 162 }
 163
 164 static int imx_mu_scu_tx(struct imx_mu_priv *priv,
 165                          struct imx_mu_con_priv *cp,
 166                          void *data)
 167 {
 168         struct imx_sc_rpc_msg_max *msg = data;
 169         u32 *arg = data;
 170         int i, ret;
 171         u32 xsr;
 172
 173         switch (cp->type) {
 174         case IMX_MU_TYPE_TX:
 175                 /*
 176                  * msg->hdr.size specifies the number of u32 words while
 177                  * sizeof yields bytes.
 178                  */
 179
 180                 if (msg->hdr.size > sizeof(*msg) / 4) {
 181                         /*
 182                          * The real message size can be different to
 183                          * struct imx_sc_rpc_msg_max size
 184                          */
 185                         dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
 186                         return -EINVAL;
 187                 }
 188
 189                 for (i = 0; i < 4 && i < msg->hdr.size; i++)
 190                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
 191                 for (; i < msg->hdr.size; i++) {
 192                         ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
 193                                                  xsr,
 194                                                  xsr & IMX_MU_xSR_TEn(i % 4),
 195                                                  0, 100);
 196                         if (ret) {
 197                                 dev_err(priv->dev, "Send data index: %d timeout\n", i);
 198                                 return ret;
 199                         }
 200                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);
 201                 }
 202
 203                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(cp->idx), 0);
 204                 break;
 205         default:
 206                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 207                 return -EINVAL;
 208         }
 209
 210         return 0;
 211 }
 212
 213 static int imx_mu_scu_rx(struct imx_mu_priv *priv,
 214                          struct imx_mu_con_priv *cp)
 215 {
 216         struct imx_sc_rpc_msg_max msg;
 217         u32 *data = (u32 *)&msg;
 218         int i, ret;
 219         u32 xsr;
 220
 221         imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(0));
 222         *data++ = imx_mu_read(priv, priv->dcfg->xRR);
 223
 224         if (msg.hdr.size > sizeof(msg) / 4) {
 225                 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
 226                 return -EINVAL;
 227         }
 228
 229         for (i = 1; i < msg.hdr.size; i++) {
 230                 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
 231                                          xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
 232                 if (ret) {
 233                         dev_err(priv->dev, "timeout read idx %d\n", i);
 234                         return ret;
 235                 }
 236                 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
 237         }
 238
 239         imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(0), 0);
 240         mbox_chan_received_data(cp->chan, (void *)&msg);
 241
 242         return 0;
 243 }
 244
 245 static void imx_mu_txdb_tasklet(unsigned long data)
 246 {
 247         struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
 248
 249         mbox_chan_txdone(cp->chan, 0);
 250 }
 251
 252 static irqreturn_t imx_mu_isr(int irq, void *p)
 253 {
 254         struct mbox_chan *chan = p;
 255         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 256         struct imx_mu_con_priv *cp = chan->con_priv;
 257         u32 val, ctrl;
 258
 259         switch (cp->type) {
 260         case IMX_MU_TYPE_TX:
 261                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
 262                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
 263                 val &= IMX_MU_xSR_TEn(cp->idx) &
 264                         (ctrl & IMX_MU_xCR_TIEn(cp->idx));
 265                 break;
 266         case IMX_MU_TYPE_RX:
 267                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
 268                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
 269                 val &= IMX_MU_xSR_RFn(cp->idx) &
 270                         (ctrl & IMX_MU_xCR_RIEn(cp->idx));
 271                 break;
 272         case IMX_MU_TYPE_RXDB:
 273                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GCR]);
 274                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
 275                 val &= IMX_MU_xSR_GIPn(cp->idx) &
 276                         (ctrl & IMX_MU_xCR_GIEn(cp->idx));
 277                 break;
 278         default:
 279                 break;
 280         }
 281
 282         if (!val)
 283                 return IRQ_NONE;
 284
 285         if (val == IMX_MU_xSR_TEn(cp->idx)) {
 286                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
 287                 mbox_chan_txdone(chan, 0);
 288         } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
 289                 priv->dcfg->rx(priv, cp);
 290         } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
 291                 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR[IMX_MU_GSR]);
 292                 mbox_chan_received_data(chan, NULL);
 293         } else {
 294                 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
 295                 return IRQ_NONE;
 296         }
 297
 298         return IRQ_HANDLED;
 299 }
 300
 301 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
 302 {
 303         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 304         struct imx_mu_con_priv *cp = chan->con_priv;
 305
 306         return priv->dcfg->tx(priv, cp, data);
 307 }
 308
 309 static int imx_mu_startup(struct mbox_chan *chan)
 310 {
 311         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 312         struct imx_mu_con_priv *cp = chan->con_priv;
 313         unsigned long irq_flag = IRQF_SHARED;
 314         int ret;
 315
 316         pm_runtime_get_sync(priv->dev);
 317         if (cp->type == IMX_MU_TYPE_TXDB) {
 318                 /* Tx doorbell don't have ACK support */
 319                 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
 320                              (unsigned long)cp);
 321                 return 0;
 322         }
 323
 324         /* IPC MU should be with IRQF_NO_SUSPEND set */
 325         if (!priv->dev->pm_domain)
 326                 irq_flag |= IRQF_NO_SUSPEND;
 327
 328         ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
 329                           cp->irq_desc, chan);
 330         if (ret) {
 331                 dev_err(priv->dev,
 332                         "Unable to acquire IRQ %d\n", priv->irq);
 333                 return ret;
 334         }
 335
 336         switch (cp->type) {
 337         case IMX_MU_TYPE_RX:
 338                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(cp->idx), 0);
 339                 break;
 340         case IMX_MU_TYPE_RXDB:
 341                 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIEn(cp->idx), 0);
 342                 break;
 343         default:
 344                 break;
 345         }
 346
 347         return 0;
 348 }
 349
 350 static void imx_mu_shutdown(struct mbox_chan *chan)
 351 {
 352         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 353         struct imx_mu_con_priv *cp = chan->con_priv;
 354
 355         if (cp->type == IMX_MU_TYPE_TXDB) {
 356                 tasklet_kill(&cp->txdb_tasklet);
 357                 pm_runtime_put_sync(priv->dev);
 358                 return;
 359         }
 360
 361         switch (cp->type) {
 362         case IMX_MU_TYPE_TX:
 363                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(cp->idx));
 364                 break;
 365         case IMX_MU_TYPE_RX:
 366                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(cp->idx));
 367                 break;
 368         case IMX_MU_TYPE_RXDB:
 369                 imx_mu_xcr_rmw(priv, IMX_MU_GCR, 0, IMX_MU_xCR_GIEn(cp->idx));
 370                 break;
 371         default:
 372                 break;
 373         }
 374
 375         free_irq(priv->irq, chan);
 376         pm_runtime_put_sync(priv->dev);
 377 }
 378
 379 static const struct mbox_chan_ops imx_mu_ops = {
 380         .send_data = imx_mu_send_data,
 381         .startup = imx_mu_startup,
 382         .shutdown = imx_mu_shutdown,
 383 };
 384
 385 static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
 386                                           const struct of_phandle_args *sp)
 387 {
 388         u32 type, idx, chan;
 389
 390         if (sp->args_count != 2) {
 391                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 392                 return ERR_PTR(-EINVAL);
 393         }
 394
 395         type = sp->args[0]; /* channel type */
 396         idx = sp->args[1]; /* index */
 397
 398         switch (type) {
 399         case IMX_MU_TYPE_TX:
 400         case IMX_MU_TYPE_RX:
 401                 if (idx != 0)
 402                         dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
 403                 chan = type;
 404                 break;
 405         case IMX_MU_TYPE_RXDB:
 406                 chan = 2 + idx;
 407                 break;
 408         default:
 409                 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
 410                 return ERR_PTR(-EINVAL);
 411         }
 412
 413         if (chan >= mbox->num_chans) {
 414                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 415                 return ERR_PTR(-EINVAL);
 416         }
 417
 418         return &mbox->chans[chan];
 419 }
 420
 421 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
 422                                        const struct of_phandle_args *sp)
 423 {
 424         u32 type, idx, chan;
 425
 426         if (sp->args_count != 2) {
 427                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 428                 return ERR_PTR(-EINVAL);
 429         }
 430
 431         type = sp->args[0]; /* channel type */
 432         idx = sp->args[1]; /* index */
 433         chan = type * 4 + idx;
 434
 435         if (chan >= mbox->num_chans) {
 436                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 437                 return ERR_PTR(-EINVAL);
 438         }
 439
 440         return &mbox->chans[chan];
 441 }
 442
 443 static void imx_mu_init_generic(struct imx_mu_priv *priv)
 444 {
 445         unsigned int i;
 446
 447         for (i = 0; i < IMX_MU_CHANS; i++) {
 448                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 449
 450                 cp->idx = i % 4;
 451                 cp->type = i >> 2;
 452                 cp->chan = &priv->mbox_chans[i];
 453                 priv->mbox_chans[i].con_priv = cp;
 454                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 455                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 456         }
 457
 458         priv->mbox.num_chans = IMX_MU_CHANS;
 459         priv->mbox.of_xlate = imx_mu_xlate;
 460
 461         if (priv->side_b)
 462                 return;
 463
 464         /* Set default MU configuration */
 465         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 466                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 467 }
 468
 469 static void imx_mu_init_scu(struct imx_mu_priv *priv)
 470 {
 471         unsigned int i;
 472
 473         for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
 474                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 475
 476                 cp->idx = i < 2 ? 0 : i - 2;
 477                 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
 478                 cp->chan = &priv->mbox_chans[i];
 479                 priv->mbox_chans[i].con_priv = cp;
 480                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 481                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 482         }
 483
 484         priv->mbox.num_chans = IMX_MU_SCU_CHANS;
 485         priv->mbox.of_xlate = imx_mu_scu_xlate;
 486
 487         /* Set default MU configuration */
 488         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 489                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 490 }
 491
 492 static int imx_mu_probe(struct platform_device *pdev)
 493 {
 494         struct device *dev = &pdev->dev;
 495         struct device_node *np = dev->of_node;
 496         struct imx_mu_priv *priv;
 497         const struct imx_mu_dcfg *dcfg;
 498         int ret;
 499
 500         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 501         if (!priv)
 502                 return -ENOMEM;
 503
 504         priv->dev = dev;
 505
 506         priv->base = devm_platform_ioremap_resource(pdev, 0);
 507         if (IS_ERR(priv->base))
 508                 return PTR_ERR(priv->base);
 509
 510         priv->irq = platform_get_irq(pdev, 0);
 511         if (priv->irq < 0)
 512                 return priv->irq;
 513
 514         dcfg = of_device_get_match_data(dev);
 515         if (!dcfg)
 516                 return -EINVAL;
 517         priv->dcfg = dcfg;
 518
 519         priv->clk = devm_clk_get(dev, NULL);
 520         if (IS_ERR(priv->clk)) {
 521                 if (PTR_ERR(priv->clk) != -ENOENT)
 522                         return PTR_ERR(priv->clk);
 523
 524                 priv->clk = NULL;
 525         }
 526
 527         ret = clk_prepare_enable(priv->clk);
 528         if (ret) {
 529                 dev_err(dev, "Failed to enable clock\n");
 530                 return ret;
 531         }
 532
 533         priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
 534
 535         priv->dcfg->init(priv);
 536
 537         spin_lock_init(&priv->xcr_lock);
 538
 539         priv->mbox.dev = dev;
 540         priv->mbox.ops = &imx_mu_ops;
 541         priv->mbox.chans = priv->mbox_chans;
 542         priv->mbox.txdone_irq = true;
 543
 544         platform_set_drvdata(pdev, priv);
 545
 546         ret = devm_mbox_controller_register(dev, &priv->mbox);
 547         if (ret) {
 548                 clk_disable_unprepare(priv->clk);
 549                 return ret;
 550         }
 551
 552         pm_runtime_enable(dev);
 553
 554         ret = pm_runtime_get_sync(dev);
 555         if (ret < 0) {
 556                 pm_runtime_put_noidle(dev);
 557                 goto disable_runtime_pm;
 558         }
 559
 560         ret = pm_runtime_put_sync(dev);
 561         if (ret < 0)
 562                 goto disable_runtime_pm;
 563
 564         clk_disable_unprepare(priv->clk);
 565
 566         return 0;
 567
 568 disable_runtime_pm:
 569         pm_runtime_disable(dev);
 570         clk_disable_unprepare(priv->clk);
 571         return ret;
 572 }
 573
 574 static int imx_mu_remove(struct platform_device *pdev)
 575 {
 576         struct imx_mu_priv *priv = platform_get_drvdata(pdev);
 577
 578         pm_runtime_disable(priv->dev);
 579
 580         return 0;
 581 }
 582
 583 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
 584         .tx     = imx_mu_generic_tx,
 585         .rx     = imx_mu_generic_rx,
 586         .init   = imx_mu_init_generic,
 587         .xTR    = 0x0,
 588         .xRR    = 0x10,
 589         .xSR    = {0x20, 0x20, 0x20, 0x20},
 590         .xCR    = {0x24, 0x24, 0x24, 0x24},
 591 };
 592
 593 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
 594         .tx     = imx_mu_generic_tx,
 595         .rx     = imx_mu_generic_rx,
 596         .init   = imx_mu_init_generic,
 597         .xTR    = 0x20,
 598         .xRR    = 0x40,
 599         .xSR    = {0x60, 0x60, 0x60, 0x60},
 600         .xCR    = {0x64, 0x64, 0x64, 0x64},
 601 };
 602
 603 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
 604         .tx     = imx_mu_scu_tx,
 605         .rx     = imx_mu_scu_rx,
 606         .init   = imx_mu_init_scu,
 607         .xTR    = 0x0
 608         .xRR    = 0x10
 609         .xSR    = {0x20, 0x20, 0x20, 0x20},
 610         .xCR    = {0x24, 0x24, 0x24, 0x24},
 611 };
 612
 613 static const struct of_device_id imx_mu_dt_ids[] = {
 614         { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
 615         { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
 616         { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
 617         { },
 618 };
 619 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
 620
 621 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
 622 {
 623         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 624         int i;
 625
 626         if (!priv->clk) {
 627                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
 628                         priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
 629         }
 630
 631         return 0;
 632 }
 633
 634 static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
 635 {
 636         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 637         int i;
 638
 639         /*
 640          * ONLY restore MU when context lost, the TIE could
 641          * be set during noirq resume as there is MU data
 642          * communication going on, and restore the saved
 643          * value will overwrite the TIE and cause MU data
 644          * send failed, may lead to system freeze. This issue
 645          * is observed by testing freeze mode suspend.
 646          */
 647         if (!imx_mu_read(priv, priv->dcfg->xCR[0]) && !priv->clk) {
 648                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
 649                         imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
 650         }
 651
 652         return 0;
 653 }
 654
 655 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
 656 {
 657         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 658
 659         clk_disable_unprepare(priv->clk);
 660
 661         return 0;
 662 }
 663
 664 static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
 665 {
 666         struct imx_mu_priv *priv = dev_get_drvdata(dev);
 667         int ret;
 668
 669         ret = clk_prepare_enable(priv->clk);
 670         if (ret)
 671                 dev_err(dev, "failed to enable clock\n");
 672
 673         return ret;
 674 }
 675
 676 static const struct dev_pm_ops imx_mu_pm_ops = {
 677         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
 678                                       imx_mu_resume_noirq)
 679         SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
 680                            imx_mu_runtime_resume, NULL)
 681 };
 682
 683 static struct platform_driver imx_mu_driver = {
 684         .probe          = imx_mu_probe,
 685         .remove         = imx_mu_remove,
 686         .driver = {
 687                 .name   = "imx_mu",
 688                 .of_match_table = imx_mu_dt_ids,
 689                 .pm = &imx_mu_pm_ops,
 690         },
 691 };
 692 module_platform_driver(imx_mu_driver);
 693
 694 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
 695 MODULE_DESCRIPTION("Message Unit driver for i.MX");
 696 MODULE_LICENSE("GPL v2");