1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
7 #include <linux/firmware/imx/ipc.h>
8 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/mailbox_controller.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/slab.h>
18 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
19 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
20 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
21 #define IMX_MU_xSR_BRDIP BIT(9)
23 /* General Purpose Interrupt Enable */
24 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
25 /* Receive Interrupt Enable */
26 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
27 /* Transmit Interrupt Enable */
28 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
29 /* General Purpose Interrupt Request */
30 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
32 #define IMX_MU_CHANS 16
33 /* TX0/RX0/RXDB[0-3] */
34 #define IMX_MU_SCU_CHANS 6
35 #define IMX_MU_CHAN_NAME_SIZE 20
37 enum imx_mu_chan_type {
38 IMX_MU_TYPE_TX, /* Tx */
39 IMX_MU_TYPE_RX, /* Rx */
40 IMX_MU_TYPE_TXDB, /* Tx doorbell */
41 IMX_MU_TYPE_RXDB, /* Rx doorbell */
44 struct imx_sc_rpc_msg_max {
45 struct imx_sc_rpc_msg hdr;
49 struct imx_mu_con_priv {
51 char irq_desc[IMX_MU_CHAN_NAME_SIZE];
52 enum imx_mu_chan_type type;
53 struct mbox_chan *chan;
54 struct tasklet_struct txdb_tasklet;
60 spinlock_t xcr_lock; /* control register lock */
62 struct mbox_controller mbox;
63 struct mbox_chan mbox_chans[IMX_MU_CHANS];
65 struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
66 const struct imx_mu_dcfg *dcfg;
76 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
77 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
78 void (*init)(struct imx_mu_priv *priv);
79 u32 xTR[4]; /* Transmit Registers */
80 u32 xRR[4]; /* Receive Registers */
81 u32 xSR; /* Status Register */
82 u32 xCR; /* Control Register */
85 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
87 return container_of(mbox, struct imx_mu_priv, mbox);
90 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
92 iowrite32(val, priv->base + offs);
95 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
97 return ioread32(priv->base + offs);
100 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
105 spin_lock_irqsave(&priv->xcr_lock, flags);
106 val = imx_mu_read(priv, priv->dcfg->xCR);
109 imx_mu_write(priv, val, priv->dcfg->xCR);
110 spin_unlock_irqrestore(&priv->xcr_lock, flags);
115 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
116 struct imx_mu_con_priv *cp,
123 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
124 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
126 case IMX_MU_TYPE_TXDB:
127 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
128 tasklet_schedule(&cp->txdb_tasklet);
131 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
138 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
139 struct imx_mu_con_priv *cp)
143 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
144 mbox_chan_received_data(cp->chan, (void *)&dat);
149 static int imx_mu_scu_tx(struct imx_mu_priv *priv,
150 struct imx_mu_con_priv *cp,
153 struct imx_sc_rpc_msg_max *msg = data;
161 * msg->hdr.size specifies the number of u32 words while
162 * sizeof yields bytes.
165 if (msg->hdr.size > sizeof(*msg) / 4) {
167 * The real message size can be different to
168 * struct imx_sc_rpc_msg_max size
170 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
174 for (i = 0; i < 4 && i < msg->hdr.size; i++)
175 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
176 for (; i < msg->hdr.size; i++) {
177 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
179 xsr & IMX_MU_xSR_TEn(i % 4),
182 dev_err(priv->dev, "Send data index: %d timeout\n", i);
185 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
188 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
191 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
198 static int imx_mu_scu_rx(struct imx_mu_priv *priv,
199 struct imx_mu_con_priv *cp)
201 struct imx_sc_rpc_msg_max msg;
202 u32 *data = (u32 *)&msg;
206 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
207 *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
209 if (msg.hdr.size > sizeof(msg) / 4) {
210 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
214 for (i = 1; i < msg.hdr.size; i++) {
215 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
216 xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
218 dev_err(priv->dev, "timeout read idx %d\n", i);
221 *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
224 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
225 mbox_chan_received_data(cp->chan, (void *)&msg);
230 static void imx_mu_txdb_tasklet(unsigned long data)
232 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
234 mbox_chan_txdone(cp->chan, 0);
237 static irqreturn_t imx_mu_isr(int irq, void *p)
239 struct mbox_chan *chan = p;
240 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
241 struct imx_mu_con_priv *cp = chan->con_priv;
244 ctrl = imx_mu_read(priv, priv->dcfg->xCR);
245 val = imx_mu_read(priv, priv->dcfg->xSR);
249 val &= IMX_MU_xSR_TEn(cp->idx) &
250 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
253 val &= IMX_MU_xSR_RFn(cp->idx) &
254 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
256 case IMX_MU_TYPE_RXDB:
257 val &= IMX_MU_xSR_GIPn(cp->idx) &
258 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
267 if (val == IMX_MU_xSR_TEn(cp->idx)) {
268 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
269 mbox_chan_txdone(chan, 0);
270 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
271 priv->dcfg->rx(priv, cp);
272 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
273 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
274 mbox_chan_received_data(chan, NULL);
276 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
283 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
285 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
286 struct imx_mu_con_priv *cp = chan->con_priv;
288 return priv->dcfg->tx(priv, cp, data);
291 static int imx_mu_startup(struct mbox_chan *chan)
293 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
294 struct imx_mu_con_priv *cp = chan->con_priv;
297 pm_runtime_get_sync(priv->dev);
298 if (cp->type == IMX_MU_TYPE_TXDB) {
299 /* Tx doorbell don't have ACK support */
300 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
305 ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED |
306 IRQF_NO_SUSPEND, cp->irq_desc, chan);
309 "Unable to acquire IRQ %d\n", priv->irq);
315 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
317 case IMX_MU_TYPE_RXDB:
318 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
327 static void imx_mu_shutdown(struct mbox_chan *chan)
329 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
330 struct imx_mu_con_priv *cp = chan->con_priv;
332 if (cp->type == IMX_MU_TYPE_TXDB) {
333 tasklet_kill(&cp->txdb_tasklet);
334 pm_runtime_put_sync(priv->dev);
340 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
343 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
345 case IMX_MU_TYPE_RXDB:
346 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
352 free_irq(priv->irq, chan);
353 pm_runtime_put_sync(priv->dev);
356 static const struct mbox_chan_ops imx_mu_ops = {
357 .send_data = imx_mu_send_data,
358 .startup = imx_mu_startup,
359 .shutdown = imx_mu_shutdown,
362 static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
363 const struct of_phandle_args *sp)
367 if (sp->args_count != 2) {
368 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
369 return ERR_PTR(-EINVAL);
372 type = sp->args[0]; /* channel type */
373 idx = sp->args[1]; /* index */
379 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
382 case IMX_MU_TYPE_RXDB:
386 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
387 return ERR_PTR(-EINVAL);
390 if (chan >= mbox->num_chans) {
391 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
392 return ERR_PTR(-EINVAL);
395 return &mbox->chans[chan];
398 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
399 const struct of_phandle_args *sp)
403 if (sp->args_count != 2) {
404 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
405 return ERR_PTR(-EINVAL);
408 type = sp->args[0]; /* channel type */
409 idx = sp->args[1]; /* index */
410 chan = type * 4 + idx;
412 if (chan >= mbox->num_chans) {
413 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
414 return ERR_PTR(-EINVAL);
417 return &mbox->chans[chan];
420 static void imx_mu_init_generic(struct imx_mu_priv *priv)
424 for (i = 0; i < IMX_MU_CHANS; i++) {
425 struct imx_mu_con_priv *cp = &priv->con_priv[i];
429 cp->chan = &priv->mbox_chans[i];
430 priv->mbox_chans[i].con_priv = cp;
431 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
432 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
435 priv->mbox.num_chans = IMX_MU_CHANS;
436 priv->mbox.of_xlate = imx_mu_xlate;
441 /* Set default MU configuration */
442 imx_mu_write(priv, 0, priv->dcfg->xCR);
445 static void imx_mu_init_scu(struct imx_mu_priv *priv)
449 for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
450 struct imx_mu_con_priv *cp = &priv->con_priv[i];
452 cp->idx = i < 2 ? 0 : i - 2;
453 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
454 cp->chan = &priv->mbox_chans[i];
455 priv->mbox_chans[i].con_priv = cp;
456 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
457 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
460 priv->mbox.num_chans = IMX_MU_SCU_CHANS;
461 priv->mbox.of_xlate = imx_mu_scu_xlate;
463 /* Set default MU configuration */
464 imx_mu_write(priv, 0, priv->dcfg->xCR);
467 static int imx_mu_probe(struct platform_device *pdev)
469 struct device *dev = &pdev->dev;
470 struct device_node *np = dev->of_node;
471 struct imx_mu_priv *priv;
472 const struct imx_mu_dcfg *dcfg;
475 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
481 priv->base = devm_platform_ioremap_resource(pdev, 0);
482 if (IS_ERR(priv->base))
483 return PTR_ERR(priv->base);
485 priv->irq = platform_get_irq(pdev, 0);
489 dcfg = of_device_get_match_data(dev);
494 priv->clk = devm_clk_get(dev, NULL);
495 if (IS_ERR(priv->clk)) {
496 if (PTR_ERR(priv->clk) != -ENOENT)
497 return PTR_ERR(priv->clk);
502 ret = clk_prepare_enable(priv->clk);
504 dev_err(dev, "Failed to enable clock\n");
508 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
510 priv->dcfg->init(priv);
512 spin_lock_init(&priv->xcr_lock);
514 priv->mbox.dev = dev;
515 priv->mbox.ops = &imx_mu_ops;
516 priv->mbox.chans = priv->mbox_chans;
517 priv->mbox.txdone_irq = true;
519 platform_set_drvdata(pdev, priv);
521 ret = devm_mbox_controller_register(dev, &priv->mbox);
523 clk_disable_unprepare(priv->clk);
527 pm_runtime_enable(dev);
529 ret = pm_runtime_get_sync(dev);
531 pm_runtime_put_noidle(dev);
532 goto disable_runtime_pm;
535 ret = pm_runtime_put_sync(dev);
537 goto disable_runtime_pm;
539 clk_disable_unprepare(priv->clk);
544 pm_runtime_disable(dev);
545 clk_disable_unprepare(priv->clk);
549 static int imx_mu_remove(struct platform_device *pdev)
551 struct imx_mu_priv *priv = platform_get_drvdata(pdev);
553 pm_runtime_disable(priv->dev);
558 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
559 .tx = imx_mu_generic_tx,
560 .rx = imx_mu_generic_rx,
561 .init = imx_mu_init_generic,
562 .xTR = {0x0, 0x4, 0x8, 0xc},
563 .xRR = {0x10, 0x14, 0x18, 0x1c},
568 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
569 .tx = imx_mu_generic_tx,
570 .rx = imx_mu_generic_rx,
571 .init = imx_mu_init_generic,
572 .xTR = {0x20, 0x24, 0x28, 0x2c},
573 .xRR = {0x40, 0x44, 0x48, 0x4c},
578 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
581 .init = imx_mu_init_scu,
582 .xTR = {0x0, 0x4, 0x8, 0xc},
583 .xRR = {0x10, 0x14, 0x18, 0x1c},
588 static const struct of_device_id imx_mu_dt_ids[] = {
589 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
590 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
591 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
594 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
596 static int imx_mu_suspend_noirq(struct device *dev)
598 struct imx_mu_priv *priv = dev_get_drvdata(dev);
601 priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
606 static int imx_mu_resume_noirq(struct device *dev)
608 struct imx_mu_priv *priv = dev_get_drvdata(dev);
611 * ONLY restore MU when context lost, the TIE could
612 * be set during noirq resume as there is MU data
613 * communication going on, and restore the saved
614 * value will overwrite the TIE and cause MU data
615 * send failed, may lead to system freeze. This issue
616 * is observed by testing freeze mode suspend.
618 if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
619 imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
624 static int imx_mu_runtime_suspend(struct device *dev)
626 struct imx_mu_priv *priv = dev_get_drvdata(dev);
628 clk_disable_unprepare(priv->clk);
633 static int imx_mu_runtime_resume(struct device *dev)
635 struct imx_mu_priv *priv = dev_get_drvdata(dev);
638 ret = clk_prepare_enable(priv->clk);
640 dev_err(dev, "failed to enable clock\n");
645 static const struct dev_pm_ops imx_mu_pm_ops = {
646 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
648 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
649 imx_mu_runtime_resume, NULL)
652 static struct platform_driver imx_mu_driver = {
653 .probe = imx_mu_probe,
654 .remove = imx_mu_remove,
657 .of_match_table = imx_mu_dt_ids,
658 .pm = &imx_mu_pm_ops,
661 module_platform_driver(imx_mu_driver);
663 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
664 MODULE_DESCRIPTION("Message Unit driver for i.MX");
665 MODULE_LICENSE("GPL v2");