drivers/mailbox/imx-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/firmware/imx/ipc.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mailbox_controller.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/slab.h>
  16
  17 #define IMX_MU_xSR_GIPn(x)      BIT(28 + (3 - (x)))
  18 #define IMX_MU_xSR_RFn(x)       BIT(24 + (3 - (x)))
  19 #define IMX_MU_xSR_TEn(x)       BIT(20 + (3 - (x)))
  20 #define IMX_MU_xSR_BRDIP        BIT(9)
  21
  22 /* General Purpose Interrupt Enable */
  23 #define IMX_MU_xCR_GIEn(x)      BIT(28 + (3 - (x)))
  24 /* Receive Interrupt Enable */
  25 #define IMX_MU_xCR_RIEn(x)      BIT(24 + (3 - (x)))
  26 /* Transmit Interrupt Enable */
  27 #define IMX_MU_xCR_TIEn(x)      BIT(20 + (3 - (x)))
  28 /* General Purpose Interrupt Request */
  29 #define IMX_MU_xCR_GIRn(x)      BIT(16 + (3 - (x)))
  30
  31 #define IMX_MU_CHANS            16
  32 /* TX0/RX0/RXDB[0-3] */
  33 #define IMX_MU_SCU_CHANS        6
  34 #define IMX_MU_CHAN_NAME_SIZE   20
  35
  36 enum imx_mu_chan_type {
  37         IMX_MU_TYPE_TX,         /* Tx */
  38         IMX_MU_TYPE_RX,         /* Rx */
  39         IMX_MU_TYPE_TXDB,       /* Tx doorbell */
  40         IMX_MU_TYPE_RXDB,       /* Rx doorbell */
  41 };
  42
  43 struct imx_sc_rpc_msg_max {
  44         struct imx_sc_rpc_msg hdr;
  45         u32 data[7];
  46 };
  47
  48 struct imx_mu_con_priv {
  49         unsigned int            idx;
  50         char                    irq_desc[IMX_MU_CHAN_NAME_SIZE];
  51         enum imx_mu_chan_type   type;
  52         struct mbox_chan        *chan;
  53         struct tasklet_struct   txdb_tasklet;
  54 };
  55
  56 struct imx_mu_priv {
  57         struct device           *dev;
  58         void __iomem            *base;
  59         spinlock_t              xcr_lock; /* control register lock */
  60
  61         struct mbox_controller  mbox;
  62         struct mbox_chan        mbox_chans[IMX_MU_CHANS];
  63
  64         struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
  65         const struct imx_mu_dcfg        *dcfg;
  66         struct clk              *clk;
  67         int                     irq;
  68
  69         bool                    side_b;
  70 };
  71
  72 struct imx_mu_dcfg {
  73         int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
  74         int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
  75         void (*init)(struct imx_mu_priv *priv);
  76         u32     xTR[4];         /* Transmit Registers */
  77         u32     xRR[4];         /* Receive Registers */
  78         u32     xSR;            /* Status Register */
  79         u32     xCR;            /* Control Register */
  80 };
  81
  82 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
  83 {
  84         return container_of(mbox, struct imx_mu_priv, mbox);
  85 }
  86
  87 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
  88 {
  89         iowrite32(val, priv->base + offs);
  90 }
  91
  92 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
  93 {
  94         return ioread32(priv->base + offs);
  95 }
  96
  97 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
  98 {
  99         unsigned long flags;
 100         u32 val;
 101
 102         spin_lock_irqsave(&priv->xcr_lock, flags);
 103         val = imx_mu_read(priv, priv->dcfg->xCR);
 104         val &= ~clr;
 105         val |= set;
 106         imx_mu_write(priv, val, priv->dcfg->xCR);
 107         spin_unlock_irqrestore(&priv->xcr_lock, flags);
 108
 109         return val;
 110 }
 111
 112 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
 113                              struct imx_mu_con_priv *cp,
 114                              void *data)
 115 {
 116         u32 *arg = data;
 117
 118         switch (cp->type) {
 119         case IMX_MU_TYPE_TX:
 120                 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
 121                 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
 122                 break;
 123         case IMX_MU_TYPE_TXDB:
 124                 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
 125                 tasklet_schedule(&cp->txdb_tasklet);
 126                 break;
 127         default:
 128                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 129                 return -EINVAL;
 130         }
 131
 132         return 0;
 133 }
 134
 135 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
 136                              struct imx_mu_con_priv *cp)
 137 {
 138         u32 dat;
 139
 140         dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
 141         mbox_chan_received_data(cp->chan, (void *)&dat);
 142
 143         return 0;
 144 }
 145
 146 static int imx_mu_scu_tx(struct imx_mu_priv *priv,
 147                          struct imx_mu_con_priv *cp,
 148                          void *data)
 149 {
 150         struct imx_sc_rpc_msg_max *msg = data;
 151         u32 *arg = data;
 152         int i, ret;
 153         u32 xsr;
 154
 155         switch (cp->type) {
 156         case IMX_MU_TYPE_TX:
 157                 if (msg->hdr.size > sizeof(*msg)) {
 158                         /*
 159                          * The real message size can be different to
 160                          * struct imx_sc_rpc_msg_max size
 161                          */
 162                         dev_err(priv->dev, "Exceed max msg size (%zu) on TX, got: %i\n", sizeof(*msg), msg->hdr.size);
 163                         return -EINVAL;
 164                 }
 165
 166                 for (i = 0; i < 4 && i < msg->hdr.size; i++)
 167                         imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
 168                 for (; i < msg->hdr.size; i++) {
 169                         ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
 170                                                  xsr,
 171                                                  xsr & IMX_MU_xSR_TEn(i % 4),
 172                                                  0, 100);
 173                         if (ret) {
 174                                 dev_err(priv->dev, "Send data index: %d timeout\n", i);
 175                                 return ret;
 176                         }
 177                         imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
 178                 }
 179
 180                 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
 181                 break;
 182         default:
 183                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 184                 return -EINVAL;
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int imx_mu_scu_rx(struct imx_mu_priv *priv,
 191                          struct imx_mu_con_priv *cp)
 192 {
 193         struct imx_sc_rpc_msg_max msg;
 194         u32 *data = (u32 *)&msg;
 195         int i, ret;
 196         u32 xsr;
 197
 198         imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
 199         *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
 200
 201         if (msg.hdr.size > sizeof(msg)) {
 202                 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
 203                         sizeof(msg), msg.hdr.size);
 204                 return -EINVAL;
 205         }
 206
 207         for (i = 1; i < msg.hdr.size; i++) {
 208                 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
 209                                          xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
 210                 if (ret) {
 211                         dev_err(priv->dev, "timeout read idx %d\n", i);
 212                         return ret;
 213                 }
 214                 *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
 215         }
 216
 217         imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
 218         mbox_chan_received_data(cp->chan, (void *)&msg);
 219
 220         return 0;
 221 }
 222
 223 static void imx_mu_txdb_tasklet(unsigned long data)
 224 {
 225         struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
 226
 227         mbox_chan_txdone(cp->chan, 0);
 228 }
 229
 230 static irqreturn_t imx_mu_isr(int irq, void *p)
 231 {
 232         struct mbox_chan *chan = p;
 233         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 234         struct imx_mu_con_priv *cp = chan->con_priv;
 235         u32 val, ctrl;
 236
 237         ctrl = imx_mu_read(priv, priv->dcfg->xCR);
 238         val = imx_mu_read(priv, priv->dcfg->xSR);
 239
 240         switch (cp->type) {
 241         case IMX_MU_TYPE_TX:
 242                 val &= IMX_MU_xSR_TEn(cp->idx) &
 243                         (ctrl & IMX_MU_xCR_TIEn(cp->idx));
 244                 break;
 245         case IMX_MU_TYPE_RX:
 246                 val &= IMX_MU_xSR_RFn(cp->idx) &
 247                         (ctrl & IMX_MU_xCR_RIEn(cp->idx));
 248                 break;
 249         case IMX_MU_TYPE_RXDB:
 250                 val &= IMX_MU_xSR_GIPn(cp->idx) &
 251                         (ctrl & IMX_MU_xCR_GIEn(cp->idx));
 252                 break;
 253         default:
 254                 break;
 255         }
 256
 257         if (!val)
 258                 return IRQ_NONE;
 259
 260         if (val == IMX_MU_xSR_TEn(cp->idx)) {
 261                 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
 262                 mbox_chan_txdone(chan, 0);
 263         } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
 264                 priv->dcfg->rx(priv, cp);
 265         } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
 266                 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
 267                 mbox_chan_received_data(chan, NULL);
 268         } else {
 269                 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
 270                 return IRQ_NONE;
 271         }
 272
 273         return IRQ_HANDLED;
 274 }
 275
 276 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
 277 {
 278         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 279         struct imx_mu_con_priv *cp = chan->con_priv;
 280
 281         return priv->dcfg->tx(priv, cp, data);
 282 }
 283
 284 static int imx_mu_startup(struct mbox_chan *chan)
 285 {
 286         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 287         struct imx_mu_con_priv *cp = chan->con_priv;
 288         int ret;
 289
 290         if (cp->type == IMX_MU_TYPE_TXDB) {
 291                 /* Tx doorbell don't have ACK support */
 292                 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
 293                              (unsigned long)cp);
 294                 return 0;
 295         }
 296
 297         ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED |
 298                           IRQF_NO_SUSPEND, cp->irq_desc, chan);
 299         if (ret) {
 300                 dev_err(priv->dev,
 301                         "Unable to acquire IRQ %d\n", priv->irq);
 302                 return ret;
 303         }
 304
 305         switch (cp->type) {
 306         case IMX_MU_TYPE_RX:
 307                 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
 308                 break;
 309         case IMX_MU_TYPE_RXDB:
 310                 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
 311                 break;
 312         default:
 313                 break;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static void imx_mu_shutdown(struct mbox_chan *chan)
 320 {
 321         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 322         struct imx_mu_con_priv *cp = chan->con_priv;
 323
 324         if (cp->type == IMX_MU_TYPE_TXDB) {
 325                 tasklet_kill(&cp->txdb_tasklet);
 326                 return;
 327         }
 328
 329         switch (cp->type) {
 330         case IMX_MU_TYPE_TX:
 331                 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
 332                 break;
 333         case IMX_MU_TYPE_RX:
 334                 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
 335                 break;
 336         case IMX_MU_TYPE_RXDB:
 337                 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
 338                 break;
 339         default:
 340                 break;
 341         }
 342
 343         free_irq(priv->irq, chan);
 344 }
 345
 346 static const struct mbox_chan_ops imx_mu_ops = {
 347         .send_data = imx_mu_send_data,
 348         .startup = imx_mu_startup,
 349         .shutdown = imx_mu_shutdown,
 350 };
 351
 352 static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
 353                                           const struct of_phandle_args *sp)
 354 {
 355         u32 type, idx, chan;
 356
 357         if (sp->args_count != 2) {
 358                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 359                 return ERR_PTR(-EINVAL);
 360         }
 361
 362         type = sp->args[0]; /* channel type */
 363         idx = sp->args[1]; /* index */
 364
 365         switch (type) {
 366         case IMX_MU_TYPE_TX:
 367         case IMX_MU_TYPE_RX:
 368                 if (idx != 0)
 369                         dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
 370                 chan = type;
 371                 break;
 372         case IMX_MU_TYPE_RXDB:
 373                 chan = 2 + idx;
 374                 break;
 375         default:
 376                 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
 377                 return NULL;
 378         }
 379
 380         if (chan >= mbox->num_chans) {
 381                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 382                 return ERR_PTR(-EINVAL);
 383         }
 384
 385         return &mbox->chans[chan];
 386 }
 387
 388 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
 389                                        const struct of_phandle_args *sp)
 390 {
 391         u32 type, idx, chan;
 392
 393         if (sp->args_count != 2) {
 394                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 395                 return ERR_PTR(-EINVAL);
 396         }
 397
 398         type = sp->args[0]; /* channel type */
 399         idx = sp->args[1]; /* index */
 400         chan = type * 4 + idx;
 401
 402         if (chan >= mbox->num_chans) {
 403                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 404                 return ERR_PTR(-EINVAL);
 405         }
 406
 407         return &mbox->chans[chan];
 408 }
 409
 410 static void imx_mu_init_generic(struct imx_mu_priv *priv)
 411 {
 412         unsigned int i;
 413
 414         for (i = 0; i < IMX_MU_CHANS; i++) {
 415                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 416
 417                 cp->idx = i % 4;
 418                 cp->type = i >> 2;
 419                 cp->chan = &priv->mbox_chans[i];
 420                 priv->mbox_chans[i].con_priv = cp;
 421                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 422                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 423         }
 424
 425         priv->mbox.num_chans = IMX_MU_CHANS;
 426         priv->mbox.of_xlate = imx_mu_xlate;
 427
 428         if (priv->side_b)
 429                 return;
 430
 431         /* Set default MU configuration */
 432         imx_mu_write(priv, 0, priv->dcfg->xCR);
 433 }
 434
 435 static void imx_mu_init_scu(struct imx_mu_priv *priv)
 436 {
 437         unsigned int i;
 438
 439         for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
 440                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 441
 442                 cp->idx = i < 2 ? 0 : i - 2;
 443                 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
 444                 cp->chan = &priv->mbox_chans[i];
 445                 priv->mbox_chans[i].con_priv = cp;
 446                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 447                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 448         }
 449
 450         priv->mbox.num_chans = IMX_MU_SCU_CHANS;
 451         priv->mbox.of_xlate = imx_mu_scu_xlate;
 452
 453         /* Set default MU configuration */
 454         imx_mu_write(priv, 0, priv->dcfg->xCR);
 455 }
 456
 457 static int imx_mu_probe(struct platform_device *pdev)
 458 {
 459         struct device *dev = &pdev->dev;
 460         struct device_node *np = dev->of_node;
 461         struct imx_mu_priv *priv;
 462         const struct imx_mu_dcfg *dcfg;
 463         int ret;
 464
 465         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 466         if (!priv)
 467                 return -ENOMEM;
 468
 469         priv->dev = dev;
 470
 471         priv->base = devm_platform_ioremap_resource(pdev, 0);
 472         if (IS_ERR(priv->base))
 473                 return PTR_ERR(priv->base);
 474
 475         priv->irq = platform_get_irq(pdev, 0);
 476         if (priv->irq < 0)
 477                 return priv->irq;
 478
 479         dcfg = of_device_get_match_data(dev);
 480         if (!dcfg)
 481                 return -EINVAL;
 482         priv->dcfg = dcfg;
 483
 484         priv->clk = devm_clk_get(dev, NULL);
 485         if (IS_ERR(priv->clk)) {
 486                 if (PTR_ERR(priv->clk) != -ENOENT)
 487                         return PTR_ERR(priv->clk);
 488
 489                 priv->clk = NULL;
 490         }
 491
 492         ret = clk_prepare_enable(priv->clk);
 493         if (ret) {
 494                 dev_err(dev, "Failed to enable clock\n");
 495                 return ret;
 496         }
 497
 498         priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
 499
 500         priv->dcfg->init(priv);
 501
 502         spin_lock_init(&priv->xcr_lock);
 503
 504         priv->mbox.dev = dev;
 505         priv->mbox.ops = &imx_mu_ops;
 506         priv->mbox.chans = priv->mbox_chans;
 507         priv->mbox.txdone_irq = true;
 508
 509         platform_set_drvdata(pdev, priv);
 510
 511         return devm_mbox_controller_register(dev, &priv->mbox);
 512 }
 513
 514 static int imx_mu_remove(struct platform_device *pdev)
 515 {
 516         struct imx_mu_priv *priv = platform_get_drvdata(pdev);
 517
 518         clk_disable_unprepare(priv->clk);
 519
 520         return 0;
 521 }
 522
 523 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
 524         .tx     = imx_mu_generic_tx,
 525         .rx     = imx_mu_generic_rx,
 526         .init   = imx_mu_init_generic,
 527         .xTR    = {0x0, 0x4, 0x8, 0xc},
 528         .xRR    = {0x10, 0x14, 0x18, 0x1c},
 529         .xSR    = 0x20,
 530         .xCR    = 0x24,
 531 };
 532
 533 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
 534         .tx     = imx_mu_generic_tx,
 535         .rx     = imx_mu_generic_rx,
 536         .init   = imx_mu_init_generic,
 537         .xTR    = {0x20, 0x24, 0x28, 0x2c},
 538         .xRR    = {0x40, 0x44, 0x48, 0x4c},
 539         .xSR    = 0x60,
 540         .xCR    = 0x64,
 541 };
 542
 543 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
 544         .tx     = imx_mu_scu_tx,
 545         .rx     = imx_mu_scu_rx,
 546         .init   = imx_mu_init_scu,
 547         .xTR    = {0x0, 0x4, 0x8, 0xc},
 548         .xRR    = {0x10, 0x14, 0x18, 0x1c},
 549         .xSR    = 0x20,
 550         .xCR    = 0x24,
 551 };
 552
 553 static const struct of_device_id imx_mu_dt_ids[] = {
 554         { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
 555         { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
 556         { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
 557         { },
 558 };
 559 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
 560
 561 static struct platform_driver imx_mu_driver = {
 562         .probe          = imx_mu_probe,
 563         .remove         = imx_mu_remove,
 564         .driver = {
 565                 .name   = "imx_mu",
 566                 .of_match_table = imx_mu_dt_ids,
 567         },
 568 };
 569 module_platform_driver(imx_mu_driver);
 570
 571 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
 572 MODULE_DESCRIPTION("Message Unit driver for i.MX");
 573 MODULE_LICENSE("GPL v2");