1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
7 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/mailbox_controller.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/slab.h>
15 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
16 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
17 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
18 #define IMX_MU_xSR_BRDIP BIT(9)
20 /* General Purpose Interrupt Enable */
21 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
22 /* Receive Interrupt Enable */
23 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
24 /* Transmit Interrupt Enable */
25 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
26 /* General Purpose Interrupt Request */
27 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
29 #define IMX_MU_CHANS 16
30 #define IMX_MU_CHAN_NAME_SIZE 20
32 enum imx_mu_chan_type {
33 IMX_MU_TYPE_TX, /* Tx */
34 IMX_MU_TYPE_RX, /* Rx */
35 IMX_MU_TYPE_TXDB, /* Tx doorbell */
36 IMX_MU_TYPE_RXDB, /* Rx doorbell */
39 struct imx_mu_con_priv {
41 char irq_desc[IMX_MU_CHAN_NAME_SIZE];
42 enum imx_mu_chan_type type;
43 struct mbox_chan *chan;
44 struct tasklet_struct txdb_tasklet;
50 spinlock_t xcr_lock; /* control register lock */
52 struct mbox_controller mbox;
53 struct mbox_chan mbox_chans[IMX_MU_CHANS];
55 struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
56 const struct imx_mu_dcfg *dcfg;
64 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
65 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
66 void (*init)(struct imx_mu_priv *priv);
67 u32 xTR[4]; /* Transmit Registers */
68 u32 xRR[4]; /* Receive Registers */
69 u32 xSR; /* Status Register */
70 u32 xCR; /* Control Register */
73 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
75 return container_of(mbox, struct imx_mu_priv, mbox);
78 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
80 iowrite32(val, priv->base + offs);
83 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
85 return ioread32(priv->base + offs);
88 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
93 spin_lock_irqsave(&priv->xcr_lock, flags);
94 val = imx_mu_read(priv, priv->dcfg->xCR);
97 imx_mu_write(priv, val, priv->dcfg->xCR);
98 spin_unlock_irqrestore(&priv->xcr_lock, flags);
103 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
104 struct imx_mu_con_priv *cp,
111 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
112 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
114 case IMX_MU_TYPE_TXDB:
115 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
116 tasklet_schedule(&cp->txdb_tasklet);
119 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
126 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
127 struct imx_mu_con_priv *cp)
131 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
132 mbox_chan_received_data(cp->chan, (void *)&dat);
137 static void imx_mu_txdb_tasklet(unsigned long data)
139 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
141 mbox_chan_txdone(cp->chan, 0);
144 static irqreturn_t imx_mu_isr(int irq, void *p)
146 struct mbox_chan *chan = p;
147 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
148 struct imx_mu_con_priv *cp = chan->con_priv;
151 ctrl = imx_mu_read(priv, priv->dcfg->xCR);
152 val = imx_mu_read(priv, priv->dcfg->xSR);
156 val &= IMX_MU_xSR_TEn(cp->idx) &
157 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
160 val &= IMX_MU_xSR_RFn(cp->idx) &
161 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
163 case IMX_MU_TYPE_RXDB:
164 val &= IMX_MU_xSR_GIPn(cp->idx) &
165 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
174 if (val == IMX_MU_xSR_TEn(cp->idx)) {
175 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
176 mbox_chan_txdone(chan, 0);
177 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
178 priv->dcfg->rx(priv, cp);
179 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
180 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
181 mbox_chan_received_data(chan, NULL);
183 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
190 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
192 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
193 struct imx_mu_con_priv *cp = chan->con_priv;
195 return priv->dcfg->tx(priv, cp, data);
198 static int imx_mu_startup(struct mbox_chan *chan)
200 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
201 struct imx_mu_con_priv *cp = chan->con_priv;
204 if (cp->type == IMX_MU_TYPE_TXDB) {
205 /* Tx doorbell don't have ACK support */
206 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
211 ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED |
212 IRQF_NO_SUSPEND, cp->irq_desc, chan);
215 "Unable to acquire IRQ %d\n", priv->irq);
221 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
223 case IMX_MU_TYPE_RXDB:
224 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
233 static void imx_mu_shutdown(struct mbox_chan *chan)
235 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
236 struct imx_mu_con_priv *cp = chan->con_priv;
238 if (cp->type == IMX_MU_TYPE_TXDB) {
239 tasklet_kill(&cp->txdb_tasklet);
245 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
248 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
250 case IMX_MU_TYPE_RXDB:
251 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
257 free_irq(priv->irq, chan);
260 static const struct mbox_chan_ops imx_mu_ops = {
261 .send_data = imx_mu_send_data,
262 .startup = imx_mu_startup,
263 .shutdown = imx_mu_shutdown,
266 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
267 const struct of_phandle_args *sp)
271 if (sp->args_count != 2) {
272 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
273 return ERR_PTR(-EINVAL);
276 type = sp->args[0]; /* channel type */
277 idx = sp->args[1]; /* index */
278 chan = type * 4 + idx;
280 if (chan >= mbox->num_chans) {
281 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
282 return ERR_PTR(-EINVAL);
285 return &mbox->chans[chan];
288 static void imx_mu_init_generic(struct imx_mu_priv *priv)
292 for (i = 0; i < IMX_MU_CHANS; i++) {
293 struct imx_mu_con_priv *cp = &priv->con_priv[i];
297 cp->chan = &priv->mbox_chans[i];
298 priv->mbox_chans[i].con_priv = cp;
299 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
300 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
303 priv->mbox.num_chans = IMX_MU_CHANS;
304 priv->mbox.of_xlate = imx_mu_xlate;
309 /* Set default MU configuration */
310 imx_mu_write(priv, 0, priv->dcfg->xCR);
313 static int imx_mu_probe(struct platform_device *pdev)
315 struct device *dev = &pdev->dev;
316 struct device_node *np = dev->of_node;
317 struct imx_mu_priv *priv;
318 const struct imx_mu_dcfg *dcfg;
321 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
327 priv->base = devm_platform_ioremap_resource(pdev, 0);
328 if (IS_ERR(priv->base))
329 return PTR_ERR(priv->base);
331 priv->irq = platform_get_irq(pdev, 0);
335 dcfg = of_device_get_match_data(dev);
340 priv->clk = devm_clk_get(dev, NULL);
341 if (IS_ERR(priv->clk)) {
342 if (PTR_ERR(priv->clk) != -ENOENT)
343 return PTR_ERR(priv->clk);
348 ret = clk_prepare_enable(priv->clk);
350 dev_err(dev, "Failed to enable clock\n");
354 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
356 priv->dcfg->init(priv);
358 spin_lock_init(&priv->xcr_lock);
360 priv->mbox.dev = dev;
361 priv->mbox.ops = &imx_mu_ops;
362 priv->mbox.chans = priv->mbox_chans;
363 priv->mbox.txdone_irq = true;
365 platform_set_drvdata(pdev, priv);
367 return devm_mbox_controller_register(dev, &priv->mbox);
370 static int imx_mu_remove(struct platform_device *pdev)
372 struct imx_mu_priv *priv = platform_get_drvdata(pdev);
374 clk_disable_unprepare(priv->clk);
379 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
380 .tx = imx_mu_generic_tx,
381 .rx = imx_mu_generic_rx,
382 .init = imx_mu_init_generic,
383 .xTR = {0x0, 0x4, 0x8, 0xc},
384 .xRR = {0x10, 0x14, 0x18, 0x1c},
389 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
390 .tx = imx_mu_generic_tx,
391 .rx = imx_mu_generic_rx,
392 .init = imx_mu_init_generic,
393 .xTR = {0x20, 0x24, 0x28, 0x2c},
394 .xRR = {0x40, 0x44, 0x48, 0x4c},
399 static const struct of_device_id imx_mu_dt_ids[] = {
400 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
401 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
404 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
406 static struct platform_driver imx_mu_driver = {
407 .probe = imx_mu_probe,
408 .remove = imx_mu_remove,
411 .of_match_table = imx_mu_dt_ids,
414 module_platform_driver(imx_mu_driver);
416 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
417 MODULE_DESCRIPTION("Message Unit driver for i.MX");
418 MODULE_LICENSE("GPL v2");