drivers/leds/blink/leds-lgm-sso.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Lightning Mountain SoC LED Serial Shift Output Controller driver
   4  *
   5  * Copyright (c) 2020 Intel Corporation.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/gpio.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/leds.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/property.h>
  18 #include <linux/regmap.h>
  19 #include <linux/sizes.h>
  20 #include <linux/uaccess.h>
  21
  22 #define SSO_DEV_NAME                    "lgm-sso"
  23
  24 #define LED_BLINK_H8_0                  0x0
  25 #define LED_BLINK_H8_1                  0x4
  26 #define GET_FREQ_OFFSET(pin, src)       (((pin) * 6) + ((src) * 2))
  27 #define GET_SRC_OFFSET(pinc)            (((pin) * 6) + 4)
  28
  29 #define DUTY_CYCLE(x)                   (0x8 + ((x) * 4))
  30 #define SSO_CON0                        0x2B0
  31 #define SSO_CON0_RZFL                   BIT(26)
  32 #define SSO_CON0_BLINK_R                BIT(30)
  33 #define SSO_CON0_SWU                    BIT(31)
  34
  35 #define SSO_CON1                        0x2B4
  36 #define SSO_CON1_FCDSC                  GENMASK(21, 20) /* Fixed Divider Shift Clock */
  37 #define SSO_CON1_FPID                   GENMASK(24, 23)
  38 #define SSO_CON1_GPTD                   GENMASK(26, 25)
  39 #define SSO_CON1_US                     GENMASK(31, 30)
  40
  41 #define SSO_CPU                         0x2B8
  42 #define SSO_CON2                        0x2C4
  43 #define SSO_CON3                        0x2C8
  44
  45 /* Driver MACRO */
  46 #define MAX_PIN_NUM_PER_BANK            SZ_32
  47 #define MAX_GROUP_NUM                   SZ_4
  48 #define PINS_PER_GROUP                  SZ_8
  49 #define FPID_FREQ_RANK_MAX              SZ_4
  50 #define SSO_LED_MAX_NUM                 SZ_32
  51 #define MAX_FREQ_RANK                   10
  52 #define DEF_GPTC_CLK_RATE               200000000
  53 #define SSO_DEF_BRIGHTNESS              LED_HALF
  54 #define DATA_CLK_EDGE                   0 /* 0-rising, 1-falling */
  55
  56 static const u32 freq_div_tbl[] = {4000, 2000, 1000, 800};
  57 static const int freq_tbl[] = {2, 4, 8, 10, 50000, 100000, 200000, 250000};
  58 static const int shift_clk_freq_tbl[] = {25000000, 12500000, 6250000, 3125000};
  59
  60 /*
  61  * Update Source to update the SOUTs
  62  * SW - Software has to update the SWU bit
  63  * GPTC - General Purpose timer is used as clock source
  64  * FPID - Divided FSC clock (FPID) is used as clock source
  65  */
  66 enum {
  67         US_SW = 0,
  68         US_GPTC = 1,
  69         US_FPID = 2
  70 };
  71
  72 enum {
  73         MAX_FPID_FREQ_RANK = 5, /* 1 to 4 */
  74         MAX_GPTC_FREQ_RANK = 9, /* 5 to 8 */
  75         MAX_GPTC_HS_FREQ_RANK = 10, /* 9 to 10 */
  76 };
  77
  78 enum {
  79         LED_GRP0_PIN_MAX = 24,
  80         LED_GRP1_PIN_MAX = 29,
  81         LED_GRP2_PIN_MAX = 32,
  82 };
  83
  84 enum {
  85         LED_GRP0_0_23,
  86         LED_GRP1_24_28,
  87         LED_GRP2_29_31,
  88         LED_GROUP_MAX,
  89 };
  90
  91 enum {
  92         CLK_SRC_FPID = 0,
  93         CLK_SRC_GPTC = 1,
  94         CLK_SRC_GPTC_HS = 2,
  95 };
  96
  97 struct sso_led_priv;
  98
  99 struct sso_led_desc {
 100         const char *name;
 101         const char *default_trigger;
 102         unsigned int brightness;
 103         unsigned int blink_rate;
 104         unsigned int retain_state_suspended:1;
 105         unsigned int retain_state_shutdown:1;
 106         unsigned int panic_indicator:1;
 107         unsigned int hw_blink:1;
 108         unsigned int hw_trig:1;
 109         unsigned int blinking:1;
 110         int freq_idx;
 111         u32 pin;
 112 };
 113
 114 struct sso_led {
 115         struct list_head list;
 116         struct led_classdev cdev;
 117         struct gpio_desc *gpiod;
 118         struct sso_led_desc desc;
 119         struct sso_led_priv *priv;
 120 };
 121
 122 struct sso_gpio {
 123         struct gpio_chip chip;
 124         int shift_clk_freq;
 125         int edge;
 126         int freq;
 127         u32 pins;
 128         u32 alloc_bitmap;
 129 };
 130
 131 struct sso_led_priv {
 132         struct regmap *mmap;
 133         struct device *dev;
 134         struct platform_device *pdev;
 135         struct clk_bulk_data clocks[2];
 136         u32 fpid_clkrate;
 137         u32 gptc_clkrate;
 138         u32 freq[MAX_FREQ_RANK];
 139         struct list_head led_list;
 140         struct sso_gpio gpio;
 141 };
 142
 143 static int sso_get_blink_rate_idx(struct sso_led_priv *priv, u32 rate)
 144 {
 145         int i;
 146
 147         for (i = 0; i < MAX_FREQ_RANK; i++) {
 148                 if (rate <= priv->freq[i])
 149                         return i;
 150         }
 151
 152         return -1;
 153 }
 154
 155 static unsigned int sso_led_pin_to_group(u32 pin)
 156 {
 157         if (pin < LED_GRP0_PIN_MAX)
 158                 return LED_GRP0_0_23;
 159         else if (pin < LED_GRP1_PIN_MAX)
 160                 return LED_GRP1_24_28;
 161         else
 162                 return LED_GRP2_29_31;
 163 }
 164
 165 static u32 sso_led_get_freq_src(int freq_idx)
 166 {
 167         if (freq_idx < MAX_FPID_FREQ_RANK)
 168                 return CLK_SRC_FPID;
 169         else if (freq_idx < MAX_GPTC_FREQ_RANK)
 170                 return CLK_SRC_GPTC;
 171         else
 172                 return CLK_SRC_GPTC_HS;
 173 }
 174
 175 static u32 sso_led_pin_blink_off(u32 pin, unsigned int group)
 176 {
 177         if (group == LED_GRP2_29_31)
 178                 return pin - LED_GRP1_PIN_MAX;
 179         else if (group == LED_GRP1_24_28)
 180                 return pin - LED_GRP0_PIN_MAX;
 181         else    /* led 0 - 23 in led 32 location */
 182                 return SSO_LED_MAX_NUM - LED_GRP1_PIN_MAX;
 183 }
 184
 185 static struct sso_led
 186 *cdev_to_sso_led_data(struct led_classdev *led_cdev)
 187 {
 188         return container_of(led_cdev, struct sso_led, cdev);
 189 }
 190
 191 static void sso_led_freq_set(struct sso_led_priv *priv, u32 pin, int freq_idx)
 192 {
 193         u32 reg, off, freq_src, val_freq;
 194         u32 low, high, val;
 195         unsigned int group;
 196
 197         if (!freq_idx)
 198                 return;
 199
 200         group = sso_led_pin_to_group(pin);
 201         freq_src = sso_led_get_freq_src(freq_idx);
 202         off = sso_led_pin_blink_off(pin, group);
 203
 204         if (group == LED_GRP0_0_23)
 205                 return;
 206         else if (group == LED_GRP1_24_28)
 207                 reg = LED_BLINK_H8_0;
 208         else
 209                 reg = LED_BLINK_H8_1;
 210
 211         if (freq_src == CLK_SRC_FPID)
 212                 val_freq = freq_idx - 1;
 213         else if (freq_src == CLK_SRC_GPTC)
 214                 val_freq = freq_idx - MAX_FPID_FREQ_RANK;
 215
 216         /* set blink rate idx */
 217         if (freq_src != CLK_SRC_GPTC_HS) {
 218                 low = GET_FREQ_OFFSET(off, freq_src);
 219                 high = low + 2;
 220                 val = val_freq << high;
 221                 regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val);
 222         }
 223
 224         /* select clock source */
 225         low = GET_SRC_OFFSET(off);
 226         high = low + 2;
 227         val = freq_src << high;
 228         regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val);
 229 }
 230
 231 static void sso_led_brightness_set(struct led_classdev *led_cdev,
 232                                    enum led_brightness brightness)
 233 {
 234         struct sso_led_priv *priv;
 235         struct sso_led_desc *desc;
 236         struct sso_led *led;
 237         int val;
 238
 239         led = cdev_to_sso_led_data(led_cdev);
 240         priv = led->priv;
 241         desc = &led->desc;
 242
 243         desc->brightness = brightness;
 244         regmap_write(priv->mmap, DUTY_CYCLE(desc->pin), brightness);
 245
 246         if (brightness == LED_OFF)
 247                 val = 0;
 248         else
 249                 val = 1;
 250
 251         /* HW blink off */
 252         if (desc->hw_blink && !val && desc->blinking) {
 253                 desc->blinking = 0;
 254                 regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin), 0);
 255         } else if (desc->hw_blink && val && !desc->blinking) {
 256                 desc->blinking = 1;
 257                 regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin),
 258                                    1 << desc->pin);
 259         }
 260
 261         if (!desc->hw_trig && led->gpiod)
 262                 gpiod_set_value(led->gpiod, val);
 263 }
 264
 265 static enum led_brightness sso_led_brightness_get(struct led_classdev *led_cdev)
 266 {
 267         struct sso_led *led = cdev_to_sso_led_data(led_cdev);
 268
 269         return (enum led_brightness)led->desc.brightness;
 270 }
 271
 272 static int
 273 delay_to_freq_idx(struct sso_led *led, unsigned long *delay_on,
 274                   unsigned long *delay_off)
 275 {
 276         struct sso_led_priv *priv = led->priv;
 277         unsigned long delay;
 278         int freq_idx;
 279         u32 freq;
 280
 281         if (!*delay_on && !*delay_off) {
 282                 *delay_on = *delay_off = (1000 / priv->freq[0]) / 2;
 283                 return 0;
 284         }
 285
 286         delay = *delay_on + *delay_off;
 287         freq = 1000 / delay;
 288
 289         freq_idx = sso_get_blink_rate_idx(priv, freq);
 290         if (freq_idx == -1)
 291                 freq_idx = MAX_FREQ_RANK - 1;
 292
 293         delay = 1000 / priv->freq[freq_idx];
 294         *delay_on = *delay_off = delay / 2;
 295
 296         if (!*delay_on)
 297                 *delay_on = *delay_off = 1;
 298
 299         return freq_idx;
 300 }
 301
 302 static int
 303 sso_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
 304                   unsigned long *delay_off)
 305 {
 306         struct sso_led_priv *priv;
 307         struct sso_led *led;
 308         int freq_idx;
 309
 310         led = cdev_to_sso_led_data(led_cdev);
 311         priv = led->priv;
 312         freq_idx = delay_to_freq_idx(led, delay_on, delay_off);
 313
 314         sso_led_freq_set(priv, led->desc.pin, freq_idx);
 315         regmap_update_bits(priv->mmap, SSO_CON2, BIT(led->desc.pin),
 316                            1 << led->desc.pin);
 317         led->desc.freq_idx = freq_idx;
 318         led->desc.blink_rate = priv->freq[freq_idx];
 319         led->desc.blinking = 1;
 320
 321         return 1;
 322 }
 323
 324 static void sso_led_hw_cfg(struct sso_led_priv *priv, struct sso_led *led)
 325 {
 326         struct sso_led_desc *desc = &led->desc;
 327
 328         /* set freq */
 329         if (desc->hw_blink) {
 330                 sso_led_freq_set(priv, desc->pin, desc->freq_idx);
 331                 regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin),
 332                                    1 << desc->pin);
 333         }
 334
 335         if (desc->hw_trig)
 336                 regmap_update_bits(priv->mmap, SSO_CON3, BIT(desc->pin),
 337                                    1 << desc->pin);
 338
 339         /* set brightness */
 340         regmap_write(priv->mmap, DUTY_CYCLE(desc->pin), desc->brightness);
 341
 342         /* enable output */
 343         if (!desc->hw_trig && desc->brightness)
 344                 gpiod_set_value(led->gpiod, 1);
 345 }
 346
 347 static int sso_create_led(struct sso_led_priv *priv, struct sso_led *led,
 348                           struct fwnode_handle *child)
 349 {
 350         struct sso_led_desc *desc = &led->desc;
 351         struct led_init_data init_data;
 352         int err;
 353
 354         init_data.fwnode = child;
 355         init_data.devicename = SSO_DEV_NAME;
 356         init_data.default_label = ":";
 357
 358         led->cdev.default_trigger = desc->default_trigger;
 359         led->cdev.brightness_set = sso_led_brightness_set;
 360         led->cdev.brightness_get = sso_led_brightness_get;
 361         led->cdev.brightness = desc->brightness;
 362         led->cdev.max_brightness = LED_FULL;
 363
 364         if (desc->retain_state_shutdown)
 365                 led->cdev.flags |= LED_RETAIN_AT_SHUTDOWN;
 366         if (desc->retain_state_suspended)
 367                 led->cdev.flags |= LED_CORE_SUSPENDRESUME;
 368         if (desc->panic_indicator)
 369                 led->cdev.flags |= LED_PANIC_INDICATOR;
 370
 371         if (desc->hw_blink)
 372                 led->cdev.blink_set = sso_led_blink_set;
 373
 374         sso_led_hw_cfg(priv, led);
 375
 376         err = devm_led_classdev_register_ext(priv->dev, &led->cdev, &init_data);
 377         if (err)
 378                 return err;
 379
 380         list_add(&led->list, &priv->led_list);
 381
 382         return 0;
 383 }
 384
 385 static void sso_init_freq(struct sso_led_priv *priv)
 386 {
 387         int i;
 388
 389         priv->freq[0] = 0;
 390         for (i = 1; i < MAX_FREQ_RANK; i++) {
 391                 if (i < MAX_FPID_FREQ_RANK) {
 392                         priv->freq[i] = priv->fpid_clkrate / freq_div_tbl[i - 1];
 393                 } else if (i < MAX_GPTC_FREQ_RANK) {
 394                         priv->freq[i] = priv->gptc_clkrate /
 395                                 freq_div_tbl[i - MAX_FPID_FREQ_RANK];
 396                 } else if (i < MAX_GPTC_HS_FREQ_RANK) {
 397                         priv->freq[i] = priv->gptc_clkrate;
 398                 }
 399         }
 400 }
 401
 402 static int sso_gpio_request(struct gpio_chip *chip, unsigned int offset)
 403 {
 404         struct sso_led_priv *priv = gpiochip_get_data(chip);
 405
 406         if (priv->gpio.alloc_bitmap & BIT(offset))
 407                 return -EINVAL;
 408
 409         priv->gpio.alloc_bitmap |= BIT(offset);
 410         regmap_write(priv->mmap, DUTY_CYCLE(offset), 0xFF);
 411
 412         return 0;
 413 }
 414
 415 static void sso_gpio_free(struct gpio_chip *chip, unsigned int offset)
 416 {
 417         struct sso_led_priv *priv = gpiochip_get_data(chip);
 418
 419         priv->gpio.alloc_bitmap &= ~BIT(offset);
 420         regmap_write(priv->mmap, DUTY_CYCLE(offset), 0x0);
 421 }
 422
 423 static int sso_gpio_get_dir(struct gpio_chip *chip, unsigned int offset)
 424 {
 425         return GPIOF_DIR_OUT;
 426 }
 427
 428 static int
 429 sso_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, int value)
 430 {
 431         struct sso_led_priv *priv = gpiochip_get_data(chip);
 432         bool bit = !!value;
 433
 434         regmap_update_bits(priv->mmap, SSO_CPU, BIT(offset), bit << offset);
 435         if (!priv->gpio.freq)
 436                 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_SWU,
 437                                    SSO_CON0_SWU);
 438
 439         return 0;
 440 }
 441
 442 static int sso_gpio_get(struct gpio_chip *chip, unsigned int offset)
 443 {
 444         struct sso_led_priv *priv = gpiochip_get_data(chip);
 445         u32 reg_val;
 446
 447         regmap_read(priv->mmap, SSO_CPU, &reg_val);
 448
 449         return !!(reg_val & BIT(offset));
 450 }
 451
 452 static void sso_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 453 {
 454         struct sso_led_priv *priv = gpiochip_get_data(chip);
 455
 456         regmap_update_bits(priv->mmap, SSO_CPU, BIT(offset), value << offset);
 457         if (!priv->gpio.freq)
 458                 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_SWU,
 459                                    SSO_CON0_SWU);
 460 }
 461
 462 static int sso_gpio_gc_init(struct device *dev, struct sso_led_priv *priv)
 463 {
 464         struct gpio_chip *gc = &priv->gpio.chip;
 465
 466         gc->request             = sso_gpio_request;
 467         gc->free                = sso_gpio_free;
 468         gc->get_direction       = sso_gpio_get_dir;
 469         gc->direction_output    = sso_gpio_dir_out;
 470         gc->get                 = sso_gpio_get;
 471         gc->set                 = sso_gpio_set;
 472
 473         gc->label               = "lgm-sso";
 474         gc->base                = -1;
 475         /* To exclude pins from control, use "gpio-reserved-ranges" */
 476         gc->ngpio               = priv->gpio.pins;
 477         gc->parent              = dev;
 478         gc->owner               = THIS_MODULE;
 479         gc->of_node             = dev->of_node;
 480
 481         return devm_gpiochip_add_data(dev, gc, priv);
 482 }
 483
 484 static int sso_gpio_get_freq_idx(int freq)
 485 {
 486         int idx;
 487
 488         for (idx = 0; idx < ARRAY_SIZE(freq_tbl); idx++) {
 489                 if (freq <= freq_tbl[idx])
 490                         return idx;
 491         }
 492
 493         return -1;
 494 }
 495
 496 static void sso_register_shift_clk(struct sso_led_priv *priv)
 497 {
 498         int idx, size = ARRAY_SIZE(shift_clk_freq_tbl);
 499         u32 val = 0;
 500
 501         for (idx = 0; idx < size; idx++) {
 502                 if (shift_clk_freq_tbl[idx] <= priv->gpio.shift_clk_freq) {
 503                         val = idx;
 504                         break;
 505                 }
 506         }
 507
 508         if (idx == size)
 509                 dev_warn(priv->dev, "%s: Invalid freq %d\n",
 510                          __func__, priv->gpio.shift_clk_freq);
 511
 512         regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_FCDSC,
 513                            FIELD_PREP(SSO_CON1_FCDSC, val));
 514 }
 515
 516 static int sso_gpio_freq_set(struct sso_led_priv *priv)
 517 {
 518         int freq_idx;
 519         u32 val;
 520
 521         freq_idx = sso_gpio_get_freq_idx(priv->gpio.freq);
 522         if (freq_idx == -1)
 523                 freq_idx = ARRAY_SIZE(freq_tbl) - 1;
 524
 525         val = freq_idx % FPID_FREQ_RANK_MAX;
 526
 527         if (!priv->gpio.freq) {
 528                 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R, 0);
 529                 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US,
 530                                    FIELD_PREP(SSO_CON1_US, US_SW));
 531         } else if (freq_idx < FPID_FREQ_RANK_MAX) {
 532                 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R,
 533                                    SSO_CON0_BLINK_R);
 534                 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US,
 535                                    FIELD_PREP(SSO_CON1_US, US_FPID));
 536                 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_FPID,
 537                                    FIELD_PREP(SSO_CON1_FPID, val));
 538         } else {
 539                 regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R,
 540                                    SSO_CON0_BLINK_R);
 541                 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US,
 542                                    FIELD_PREP(SSO_CON1_US, US_GPTC));
 543                 regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_GPTD,
 544                                    FIELD_PREP(SSO_CON1_GPTD, val));
 545         }
 546
 547         return 0;
 548 }
 549
 550 static int sso_gpio_hw_init(struct sso_led_priv *priv)
 551 {
 552         u32 activate;
 553         int i, err;
 554
 555         /* Clear all duty cycles */
 556         for (i = 0; i < priv->gpio.pins; i++) {
 557                 err = regmap_write(priv->mmap, DUTY_CYCLE(i), 0);
 558                 if (err)
 559                         return err;
 560         }
 561
 562         /* 4 groups for total 32 pins */
 563         for (i = 1; i <= MAX_GROUP_NUM; i++) {
 564                 activate = !!(i * PINS_PER_GROUP <= priv->gpio.pins ||
 565                               priv->gpio.pins > (i - 1) * PINS_PER_GROUP);
 566                 err = regmap_update_bits(priv->mmap, SSO_CON1, BIT(i - 1),
 567                                          activate << (i - 1));
 568                 if (err)
 569                         return err;
 570         }
 571
 572         /* NO HW directly controlled pin by default */
 573         err = regmap_write(priv->mmap, SSO_CON3, 0);
 574         if (err)
 575                 return err;
 576
 577         /* NO BLINK for all pins */
 578         err = regmap_write(priv->mmap, SSO_CON2, 0);
 579         if (err)
 580                 return err;
 581
 582         /* OUTPUT 0 by default */
 583         err = regmap_write(priv->mmap, SSO_CPU, 0);
 584         if (err)
 585                 return err;
 586
 587         /* update edge */
 588         err = regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_RZFL,
 589                                  FIELD_PREP(SSO_CON0_RZFL, priv->gpio.edge));
 590         if (err)
 591                 return err;
 592
 593         /* Set GPIO update rate */
 594         sso_gpio_freq_set(priv);
 595
 596         /* Register shift clock */
 597         sso_register_shift_clk(priv);
 598
 599         return 0;
 600 }
 601
 602 static void sso_led_shutdown(struct sso_led *led)
 603 {
 604         struct sso_led_priv *priv = led->priv;
 605
 606         /* unregister led */
 607         devm_led_classdev_unregister(priv->dev, &led->cdev);
 608
 609         /* clear HW control bit */
 610         if (led->desc.hw_trig)
 611                 regmap_update_bits(priv->mmap, SSO_CON3, BIT(led->desc.pin), 0);
 612
 613         if (led->gpiod)
 614                 devm_gpiod_put(priv->dev, led->gpiod);
 615
 616         led->priv = NULL;
 617 }
 618
 619 static int
 620 __sso_led_dt_parse(struct sso_led_priv *priv, struct fwnode_handle *fw_ssoled)
 621 {
 622         struct fwnode_handle *fwnode_child;
 623         struct device *dev = priv->dev;
 624         struct sso_led_desc *desc;
 625         struct sso_led *led;
 626         struct list_head *p;
 627         const char *tmp;
 628         u32 prop;
 629         int ret;
 630
 631         fwnode_for_each_child_node(fw_ssoled, fwnode_child) {
 632                 led = devm_kzalloc(dev, sizeof(*led), GFP_KERNEL);
 633                 if (!led)
 634                         return -ENOMEM;
 635
 636                 INIT_LIST_HEAD(&led->list);
 637                 led->priv = priv;
 638                 desc = &led->desc;
 639
 640                 led->gpiod = devm_fwnode_get_gpiod_from_child(dev, NULL,
 641                                                               fwnode_child,
 642                                                               GPIOD_ASIS, NULL);
 643                 if (IS_ERR(led->gpiod)) {
 644                         dev_err(dev, "led: get gpio fail!\n");
 645                         goto __dt_err;
 646                 }
 647
 648                 fwnode_property_read_string(fwnode_child,
 649                                             "linux,default-trigger",
 650                                             &desc->default_trigger);
 651
 652                 if (fwnode_property_present(fwnode_child,
 653                                             "retain-state-suspended"))
 654                         desc->retain_state_suspended = 1;
 655
 656                 if (fwnode_property_present(fwnode_child,
 657                                             "retain-state-shutdown"))
 658                         desc->retain_state_shutdown = 1;
 659
 660                 if (fwnode_property_present(fwnode_child, "panic-indicator"))
 661                         desc->panic_indicator = 1;
 662
 663                 ret = fwnode_property_read_u32(fwnode_child, "reg", &prop);
 664                 if (ret != 0 || prop >= SSO_LED_MAX_NUM) {
 665                         dev_err(dev, "invalid LED pin:%u\n", prop);
 666                         goto __dt_err;
 667                 }
 668                 desc->pin = prop;
 669
 670                 if (fwnode_property_present(fwnode_child, "intel,sso-hw-blink"))
 671                         desc->hw_blink = 1;
 672
 673                 desc->hw_trig = fwnode_property_read_bool(fwnode_child,
 674                                                           "intel,sso-hw-trigger");
 675                 if (desc->hw_trig) {
 676                         desc->default_trigger = NULL;
 677                         desc->retain_state_shutdown = 0;
 678                         desc->retain_state_suspended = 0;
 679                         desc->panic_indicator = 0;
 680                         desc->hw_blink = 0;
 681                 }
 682
 683                 if (fwnode_property_read_u32(fwnode_child,
 684                                              "intel,sso-blink-rate-hz", &prop)) {
 685                         /* default first freq rate */
 686                         desc->freq_idx = 0;
 687                         desc->blink_rate = priv->freq[desc->freq_idx];
 688                 } else {
 689                         desc->freq_idx = sso_get_blink_rate_idx(priv, prop);
 690                         if (desc->freq_idx == -1)
 691                                 desc->freq_idx = MAX_FREQ_RANK - 1;
 692
 693                         desc->blink_rate = priv->freq[desc->freq_idx];
 694                 }
 695
 696                 if (!fwnode_property_read_string(fwnode_child, "default-state", &tmp)) {
 697                         if (!strcmp(tmp, "on"))
 698                                 desc->brightness = LED_FULL;
 699                 }
 700
 701                 if (sso_create_led(priv, led, fwnode_child))
 702                         goto __dt_err;
 703         }
 704         fwnode_handle_put(fw_ssoled);
 705
 706         return 0;
 707 __dt_err:
 708         fwnode_handle_put(fw_ssoled);
 709         /* unregister leds */
 710         list_for_each(p, &priv->led_list) {
 711                 led = list_entry(p, struct sso_led, list);
 712                 sso_led_shutdown(led);
 713         }
 714
 715         return -EINVAL;
 716 }
 717
 718 static int sso_led_dt_parse(struct sso_led_priv *priv)
 719 {
 720         struct fwnode_handle *fwnode = dev_fwnode(priv->dev);
 721         struct fwnode_handle *fw_ssoled;
 722         struct device *dev = priv->dev;
 723         int count;
 724         int ret;
 725
 726         count = device_get_child_node_count(dev);
 727         if (!count)
 728                 return 0;
 729
 730         fw_ssoled = fwnode_get_named_child_node(fwnode, "ssoled");
 731         if (fw_ssoled) {
 732                 ret = __sso_led_dt_parse(priv, fw_ssoled);
 733                 if (ret)
 734                         return ret;
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int sso_probe_gpios(struct sso_led_priv *priv)
 741 {
 742         struct device *dev = priv->dev;
 743         int ret;
 744
 745         if (device_property_read_u32(dev, "ngpios", &priv->gpio.pins))
 746                 priv->gpio.pins = MAX_PIN_NUM_PER_BANK;
 747
 748         if (priv->gpio.pins > MAX_PIN_NUM_PER_BANK)
 749                 return -EINVAL;
 750
 751         if (device_property_read_u32(dev, "intel,sso-update-rate-hz",
 752                                      &priv->gpio.freq))
 753                 priv->gpio.freq = 0;
 754
 755         priv->gpio.edge = DATA_CLK_EDGE;
 756         priv->gpio.shift_clk_freq = -1;
 757
 758         ret = sso_gpio_hw_init(priv);
 759         if (ret)
 760                 return ret;
 761
 762         return sso_gpio_gc_init(dev, priv);
 763 }
 764
 765 static void sso_clock_disable_unprepare(void *data)
 766 {
 767         struct sso_led_priv *priv = data;
 768
 769         clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clocks), priv->clocks);
 770 }
 771
 772 static int intel_sso_led_probe(struct platform_device *pdev)
 773 {
 774         struct device *dev = &pdev->dev;
 775         struct sso_led_priv *priv;
 776         int ret;
 777
 778         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 779         if (!priv)
 780                 return -ENOMEM;
 781
 782         priv->pdev = pdev;
 783         priv->dev = dev;
 784
 785         /* gate clock */
 786         priv->clocks[0].id = "sso";
 787
 788         /* fpid clock */
 789         priv->clocks[1].id = "fpid";
 790
 791         ret = devm_clk_bulk_get(dev, ARRAY_SIZE(priv->clocks), priv->clocks);
 792         if (ret) {
 793                 dev_err(dev, "Getting clocks failed!\n");
 794                 return ret;
 795         }
 796
 797         ret = clk_bulk_prepare_enable(ARRAY_SIZE(priv->clocks), priv->clocks);
 798         if (ret) {
 799                 dev_err(dev, "Failed to prepare and enable clocks!\n");
 800                 return ret;
 801         }
 802
 803         ret = devm_add_action_or_reset(dev, sso_clock_disable_unprepare, priv);
 804         if (ret)
 805                 return ret;
 806
 807         priv->fpid_clkrate = clk_get_rate(priv->clocks[1].clk);
 808
 809         priv->mmap = syscon_node_to_regmap(dev->of_node);
 810
 811         priv->mmap = syscon_node_to_regmap(dev->of_node);
 812         if (IS_ERR(priv->mmap)) {
 813                 dev_err(dev, "Failed to map iomem!\n");
 814                 return PTR_ERR(priv->mmap);
 815         }
 816
 817         ret = sso_probe_gpios(priv);
 818         if (ret) {
 819                 regmap_exit(priv->mmap);
 820                 return ret;
 821         }
 822
 823         INIT_LIST_HEAD(&priv->led_list);
 824
 825         platform_set_drvdata(pdev, priv);
 826         sso_init_freq(priv);
 827
 828         priv->gptc_clkrate = DEF_GPTC_CLK_RATE;
 829
 830         ret = sso_led_dt_parse(priv);
 831         if (ret) {
 832                 regmap_exit(priv->mmap);
 833                 return ret;
 834         }
 835         dev_info(priv->dev, "sso LED init success!\n");
 836
 837         return 0;
 838 }
 839
 840 static int intel_sso_led_remove(struct platform_device *pdev)
 841 {
 842         struct sso_led_priv *priv;
 843         struct list_head *pos, *n;
 844         struct sso_led *led;
 845
 846         priv = platform_get_drvdata(pdev);
 847
 848         list_for_each_safe(pos, n, &priv->led_list) {
 849                 list_del(pos);
 850                 led = list_entry(pos, struct sso_led, list);
 851                 sso_led_shutdown(led);
 852         }
 853
 854         regmap_exit(priv->mmap);
 855
 856         return 0;
 857 }
 858
 859 static const struct of_device_id of_sso_led_match[] = {
 860         { .compatible = "intel,lgm-ssoled" },
 861         {}
 862 };
 863
 864 MODULE_DEVICE_TABLE(of, of_sso_led_match);
 865
 866 static struct platform_driver intel_sso_led_driver = {
 867         .probe          = intel_sso_led_probe,
 868         .remove         = intel_sso_led_remove,
 869         .driver         = {
 870                         .name = "lgm-ssoled",
 871                         .of_match_table = of_sso_led_match,
 872         },
 873 };
 874
 875 module_platform_driver(intel_sso_led_driver);
 876
 877 MODULE_DESCRIPTION("Intel SSO LED/GPIO driver");
 878 MODULE_LICENSE("GPL v2");