1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/hwspinlock.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/syscore_ops.h>
23 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 #define IRQS_PER_BANK 32
27 #define HWSPNLCK_TIMEOUT 1000 /* usec */
28 #define HWSPNLCK_RETRY_DELAY 100 /* usec */
30 struct stm32_exti_bank {
42 struct stm32_desc_irq {
47 struct stm32_exti_drv_data {
48 const struct stm32_exti_bank **exti_banks;
49 const struct stm32_desc_irq *desc_irqs;
54 struct stm32_exti_chip_data {
55 struct stm32_exti_host_data *host_data;
56 const struct stm32_exti_bank *reg_bank;
57 struct raw_spinlock rlock;
64 struct stm32_exti_host_data {
66 struct stm32_exti_chip_data *chips_data;
67 const struct stm32_exti_drv_data *drv_data;
68 struct hwspinlock *hwlock;
71 static struct stm32_exti_host_data *stm32_host_data;
73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
80 .fpr_ofst = UNDEF_REG,
83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
88 .exti_banks = stm32f4xx_exti_banks,
89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
99 .fpr_ofst = UNDEF_REG,
102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
109 .fpr_ofst = UNDEF_REG,
112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
119 .fpr_ofst = UNDEF_REG,
122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
129 .exti_banks = stm32h7xx_exti_banks,
130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
133 static const struct stm32_exti_bank stm32mp1_exti_b1 = {
143 static const struct stm32_exti_bank stm32mp1_exti_b2 = {
153 static const struct stm32_exti_bank stm32mp1_exti_b3 = {
163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
169 static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
170 { .exti = 0, .irq_parent = 6 },
171 { .exti = 1, .irq_parent = 7 },
172 { .exti = 2, .irq_parent = 8 },
173 { .exti = 3, .irq_parent = 9 },
174 { .exti = 4, .irq_parent = 10 },
175 { .exti = 5, .irq_parent = 23 },
176 { .exti = 6, .irq_parent = 64 },
177 { .exti = 7, .irq_parent = 65 },
178 { .exti = 8, .irq_parent = 66 },
179 { .exti = 9, .irq_parent = 67 },
180 { .exti = 10, .irq_parent = 40 },
181 { .exti = 11, .irq_parent = 42 },
182 { .exti = 12, .irq_parent = 76 },
183 { .exti = 13, .irq_parent = 77 },
184 { .exti = 14, .irq_parent = 121 },
185 { .exti = 15, .irq_parent = 127 },
186 { .exti = 16, .irq_parent = 1 },
187 { .exti = 65, .irq_parent = 144 },
188 { .exti = 68, .irq_parent = 143 },
189 { .exti = 73, .irq_parent = 129 },
192 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
193 .exti_banks = stm32mp1_exti_banks,
194 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
195 .desc_irqs = stm32mp1_desc_irq,
196 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
199 static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
200 irq_hw_number_t hwirq)
202 const struct stm32_desc_irq *desc_irq;
205 if (!drv_data->desc_irqs)
208 for (i = 0; i < drv_data->irq_nr; i++) {
209 desc_irq = &drv_data->desc_irqs[i];
210 if (desc_irq->exti == hwirq)
211 return desc_irq->irq_parent;
217 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
219 struct stm32_exti_chip_data *chip_data = gc->private;
220 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
221 unsigned long pending;
223 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
224 if (stm32_bank->fpr_ofst != UNDEF_REG)
225 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
230 static void stm32_irq_handler(struct irq_desc *desc)
232 struct irq_domain *domain = irq_desc_get_handler_data(desc);
233 struct irq_chip *chip = irq_desc_get_chip(desc);
234 unsigned int virq, nbanks = domain->gc->num_chips;
235 struct irq_chip_generic *gc;
236 unsigned long pending;
237 int n, i, irq_base = 0;
239 chained_irq_enter(chip, desc);
241 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
242 gc = irq_get_domain_generic_chip(domain, irq_base);
244 while ((pending = stm32_exti_pending(gc))) {
245 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
246 virq = irq_find_mapping(domain, irq_base + n);
247 generic_handle_irq(virq);
252 chained_irq_exit(chip, desc);
255 static int stm32_exti_set_type(struct irq_data *d,
256 unsigned int type, u32 *rtsr, u32 *ftsr)
258 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
261 case IRQ_TYPE_EDGE_RISING:
265 case IRQ_TYPE_EDGE_FALLING:
269 case IRQ_TYPE_EDGE_BOTH:
280 static int stm32_exti_hwspin_lock(struct stm32_exti_chip_data *chip_data)
282 int ret, timeout = 0;
284 if (!chip_data->host_data->hwlock)
288 * Use the x_raw API since we are under spin_lock protection.
289 * Do not use the x_timeout API because we are under irq_disable
290 * mode (see __setup_irq())
293 ret = hwspin_trylock_raw(chip_data->host_data->hwlock);
297 udelay(HWSPNLCK_RETRY_DELAY);
298 timeout += HWSPNLCK_RETRY_DELAY;
299 } while (timeout < HWSPNLCK_TIMEOUT);
305 pr_err("%s can't get hwspinlock (%d)\n", __func__, ret);
310 static void stm32_exti_hwspin_unlock(struct stm32_exti_chip_data *chip_data)
312 if (chip_data->host_data->hwlock)
313 hwspin_unlock_raw(chip_data->host_data->hwlock);
316 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
318 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
319 struct stm32_exti_chip_data *chip_data = gc->private;
320 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
326 err = stm32_exti_hwspin_lock(chip_data);
330 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
331 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
333 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
337 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
338 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
341 stm32_exti_hwspin_unlock(chip_data);
348 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
351 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
352 void __iomem *base = chip_data->host_data->base;
354 /* save rtsr, ftsr registers */
355 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
356 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
358 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
361 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
364 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
365 void __iomem *base = chip_data->host_data->base;
367 /* restore rtsr, ftsr, registers */
368 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
369 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
371 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
374 static void stm32_irq_suspend(struct irq_chip_generic *gc)
376 struct stm32_exti_chip_data *chip_data = gc->private;
379 stm32_chip_suspend(chip_data, gc->wake_active);
383 static void stm32_irq_resume(struct irq_chip_generic *gc)
385 struct stm32_exti_chip_data *chip_data = gc->private;
388 stm32_chip_resume(chip_data, gc->mask_cache);
392 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
393 unsigned int nr_irqs, void *data)
395 struct irq_fwspec *fwspec = data;
396 irq_hw_number_t hwirq;
398 hwirq = fwspec->param[0];
400 irq_map_generic_chip(d, virq, hwirq);
405 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
406 unsigned int nr_irqs)
408 struct irq_data *data = irq_domain_get_irq_data(d, virq);
410 irq_domain_reset_irq_data(data);
413 static const struct irq_domain_ops irq_exti_domain_ops = {
414 .map = irq_map_generic_chip,
415 .alloc = stm32_exti_alloc,
416 .free = stm32_exti_free,
419 static void stm32_irq_ack(struct irq_data *d)
421 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
422 struct stm32_exti_chip_data *chip_data = gc->private;
423 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
427 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
428 if (stm32_bank->fpr_ofst != UNDEF_REG)
429 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
434 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
436 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
437 void __iomem *base = chip_data->host_data->base;
440 val = readl_relaxed(base + reg);
441 val |= BIT(d->hwirq % IRQS_PER_BANK);
442 writel_relaxed(val, base + reg);
447 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
449 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
450 void __iomem *base = chip_data->host_data->base;
453 val = readl_relaxed(base + reg);
454 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
455 writel_relaxed(val, base + reg);
460 static void stm32_exti_h_eoi(struct irq_data *d)
462 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
463 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
465 raw_spin_lock(&chip_data->rlock);
467 stm32_exti_set_bit(d, stm32_bank->rpr_ofst);
468 if (stm32_bank->fpr_ofst != UNDEF_REG)
469 stm32_exti_set_bit(d, stm32_bank->fpr_ofst);
471 raw_spin_unlock(&chip_data->rlock);
473 if (d->parent_data->chip)
474 irq_chip_eoi_parent(d);
477 static void stm32_exti_h_mask(struct irq_data *d)
479 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
480 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
482 raw_spin_lock(&chip_data->rlock);
483 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
484 raw_spin_unlock(&chip_data->rlock);
486 if (d->parent_data->chip)
487 irq_chip_mask_parent(d);
490 static void stm32_exti_h_unmask(struct irq_data *d)
492 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
493 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
495 raw_spin_lock(&chip_data->rlock);
496 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
497 raw_spin_unlock(&chip_data->rlock);
499 if (d->parent_data->chip)
500 irq_chip_unmask_parent(d);
503 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
505 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
506 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
507 void __iomem *base = chip_data->host_data->base;
511 raw_spin_lock(&chip_data->rlock);
513 err = stm32_exti_hwspin_lock(chip_data);
517 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
518 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
520 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
524 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
525 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
528 stm32_exti_hwspin_unlock(chip_data);
530 raw_spin_unlock(&chip_data->rlock);
535 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
537 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
538 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
540 raw_spin_lock(&chip_data->rlock);
543 chip_data->wake_active |= mask;
545 chip_data->wake_active &= ~mask;
547 raw_spin_unlock(&chip_data->rlock);
552 static int stm32_exti_h_set_affinity(struct irq_data *d,
553 const struct cpumask *dest, bool force)
555 if (d->parent_data->chip)
556 return irq_chip_set_affinity_parent(d, dest, force);
561 static int __maybe_unused stm32_exti_h_suspend(void)
563 struct stm32_exti_chip_data *chip_data;
566 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
567 chip_data = &stm32_host_data->chips_data[i];
568 raw_spin_lock(&chip_data->rlock);
569 stm32_chip_suspend(chip_data, chip_data->wake_active);
570 raw_spin_unlock(&chip_data->rlock);
576 static void __maybe_unused stm32_exti_h_resume(void)
578 struct stm32_exti_chip_data *chip_data;
581 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
582 chip_data = &stm32_host_data->chips_data[i];
583 raw_spin_lock(&chip_data->rlock);
584 stm32_chip_resume(chip_data, chip_data->mask_cache);
585 raw_spin_unlock(&chip_data->rlock);
589 static struct syscore_ops stm32_exti_h_syscore_ops = {
590 #ifdef CONFIG_PM_SLEEP
591 .suspend = stm32_exti_h_suspend,
592 .resume = stm32_exti_h_resume,
596 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
598 stm32_host_data = host_data;
599 register_syscore_ops(&stm32_exti_h_syscore_ops);
602 static void stm32_exti_h_syscore_deinit(void)
604 unregister_syscore_ops(&stm32_exti_h_syscore_ops);
607 static int stm32_exti_h_retrigger(struct irq_data *d)
609 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
610 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
611 void __iomem *base = chip_data->host_data->base;
612 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
614 writel_relaxed(mask, base + stm32_bank->swier_ofst);
619 static struct irq_chip stm32_exti_h_chip = {
620 .name = "stm32-exti-h",
621 .irq_eoi = stm32_exti_h_eoi,
622 .irq_mask = stm32_exti_h_mask,
623 .irq_unmask = stm32_exti_h_unmask,
624 .irq_retrigger = stm32_exti_h_retrigger,
625 .irq_set_type = stm32_exti_h_set_type,
626 .irq_set_wake = stm32_exti_h_set_wake,
627 .flags = IRQCHIP_MASK_ON_SUSPEND,
628 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
631 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
633 unsigned int nr_irqs, void *data)
635 struct stm32_exti_host_data *host_data = dm->host_data;
636 struct stm32_exti_chip_data *chip_data;
637 struct irq_fwspec *fwspec = data;
638 struct irq_fwspec p_fwspec;
639 irq_hw_number_t hwirq;
642 hwirq = fwspec->param[0];
643 bank = hwirq / IRQS_PER_BANK;
644 chip_data = &host_data->chips_data[bank];
646 irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
647 &stm32_exti_h_chip, chip_data);
649 p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
651 p_fwspec.fwnode = dm->parent->fwnode;
652 p_fwspec.param_count = 3;
653 p_fwspec.param[0] = GIC_SPI;
654 p_fwspec.param[1] = p_irq;
655 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
657 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
664 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
665 struct device_node *node)
667 struct stm32_exti_host_data *host_data;
669 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
673 host_data->drv_data = dd;
674 host_data->chips_data = kcalloc(dd->bank_nr,
675 sizeof(struct stm32_exti_chip_data),
677 if (!host_data->chips_data)
680 host_data->base = of_iomap(node, 0);
681 if (!host_data->base) {
682 pr_err("%pOF: Unable to map registers\n", node);
683 goto free_chips_data;
686 stm32_host_data = host_data;
691 kfree(host_data->chips_data);
699 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
701 struct device_node *node)
703 const struct stm32_exti_bank *stm32_bank;
704 struct stm32_exti_chip_data *chip_data;
705 void __iomem *base = h_data->base;
707 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
708 chip_data = &h_data->chips_data[bank_idx];
709 chip_data->host_data = h_data;
710 chip_data->reg_bank = stm32_bank;
712 raw_spin_lock_init(&chip_data->rlock);
715 * This IP has no reset, so after hot reboot we should
716 * clear registers to avoid residue
718 writel_relaxed(0, base + stm32_bank->imr_ofst);
719 writel_relaxed(0, base + stm32_bank->emr_ofst);
721 pr_info("%pOF: bank%d\n", node, bank_idx);
726 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
727 struct device_node *node)
729 struct stm32_exti_host_data *host_data;
730 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
732 struct irq_chip_generic *gc;
733 struct irq_domain *domain;
735 host_data = stm32_exti_host_init(drv_data, node);
739 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
740 &irq_exti_domain_ops, NULL);
742 pr_err("%pOFn: Could not register interrupt domain.\n",
748 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
749 handle_edge_irq, clr, 0, 0);
751 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
753 goto out_free_domain;
756 for (i = 0; i < drv_data->bank_nr; i++) {
757 const struct stm32_exti_bank *stm32_bank;
758 struct stm32_exti_chip_data *chip_data;
760 stm32_bank = drv_data->exti_banks[i];
761 chip_data = stm32_exti_chip_init(host_data, i, node);
763 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
765 gc->reg_base = host_data->base;
766 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
767 gc->chip_types->chip.irq_ack = stm32_irq_ack;
768 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
769 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
770 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
771 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
772 gc->suspend = stm32_irq_suspend;
773 gc->resume = stm32_irq_resume;
774 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
776 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
777 gc->private = (void *)chip_data;
780 nr_irqs = of_irq_count(node);
781 for (i = 0; i < nr_irqs; i++) {
782 unsigned int irq = irq_of_parse_and_map(node, i);
784 irq_set_handler_data(irq, domain);
785 irq_set_chained_handler(irq, stm32_irq_handler);
791 irq_domain_remove(domain);
793 iounmap(host_data->base);
794 kfree(host_data->chips_data);
799 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
800 .alloc = stm32_exti_h_domain_alloc,
801 .free = irq_domain_free_irqs_common,
802 .xlate = irq_domain_xlate_twocell,
805 static void stm32_exti_remove_irq(void *data)
807 struct irq_domain *domain = data;
809 irq_domain_remove(domain);
812 static int stm32_exti_remove(struct platform_device *pdev)
814 stm32_exti_h_syscore_deinit();
818 static int stm32_exti_probe(struct platform_device *pdev)
821 struct device *dev = &pdev->dev;
822 struct device_node *np = dev->of_node;
823 struct irq_domain *parent_domain, *domain;
824 struct stm32_exti_host_data *host_data;
825 const struct stm32_exti_drv_data *drv_data;
826 struct resource *res;
828 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
832 /* check for optional hwspinlock which may be not available yet */
833 ret = of_hwspin_lock_get_id(np, 0);
834 if (ret == -EPROBE_DEFER)
835 /* hwspinlock framework not yet ready */
839 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
840 if (!host_data->hwlock) {
841 dev_err(dev, "Failed to request hwspinlock\n");
844 } else if (ret != -ENOENT) {
845 /* note: ENOENT is a valid case (means 'no hwspinlock') */
846 dev_err(dev, "Failed to get hwspinlock\n");
850 /* initialize host_data */
851 drv_data = of_device_get_match_data(dev);
853 dev_err(dev, "no of match data\n");
856 host_data->drv_data = drv_data;
858 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
859 sizeof(*host_data->chips_data),
861 if (!host_data->chips_data)
864 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
865 host_data->base = devm_ioremap_resource(dev, res);
866 if (IS_ERR(host_data->base)) {
867 dev_err(dev, "Unable to map registers\n");
868 return PTR_ERR(host_data->base);
871 for (i = 0; i < drv_data->bank_nr; i++)
872 stm32_exti_chip_init(host_data, i, np);
874 parent_domain = irq_find_host(of_irq_find_parent(np));
875 if (!parent_domain) {
876 dev_err(dev, "GIC interrupt-parent not found\n");
880 domain = irq_domain_add_hierarchy(parent_domain, 0,
881 drv_data->bank_nr * IRQS_PER_BANK,
882 np, &stm32_exti_h_domain_ops,
886 dev_err(dev, "Could not register exti domain\n");
890 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
894 stm32_exti_h_syscore_init(host_data);
899 /* platform driver only for MP1 */
900 static const struct of_device_id stm32_exti_ids[] = {
901 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
904 MODULE_DEVICE_TABLE(of, stm32_exti_ids);
906 static struct platform_driver stm32_exti_driver = {
907 .probe = stm32_exti_probe,
908 .remove = stm32_exti_remove,
910 .name = "stm32_exti",
911 .of_match_table = stm32_exti_ids,
915 static int __init stm32_exti_arch_init(void)
917 return platform_driver_register(&stm32_exti_driver);
920 static void __exit stm32_exti_arch_exit(void)
922 return platform_driver_unregister(&stm32_exti_driver);
925 arch_initcall(stm32_exti_arch_init);
926 module_exit(stm32_exti_arch_exit);
928 /* no platform driver for F4 and H7 */
929 static int __init stm32f4_exti_of_init(struct device_node *np,
930 struct device_node *parent)
932 return stm32_exti_init(&stm32f4xx_drv_data, np);
935 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
937 static int __init stm32h7_exti_of_init(struct device_node *np,
938 struct device_node *parent)
940 return stm32_exti_init(&stm32h7xx_drv_data, np);
943 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);