drivers/irqchip/irq-sifive-plic.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 SiFive
   4  * Copyright (C) 2018 Christoph Hellwig
   5  */
   6 #define pr_fmt(fmt) "plic: " fmt
   7 #include <linux/cpu.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/irq.h>
  11 #include <linux/irqchip.h>
  12 #include <linux/irqchip/chained_irq.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spinlock.h>
  20 #include <asm/smp.h>
  21
  22 /*
  23  * This driver implements a version of the RISC-V PLIC with the actual layout
  24  * specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
  25  *
  26  *     https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
  27  *
  28  * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
  29  * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
  30  * Spec.
  31  */
  32
  33 #define MAX_DEVICES                     1024
  34 #define MAX_CONTEXTS                    15872
  35
  36 /*
  37  * Each interrupt source has a priority register associated with it.
  38  * We always hardwire it to one in Linux.
  39  */
  40 #define PRIORITY_BASE                   0
  41 #define     PRIORITY_PER_ID             4
  42
  43 /*
  44  * Each hart context has a vector of interrupt enable bits associated with it.
  45  * There's one bit for each interrupt source.
  46  */
  47 #define CONTEXT_ENABLE_BASE             0x2000
  48 #define     CONTEXT_ENABLE_SIZE         0x80
  49
  50 /*
  51  * Each hart context has a set of control registers associated with it.  Right
  52  * now there's only two: a source priority threshold over which the hart will
  53  * take an interrupt, and a register to claim interrupts.
  54  */
  55 #define CONTEXT_BASE                    0x200000
  56 #define     CONTEXT_SIZE                0x1000
  57 #define     CONTEXT_THRESHOLD           0x00
  58 #define     CONTEXT_CLAIM               0x04
  59
  60 #define PLIC_DISABLE_THRESHOLD          0x7
  61 #define PLIC_ENABLE_THRESHOLD           0
  62
  63 #define PLIC_QUIRK_EDGE_INTERRUPT       0
  64
  65 struct plic_priv {
  66         struct cpumask lmask;
  67         struct irq_domain *irqdomain;
  68         void __iomem *regs;
  69         unsigned long plic_quirks;
  70 };
  71
  72 struct plic_handler {
  73         bool                    present;
  74         void __iomem            *hart_base;
  75         /*
  76          * Protect mask operations on the registers given that we can't
  77          * assume atomic memory operations work on them.
  78          */
  79         raw_spinlock_t          enable_lock;
  80         void __iomem            *enable_base;
  81         struct plic_priv        *priv;
  82 };
  83 static int plic_parent_irq __ro_after_init;
  84 static bool plic_cpuhp_setup_done __ro_after_init;
  85 static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
  86
  87 static int plic_irq_set_type(struct irq_data *d, unsigned int type);
  88
  89 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
  90 {
  91         u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
  92         u32 hwirq_mask = 1 << (hwirq % 32);
  93
  94         if (enable)
  95                 writel(readl(reg) | hwirq_mask, reg);
  96         else
  97                 writel(readl(reg) & ~hwirq_mask, reg);
  98 }
  99
 100 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
 101 {
 102         raw_spin_lock(&handler->enable_lock);
 103         __plic_toggle(handler->enable_base, hwirq, enable);
 104         raw_spin_unlock(&handler->enable_lock);
 105 }
 106
 107 static inline void plic_irq_toggle(const struct cpumask *mask,
 108                                    struct irq_data *d, int enable)
 109 {
 110         int cpu;
 111         struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 112
 113         writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
 114         for_each_cpu(cpu, mask) {
 115                 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
 116
 117                 if (handler->present &&
 118                     cpumask_test_cpu(cpu, &handler->priv->lmask))
 119                         plic_toggle(handler, d->hwirq, enable);
 120         }
 121 }
 122
 123 static void plic_irq_unmask(struct irq_data *d)
 124 {
 125         struct cpumask amask;
 126         unsigned int cpu;
 127         struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 128
 129         cpumask_and(&amask, &priv->lmask, cpu_online_mask);
 130         cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
 131                                            &amask);
 132         if (WARN_ON_ONCE(cpu >= nr_cpu_ids))
 133                 return;
 134         plic_irq_toggle(cpumask_of(cpu), d, 1);
 135 }
 136
 137 static void plic_irq_mask(struct irq_data *d)
 138 {
 139         struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 140
 141         plic_irq_toggle(&priv->lmask, d, 0);
 142 }
 143
 144 #ifdef CONFIG_SMP
 145 static int plic_set_affinity(struct irq_data *d,
 146                              const struct cpumask *mask_val, bool force)
 147 {
 148         unsigned int cpu;
 149         struct cpumask amask;
 150         struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 151
 152         cpumask_and(&amask, &priv->lmask, mask_val);
 153
 154         if (force)
 155                 cpu = cpumask_first(&amask);
 156         else
 157                 cpu = cpumask_any_and(&amask, cpu_online_mask);
 158
 159         if (cpu >= nr_cpu_ids)
 160                 return -EINVAL;
 161
 162         plic_irq_toggle(&priv->lmask, d, 0);
 163         plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d));
 164
 165         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 166
 167         return IRQ_SET_MASK_OK_DONE;
 168 }
 169 #endif
 170
 171 static void plic_irq_eoi(struct irq_data *d)
 172 {
 173         struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
 174
 175         if (irqd_irq_masked(d)) {
 176                 plic_irq_unmask(d);
 177                 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
 178                 plic_irq_mask(d);
 179         } else {
 180                 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
 181         }
 182 }
 183
 184 static struct irq_chip plic_edge_chip = {
 185         .name           = "SiFive PLIC",
 186         .irq_ack        = plic_irq_eoi,
 187         .irq_mask       = plic_irq_mask,
 188         .irq_unmask     = plic_irq_unmask,
 189 #ifdef CONFIG_SMP
 190         .irq_set_affinity = plic_set_affinity,
 191 #endif
 192         .irq_set_type   = plic_irq_set_type,
 193 };
 194
 195 static struct irq_chip plic_chip = {
 196         .name           = "SiFive PLIC",
 197         .irq_mask       = plic_irq_mask,
 198         .irq_unmask     = plic_irq_unmask,
 199         .irq_eoi        = plic_irq_eoi,
 200 #ifdef CONFIG_SMP
 201         .irq_set_affinity = plic_set_affinity,
 202 #endif
 203         .irq_set_type   = plic_irq_set_type,
 204 };
 205
 206 static int plic_irq_set_type(struct irq_data *d, unsigned int type)
 207 {
 208         struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 209
 210         if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
 211                 return IRQ_SET_MASK_OK_NOCOPY;
 212
 213         switch (type) {
 214         case IRQ_TYPE_EDGE_RISING:
 215                 irq_set_chip_handler_name_locked(d, &plic_edge_chip,
 216                                                  handle_edge_irq, NULL);
 217                 break;
 218         case IRQ_TYPE_LEVEL_HIGH:
 219                 irq_set_chip_handler_name_locked(d, &plic_chip,
 220                                                  handle_fasteoi_irq, NULL);
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         return IRQ_SET_MASK_OK;
 227 }
 228
 229 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 230                               irq_hw_number_t hwirq)
 231 {
 232         struct plic_priv *priv = d->host_data;
 233
 234         irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
 235                             handle_fasteoi_irq, NULL, NULL);
 236         irq_set_noprobe(irq);
 237         irq_set_affinity(irq, &priv->lmask);
 238         return 0;
 239 }
 240
 241 static int plic_irq_domain_translate(struct irq_domain *d,
 242                                      struct irq_fwspec *fwspec,
 243                                      unsigned long *hwirq,
 244                                      unsigned int *type)
 245 {
 246         struct plic_priv *priv = d->host_data;
 247
 248         if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
 249                 return irq_domain_translate_twocell(d, fwspec, hwirq, type);
 250
 251         return irq_domain_translate_onecell(d, fwspec, hwirq, type);
 252 }
 253
 254 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 255                                  unsigned int nr_irqs, void *arg)
 256 {
 257         int i, ret;
 258         irq_hw_number_t hwirq;
 259         unsigned int type;
 260         struct irq_fwspec *fwspec = arg;
 261
 262         ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
 263         if (ret)
 264                 return ret;
 265
 266         for (i = 0; i < nr_irqs; i++) {
 267                 ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
 268                 if (ret)
 269                         return ret;
 270         }
 271
 272         return 0;
 273 }
 274
 275 static const struct irq_domain_ops plic_irqdomain_ops = {
 276         .translate      = plic_irq_domain_translate,
 277         .alloc          = plic_irq_domain_alloc,
 278         .free           = irq_domain_free_irqs_top,
 279 };
 280
 281 /*
 282  * Handling an interrupt is a two-step process: first you claim the interrupt
 283  * by reading the claim register, then you complete the interrupt by writing
 284  * that source ID back to the same claim register.  This automatically enables
 285  * and disables the interrupt, so there's nothing else to do.
 286  */
 287 static void plic_handle_irq(struct irq_desc *desc)
 288 {
 289         struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
 290         struct irq_chip *chip = irq_desc_get_chip(desc);
 291         void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
 292         irq_hw_number_t hwirq;
 293
 294         WARN_ON_ONCE(!handler->present);
 295
 296         chained_irq_enter(chip, desc);
 297
 298         while ((hwirq = readl(claim))) {
 299                 int err = generic_handle_domain_irq(handler->priv->irqdomain,
 300                                                     hwirq);
 301                 if (unlikely(err))
 302                         pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
 303                                         hwirq);
 304         }
 305
 306         chained_irq_exit(chip, desc);
 307 }
 308
 309 static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
 310 {
 311         /* priority must be > threshold to trigger an interrupt */
 312         writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
 313 }
 314
 315 static int plic_dying_cpu(unsigned int cpu)
 316 {
 317         if (plic_parent_irq)
 318                 disable_percpu_irq(plic_parent_irq);
 319
 320         return 0;
 321 }
 322
 323 static int plic_starting_cpu(unsigned int cpu)
 324 {
 325         struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
 326
 327         if (plic_parent_irq)
 328                 enable_percpu_irq(plic_parent_irq,
 329                                   irq_get_trigger_type(plic_parent_irq));
 330         else
 331                 pr_warn("cpu%d: parent irq not available\n", cpu);
 332         plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD);
 333
 334         return 0;
 335 }
 336
 337 static int __init __plic_init(struct device_node *node,
 338                               struct device_node *parent,
 339                               unsigned long plic_quirks)
 340 {
 341         int error = 0, nr_contexts, nr_handlers = 0, i;
 342         u32 nr_irqs;
 343         struct plic_priv *priv;
 344         struct plic_handler *handler;
 345
 346         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 347         if (!priv)
 348                 return -ENOMEM;
 349
 350         priv->plic_quirks = plic_quirks;
 351
 352         priv->regs = of_iomap(node, 0);
 353         if (WARN_ON(!priv->regs)) {
 354                 error = -EIO;
 355                 goto out_free_priv;
 356         }
 357
 358         error = -EINVAL;
 359         of_property_read_u32(node, "riscv,ndev", &nr_irqs);
 360         if (WARN_ON(!nr_irqs))
 361                 goto out_iounmap;
 362
 363         nr_contexts = of_irq_count(node);
 364         if (WARN_ON(!nr_contexts))
 365                 goto out_iounmap;
 366
 367         error = -ENOMEM;
 368         priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
 369                         &plic_irqdomain_ops, priv);
 370         if (WARN_ON(!priv->irqdomain))
 371                 goto out_iounmap;
 372
 373         for (i = 0; i < nr_contexts; i++) {
 374                 struct of_phandle_args parent;
 375                 irq_hw_number_t hwirq;
 376                 int cpu, hartid;
 377
 378                 if (of_irq_parse_one(node, i, &parent)) {
 379                         pr_err("failed to parse parent for context %d.\n", i);
 380                         continue;
 381                 }
 382
 383                 /*
 384                  * Skip contexts other than external interrupts for our
 385                  * privilege level.
 386                  */
 387                 if (parent.args[0] != RV_IRQ_EXT) {
 388                         /* Disable S-mode enable bits if running in M-mode. */
 389                         if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
 390                                 void __iomem *enable_base = priv->regs +
 391                                         CONTEXT_ENABLE_BASE +
 392                                         i * CONTEXT_ENABLE_SIZE;
 393
 394                                 for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
 395                                         __plic_toggle(enable_base, hwirq, 0);
 396                         }
 397                         continue;
 398                 }
 399
 400                 hartid = riscv_of_parent_hartid(parent.np);
 401                 if (hartid < 0) {
 402                         pr_warn("failed to parse hart ID for context %d.\n", i);
 403                         continue;
 404                 }
 405
 406                 cpu = riscv_hartid_to_cpuid(hartid);
 407                 if (cpu < 0) {
 408                         pr_warn("Invalid cpuid for context %d\n", i);
 409                         continue;
 410                 }
 411
 412                 /* Find parent domain and register chained handler */
 413                 if (!plic_parent_irq && irq_find_host(parent.np)) {
 414                         plic_parent_irq = irq_of_parse_and_map(node, i);
 415                         if (plic_parent_irq)
 416                                 irq_set_chained_handler(plic_parent_irq,
 417                                                         plic_handle_irq);
 418                 }
 419
 420                 /*
 421                  * When running in M-mode we need to ignore the S-mode handler.
 422                  * Here we assume it always comes later, but that might be a
 423                  * little fragile.
 424                  */
 425                 handler = per_cpu_ptr(&plic_handlers, cpu);
 426                 if (handler->present) {
 427                         pr_warn("handler already present for context %d.\n", i);
 428                         plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
 429                         goto done;
 430                 }
 431
 432                 cpumask_set_cpu(cpu, &priv->lmask);
 433                 handler->present = true;
 434                 handler->hart_base = priv->regs + CONTEXT_BASE +
 435                         i * CONTEXT_SIZE;
 436                 raw_spin_lock_init(&handler->enable_lock);
 437                 handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
 438                         i * CONTEXT_ENABLE_SIZE;
 439                 handler->priv = priv;
 440 done:
 441                 for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
 442                         plic_toggle(handler, hwirq, 0);
 443                 nr_handlers++;
 444         }
 445
 446         /*
 447          * We can have multiple PLIC instances so setup cpuhp state only
 448          * when context handler for current/boot CPU is present.
 449          */
 450         handler = this_cpu_ptr(&plic_handlers);
 451         if (handler->present && !plic_cpuhp_setup_done) {
 452                 cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
 453                                   "irqchip/sifive/plic:starting",
 454                                   plic_starting_cpu, plic_dying_cpu);
 455                 plic_cpuhp_setup_done = true;
 456         }
 457
 458         pr_info("%pOFP: mapped %d interrupts with %d handlers for"
 459                 " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
 460         return 0;
 461
 462 out_iounmap:
 463         iounmap(priv->regs);
 464 out_free_priv:
 465         kfree(priv);
 466         return error;
 467 }
 468
 469 static int __init plic_init(struct device_node *node,
 470                             struct device_node *parent)
 471 {
 472         return __plic_init(node, parent, 0);
 473 }
 474
 475 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
 476 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
 477
 478 static int __init plic_edge_init(struct device_node *node,
 479                                  struct device_node *parent)
 480 {
 481         return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT));
 482 }
 483
 484 IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
 485 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);