1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
4 * Loongson PCH PIC support
7 #define pr_fmt(fmt) "pch-pic: " fmt
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/irqchip.h>
12 #include <linux/irqdomain.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
20 #define PCH_PIC_MASK 0x20
21 #define PCH_PIC_HTMSI_EN 0x40
22 #define PCH_PIC_EDGE 0x60
23 #define PCH_PIC_CLR 0x80
24 #define PCH_PIC_AUTO0 0xc0
25 #define PCH_PIC_AUTO1 0xe0
26 #define PCH_INT_ROUTE(irq) (0x100 + irq)
27 #define PCH_INT_HTVEC(irq) (0x200 + irq)
28 #define PCH_PIC_POL 0x3e0
30 #define PIC_COUNT_PER_REG 32
31 #define PIC_REG_COUNT 2
32 #define PIC_COUNT (PIC_COUNT_PER_REG * PIC_REG_COUNT)
33 #define PIC_REG_IDX(irq_id) ((irq_id) / PIC_COUNT_PER_REG)
34 #define PIC_REG_BIT(irq_id) ((irq_id) % PIC_COUNT_PER_REG)
38 struct irq_domain *pic_domain;
40 raw_spinlock_t pic_lock;
43 static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
46 void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4;
48 raw_spin_lock(&priv->pic_lock);
50 reg |= BIT(PIC_REG_BIT(bit));
52 raw_spin_unlock(&priv->pic_lock);
55 static void pch_pic_bitclr(struct pch_pic *priv, int offset, int bit)
58 void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4;
60 raw_spin_lock(&priv->pic_lock);
62 reg &= ~BIT(PIC_REG_BIT(bit));
64 raw_spin_unlock(&priv->pic_lock);
67 static void pch_pic_mask_irq(struct irq_data *d)
69 struct pch_pic *priv = irq_data_get_irq_chip_data(d);
71 pch_pic_bitset(priv, PCH_PIC_MASK, d->hwirq);
72 irq_chip_mask_parent(d);
75 static void pch_pic_unmask_irq(struct irq_data *d)
77 struct pch_pic *priv = irq_data_get_irq_chip_data(d);
79 writel(BIT(PIC_REG_BIT(d->hwirq)),
80 priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4);
82 irq_chip_unmask_parent(d);
83 pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq);
86 static int pch_pic_set_type(struct irq_data *d, unsigned int type)
88 struct pch_pic *priv = irq_data_get_irq_chip_data(d);
92 case IRQ_TYPE_EDGE_RISING:
93 pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);
94 pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);
96 case IRQ_TYPE_EDGE_FALLING:
97 pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq);
98 pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);
100 case IRQ_TYPE_LEVEL_HIGH:
101 pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);
102 pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq);
104 case IRQ_TYPE_LEVEL_LOW:
105 pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq);
106 pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq);
116 static struct irq_chip pch_pic_irq_chip = {
118 .irq_mask = pch_pic_mask_irq,
119 .irq_unmask = pch_pic_unmask_irq,
120 .irq_ack = irq_chip_ack_parent,
121 .irq_set_affinity = irq_chip_set_affinity_parent,
122 .irq_set_type = pch_pic_set_type,
125 static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
126 unsigned int nr_irqs, void *arg)
131 struct irq_fwspec *fwspec = arg;
132 struct irq_fwspec parent_fwspec;
133 struct pch_pic *priv = domain->host_data;
135 err = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
139 parent_fwspec.fwnode = domain->parent->fwnode;
140 parent_fwspec.param_count = 1;
141 parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
143 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
147 irq_domain_set_info(domain, virq, hwirq,
148 &pch_pic_irq_chip, priv,
149 handle_level_irq, NULL, NULL);
155 static const struct irq_domain_ops pch_pic_domain_ops = {
156 .translate = irq_domain_translate_twocell,
157 .alloc = pch_pic_alloc,
158 .free = irq_domain_free_irqs_parent,
161 static void pch_pic_reset(struct pch_pic *priv)
165 for (i = 0; i < PIC_COUNT; i++) {
166 /* Write vectored ID */
167 writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
168 /* Hardcode route to HT0 Lo */
169 writeb(1, priv->base + PCH_INT_ROUTE(i));
172 for (i = 0; i < PIC_REG_COUNT; i++) {
173 /* Clear IRQ cause registers, mask all interrupts */
174 writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_MASK + 4 * i);
175 writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_CLR + 4 * i);
176 /* Clear auto bounce, we don't need that */
177 writel_relaxed(0, priv->base + PCH_PIC_AUTO0 + 4 * i);
178 writel_relaxed(0, priv->base + PCH_PIC_AUTO1 + 4 * i);
179 /* Enable HTMSI transformer */
180 writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_HTMSI_EN + 4 * i);
184 static int pch_pic_of_init(struct device_node *node,
185 struct device_node *parent)
187 struct pch_pic *priv;
188 struct irq_domain *parent_domain;
191 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
195 raw_spin_lock_init(&priv->pic_lock);
196 priv->base = of_iomap(node, 0);
202 parent_domain = irq_find_host(parent);
203 if (!parent_domain) {
204 pr_err("Failed to find the parent domain\n");
209 if (of_property_read_u32(node, "loongson,pic-base-vec",
210 &priv->ht_vec_base)) {
211 pr_err("Failed to determine pic-base-vec\n");
216 priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
218 of_node_to_fwnode(node),
221 if (!priv->pic_domain) {
222 pr_err("Failed to create IRQ domain\n");
239 IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init);