drivers/irqchip/irq-loongson-liointc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
   4  *  Loongson Local IO Interrupt Controller support
   5  */
   6
   7 #include <linux/errno.h>
   8 #include <linux/init.h>
   9 #include <linux/types.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/ioport.h>
  12 #include <linux/irqchip.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/io.h>
  16 #include <linux/smp.h>
  17 #include <linux/irqchip/chained_irq.h>
  18
  19 #ifdef CONFIG_MIPS
  20 #include <loongson.h>
  21 #else
  22 #include <asm/loongson.h>
  23 #endif
  24
  25 #define LIOINTC_CHIP_IRQ        32
  26 #define LIOINTC_NUM_PARENT 4
  27 #define LIOINTC_NUM_CORES       4
  28
  29 #define LIOINTC_INTC_CHIP_START 0x20
  30
  31 #define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
  32 #define LIOINTC_REG_INTC_EN_STATUS      (LIOINTC_INTC_CHIP_START + 0x04)
  33 #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
  34 #define LIOINTC_REG_INTC_DISABLE        (LIOINTC_INTC_CHIP_START + 0x0c)
  35 #define LIOINTC_REG_INTC_POL    (LIOINTC_INTC_CHIP_START + 0x10)
  36 #define LIOINTC_REG_INTC_EDGE   (LIOINTC_INTC_CHIP_START + 0x14)
  37
  38 #define LIOINTC_SHIFT_INTx      4
  39
  40 #define LIOINTC_ERRATA_IRQ      10
  41
  42 #if defined(CONFIG_MIPS)
  43 #define liointc_core_id get_ebase_cpunum()
  44 #else
  45 #define liointc_core_id get_csr_cpuid()
  46 #endif
  47
  48 struct liointc_handler_data {
  49         struct liointc_priv     *priv;
  50         u32                     parent_int_map;
  51 };
  52
  53 struct liointc_priv {
  54         struct irq_chip_generic         *gc;
  55         struct liointc_handler_data     handler[LIOINTC_NUM_PARENT];
  56         void __iomem                    *core_isr[LIOINTC_NUM_CORES];
  57         u8                              map_cache[LIOINTC_CHIP_IRQ];
  58         bool                            has_lpc_irq_errata;
  59 };
  60
  61 static void liointc_chained_handle_irq(struct irq_desc *desc)
  62 {
  63         struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
  64         struct irq_chip *chip = irq_desc_get_chip(desc);
  65         struct irq_chip_generic *gc = handler->priv->gc;
  66         int core = liointc_core_id % LIOINTC_NUM_CORES;
  67         u32 pending;
  68
  69         chained_irq_enter(chip, desc);
  70
  71         pending = readl(handler->priv->core_isr[core]);
  72
  73         if (!pending) {
  74                 /* Always blame LPC IRQ if we have that bug */
  75                 if (handler->priv->has_lpc_irq_errata &&
  76                         (handler->parent_int_map & gc->mask_cache &
  77                         BIT(LIOINTC_ERRATA_IRQ)))
  78                         pending = BIT(LIOINTC_ERRATA_IRQ);
  79                 else
  80                         spurious_interrupt();
  81         }
  82
  83         while (pending) {
  84                 int bit = __ffs(pending);
  85
  86                 generic_handle_domain_irq(gc->domain, bit);
  87                 pending &= ~BIT(bit);
  88         }
  89
  90         chained_irq_exit(chip, desc);
  91 }
  92
  93 static void liointc_set_bit(struct irq_chip_generic *gc,
  94                                 unsigned int offset,
  95                                 u32 mask, bool set)
  96 {
  97         if (set)
  98                 writel(readl(gc->reg_base + offset) | mask,
  99                                 gc->reg_base + offset);
 100         else
 101                 writel(readl(gc->reg_base + offset) & ~mask,
 102                                 gc->reg_base + offset);
 103 }
 104
 105 static int liointc_set_type(struct irq_data *data, unsigned int type)
 106 {
 107         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
 108         u32 mask = data->mask;
 109         unsigned long flags;
 110
 111         irq_gc_lock_irqsave(gc, flags);
 112         switch (type) {
 113         case IRQ_TYPE_LEVEL_HIGH:
 114                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
 115                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
 116                 break;
 117         case IRQ_TYPE_LEVEL_LOW:
 118                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
 119                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
 120                 break;
 121         case IRQ_TYPE_EDGE_RISING:
 122                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
 123                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
 124                 break;
 125         case IRQ_TYPE_EDGE_FALLING:
 126                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
 127                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
 128                 break;
 129         default:
 130                 irq_gc_unlock_irqrestore(gc, flags);
 131                 return -EINVAL;
 132         }
 133         irq_gc_unlock_irqrestore(gc, flags);
 134
 135         irqd_set_trigger_type(data, type);
 136         return 0;
 137 }
 138
 139 static void liointc_resume(struct irq_chip_generic *gc)
 140 {
 141         struct liointc_priv *priv = gc->private;
 142         unsigned long flags;
 143         int i;
 144
 145         irq_gc_lock_irqsave(gc, flags);
 146         /* Disable all at first */
 147         writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
 148         /* Restore map cache */
 149         for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
 150                 writeb(priv->map_cache[i], gc->reg_base + i);
 151         /* Restore mask cache */
 152         writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
 153         irq_gc_unlock_irqrestore(gc, flags);
 154 }
 155
 156 static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
 157 static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
 158
 159 static void __iomem *liointc_get_reg_byname(struct device_node *node,
 160                                                 const char *name)
 161 {
 162         int index = of_property_match_string(node, "reg-names", name);
 163
 164         if (index < 0)
 165                 return NULL;
 166
 167         return of_iomap(node, index);
 168 }
 169
 170 static int __init liointc_of_init(struct device_node *node,
 171                                   struct device_node *parent)
 172 {
 173         struct irq_chip_generic *gc;
 174         struct irq_domain *domain;
 175         struct irq_chip_type *ct;
 176         struct liointc_priv *priv;
 177         void __iomem *base;
 178         u32 of_parent_int_map[LIOINTC_NUM_PARENT];
 179         int parent_irq[LIOINTC_NUM_PARENT];
 180         bool have_parent = FALSE;
 181         int sz, i, err = 0;
 182
 183         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 184         if (!priv)
 185                 return -ENOMEM;
 186
 187         if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
 188                 base = liointc_get_reg_byname(node, "main");
 189                 if (!base) {
 190                         err = -ENODEV;
 191                         goto out_free_priv;
 192                 }
 193
 194                 for (i = 0; i < LIOINTC_NUM_CORES; i++)
 195                         priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
 196                 if (!priv->core_isr[0]) {
 197                         err = -ENODEV;
 198                         goto out_iounmap_base;
 199                 }
 200         } else {
 201                 base = of_iomap(node, 0);
 202                 if (!base) {
 203                         err = -ENODEV;
 204                         goto out_free_priv;
 205                 }
 206
 207                 for (i = 0; i < LIOINTC_NUM_CORES; i++)
 208                         priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
 209         }
 210
 211         for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
 212                 parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
 213                 if (parent_irq[i] > 0)
 214                         have_parent = TRUE;
 215         }
 216         if (!have_parent) {
 217                 err = -ENODEV;
 218                 goto out_iounmap_isr;
 219         }
 220
 221         sz = of_property_read_variable_u32_array(node,
 222                                                 "loongson,parent_int_map",
 223                                                 &of_parent_int_map[0],
 224                                                 LIOINTC_NUM_PARENT,
 225                                                 LIOINTC_NUM_PARENT);
 226         if (sz < 4) {
 227                 pr_err("loongson-liointc: No parent_int_map\n");
 228                 err = -ENODEV;
 229                 goto out_iounmap_isr;
 230         }
 231
 232         for (i = 0; i < LIOINTC_NUM_PARENT; i++)
 233                 priv->handler[i].parent_int_map = of_parent_int_map[i];
 234
 235         /* Setup IRQ domain */
 236         domain = irq_domain_add_linear(node, 32,
 237                                         &irq_generic_chip_ops, priv);
 238         if (!domain) {
 239                 pr_err("loongson-liointc: cannot add IRQ domain\n");
 240                 err = -EINVAL;
 241                 goto out_iounmap_isr;
 242         }
 243
 244         err = irq_alloc_domain_generic_chips(domain, 32, 1,
 245                                         node->full_name, handle_level_irq,
 246                                         IRQ_NOPROBE, 0, 0);
 247         if (err) {
 248                 pr_err("loongson-liointc: unable to register IRQ domain\n");
 249                 goto out_free_domain;
 250         }
 251
 252
 253         /* Disable all IRQs */
 254         writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
 255         /* Set to level triggered */
 256         writel(0x0, base + LIOINTC_REG_INTC_EDGE);
 257
 258         /* Generate parent INT part of map cache */
 259         for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
 260                 u32 pending = priv->handler[i].parent_int_map;
 261
 262                 while (pending) {
 263                         int bit = __ffs(pending);
 264
 265                         priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
 266                         pending &= ~BIT(bit);
 267                 }
 268         }
 269
 270         for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
 271                 /* Generate core part of map cache */
 272                 priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
 273                 writeb(priv->map_cache[i], base + i);
 274         }
 275
 276         gc = irq_get_domain_generic_chip(domain, 0);
 277         gc->private = priv;
 278         gc->reg_base = base;
 279         gc->domain = domain;
 280         gc->resume = liointc_resume;
 281
 282         ct = gc->chip_types;
 283         ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
 284         ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
 285         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 286         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 287         ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
 288         ct->chip.irq_set_type = liointc_set_type;
 289
 290         gc->mask_cache = 0;
 291         priv->gc = gc;
 292
 293         for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
 294                 if (parent_irq[i] <= 0)
 295                         continue;
 296
 297                 priv->handler[i].priv = priv;
 298                 irq_set_chained_handler_and_data(parent_irq[i],
 299                                 liointc_chained_handle_irq, &priv->handler[i]);
 300         }
 301
 302         return 0;
 303
 304 out_free_domain:
 305         irq_domain_remove(domain);
 306 out_iounmap_isr:
 307         for (i = 0; i < LIOINTC_NUM_CORES; i++) {
 308                 if (!priv->core_isr[i])
 309                         continue;
 310                 iounmap(priv->core_isr[i]);
 311         }
 312 out_iounmap_base:
 313         iounmap(base);
 314 out_free_priv:
 315         kfree(priv);
 316
 317         return err;
 318 }
 319
 320 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
 321 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
 322 IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);