1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
4 * Loongson HyperTransport Interrupt Vector support
7 #define pr_fmt(fmt) "htvec: " fmt
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/irqchip.h>
12 #include <linux/irqdomain.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/syscore_ops.h>
22 #define HTVEC_EN_OFF 0x20
23 #define HTVEC_MAX_PARENT_IRQ 8
24 #define VEC_COUNT_PER_REG 32
25 #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
26 #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
31 struct irq_domain *htvec_domain;
32 raw_spinlock_t htvec_lock;
33 u32 saved_vec_en[HTVEC_MAX_PARENT_IRQ];
36 static struct htvec *htvec_priv;
38 static void htvec_irq_dispatch(struct irq_desc *desc)
43 struct irq_chip *chip = irq_desc_get_chip(desc);
44 struct htvec *priv = irq_desc_get_handler_data(desc);
46 chained_irq_enter(chip, desc);
48 for (i = 0; i < priv->num_parents; i++) {
49 pending = readl(priv->base + 4 * i);
51 int bit = __ffs(pending);
53 generic_handle_domain_irq(priv->htvec_domain,
54 bit + VEC_COUNT_PER_REG * i);
63 chained_irq_exit(chip, desc);
66 static void htvec_ack_irq(struct irq_data *d)
68 struct htvec *priv = irq_data_get_irq_chip_data(d);
70 writel(BIT(VEC_REG_BIT(d->hwirq)),
71 priv->base + VEC_REG_IDX(d->hwirq) * 4);
74 static void htvec_mask_irq(struct irq_data *d)
78 struct htvec *priv = irq_data_get_irq_chip_data(d);
80 raw_spin_lock(&priv->htvec_lock);
81 addr = priv->base + HTVEC_EN_OFF;
82 addr += VEC_REG_IDX(d->hwirq) * 4;
84 reg &= ~BIT(VEC_REG_BIT(d->hwirq));
86 raw_spin_unlock(&priv->htvec_lock);
89 static void htvec_unmask_irq(struct irq_data *d)
93 struct htvec *priv = irq_data_get_irq_chip_data(d);
95 raw_spin_lock(&priv->htvec_lock);
96 addr = priv->base + HTVEC_EN_OFF;
97 addr += VEC_REG_IDX(d->hwirq) * 4;
99 reg |= BIT(VEC_REG_BIT(d->hwirq));
101 raw_spin_unlock(&priv->htvec_lock);
104 static struct irq_chip htvec_irq_chip = {
105 .name = "LOONGSON_HTVEC",
106 .irq_mask = htvec_mask_irq,
107 .irq_unmask = htvec_unmask_irq,
108 .irq_ack = htvec_ack_irq,
111 static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq,
112 unsigned int nr_irqs, void *arg)
116 unsigned int type, i;
117 struct htvec *priv = domain->host_data;
119 ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
123 for (i = 0; i < nr_irqs; i++) {
124 irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
125 priv, handle_edge_irq, NULL, NULL);
131 static void htvec_domain_free(struct irq_domain *domain, unsigned int virq,
132 unsigned int nr_irqs)
136 for (i = 0; i < nr_irqs; i++) {
137 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
139 irq_set_handler(virq + i, NULL);
140 irq_domain_reset_irq_data(d);
144 static const struct irq_domain_ops htvec_domain_ops = {
145 .translate = irq_domain_translate_onecell,
146 .alloc = htvec_domain_alloc,
147 .free = htvec_domain_free,
150 static void htvec_reset(struct htvec *priv)
154 /* Clear IRQ cause registers, mask all interrupts */
155 for (idx = 0; idx < priv->num_parents; idx++) {
156 writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
157 writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
161 static int htvec_suspend(void)
165 for (i = 0; i < htvec_priv->num_parents; i++)
166 htvec_priv->saved_vec_en[i] = readl(htvec_priv->base + HTVEC_EN_OFF + 4 * i);
171 static void htvec_resume(void)
175 for (i = 0; i < htvec_priv->num_parents; i++)
176 writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i);
179 static struct syscore_ops htvec_syscore_ops = {
180 .suspend = htvec_suspend,
181 .resume = htvec_resume,
184 static int htvec_init(phys_addr_t addr, unsigned long size,
185 int num_parents, int parent_irq[], struct fwnode_handle *domain_handle)
190 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
194 priv->num_parents = num_parents;
195 priv->base = ioremap(addr, size);
196 raw_spin_lock_init(&priv->htvec_lock);
198 /* Setup IRQ domain */
199 priv->htvec_domain = irq_domain_create_linear(domain_handle,
200 (VEC_COUNT_PER_REG * priv->num_parents),
201 &htvec_domain_ops, priv);
202 if (!priv->htvec_domain) {
203 pr_err("loongson-htvec: cannot add IRQ domain\n");
209 for (i = 0; i < priv->num_parents; i++) {
210 irq_set_chained_handler_and_data(parent_irq[i],
211 htvec_irq_dispatch, priv);
216 register_syscore_ops(&htvec_syscore_ops);
229 static int htvec_of_init(struct device_node *node,
230 struct device_node *parent)
237 if (of_address_to_resource(node, 0, &res))
240 /* Interrupt may come from any of the 8 interrupt lines */
241 for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
242 parent_irq[i] = irq_of_parse_and_map(node, i);
243 if (parent_irq[i] <= 0)
249 err = htvec_init(res.start, resource_size(&res),
250 num_parents, parent_irq, of_node_to_fwnode(node));
257 IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);
262 static int __init pch_pic_parse_madt(union acpi_subtable_headers *header,
263 const unsigned long end)
265 struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
267 return pch_pic_acpi_init(htvec_priv->htvec_domain, pchpic_entry);
270 static int __init pch_msi_parse_madt(union acpi_subtable_headers *header,
271 const unsigned long end)
273 struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
275 return pch_msi_acpi_init(htvec_priv->htvec_domain, pchmsi_entry);
278 static int __init acpi_cascade_irqdomain_init(void)
282 r = acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC, pch_pic_parse_madt, 0);
286 r = acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, 0);
293 int __init htvec_acpi_init(struct irq_domain *parent,
294 struct acpi_madt_ht_pic *acpi_htvec)
297 int num_parents, parent_irq[8];
298 struct fwnode_handle *domain_handle;
303 num_parents = HTVEC_MAX_PARENT_IRQ;
305 domain_handle = irq_domain_alloc_fwnode(&acpi_htvec->address);
306 if (!domain_handle) {
307 pr_err("Unable to allocate domain handle\n");
311 /* Interrupt may come from any of the 8 interrupt lines */
312 for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++)
313 parent_irq[i] = irq_create_mapping(parent, acpi_htvec->cascade[i]);
315 ret = htvec_init(acpi_htvec->address, acpi_htvec->size,
316 num_parents, parent_irq, domain_handle);
319 ret = acpi_cascade_irqdomain_init();
321 irq_domain_free_fwnode(domain_handle);