drivers/irqchip/irq-imx-gpcv2.c

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/of_address.h>
  10 #include <linux/of_irq.h>
  11 #include <linux/slab.h>
  12 #include <linux/irqchip.h>
  13 #include <linux/syscore_ops.h>
  14
  15 #define IMR_NUM                 4
  16 #define GPC_MAX_IRQS            (IMR_NUM * 32)
  17
  18 #define GPC_IMR1_CORE0          0x30
  19 #define GPC_IMR1_CORE1          0x40
  20
  21 struct gpcv2_irqchip_data {
  22         struct raw_spinlock     rlock;
  23         void __iomem            *gpc_base;
  24         u32                     wakeup_sources[IMR_NUM];
  25         u32                     saved_irq_mask[IMR_NUM];
  26         u32                     cpu2wakeup;
  27 };
  28
  29 static struct gpcv2_irqchip_data *imx_gpcv2_instance;
  30
  31 static int gpcv2_wakeup_source_save(void)
  32 {
  33         struct gpcv2_irqchip_data *cd;
  34         void __iomem *reg;
  35         int i;
  36
  37         cd = imx_gpcv2_instance;
  38         if (!cd)
  39                 return 0;
  40
  41         for (i = 0; i < IMR_NUM; i++) {
  42                 reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
  43                 cd->saved_irq_mask[i] = readl_relaxed(reg);
  44                 writel_relaxed(cd->wakeup_sources[i], reg);
  45         }
  46
  47         return 0;
  48 }
  49
  50 static void gpcv2_wakeup_source_restore(void)
  51 {
  52         struct gpcv2_irqchip_data *cd;
  53         void __iomem *reg;
  54         int i;
  55
  56         cd = imx_gpcv2_instance;
  57         if (!cd)
  58                 return;
  59
  60         for (i = 0; i < IMR_NUM; i++) {
  61                 reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
  62                 writel_relaxed(cd->saved_irq_mask[i], reg);
  63         }
  64 }
  65
  66 static struct syscore_ops imx_gpcv2_syscore_ops = {
  67         .suspend        = gpcv2_wakeup_source_save,
  68         .resume         = gpcv2_wakeup_source_restore,
  69 };
  70
  71 static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
  72 {
  73         struct gpcv2_irqchip_data *cd = d->chip_data;
  74         unsigned int idx = d->hwirq / 32;
  75         unsigned long flags;
  76         u32 mask, val;
  77
  78         raw_spin_lock_irqsave(&cd->rlock, flags);
  79         mask = 1 << d->hwirq % 32;
  80         val = cd->wakeup_sources[idx];
  81
  82         cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
  83         raw_spin_unlock_irqrestore(&cd->rlock, flags);
  84
  85         /*
  86          * Do *not* call into the parent, as the GIC doesn't have any
  87          * wake-up facility...
  88          */
  89
  90         return 0;
  91 }
  92
  93 static void imx_gpcv2_irq_unmask(struct irq_data *d)
  94 {
  95         struct gpcv2_irqchip_data *cd = d->chip_data;
  96         void __iomem *reg;
  97         u32 val;
  98
  99         raw_spin_lock(&cd->rlock);
 100         reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
 101         val = readl_relaxed(reg);
 102         val &= ~(1 << d->hwirq % 32);
 103         writel_relaxed(val, reg);
 104         raw_spin_unlock(&cd->rlock);
 105
 106         irq_chip_unmask_parent(d);
 107 }
 108
 109 static void imx_gpcv2_irq_mask(struct irq_data *d)
 110 {
 111         struct gpcv2_irqchip_data *cd = d->chip_data;
 112         void __iomem *reg;
 113         u32 val;
 114
 115         raw_spin_lock(&cd->rlock);
 116         reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
 117         val = readl_relaxed(reg);
 118         val |= 1 << (d->hwirq % 32);
 119         writel_relaxed(val, reg);
 120         raw_spin_unlock(&cd->rlock);
 121
 122         irq_chip_mask_parent(d);
 123 }
 124
 125 static struct irq_chip gpcv2_irqchip_data_chip = {
 126         .name                   = "GPCv2",
 127         .irq_eoi                = irq_chip_eoi_parent,
 128         .irq_mask               = imx_gpcv2_irq_mask,
 129         .irq_unmask             = imx_gpcv2_irq_unmask,
 130         .irq_set_wake           = imx_gpcv2_irq_set_wake,
 131         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 132 #ifdef CONFIG_SMP
 133         .irq_set_affinity       = irq_chip_set_affinity_parent,
 134 #endif
 135 };
 136
 137 static int imx_gpcv2_domain_translate(struct irq_domain *d,
 138                                       struct irq_fwspec *fwspec,
 139                                       unsigned long *hwirq,
 140                                       unsigned int *type)
 141 {
 142         if (is_of_node(fwspec->fwnode)) {
 143                 if (fwspec->param_count != 3)
 144                         return -EINVAL;
 145
 146                 /* No PPI should point to this domain */
 147                 if (fwspec->param[0] != 0)
 148                         return -EINVAL;
 149
 150                 *hwirq = fwspec->param[1];
 151                 *type = fwspec->param[2];
 152                 return 0;
 153         }
 154
 155         return -EINVAL;
 156 }
 157
 158 static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
 159                                   unsigned int irq, unsigned int nr_irqs,
 160                                   void *data)
 161 {
 162         struct irq_fwspec *fwspec = data;
 163         struct irq_fwspec parent_fwspec;
 164         irq_hw_number_t hwirq;
 165         unsigned int type;
 166         int err;
 167         int i;
 168
 169         err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type);
 170         if (err)
 171                 return err;
 172
 173         if (hwirq >= GPC_MAX_IRQS)
 174                 return -EINVAL;
 175
 176         for (i = 0; i < nr_irqs; i++) {
 177                 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
 178                                 &gpcv2_irqchip_data_chip, domain->host_data);
 179         }
 180
 181         parent_fwspec = *fwspec;
 182         parent_fwspec.fwnode = domain->parent->fwnode;
 183         return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
 184                                             &parent_fwspec);
 185 }
 186
 187 static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
 188         .translate      = imx_gpcv2_domain_translate,
 189         .alloc          = imx_gpcv2_domain_alloc,
 190         .free           = irq_domain_free_irqs_common,
 191 };
 192
 193 static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 194                                struct device_node *parent)
 195 {
 196         struct irq_domain *parent_domain, *domain;
 197         struct gpcv2_irqchip_data *cd;
 198         int i;
 199
 200         if (!parent) {
 201                 pr_err("%pOF: no parent, giving up\n", node);
 202                 return -ENODEV;
 203         }
 204
 205         parent_domain = irq_find_host(parent);
 206         if (!parent_domain) {
 207                 pr_err("%pOF: unable to get parent domain\n", node);
 208                 return -ENXIO;
 209         }
 210
 211         cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
 212         if (!cd) {
 213                 pr_err("kzalloc failed!\n");
 214                 return -ENOMEM;
 215         }
 216
 217         raw_spin_lock_init(&cd->rlock);
 218
 219         cd->gpc_base = of_iomap(node, 0);
 220         if (!cd->gpc_base) {
 221                 pr_err("fsl-gpcv2: unable to map gpc registers\n");
 222                 kfree(cd);
 223                 return -ENOMEM;
 224         }
 225
 226         domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
 227                                 node, &gpcv2_irqchip_data_domain_ops, cd);
 228         if (!domain) {
 229                 iounmap(cd->gpc_base);
 230                 kfree(cd);
 231                 return -ENOMEM;
 232         }
 233         irq_set_default_host(domain);
 234
 235         /* Initially mask all interrupts */
 236         for (i = 0; i < IMR_NUM; i++) {
 237                 writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4);
 238                 writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4);
 239                 cd->wakeup_sources[i] = ~0;
 240         }
 241
 242         /* Let CORE0 as the default CPU to wake up by GPC */
 243         cd->cpu2wakeup = GPC_IMR1_CORE0;
 244
 245         /*
 246          * Due to hardware design failure, need to make sure GPR
 247          * interrupt(#32) is unmasked during RUN mode to avoid entering
 248          * DSM by mistake.
 249          */
 250         writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
 251
 252         imx_gpcv2_instance = cd;
 253         register_syscore_ops(&imx_gpcv2_syscore_ops);
 254
 255         /*
 256          * Clear the OF_POPULATED flag set in of_irq_init so that
 257          * later the GPC power domain driver will not be skipped.
 258          */
 259         of_node_clear_flag(node, OF_POPULATED);
 260         return 0;
 261 }
 262
 263 IRQCHIP_DECLARE(imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);