drivers/irqchip/irq-gic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   4  *
   5  * Interrupt architecture for the GIC:
   6  *
   7  * o There is one Interrupt Distributor, which receives interrupts
   8  *   from system devices and sends them to the Interrupt Controllers.
   9  *
  10  * o There is one CPU Interface per CPU, which sends interrupts sent
  11  *   by the Distributor, and interrupts generated locally, to the
  12  *   associated CPU. The base address of the CPU interface is usually
  13  *   aliased so that the same address points to different chips depending
  14  *   on the CPU it is accessed from.
  15  *
  16  * Note that IRQs 0-31 are special - they are local to each CPU.
  17  * As such, the enable set/clear, pending set/clear and active bit
  18  * registers are banked per-cpu for these sources.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/err.h>
  23 #include <linux/module.h>
  24 #include <linux/list.h>
  25 #include <linux/smp.h>
  26 #include <linux/cpu.h>
  27 #include <linux/cpu_pm.h>
  28 #include <linux/cpumask.h>
  29 #include <linux/io.h>
  30 #include <linux/of.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/acpi.h>
  34 #include <linux/irqdomain.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/percpu.h>
  37 #include <linux/slab.h>
  38 #include <linux/irqchip.h>
  39 #include <linux/irqchip/chained_irq.h>
  40 #include <linux/irqchip/arm-gic.h>
  41
  42 #include <asm/cputype.h>
  43 #include <asm/irq.h>
  44 #include <asm/exception.h>
  45 #include <asm/smp_plat.h>
  46 #include <asm/virt.h>
  47
  48 #include "irq-gic-common.h"
  49
  50 #ifdef CONFIG_ARM64
  51 #include <asm/cpufeature.h>
  52
  53 static void gic_check_cpu_features(void)
  54 {
  55         WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
  56                         TAINT_CPU_OUT_OF_SPEC,
  57                         "GICv3 system registers enabled, broken firmware!\n");
  58 }
  59 #else
  60 #define gic_check_cpu_features()        do { } while(0)
  61 #endif
  62
  63 union gic_base {
  64         void __iomem *common_base;
  65         void __percpu * __iomem *percpu_base;
  66 };
  67
  68 struct gic_chip_data {
  69         struct irq_chip chip;
  70         union gic_base dist_base;
  71         union gic_base cpu_base;
  72         void __iomem *raw_dist_base;
  73         void __iomem *raw_cpu_base;
  74         u32 percpu_offset;
  75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
  76         u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
  77         u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
  78         u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
  79         u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
  80         u32 __percpu *saved_ppi_enable;
  81         u32 __percpu *saved_ppi_active;
  82         u32 __percpu *saved_ppi_conf;
  83 #endif
  84         struct irq_domain *domain;
  85         unsigned int gic_irqs;
  86 #ifdef CONFIG_GIC_NON_BANKED
  87         void __iomem *(*get_base)(union gic_base *);
  88 #endif
  89 };
  90
  91 #ifdef CONFIG_BL_SWITCHER
  92
  93 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
  94
  95 #define gic_lock_irqsave(f)             \
  96         raw_spin_lock_irqsave(&cpu_map_lock, (f))
  97 #define gic_unlock_irqrestore(f)        \
  98         raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
  99
 100 #define gic_lock()                      raw_spin_lock(&cpu_map_lock)
 101 #define gic_unlock()                    raw_spin_unlock(&cpu_map_lock)
 102
 103 #else
 104
 105 #define gic_lock_irqsave(f)             do { (void)(f); } while(0)
 106 #define gic_unlock_irqrestore(f)        do { (void)(f); } while(0)
 107
 108 #define gic_lock()                      do { } while(0)
 109 #define gic_unlock()                    do { } while(0)
 110
 111 #endif
 112
 113 /*
 114  * The GIC mapping of CPU interfaces does not necessarily match
 115  * the logical CPU numbering.  Let's use a mapping as returned
 116  * by the GIC itself.
 117  */
 118 #define NR_GIC_CPU_IF 8
 119 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 120
 121 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
 122
 123 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
 124
 125 static struct gic_kvm_info gic_v2_kvm_info;
 126
 127 #ifdef CONFIG_GIC_NON_BANKED
 128 static void __iomem *gic_get_percpu_base(union gic_base *base)
 129 {
 130         return raw_cpu_read(*base->percpu_base);
 131 }
 132
 133 static void __iomem *gic_get_common_base(union gic_base *base)
 134 {
 135         return base->common_base;
 136 }
 137
 138 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
 139 {
 140         return data->get_base(&data->dist_base);
 141 }
 142
 143 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
 144 {
 145         return data->get_base(&data->cpu_base);
 146 }
 147
 148 static inline void gic_set_base_accessor(struct gic_chip_data *data,
 149                                          void __iomem *(*f)(union gic_base *))
 150 {
 151         data->get_base = f;
 152 }
 153 #else
 154 #define gic_data_dist_base(d)   ((d)->dist_base.common_base)
 155 #define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
 156 #define gic_set_base_accessor(d, f)
 157 #endif
 158
 159 static inline void __iomem *gic_dist_base(struct irq_data *d)
 160 {
 161         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 162         return gic_data_dist_base(gic_data);
 163 }
 164
 165 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 166 {
 167         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 168         return gic_data_cpu_base(gic_data);
 169 }
 170
 171 static inline unsigned int gic_irq(struct irq_data *d)
 172 {
 173         return d->hwirq;
 174 }
 175
 176 static inline bool cascading_gic_irq(struct irq_data *d)
 177 {
 178         void *data = irq_data_get_irq_handler_data(d);
 179
 180         /*
 181          * If handler_data is set, this is a cascading interrupt, and
 182          * it cannot possibly be forwarded.
 183          */
 184         return data != NULL;
 185 }
 186
 187 /*
 188  * Routines to acknowledge, disable and enable interrupts
 189  */
 190 static void gic_poke_irq(struct irq_data *d, u32 offset)
 191 {
 192         u32 mask = 1 << (gic_irq(d) % 32);
 193         writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
 194 }
 195
 196 static int gic_peek_irq(struct irq_data *d, u32 offset)
 197 {
 198         u32 mask = 1 << (gic_irq(d) % 32);
 199         return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
 200 }
 201
 202 static void gic_mask_irq(struct irq_data *d)
 203 {
 204         gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
 205 }
 206
 207 static void gic_eoimode1_mask_irq(struct irq_data *d)
 208 {
 209         gic_mask_irq(d);
 210         /*
 211          * When masking a forwarded interrupt, make sure it is
 212          * deactivated as well.
 213          *
 214          * This ensures that an interrupt that is getting
 215          * disabled/masked will not get "stuck", because there is
 216          * noone to deactivate it (guest is being terminated).
 217          */
 218         if (irqd_is_forwarded_to_vcpu(d))
 219                 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
 220 }
 221
 222 static void gic_unmask_irq(struct irq_data *d)
 223 {
 224         gic_poke_irq(d, GIC_DIST_ENABLE_SET);
 225 }
 226
 227 static void gic_eoi_irq(struct irq_data *d)
 228 {
 229         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
 230 }
 231
 232 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 233 {
 234         /* Do not deactivate an IRQ forwarded to a vcpu. */
 235         if (irqd_is_forwarded_to_vcpu(d))
 236                 return;
 237
 238         writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
 239 }
 240
 241 static int gic_irq_set_irqchip_state(struct irq_data *d,
 242                                      enum irqchip_irq_state which, bool val)
 243 {
 244         u32 reg;
 245
 246         switch (which) {
 247         case IRQCHIP_STATE_PENDING:
 248                 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
 249                 break;
 250
 251         case IRQCHIP_STATE_ACTIVE:
 252                 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
 253                 break;
 254
 255         case IRQCHIP_STATE_MASKED:
 256                 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
 257                 break;
 258
 259         default:
 260                 return -EINVAL;
 261         }
 262
 263         gic_poke_irq(d, reg);
 264         return 0;
 265 }
 266
 267 static int gic_irq_get_irqchip_state(struct irq_data *d,
 268                                       enum irqchip_irq_state which, bool *val)
 269 {
 270         switch (which) {
 271         case IRQCHIP_STATE_PENDING:
 272                 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
 273                 break;
 274
 275         case IRQCHIP_STATE_ACTIVE:
 276                 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
 277                 break;
 278
 279         case IRQCHIP_STATE_MASKED:
 280                 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
 281                 break;
 282
 283         default:
 284                 return -EINVAL;
 285         }
 286
 287         return 0;
 288 }
 289
 290 static int gic_set_type(struct irq_data *d, unsigned int type)
 291 {
 292         void __iomem *base = gic_dist_base(d);
 293         unsigned int gicirq = gic_irq(d);
 294         int ret;
 295
 296         /* Interrupt configuration for SGIs can't be changed */
 297         if (gicirq < 16)
 298                 return -EINVAL;
 299
 300         /* SPIs have restrictions on the supported types */
 301         if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
 302                             type != IRQ_TYPE_EDGE_RISING)
 303                 return -EINVAL;
 304
 305         ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
 306         if (ret && gicirq < 32) {
 307                 /* Misconfigured PPIs are usually not fatal */
 308                 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
 309                 ret = 0;
 310         }
 311
 312         return ret;
 313 }
 314
 315 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 316 {
 317         /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
 318         if (cascading_gic_irq(d))
 319                 return -EINVAL;
 320
 321         if (vcpu)
 322                 irqd_set_forwarded_to_vcpu(d);
 323         else
 324                 irqd_clr_forwarded_to_vcpu(d);
 325         return 0;
 326 }
 327
 328 #ifdef CONFIG_SMP
 329 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 330                             bool force)
 331 {
 332         void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
 333         unsigned int cpu;
 334
 335         if (!force)
 336                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
 337         else
 338                 cpu = cpumask_first(mask_val);
 339
 340         if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
 341                 return -EINVAL;
 342
 343         writeb_relaxed(gic_cpu_map[cpu], reg);
 344         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 345
 346         return IRQ_SET_MASK_OK_DONE;
 347 }
 348 #endif
 349
 350 static int gic_retrigger(struct irq_data *data)
 351 {
 352         return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
 353 }
 354
 355 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 356 {
 357         u32 irqstat, irqnr;
 358         struct gic_chip_data *gic = &gic_data[0];
 359         void __iomem *cpu_base = gic_data_cpu_base(gic);
 360
 361         do {
 362                 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
 363                 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 364
 365                 if (likely(irqnr > 15 && irqnr < 1020)) {
 366                         if (static_branch_likely(&supports_deactivate_key))
 367                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 368                         isb();
 369                         handle_domain_irq(gic->domain, irqnr, regs);
 370                         continue;
 371                 }
 372                 if (irqnr < 16) {
 373                         writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 374                         if (static_branch_likely(&supports_deactivate_key))
 375                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
 376 #ifdef CONFIG_SMP
 377                         /*
 378                          * Ensure any shared data written by the CPU sending
 379                          * the IPI is read after we've read the ACK register
 380                          * on the GIC.
 381                          *
 382                          * Pairs with the write barrier in gic_raise_softirq
 383                          */
 384                         smp_rmb();
 385                         handle_IPI(irqnr, regs);
 386 #endif
 387                         continue;
 388                 }
 389                 break;
 390         } while (1);
 391 }
 392
 393 static void gic_handle_cascade_irq(struct irq_desc *desc)
 394 {
 395         struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
 396         struct irq_chip *chip = irq_desc_get_chip(desc);
 397         unsigned int cascade_irq, gic_irq;
 398         unsigned long status;
 399
 400         chained_irq_enter(chip, desc);
 401
 402         status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
 403
 404         gic_irq = (status & GICC_IAR_INT_ID_MASK);
 405         if (gic_irq == GICC_INT_SPURIOUS)
 406                 goto out;
 407
 408         cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
 409         if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
 410                 handle_bad_irq(desc);
 411         } else {
 412                 isb();
 413                 generic_handle_irq(cascade_irq);
 414         }
 415
 416  out:
 417         chained_irq_exit(chip, desc);
 418 }
 419
 420 static const struct irq_chip gic_chip = {
 421         .irq_mask               = gic_mask_irq,
 422         .irq_unmask             = gic_unmask_irq,
 423         .irq_eoi                = gic_eoi_irq,
 424         .irq_set_type           = gic_set_type,
 425         .irq_retrigger          = gic_retrigger,
 426         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 427         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 428         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 429                                   IRQCHIP_SKIP_SET_WAKE |
 430                                   IRQCHIP_MASK_ON_SUSPEND,
 431 };
 432
 433 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 434 {
 435         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 436         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
 437                                          &gic_data[gic_nr]);
 438 }
 439
 440 static u8 gic_get_cpumask(struct gic_chip_data *gic)
 441 {
 442         void __iomem *base = gic_data_dist_base(gic);
 443         u32 mask, i;
 444
 445         for (i = mask = 0; i < 32; i += 4) {
 446                 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
 447                 mask |= mask >> 16;
 448                 mask |= mask >> 8;
 449                 if (mask)
 450                         break;
 451         }
 452
 453         if (!mask && num_possible_cpus() > 1)
 454                 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 455
 456         return mask;
 457 }
 458
 459 static bool gic_check_gicv2(void __iomem *base)
 460 {
 461         u32 val = readl_relaxed(base + GIC_CPU_IDENT);
 462         return (val & 0xff0fff) == 0x02043B;
 463 }
 464
 465 static void gic_cpu_if_up(struct gic_chip_data *gic)
 466 {
 467         void __iomem *cpu_base = gic_data_cpu_base(gic);
 468         u32 bypass = 0;
 469         u32 mode = 0;
 470         int i;
 471
 472         if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
 473                 mode = GIC_CPU_CTRL_EOImodeNS;
 474
 475         if (gic_check_gicv2(cpu_base))
 476                 for (i = 0; i < 4; i++)
 477                         writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
 478
 479         /*
 480         * Preserve bypass disable bits to be written back later
 481         */
 482         bypass = readl(cpu_base + GIC_CPU_CTRL);
 483         bypass &= GICC_DIS_BYPASS_MASK;
 484
 485         writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
 486 }
 487
 488
 489 static void gic_dist_init(struct gic_chip_data *gic)
 490 {
 491         unsigned int i;
 492         u32 cpumask;
 493         unsigned int gic_irqs = gic->gic_irqs;
 494         void __iomem *base = gic_data_dist_base(gic);
 495
 496         writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
 497
 498         /*
 499          * Set all global interrupts to this CPU only.
 500          */
 501         cpumask = gic_get_cpumask(gic);
 502         cpumask |= cpumask << 8;
 503         cpumask |= cpumask << 16;
 504         for (i = 32; i < gic_irqs; i += 4)
 505                 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 506
 507         gic_dist_config(base, gic_irqs, NULL);
 508
 509         writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
 510 }
 511
 512 static int gic_cpu_init(struct gic_chip_data *gic)
 513 {
 514         void __iomem *dist_base = gic_data_dist_base(gic);
 515         void __iomem *base = gic_data_cpu_base(gic);
 516         unsigned int cpu_mask, cpu = smp_processor_id();
 517         int i;
 518
 519         /*
 520          * Setting up the CPU map is only relevant for the primary GIC
 521          * because any nested/secondary GICs do not directly interface
 522          * with the CPU(s).
 523          */
 524         if (gic == &gic_data[0]) {
 525                 /*
 526                  * Get what the GIC says our CPU mask is.
 527                  */
 528                 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
 529                         return -EINVAL;
 530
 531                 gic_check_cpu_features();
 532                 cpu_mask = gic_get_cpumask(gic);
 533                 gic_cpu_map[cpu] = cpu_mask;
 534
 535                 /*
 536                  * Clear our mask from the other map entries in case they're
 537                  * still undefined.
 538                  */
 539                 for (i = 0; i < NR_GIC_CPU_IF; i++)
 540                         if (i != cpu)
 541                                 gic_cpu_map[i] &= ~cpu_mask;
 542         }
 543
 544         gic_cpu_config(dist_base, 32, NULL);
 545
 546         writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
 547         gic_cpu_if_up(gic);
 548
 549         return 0;
 550 }
 551
 552 int gic_cpu_if_down(unsigned int gic_nr)
 553 {
 554         void __iomem *cpu_base;
 555         u32 val = 0;
 556
 557         if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
 558                 return -EINVAL;
 559
 560         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
 561         val = readl(cpu_base + GIC_CPU_CTRL);
 562         val &= ~GICC_ENABLE;
 563         writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
 564
 565         return 0;
 566 }
 567
 568 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
 569 /*
 570  * Saves the GIC distributor registers during suspend or idle.  Must be called
 571  * with interrupts disabled but before powering down the GIC.  After calling
 572  * this function, no interrupts will be delivered by the GIC, and another
 573  * platform-specific wakeup source must be enabled.
 574  */
 575 void gic_dist_save(struct gic_chip_data *gic)
 576 {
 577         unsigned int gic_irqs;
 578         void __iomem *dist_base;
 579         int i;
 580
 581         if (WARN_ON(!gic))
 582                 return;
 583
 584         gic_irqs = gic->gic_irqs;
 585         dist_base = gic_data_dist_base(gic);
 586
 587         if (!dist_base)
 588                 return;
 589
 590         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 591                 gic->saved_spi_conf[i] =
 592                         readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 593
 594         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 595                 gic->saved_spi_target[i] =
 596                         readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 597
 598         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 599                 gic->saved_spi_enable[i] =
 600                         readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 601
 602         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
 603                 gic->saved_spi_active[i] =
 604                         readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 605 }
 606
 607 /*
 608  * Restores the GIC distributor registers during resume or when coming out of
 609  * idle.  Must be called before enabling interrupts.  If a level interrupt
 610  * that occurred while the GIC was suspended is still present, it will be
 611  * handled normally, but any edge interrupts that occurred will not be seen by
 612  * the GIC and need to be handled by the platform-specific wakeup source.
 613  */
 614 void gic_dist_restore(struct gic_chip_data *gic)
 615 {
 616         unsigned int gic_irqs;
 617         unsigned int i;
 618         void __iomem *dist_base;
 619
 620         if (WARN_ON(!gic))
 621                 return;
 622
 623         gic_irqs = gic->gic_irqs;
 624         dist_base = gic_data_dist_base(gic);
 625
 626         if (!dist_base)
 627                 return;
 628
 629         writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
 630
 631         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
 632                 writel_relaxed(gic->saved_spi_conf[i],
 633                         dist_base + GIC_DIST_CONFIG + i * 4);
 634
 635         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 636                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 637                         dist_base + GIC_DIST_PRI + i * 4);
 638
 639         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
 640                 writel_relaxed(gic->saved_spi_target[i],
 641                         dist_base + GIC_DIST_TARGET + i * 4);
 642
 643         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 644                 writel_relaxed(GICD_INT_EN_CLR_X32,
 645                         dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 646                 writel_relaxed(gic->saved_spi_enable[i],
 647                         dist_base + GIC_DIST_ENABLE_SET + i * 4);
 648         }
 649
 650         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
 651                 writel_relaxed(GICD_INT_EN_CLR_X32,
 652                         dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 653                 writel_relaxed(gic->saved_spi_active[i],
 654                         dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 655         }
 656
 657         writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
 658 }
 659
 660 void gic_cpu_save(struct gic_chip_data *gic)
 661 {
 662         int i;
 663         u32 *ptr;
 664         void __iomem *dist_base;
 665         void __iomem *cpu_base;
 666
 667         if (WARN_ON(!gic))
 668                 return;
 669
 670         dist_base = gic_data_dist_base(gic);
 671         cpu_base = gic_data_cpu_base(gic);
 672
 673         if (!dist_base || !cpu_base)
 674                 return;
 675
 676         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 677         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 678                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 679
 680         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 681         for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
 682                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 683
 684         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 685         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 686                 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 687
 688 }
 689
 690 void gic_cpu_restore(struct gic_chip_data *gic)
 691 {
 692         int i;
 693         u32 *ptr;
 694         void __iomem *dist_base;
 695         void __iomem *cpu_base;
 696
 697         if (WARN_ON(!gic))
 698                 return;
 699
 700         dist_base = gic_data_dist_base(gic);
 701         cpu_base = gic_data_cpu_base(gic);
 702
 703         if (!dist_base || !cpu_base)
 704                 return;
 705
 706         ptr = raw_cpu_ptr(gic->saved_ppi_enable);
 707         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 708                 writel_relaxed(GICD_INT_EN_CLR_X32,
 709                                dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
 710                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
 711         }
 712
 713         ptr = raw_cpu_ptr(gic->saved_ppi_active);
 714         for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
 715                 writel_relaxed(GICD_INT_EN_CLR_X32,
 716                                dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
 717                 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
 718         }
 719
 720         ptr = raw_cpu_ptr(gic->saved_ppi_conf);
 721         for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
 722                 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
 723
 724         for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
 725                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 726                                         dist_base + GIC_DIST_PRI + i * 4);
 727
 728         writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
 729         gic_cpu_if_up(gic);
 730 }
 731
 732 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 733 {
 734         int i;
 735
 736         for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
 737 #ifdef CONFIG_GIC_NON_BANKED
 738                 /* Skip over unused GICs */
 739                 if (!gic_data[i].get_base)
 740                         continue;
 741 #endif
 742                 switch (cmd) {
 743                 case CPU_PM_ENTER:
 744                         gic_cpu_save(&gic_data[i]);
 745                         break;
 746                 case CPU_PM_ENTER_FAILED:
 747                 case CPU_PM_EXIT:
 748                         gic_cpu_restore(&gic_data[i]);
 749                         break;
 750                 case CPU_CLUSTER_PM_ENTER:
 751                         gic_dist_save(&gic_data[i]);
 752                         break;
 753                 case CPU_CLUSTER_PM_ENTER_FAILED:
 754                 case CPU_CLUSTER_PM_EXIT:
 755                         gic_dist_restore(&gic_data[i]);
 756                         break;
 757                 }
 758         }
 759
 760         return NOTIFY_OK;
 761 }
 762
 763 static struct notifier_block gic_notifier_block = {
 764         .notifier_call = gic_notifier,
 765 };
 766
 767 static int gic_pm_init(struct gic_chip_data *gic)
 768 {
 769         gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 770                 sizeof(u32));
 771         if (WARN_ON(!gic->saved_ppi_enable))
 772                 return -ENOMEM;
 773
 774         gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
 775                 sizeof(u32));
 776         if (WARN_ON(!gic->saved_ppi_active))
 777                 goto free_ppi_enable;
 778
 779         gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
 780                 sizeof(u32));
 781         if (WARN_ON(!gic->saved_ppi_conf))
 782                 goto free_ppi_active;
 783
 784         if (gic == &gic_data[0])
 785                 cpu_pm_register_notifier(&gic_notifier_block);
 786
 787         return 0;
 788
 789 free_ppi_active:
 790         free_percpu(gic->saved_ppi_active);
 791 free_ppi_enable:
 792         free_percpu(gic->saved_ppi_enable);
 793
 794         return -ENOMEM;
 795 }
 796 #else
 797 static int gic_pm_init(struct gic_chip_data *gic)
 798 {
 799         return 0;
 800 }
 801 #endif
 802
 803 #ifdef CONFIG_SMP
 804 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 805 {
 806         int cpu;
 807         unsigned long flags, map = 0;
 808
 809         if (unlikely(nr_cpu_ids == 1)) {
 810                 /* Only one CPU? let's do a self-IPI... */
 811                 writel_relaxed(2 << 24 | irq,
 812                                gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 813                 return;
 814         }
 815
 816         gic_lock_irqsave(flags);
 817
 818         /* Convert our logical CPU mask into a physical one. */
 819         for_each_cpu(cpu, mask)
 820                 map |= gic_cpu_map[cpu];
 821
 822         /*
 823          * Ensure that stores to Normal memory are visible to the
 824          * other CPUs before they observe us issuing the IPI.
 825          */
 826         dmb(ishst);
 827
 828         /* this always happens on GIC0 */
 829         writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 830
 831         gic_unlock_irqrestore(flags);
 832 }
 833 #endif
 834
 835 #ifdef CONFIG_BL_SWITCHER
 836 /*
 837  * gic_send_sgi - send a SGI directly to given CPU interface number
 838  *
 839  * cpu_id: the ID for the destination CPU interface
 840  * irq: the IPI number to send a SGI for
 841  */
 842 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 843 {
 844         BUG_ON(cpu_id >= NR_GIC_CPU_IF);
 845         cpu_id = 1 << cpu_id;
 846         /* this always happens on GIC0 */
 847         writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 848 }
 849
 850 /*
 851  * gic_get_cpu_id - get the CPU interface ID for the specified CPU
 852  *
 853  * @cpu: the logical CPU number to get the GIC ID for.
 854  *
 855  * Return the CPU interface ID for the given logical CPU number,
 856  * or -1 if the CPU number is too large or the interface ID is
 857  * unknown (more than one bit set).
 858  */
 859 int gic_get_cpu_id(unsigned int cpu)
 860 {
 861         unsigned int cpu_bit;
 862
 863         if (cpu >= NR_GIC_CPU_IF)
 864                 return -1;
 865         cpu_bit = gic_cpu_map[cpu];
 866         if (cpu_bit & (cpu_bit - 1))
 867                 return -1;
 868         return __ffs(cpu_bit);
 869 }
 870
 871 /*
 872  * gic_migrate_target - migrate IRQs to another CPU interface
 873  *
 874  * @new_cpu_id: the CPU target ID to migrate IRQs to
 875  *
 876  * Migrate all peripheral interrupts with a target matching the current CPU
 877  * to the interface corresponding to @new_cpu_id.  The CPU interface mapping
 878  * is also updated.  Targets to other CPU interfaces are unchanged.
 879  * This must be called with IRQs locally disabled.
 880  */
 881 void gic_migrate_target(unsigned int new_cpu_id)
 882 {
 883         unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
 884         void __iomem *dist_base;
 885         int i, ror_val, cpu = smp_processor_id();
 886         u32 val, cur_target_mask, active_mask;
 887
 888         BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 889
 890         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
 891         if (!dist_base)
 892                 return;
 893         gic_irqs = gic_data[gic_nr].gic_irqs;
 894
 895         cur_cpu_id = __ffs(gic_cpu_map[cpu]);
 896         cur_target_mask = 0x01010101 << cur_cpu_id;
 897         ror_val = (cur_cpu_id - new_cpu_id) & 31;
 898
 899         gic_lock();
 900
 901         /* Update the target interface for this logical CPU */
 902         gic_cpu_map[cpu] = 1 << new_cpu_id;
 903
 904         /*
 905          * Find all the peripheral interrupts targeting the current
 906          * CPU interface and migrate them to the new CPU interface.
 907          * We skip DIST_TARGET 0 to 7 as they are read-only.
 908          */
 909         for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
 910                 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 911                 active_mask = val & cur_target_mask;
 912                 if (active_mask) {
 913                         val &= ~active_mask;
 914                         val |= ror32(active_mask, ror_val);
 915                         writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
 916                 }
 917         }
 918
 919         gic_unlock();
 920
 921         /*
 922          * Now let's migrate and clear any potential SGIs that might be
 923          * pending for us (cur_cpu_id).  Since GIC_DIST_SGI_PENDING_SET
 924          * is a banked register, we can only forward the SGI using
 925          * GIC_DIST_SOFTINT.  The original SGI source is lost but Linux
 926          * doesn't use that information anyway.
 927          *
 928          * For the same reason we do not adjust SGI source information
 929          * for previously sent SGIs by us to other CPUs either.
 930          */
 931         for (i = 0; i < 16; i += 4) {
 932                 int j;
 933                 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
 934                 if (!val)
 935                         continue;
 936                 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
 937                 for (j = i; j < i + 4; j++) {
 938                         if (val & 0xff)
 939                                 writel_relaxed((1 << (new_cpu_id + 16)) | j,
 940                                                 dist_base + GIC_DIST_SOFTINT);
 941                         val >>= 8;
 942                 }
 943         }
 944 }
 945
 946 /*
 947  * gic_get_sgir_physaddr - get the physical address for the SGI register
 948  *
 949  * REturn the physical address of the SGI register to be used
 950  * by some early assembly code when the kernel is not yet available.
 951  */
 952 static unsigned long gic_dist_physaddr;
 953
 954 unsigned long gic_get_sgir_physaddr(void)
 955 {
 956         if (!gic_dist_physaddr)
 957                 return 0;
 958         return gic_dist_physaddr + GIC_DIST_SOFTINT;
 959 }
 960
 961 static void __init gic_init_physaddr(struct device_node *node)
 962 {
 963         struct resource res;
 964         if (of_address_to_resource(node, 0, &res) == 0) {
 965                 gic_dist_physaddr = res.start;
 966                 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
 967         }
 968 }
 969
 970 #else
 971 #define gic_init_physaddr(node)  do { } while (0)
 972 #endif
 973
 974 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 975                                 irq_hw_number_t hw)
 976 {
 977         struct gic_chip_data *gic = d->host_data;
 978
 979         if (hw < 32) {
 980                 irq_set_percpu_devid(irq);
 981                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 982                                     handle_percpu_devid_irq, NULL, NULL);
 983         } else {
 984                 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
 985                                     handle_fasteoi_irq, NULL, NULL);
 986                 irq_set_probe(irq);
 987                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
 988         }
 989         return 0;
 990 }
 991
 992 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 993 {
 994 }
 995
 996 static int gic_irq_domain_translate(struct irq_domain *d,
 997                                     struct irq_fwspec *fwspec,
 998                                     unsigned long *hwirq,
 999                                     unsigned int *type)
1000 {
1001         if (is_of_node(fwspec->fwnode)) {
1002                 if (fwspec->param_count < 3)
1003                         return -EINVAL;
1004
1005                 /* Get the interrupt number and add 16 to skip over SGIs */
1006                 *hwirq = fwspec->param[1] + 16;
1007
1008                 /*
1009                  * For SPIs, we need to add 16 more to get the GIC irq
1010                  * ID number
1011                  */
1012                 if (!fwspec->param[0])
1013                         *hwirq += 16;
1014
1015                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1016
1017                 /* Make it clear that broken DTs are... broken */
1018                 WARN_ON(*type == IRQ_TYPE_NONE);
1019                 return 0;
1020         }
1021
1022         if (is_fwnode_irqchip(fwspec->fwnode)) {
1023                 if(fwspec->param_count != 2)
1024                         return -EINVAL;
1025
1026                 *hwirq = fwspec->param[0];
1027                 *type = fwspec->param[1];
1028
1029                 WARN_ON(*type == IRQ_TYPE_NONE);
1030                 return 0;
1031         }
1032
1033         return -EINVAL;
1034 }
1035
1036 static int gic_starting_cpu(unsigned int cpu)
1037 {
1038         gic_cpu_init(&gic_data[0]);
1039         return 0;
1040 }
1041
1042 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1043                                 unsigned int nr_irqs, void *arg)
1044 {
1045         int i, ret;
1046         irq_hw_number_t hwirq;
1047         unsigned int type = IRQ_TYPE_NONE;
1048         struct irq_fwspec *fwspec = arg;
1049
1050         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1051         if (ret)
1052                 return ret;
1053
1054         for (i = 0; i < nr_irqs; i++) {
1055                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1056                 if (ret)
1057                         return ret;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1064         .translate = gic_irq_domain_translate,
1065         .alloc = gic_irq_domain_alloc,
1066         .free = irq_domain_free_irqs_top,
1067 };
1068
1069 static const struct irq_domain_ops gic_irq_domain_ops = {
1070         .map = gic_irq_domain_map,
1071         .unmap = gic_irq_domain_unmap,
1072 };
1073
1074 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1075                           const char *name, bool use_eoimode1)
1076 {
1077         /* Initialize irq_chip */
1078         gic->chip = gic_chip;
1079         gic->chip.name = name;
1080         gic->chip.parent_device = dev;
1081
1082         if (use_eoimode1) {
1083                 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1084                 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1085                 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1086         }
1087
1088 #ifdef CONFIG_SMP
1089         if (gic == &gic_data[0])
1090                 gic->chip.irq_set_affinity = gic_set_affinity;
1091 #endif
1092 }
1093
1094 static int gic_init_bases(struct gic_chip_data *gic,
1095                           struct fwnode_handle *handle)
1096 {
1097         int gic_irqs, ret;
1098
1099         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1100                 /* Frankein-GIC without banked registers... */
1101                 unsigned int cpu;
1102
1103                 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1104                 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1105                 if (WARN_ON(!gic->dist_base.percpu_base ||
1106                             !gic->cpu_base.percpu_base)) {
1107                         ret = -ENOMEM;
1108                         goto error;
1109                 }
1110
1111                 for_each_possible_cpu(cpu) {
1112                         u32 mpidr = cpu_logical_map(cpu);
1113                         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1114                         unsigned long offset = gic->percpu_offset * core_id;
1115                         *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1116                                 gic->raw_dist_base + offset;
1117                         *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1118                                 gic->raw_cpu_base + offset;
1119                 }
1120
1121                 gic_set_base_accessor(gic, gic_get_percpu_base);
1122         } else {
1123                 /* Normal, sane GIC... */
1124                 WARN(gic->percpu_offset,
1125                      "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1126                      gic->percpu_offset);
1127                 gic->dist_base.common_base = gic->raw_dist_base;
1128                 gic->cpu_base.common_base = gic->raw_cpu_base;
1129                 gic_set_base_accessor(gic, gic_get_common_base);
1130         }
1131
1132         /*
1133          * Find out how many interrupts are supported.
1134          * The GIC only supports up to 1020 interrupt sources.
1135          */
1136         gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1137         gic_irqs = (gic_irqs + 1) * 32;
1138         if (gic_irqs > 1020)
1139                 gic_irqs = 1020;
1140         gic->gic_irqs = gic_irqs;
1141
1142         if (handle) {           /* DT/ACPI */
1143                 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1144                                                        &gic_irq_domain_hierarchy_ops,
1145                                                        gic);
1146         } else {                /* Legacy support */
1147                 /*
1148                  * For primary GICs, skip over SGIs.
1149                  * No secondary GIC support whatsoever.
1150                  */
1151                 int irq_base;
1152
1153                 gic_irqs -= 16; /* calculate # of irqs to allocate */
1154
1155                 irq_base = irq_alloc_descs(16, 16, gic_irqs,
1156                                            numa_node_id());
1157                 if (irq_base < 0) {
1158                         WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1159                         irq_base = 16;
1160                 }
1161
1162                 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1163                                                     16, &gic_irq_domain_ops, gic);
1164         }
1165
1166         if (WARN_ON(!gic->domain)) {
1167                 ret = -ENODEV;
1168                 goto error;
1169         }
1170
1171         gic_dist_init(gic);
1172         ret = gic_cpu_init(gic);
1173         if (ret)
1174                 goto error;
1175
1176         ret = gic_pm_init(gic);
1177         if (ret)
1178                 goto error;
1179
1180         return 0;
1181
1182 error:
1183         if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1184                 free_percpu(gic->dist_base.percpu_base);
1185                 free_percpu(gic->cpu_base.percpu_base);
1186         }
1187
1188         return ret;
1189 }
1190
1191 static int __init __gic_init_bases(struct gic_chip_data *gic,
1192                                    struct fwnode_handle *handle)
1193 {
1194         char *name;
1195         int i, ret;
1196
1197         if (WARN_ON(!gic || gic->domain))
1198                 return -EINVAL;
1199
1200         if (gic == &gic_data[0]) {
1201                 /*
1202                  * Initialize the CPU interface map to all CPUs.
1203                  * It will be refined as each CPU probes its ID.
1204                  * This is only necessary for the primary GIC.
1205                  */
1206                 for (i = 0; i < NR_GIC_CPU_IF; i++)
1207                         gic_cpu_map[i] = 0xff;
1208 #ifdef CONFIG_SMP
1209                 set_smp_cross_call(gic_raise_softirq);
1210 #endif
1211                 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1212                                           "irqchip/arm/gic:starting",
1213                                           gic_starting_cpu, NULL);
1214                 set_handle_irq(gic_handle_irq);
1215                 if (static_branch_likely(&supports_deactivate_key))
1216                         pr_info("GIC: Using split EOI/Deactivate mode\n");
1217         }
1218
1219         if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1220                 name = kasprintf(GFP_KERNEL, "GICv2");
1221                 gic_init_chip(gic, NULL, name, true);
1222         } else {
1223                 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1224                 gic_init_chip(gic, NULL, name, false);
1225         }
1226
1227         ret = gic_init_bases(gic, handle);
1228         if (ret)
1229                 kfree(name);
1230
1231         return ret;
1232 }
1233
1234 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
1235 {
1236         struct gic_chip_data *gic;
1237
1238         /*
1239          * Non-DT/ACPI systems won't run a hypervisor, so let's not
1240          * bother with these...
1241          */
1242         static_branch_disable(&supports_deactivate_key);
1243
1244         gic = &gic_data[0];
1245         gic->raw_dist_base = dist_base;
1246         gic->raw_cpu_base = cpu_base;
1247
1248         __gic_init_bases(gic, NULL);
1249 }
1250
1251 static void gic_teardown(struct gic_chip_data *gic)
1252 {
1253         if (WARN_ON(!gic))
1254                 return;
1255
1256         if (gic->raw_dist_base)
1257                 iounmap(gic->raw_dist_base);
1258         if (gic->raw_cpu_base)
1259                 iounmap(gic->raw_cpu_base);
1260 }
1261
1262 #ifdef CONFIG_OF
1263 static int gic_cnt __initdata;
1264 static bool gicv2_force_probe;
1265
1266 static int __init gicv2_force_probe_cfg(char *buf)
1267 {
1268         return strtobool(buf, &gicv2_force_probe);
1269 }
1270 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1271
1272 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1273 {
1274         struct resource cpuif_res;
1275
1276         of_address_to_resource(node, 1, &cpuif_res);
1277
1278         if (!is_hyp_mode_available())
1279                 return false;
1280         if (resource_size(&cpuif_res) < SZ_8K) {
1281                 void __iomem *alt;
1282                 /*
1283                  * Check for a stupid firmware that only exposes the
1284                  * first page of a GICv2.
1285                  */
1286                 if (!gic_check_gicv2(*base))
1287                         return false;
1288
1289                 if (!gicv2_force_probe) {
1290                         pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1291                         return false;
1292                 }
1293
1294                 alt = ioremap(cpuif_res.start, SZ_8K);
1295                 if (!alt)
1296                         return false;
1297                 if (!gic_check_gicv2(alt + SZ_4K)) {
1298                         /*
1299                          * The first page was that of a GICv2, and
1300                          * the second was *something*. Let's trust it
1301                          * to be a GICv2, and update the mapping.
1302                          */
1303                         pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1304                                 &cpuif_res.start);
1305                         iounmap(*base);
1306                         *base = alt;
1307                         return true;
1308                 }
1309
1310                 /*
1311                  * We detected *two* initial GICv2 pages in a
1312                  * row. Could be a GICv2 aliased over two 64kB
1313                  * pages. Update the resource, map the iospace, and
1314                  * pray.
1315                  */
1316                 iounmap(alt);
1317                 alt = ioremap(cpuif_res.start, SZ_128K);
1318                 if (!alt)
1319                         return false;
1320                 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1321                         &cpuif_res.start);
1322                 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1323                 iounmap(*base);
1324                 *base = alt;
1325         }
1326         if (resource_size(&cpuif_res) == SZ_128K) {
1327                 /*
1328                  * Verify that we have the first 4kB of a GICv2
1329                  * aliased over the first 64kB by checking the
1330                  * GICC_IIDR register on both ends.
1331                  */
1332                 if (!gic_check_gicv2(*base) ||
1333                     !gic_check_gicv2(*base + 0xf000))
1334                         return false;
1335
1336                 /*
1337                  * Move the base up by 60kB, so that we have a 8kB
1338                  * contiguous region, which allows us to use GICC_DIR
1339                  * at its normal offset. Please pass me that bucket.
1340                  */
1341                 *base += 0xf000;
1342                 cpuif_res.start += 0xf000;
1343                 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1344                         &cpuif_res.start);
1345         }
1346
1347         return true;
1348 }
1349
1350 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1351 {
1352         if (!gic || !node)
1353                 return -EINVAL;
1354
1355         gic->raw_dist_base = of_iomap(node, 0);
1356         if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1357                 goto error;
1358
1359         gic->raw_cpu_base = of_iomap(node, 1);
1360         if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1361                 goto error;
1362
1363         if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1364                 gic->percpu_offset = 0;
1365
1366         return 0;
1367
1368 error:
1369         gic_teardown(gic);
1370
1371         return -ENOMEM;
1372 }
1373
1374 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1375 {
1376         int ret;
1377
1378         if (!dev || !dev->of_node || !gic || !irq)
1379                 return -EINVAL;
1380
1381         *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1382         if (!*gic)
1383                 return -ENOMEM;
1384
1385         gic_init_chip(*gic, dev, dev->of_node->name, false);
1386
1387         ret = gic_of_setup(*gic, dev->of_node);
1388         if (ret)
1389                 return ret;
1390
1391         ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1392         if (ret) {
1393                 gic_teardown(*gic);
1394                 return ret;
1395         }
1396
1397         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1398
1399         return 0;
1400 }
1401
1402 static void __init gic_of_setup_kvm_info(struct device_node *node)
1403 {
1404         int ret;
1405         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1406         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1407
1408         gic_v2_kvm_info.type = GIC_V2;
1409
1410         gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1411         if (!gic_v2_kvm_info.maint_irq)
1412                 return;
1413
1414         ret = of_address_to_resource(node, 2, vctrl_res);
1415         if (ret)
1416                 return;
1417
1418         ret = of_address_to_resource(node, 3, vcpu_res);
1419         if (ret)
1420                 return;
1421
1422         if (static_branch_likely(&supports_deactivate_key))
1423                 gic_set_kvm_info(&gic_v2_kvm_info);
1424 }
1425
1426 int __init
1427 gic_of_init(struct device_node *node, struct device_node *parent)
1428 {
1429         struct gic_chip_data *gic;
1430         int irq, ret;
1431
1432         if (WARN_ON(!node))
1433                 return -ENODEV;
1434
1435         if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1436                 return -EINVAL;
1437
1438         gic = &gic_data[gic_cnt];
1439
1440         ret = gic_of_setup(gic, node);
1441         if (ret)
1442                 return ret;
1443
1444         /*
1445          * Disable split EOI/Deactivate if either HYP is not available
1446          * or the CPU interface is too small.
1447          */
1448         if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1449                 static_branch_disable(&supports_deactivate_key);
1450
1451         ret = __gic_init_bases(gic, &node->fwnode);
1452         if (ret) {
1453                 gic_teardown(gic);
1454                 return ret;
1455         }
1456
1457         if (!gic_cnt) {
1458                 gic_init_physaddr(node);
1459                 gic_of_setup_kvm_info(node);
1460         }
1461
1462         if (parent) {
1463                 irq = irq_of_parse_and_map(node, 0);
1464                 gic_cascade_irq(gic_cnt, irq);
1465         }
1466
1467         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1468                 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1469
1470         gic_cnt++;
1471         return 0;
1472 }
1473 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1474 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1475 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1476 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1477 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1478 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1479 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1480 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1481 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1482 #else
1483 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1484 {
1485         return -ENOTSUPP;
1486 }
1487 #endif
1488
1489 #ifdef CONFIG_ACPI
1490 static struct
1491 {
1492         phys_addr_t cpu_phys_base;
1493         u32 maint_irq;
1494         int maint_irq_mode;
1495         phys_addr_t vctrl_base;
1496         phys_addr_t vcpu_base;
1497 } acpi_data __initdata;
1498
1499 static int __init
1500 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
1501                         const unsigned long end)
1502 {
1503         struct acpi_madt_generic_interrupt *processor;
1504         phys_addr_t gic_cpu_base;
1505         static int cpu_base_assigned;
1506
1507         processor = (struct acpi_madt_generic_interrupt *)header;
1508
1509         if (BAD_MADT_GICC_ENTRY(processor, end))
1510                 return -EINVAL;
1511
1512         /*
1513          * There is no support for non-banked GICv1/2 register in ACPI spec.
1514          * All CPU interface addresses have to be the same.
1515          */
1516         gic_cpu_base = processor->base_address;
1517         if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1518                 return -EINVAL;
1519
1520         acpi_data.cpu_phys_base = gic_cpu_base;
1521         acpi_data.maint_irq = processor->vgic_interrupt;
1522         acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1523                                     ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1524         acpi_data.vctrl_base = processor->gich_base_address;
1525         acpi_data.vcpu_base = processor->gicv_base_address;
1526
1527         cpu_base_assigned = 1;
1528         return 0;
1529 }
1530
1531 /* The things you have to do to just *count* something... */
1532 static int __init acpi_dummy_func(union acpi_subtable_headers *header,
1533                                   const unsigned long end)
1534 {
1535         return 0;
1536 }
1537
1538 static bool __init acpi_gic_redist_is_present(void)
1539 {
1540         return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1541                                      acpi_dummy_func, 0) > 0;
1542 }
1543
1544 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1545                                      struct acpi_probe_entry *ape)
1546 {
1547         struct acpi_madt_generic_distributor *dist;
1548         dist = (struct acpi_madt_generic_distributor *)header;
1549
1550         return (dist->version == ape->driver_data &&
1551                 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1552                  !acpi_gic_redist_is_present()));
1553 }
1554
1555 #define ACPI_GICV2_DIST_MEM_SIZE        (SZ_4K)
1556 #define ACPI_GIC_CPU_IF_MEM_SIZE        (SZ_8K)
1557 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
1558 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
1559
1560 static void __init gic_acpi_setup_kvm_info(void)
1561 {
1562         int irq;
1563         struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1564         struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1565
1566         gic_v2_kvm_info.type = GIC_V2;
1567
1568         if (!acpi_data.vctrl_base)
1569                 return;
1570
1571         vctrl_res->flags = IORESOURCE_MEM;
1572         vctrl_res->start = acpi_data.vctrl_base;
1573         vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1574
1575         if (!acpi_data.vcpu_base)
1576                 return;
1577
1578         vcpu_res->flags = IORESOURCE_MEM;
1579         vcpu_res->start = acpi_data.vcpu_base;
1580         vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1581
1582         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1583                                 acpi_data.maint_irq_mode,
1584                                 ACPI_ACTIVE_HIGH);
1585         if (irq <= 0)
1586                 return;
1587
1588         gic_v2_kvm_info.maint_irq = irq;
1589
1590         gic_set_kvm_info(&gic_v2_kvm_info);
1591 }
1592
1593 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
1594                                    const unsigned long end)
1595 {
1596         struct acpi_madt_generic_distributor *dist;
1597         struct fwnode_handle *domain_handle;
1598         struct gic_chip_data *gic = &gic_data[0];
1599         int count, ret;
1600
1601         /* Collect CPU base addresses */
1602         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1603                                       gic_acpi_parse_madt_cpu, 0);
1604         if (count <= 0) {
1605                 pr_err("No valid GICC entries exist\n");
1606                 return -EINVAL;
1607         }
1608
1609         gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1610         if (!gic->raw_cpu_base) {
1611                 pr_err("Unable to map GICC registers\n");
1612                 return -ENOMEM;
1613         }
1614
1615         dist = (struct acpi_madt_generic_distributor *)header;
1616         gic->raw_dist_base = ioremap(dist->base_address,
1617                                      ACPI_GICV2_DIST_MEM_SIZE);
1618         if (!gic->raw_dist_base) {
1619                 pr_err("Unable to map GICD registers\n");
1620                 gic_teardown(gic);
1621                 return -ENOMEM;
1622         }
1623
1624         /*
1625          * Disable split EOI/Deactivate if HYP is not available. ACPI
1626          * guarantees that we'll always have a GICv2, so the CPU
1627          * interface will always be the right size.
1628          */
1629         if (!is_hyp_mode_available())
1630                 static_branch_disable(&supports_deactivate_key);
1631
1632         /*
1633          * Initialize GIC instance zero (no multi-GIC support).
1634          */
1635         domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
1636         if (!domain_handle) {
1637                 pr_err("Unable to allocate domain handle\n");
1638                 gic_teardown(gic);
1639                 return -ENOMEM;
1640         }
1641
1642         ret = __gic_init_bases(gic, domain_handle);
1643         if (ret) {
1644                 pr_err("Failed to initialise GIC\n");
1645                 irq_domain_free_fwnode(domain_handle);
1646                 gic_teardown(gic);
1647                 return ret;
1648         }
1649
1650         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1651
1652         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1653                 gicv2m_init(NULL, gic_data[0].domain);
1654
1655         if (static_branch_likely(&supports_deactivate_key))
1656                 gic_acpi_setup_kvm_info();
1657
1658         return 0;
1659 }
1660 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1661                      gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1662                      gic_v2_acpi_init);
1663 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1664                      gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1665                      gic_v2_acpi_init);
1666 #endif