1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitfield.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/dma-iommu.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/irqdomain.h>
19 #include <linux/list.h>
20 #include <linux/log2.h>
21 #include <linux/memblock.h>
23 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/percpu.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
40 #include "irq-gic-common.h"
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
46 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
47 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
49 #define RD_LOCAL_LPI_ENABLED BIT(0)
50 #define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1)
51 #define RD_LOCAL_MEMRESERVE_DONE BIT(2)
53 static u32 lpi_id_bits;
56 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
57 * deal with (one configuration byte per interrupt). PENDBASE has to
58 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
60 #define LPI_NRBITS lpi_id_bits
61 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
62 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
64 #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
67 * Collection structure - just an ID, and a redistributor address to
68 * ping. We use one per CPU as a bag of interrupts assigned to this
71 struct its_collection {
77 * The ITS_BASER structure - contains memory information, cached
78 * value of BASER register configuration and ITS page size.
90 * The ITS structure - contains most of the infrastructure, with the
91 * top-level MSI domain, the command queue, the collections, and the
92 * list of devices writing to it.
94 * dev_alloc_lock has to be taken for device allocations, while the
95 * spinlock must be taken to parse data structures such as the device
100 struct mutex dev_alloc_lock;
101 struct list_head entry;
103 void __iomem *sgir_base;
104 phys_addr_t phys_base;
105 struct its_cmd_block *cmd_base;
106 struct its_cmd_block *cmd_write;
107 struct its_baser tables[GITS_BASER_NR_REGS];
108 struct its_collection *collections;
109 struct fwnode_handle *fwnode_handle;
110 u64 (*get_msi_base)(struct its_device *its_dev);
115 struct list_head its_device_list;
117 unsigned long list_nr;
119 unsigned int msi_domain_flags;
120 u32 pre_its_base; /* for Socionext Synquacer */
121 int vlpi_redist_offset;
124 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
125 #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
126 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
128 #define ITS_ITT_ALIGN SZ_256
130 /* The maximum number of VPEID bits supported by VLPI commands */
131 #define ITS_MAX_VPEID_BITS \
134 if (gic_rdists->has_rvpeid && \
135 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
136 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
141 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
143 /* Convert page order to size in bytes */
144 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
146 struct event_lpi_map {
147 unsigned long *lpi_map;
149 irq_hw_number_t lpi_base;
151 raw_spinlock_t vlpi_lock;
153 struct its_vlpi_map *vlpi_maps;
158 * The ITS view of a device - belongs to an ITS, owns an interrupt
159 * translation table, and a list of interrupts. If it some of its
160 * LPIs are injected into a guest (GICv4), the event_map.vm field
161 * indicates which one.
164 struct list_head entry;
165 struct its_node *its;
166 struct event_lpi_map event_map;
175 struct its_device *dev;
176 struct its_vpe **vpes;
180 struct cpu_lpi_count {
185 static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
187 static LIST_HEAD(its_nodes);
188 static DEFINE_RAW_SPINLOCK(its_lock);
189 static struct rdists *gic_rdists;
190 static struct irq_domain *its_parent;
192 static unsigned long its_list_map;
193 static u16 vmovp_seq_num;
194 static DEFINE_RAW_SPINLOCK(vmovp_lock);
196 static DEFINE_IDA(its_vpeid_ida);
198 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
199 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
200 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
201 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
204 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
205 * always have vSGIs mapped.
207 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
209 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
212 static u16 get_its_list(struct its_vm *vm)
214 struct its_node *its;
215 unsigned long its_list = 0;
217 list_for_each_entry(its, &its_nodes, entry) {
221 if (require_its_list_vmovp(vm, its))
222 __set_bit(its->list_nr, &its_list);
225 return (u16)its_list;
228 static inline u32 its_get_event_id(struct irq_data *d)
230 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
231 return d->hwirq - its_dev->event_map.lpi_base;
234 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
237 struct its_node *its = its_dev->its;
239 return its->collections + its_dev->event_map.col_map[event];
242 static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
245 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
248 return &its_dev->event_map.vlpi_maps[event];
251 static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
253 if (irqd_is_forwarded_to_vcpu(d)) {
254 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
255 u32 event = its_get_event_id(d);
257 return dev_event_to_vlpi_map(its_dev, event);
263 static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
265 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
269 static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
271 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
274 static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
276 struct its_vlpi_map *map = get_vlpi_map(d);
280 cpu = vpe_to_cpuid_lock(map->vpe, flags);
282 /* Physical LPIs are already locked via the irq_desc lock */
283 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
284 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
285 /* Keep GCC quiet... */
292 static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
294 struct its_vlpi_map *map = get_vlpi_map(d);
297 vpe_to_cpuid_unlock(map->vpe, flags);
300 static struct its_collection *valid_col(struct its_collection *col)
302 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
308 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
310 if (valid_col(its->collections + vpe->col_idx))
317 * ITS command descriptors - parameters to be encoded in a command
320 struct its_cmd_desc {
323 struct its_device *dev;
328 struct its_device *dev;
333 struct its_device *dev;
338 struct its_device *dev;
343 struct its_collection *col;
348 struct its_device *dev;
354 struct its_device *dev;
355 struct its_collection *col;
360 struct its_device *dev;
365 struct its_collection *col;
374 struct its_collection *col;
380 struct its_device *dev;
388 struct its_device *dev;
395 struct its_collection *col;
416 * The ITS command block, which is what the ITS actually parses.
418 struct its_cmd_block {
421 __le64 raw_cmd_le[4];
425 #define ITS_CMD_QUEUE_SZ SZ_64K
426 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
428 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
429 struct its_cmd_block *,
430 struct its_cmd_desc *);
432 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
433 struct its_cmd_block *,
434 struct its_cmd_desc *);
436 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
438 u64 mask = GENMASK_ULL(h, l);
440 *raw_cmd |= (val << l) & mask;
443 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
445 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
448 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
450 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
453 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
455 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
458 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
460 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
463 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
465 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
468 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
470 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
473 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
475 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
478 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
480 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
483 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
485 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
488 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
490 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
493 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
495 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
498 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
500 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
503 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
505 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
508 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
510 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
513 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
515 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
518 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
520 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
523 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
525 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
528 static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
530 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
533 static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
535 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
538 static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
540 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
543 static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
546 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
549 static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
552 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
555 static void its_encode_db(struct its_cmd_block *cmd, bool db)
557 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
560 static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
562 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
565 static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
567 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
570 static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
572 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
575 static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
577 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
580 static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
582 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
585 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
587 /* Let's fixup BE commands */
588 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
589 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
590 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
591 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
594 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
595 struct its_cmd_block *cmd,
596 struct its_cmd_desc *desc)
598 unsigned long itt_addr;
599 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
601 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
602 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
604 its_encode_cmd(cmd, GITS_CMD_MAPD);
605 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
606 its_encode_size(cmd, size - 1);
607 its_encode_itt(cmd, itt_addr);
608 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
615 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
616 struct its_cmd_block *cmd,
617 struct its_cmd_desc *desc)
619 its_encode_cmd(cmd, GITS_CMD_MAPC);
620 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
621 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
622 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
626 return desc->its_mapc_cmd.col;
629 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
630 struct its_cmd_block *cmd,
631 struct its_cmd_desc *desc)
633 struct its_collection *col;
635 col = dev_event_to_col(desc->its_mapti_cmd.dev,
636 desc->its_mapti_cmd.event_id);
638 its_encode_cmd(cmd, GITS_CMD_MAPTI);
639 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
640 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
641 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
642 its_encode_collection(cmd, col->col_id);
646 return valid_col(col);
649 static struct its_collection *its_build_movi_cmd(struct its_node *its,
650 struct its_cmd_block *cmd,
651 struct its_cmd_desc *desc)
653 struct its_collection *col;
655 col = dev_event_to_col(desc->its_movi_cmd.dev,
656 desc->its_movi_cmd.event_id);
658 its_encode_cmd(cmd, GITS_CMD_MOVI);
659 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
660 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
661 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
665 return valid_col(col);
668 static struct its_collection *its_build_discard_cmd(struct its_node *its,
669 struct its_cmd_block *cmd,
670 struct its_cmd_desc *desc)
672 struct its_collection *col;
674 col = dev_event_to_col(desc->its_discard_cmd.dev,
675 desc->its_discard_cmd.event_id);
677 its_encode_cmd(cmd, GITS_CMD_DISCARD);
678 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
679 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
683 return valid_col(col);
686 static struct its_collection *its_build_inv_cmd(struct its_node *its,
687 struct its_cmd_block *cmd,
688 struct its_cmd_desc *desc)
690 struct its_collection *col;
692 col = dev_event_to_col(desc->its_inv_cmd.dev,
693 desc->its_inv_cmd.event_id);
695 its_encode_cmd(cmd, GITS_CMD_INV);
696 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
697 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
701 return valid_col(col);
704 static struct its_collection *its_build_int_cmd(struct its_node *its,
705 struct its_cmd_block *cmd,
706 struct its_cmd_desc *desc)
708 struct its_collection *col;
710 col = dev_event_to_col(desc->its_int_cmd.dev,
711 desc->its_int_cmd.event_id);
713 its_encode_cmd(cmd, GITS_CMD_INT);
714 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
715 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
719 return valid_col(col);
722 static struct its_collection *its_build_clear_cmd(struct its_node *its,
723 struct its_cmd_block *cmd,
724 struct its_cmd_desc *desc)
726 struct its_collection *col;
728 col = dev_event_to_col(desc->its_clear_cmd.dev,
729 desc->its_clear_cmd.event_id);
731 its_encode_cmd(cmd, GITS_CMD_CLEAR);
732 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
733 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
737 return valid_col(col);
740 static struct its_collection *its_build_invall_cmd(struct its_node *its,
741 struct its_cmd_block *cmd,
742 struct its_cmd_desc *desc)
744 its_encode_cmd(cmd, GITS_CMD_INVALL);
745 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
749 return desc->its_invall_cmd.col;
752 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
753 struct its_cmd_block *cmd,
754 struct its_cmd_desc *desc)
756 its_encode_cmd(cmd, GITS_CMD_VINVALL);
757 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
761 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
764 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
765 struct its_cmd_block *cmd,
766 struct its_cmd_desc *desc)
768 unsigned long vpt_addr, vconf_addr;
772 its_encode_cmd(cmd, GITS_CMD_VMAPP);
773 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
774 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
776 if (!desc->its_vmapp_cmd.valid) {
778 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
779 its_encode_alloc(cmd, alloc);
785 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
786 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
788 its_encode_target(cmd, target);
789 its_encode_vpt_addr(cmd, vpt_addr);
790 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
795 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
797 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
799 its_encode_alloc(cmd, alloc);
802 * GICv4.1 provides a way to get the VLPI state, which needs the vPE
803 * to be unmapped first, and in this case, we may remap the vPE
804 * back while the VPT is not empty. So we can't assume that the
805 * VPT is empty on map. This is why we never advertise PTZ.
807 its_encode_ptz(cmd, false);
808 its_encode_vconf_addr(cmd, vconf_addr);
809 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
814 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
817 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
818 struct its_cmd_block *cmd,
819 struct its_cmd_desc *desc)
823 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
824 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
828 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
829 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
830 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
831 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
832 its_encode_db_phys_id(cmd, db);
833 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
837 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
840 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
841 struct its_cmd_block *cmd,
842 struct its_cmd_desc *desc)
846 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
847 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
851 its_encode_cmd(cmd, GITS_CMD_VMOVI);
852 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
853 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
854 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
855 its_encode_db_phys_id(cmd, db);
856 its_encode_db_valid(cmd, true);
860 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
863 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
864 struct its_cmd_block *cmd,
865 struct its_cmd_desc *desc)
869 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
870 its_encode_cmd(cmd, GITS_CMD_VMOVP);
871 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
872 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
873 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
874 its_encode_target(cmd, target);
877 its_encode_db(cmd, true);
878 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
883 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
886 static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
887 struct its_cmd_block *cmd,
888 struct its_cmd_desc *desc)
890 struct its_vlpi_map *map;
892 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
893 desc->its_inv_cmd.event_id);
895 its_encode_cmd(cmd, GITS_CMD_INV);
896 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
897 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
901 return valid_vpe(its, map->vpe);
904 static struct its_vpe *its_build_vint_cmd(struct its_node *its,
905 struct its_cmd_block *cmd,
906 struct its_cmd_desc *desc)
908 struct its_vlpi_map *map;
910 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
911 desc->its_int_cmd.event_id);
913 its_encode_cmd(cmd, GITS_CMD_INT);
914 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
915 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
919 return valid_vpe(its, map->vpe);
922 static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
923 struct its_cmd_block *cmd,
924 struct its_cmd_desc *desc)
926 struct its_vlpi_map *map;
928 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
929 desc->its_clear_cmd.event_id);
931 its_encode_cmd(cmd, GITS_CMD_CLEAR);
932 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
933 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
937 return valid_vpe(its, map->vpe);
940 static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
941 struct its_cmd_block *cmd,
942 struct its_cmd_desc *desc)
944 if (WARN_ON(!is_v4_1(its)))
947 its_encode_cmd(cmd, GITS_CMD_INVDB);
948 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
952 return valid_vpe(its, desc->its_invdb_cmd.vpe);
955 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
956 struct its_cmd_block *cmd,
957 struct its_cmd_desc *desc)
959 if (WARN_ON(!is_v4_1(its)))
962 its_encode_cmd(cmd, GITS_CMD_VSGI);
963 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
964 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
965 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
966 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
967 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
968 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
972 return valid_vpe(its, desc->its_vsgi_cmd.vpe);
975 static u64 its_cmd_ptr_to_offset(struct its_node *its,
976 struct its_cmd_block *ptr)
978 return (ptr - its->cmd_base) * sizeof(*ptr);
981 static int its_queue_full(struct its_node *its)
986 widx = its->cmd_write - its->cmd_base;
987 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
989 /* This is incredibly unlikely to happen, unless the ITS locks up. */
990 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
996 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
998 struct its_cmd_block *cmd;
999 u32 count = 1000000; /* 1s! */
1001 while (its_queue_full(its)) {
1004 pr_err_ratelimited("ITS queue not draining\n");
1011 cmd = its->cmd_write++;
1013 /* Handle queue wrapping */
1014 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1015 its->cmd_write = its->cmd_base;
1018 cmd->raw_cmd[0] = 0;
1019 cmd->raw_cmd[1] = 0;
1020 cmd->raw_cmd[2] = 0;
1021 cmd->raw_cmd[3] = 0;
1026 static struct its_cmd_block *its_post_commands(struct its_node *its)
1028 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1030 writel_relaxed(wr, its->base + GITS_CWRITER);
1032 return its->cmd_write;
1035 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1038 * Make sure the commands written to memory are observable by
1041 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1042 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1047 static int its_wait_for_range_completion(struct its_node *its,
1049 struct its_cmd_block *to)
1051 u64 rd_idx, to_idx, linear_idx;
1052 u32 count = 1000000; /* 1s! */
1054 /* Linearize to_idx if the command set has wrapped around */
1055 to_idx = its_cmd_ptr_to_offset(its, to);
1056 if (to_idx < prev_idx)
1057 to_idx += ITS_CMD_QUEUE_SZ;
1059 linear_idx = prev_idx;
1064 rd_idx = readl_relaxed(its->base + GITS_CREADR);
1067 * Compute the read pointer progress, taking the
1068 * potential wrap-around into account.
1070 delta = rd_idx - prev_idx;
1071 if (rd_idx < prev_idx)
1072 delta += ITS_CMD_QUEUE_SZ;
1074 linear_idx += delta;
1075 if (linear_idx >= to_idx)
1080 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1081 to_idx, linear_idx);
1092 /* Warning, macro hell follows */
1093 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
1094 void name(struct its_node *its, \
1095 buildtype builder, \
1096 struct its_cmd_desc *desc) \
1098 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
1099 synctype *sync_obj; \
1100 unsigned long flags; \
1103 raw_spin_lock_irqsave(&its->lock, flags); \
1105 cmd = its_allocate_entry(its); \
1106 if (!cmd) { /* We're soooooo screewed... */ \
1107 raw_spin_unlock_irqrestore(&its->lock, flags); \
1110 sync_obj = builder(its, cmd, desc); \
1111 its_flush_cmd(its, cmd); \
1114 sync_cmd = its_allocate_entry(its); \
1118 buildfn(its, sync_cmd, sync_obj); \
1119 its_flush_cmd(its, sync_cmd); \
1123 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1124 next_cmd = its_post_commands(its); \
1125 raw_spin_unlock_irqrestore(&its->lock, flags); \
1127 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1128 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1131 static void its_build_sync_cmd(struct its_node *its,
1132 struct its_cmd_block *sync_cmd,
1133 struct its_collection *sync_col)
1135 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1136 its_encode_target(sync_cmd, sync_col->target_address);
1138 its_fixup_cmd(sync_cmd);
1141 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1142 struct its_collection, its_build_sync_cmd)
1144 static void its_build_vsync_cmd(struct its_node *its,
1145 struct its_cmd_block *sync_cmd,
1146 struct its_vpe *sync_vpe)
1148 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1149 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1151 its_fixup_cmd(sync_cmd);
1154 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1155 struct its_vpe, its_build_vsync_cmd)
1157 static void its_send_int(struct its_device *dev, u32 event_id)
1159 struct its_cmd_desc desc;
1161 desc.its_int_cmd.dev = dev;
1162 desc.its_int_cmd.event_id = event_id;
1164 its_send_single_command(dev->its, its_build_int_cmd, &desc);
1167 static void its_send_clear(struct its_device *dev, u32 event_id)
1169 struct its_cmd_desc desc;
1171 desc.its_clear_cmd.dev = dev;
1172 desc.its_clear_cmd.event_id = event_id;
1174 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1177 static void its_send_inv(struct its_device *dev, u32 event_id)
1179 struct its_cmd_desc desc;
1181 desc.its_inv_cmd.dev = dev;
1182 desc.its_inv_cmd.event_id = event_id;
1184 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1187 static void its_send_mapd(struct its_device *dev, int valid)
1189 struct its_cmd_desc desc;
1191 desc.its_mapd_cmd.dev = dev;
1192 desc.its_mapd_cmd.valid = !!valid;
1194 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1197 static void its_send_mapc(struct its_node *its, struct its_collection *col,
1200 struct its_cmd_desc desc;
1202 desc.its_mapc_cmd.col = col;
1203 desc.its_mapc_cmd.valid = !!valid;
1205 its_send_single_command(its, its_build_mapc_cmd, &desc);
1208 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1210 struct its_cmd_desc desc;
1212 desc.its_mapti_cmd.dev = dev;
1213 desc.its_mapti_cmd.phys_id = irq_id;
1214 desc.its_mapti_cmd.event_id = id;
1216 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1219 static void its_send_movi(struct its_device *dev,
1220 struct its_collection *col, u32 id)
1222 struct its_cmd_desc desc;
1224 desc.its_movi_cmd.dev = dev;
1225 desc.its_movi_cmd.col = col;
1226 desc.its_movi_cmd.event_id = id;
1228 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1231 static void its_send_discard(struct its_device *dev, u32 id)
1233 struct its_cmd_desc desc;
1235 desc.its_discard_cmd.dev = dev;
1236 desc.its_discard_cmd.event_id = id;
1238 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1241 static void its_send_invall(struct its_node *its, struct its_collection *col)
1243 struct its_cmd_desc desc;
1245 desc.its_invall_cmd.col = col;
1247 its_send_single_command(its, its_build_invall_cmd, &desc);
1250 static void its_send_vmapti(struct its_device *dev, u32 id)
1252 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1253 struct its_cmd_desc desc;
1255 desc.its_vmapti_cmd.vpe = map->vpe;
1256 desc.its_vmapti_cmd.dev = dev;
1257 desc.its_vmapti_cmd.virt_id = map->vintid;
1258 desc.its_vmapti_cmd.event_id = id;
1259 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1261 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1264 static void its_send_vmovi(struct its_device *dev, u32 id)
1266 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1267 struct its_cmd_desc desc;
1269 desc.its_vmovi_cmd.vpe = map->vpe;
1270 desc.its_vmovi_cmd.dev = dev;
1271 desc.its_vmovi_cmd.event_id = id;
1272 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1274 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1277 static void its_send_vmapp(struct its_node *its,
1278 struct its_vpe *vpe, bool valid)
1280 struct its_cmd_desc desc;
1282 desc.its_vmapp_cmd.vpe = vpe;
1283 desc.its_vmapp_cmd.valid = valid;
1284 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1286 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1289 static void its_send_vmovp(struct its_vpe *vpe)
1291 struct its_cmd_desc desc = {};
1292 struct its_node *its;
1293 unsigned long flags;
1294 int col_id = vpe->col_idx;
1296 desc.its_vmovp_cmd.vpe = vpe;
1298 if (!its_list_map) {
1299 its = list_first_entry(&its_nodes, struct its_node, entry);
1300 desc.its_vmovp_cmd.col = &its->collections[col_id];
1301 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1306 * Yet another marvel of the architecture. If using the
1307 * its_list "feature", we need to make sure that all ITSs
1308 * receive all VMOVP commands in the same order. The only way
1309 * to guarantee this is to make vmovp a serialization point.
1313 raw_spin_lock_irqsave(&vmovp_lock, flags);
1315 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1316 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1319 list_for_each_entry(its, &its_nodes, entry) {
1323 if (!require_its_list_vmovp(vpe->its_vm, its))
1326 desc.its_vmovp_cmd.col = &its->collections[col_id];
1327 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1330 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1333 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1335 struct its_cmd_desc desc;
1337 desc.its_vinvall_cmd.vpe = vpe;
1338 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1341 static void its_send_vinv(struct its_device *dev, u32 event_id)
1343 struct its_cmd_desc desc;
1346 * There is no real VINV command. This is just a normal INV,
1347 * with a VSYNC instead of a SYNC.
1349 desc.its_inv_cmd.dev = dev;
1350 desc.its_inv_cmd.event_id = event_id;
1352 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1355 static void its_send_vint(struct its_device *dev, u32 event_id)
1357 struct its_cmd_desc desc;
1360 * There is no real VINT command. This is just a normal INT,
1361 * with a VSYNC instead of a SYNC.
1363 desc.its_int_cmd.dev = dev;
1364 desc.its_int_cmd.event_id = event_id;
1366 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1369 static void its_send_vclear(struct its_device *dev, u32 event_id)
1371 struct its_cmd_desc desc;
1374 * There is no real VCLEAR command. This is just a normal CLEAR,
1375 * with a VSYNC instead of a SYNC.
1377 desc.its_clear_cmd.dev = dev;
1378 desc.its_clear_cmd.event_id = event_id;
1380 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1383 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1385 struct its_cmd_desc desc;
1387 desc.its_invdb_cmd.vpe = vpe;
1388 its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1392 * irqchip functions - assumes MSI, mostly.
1394 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1396 struct its_vlpi_map *map = get_vlpi_map(d);
1397 irq_hw_number_t hwirq;
1402 va = page_address(map->vm->vprop_page);
1403 hwirq = map->vintid;
1405 /* Remember the updated property */
1406 map->properties &= ~clr;
1407 map->properties |= set | LPI_PROP_GROUP1;
1409 va = gic_rdists->prop_table_va;
1413 cfg = va + hwirq - 8192;
1415 *cfg |= set | LPI_PROP_GROUP1;
1418 * Make the above write visible to the redistributors.
1419 * And yes, we're flushing exactly: One. Single. Byte.
1422 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1423 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1428 static void wait_for_syncr(void __iomem *rdbase)
1430 while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1434 static void direct_lpi_inv(struct irq_data *d)
1436 struct its_vlpi_map *map = get_vlpi_map(d);
1437 void __iomem *rdbase;
1438 unsigned long flags;
1443 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1445 WARN_ON(!is_v4_1(its_dev->its));
1447 val = GICR_INVLPIR_V;
1448 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1449 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1454 /* Target the redistributor this LPI is currently routed to */
1455 cpu = irq_to_cpuid_lock(d, &flags);
1456 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1457 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1458 gic_write_lpir(val, rdbase + GICR_INVLPIR);
1460 wait_for_syncr(rdbase);
1461 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1462 irq_to_cpuid_unlock(d, flags);
1465 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1467 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1469 lpi_write_config(d, clr, set);
1470 if (gic_rdists->has_direct_lpi &&
1471 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1473 else if (!irqd_is_forwarded_to_vcpu(d))
1474 its_send_inv(its_dev, its_get_event_id(d));
1476 its_send_vinv(its_dev, its_get_event_id(d));
1479 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1481 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1482 u32 event = its_get_event_id(d);
1483 struct its_vlpi_map *map;
1486 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1489 if (is_v4_1(its_dev->its))
1492 map = dev_event_to_vlpi_map(its_dev, event);
1494 if (map->db_enabled == enable)
1497 map->db_enabled = enable;
1500 * More fun with the architecture:
1502 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1503 * value or to 1023, depending on the enable bit. But that
1504 * would be issuing a mapping for an /existing/ DevID+EventID
1505 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1506 * to the /same/ vPE, using this opportunity to adjust the
1507 * doorbell. Mouahahahaha. We loves it, Precious.
1509 its_send_vmovi(its_dev, event);
1512 static void its_mask_irq(struct irq_data *d)
1514 if (irqd_is_forwarded_to_vcpu(d))
1515 its_vlpi_set_doorbell(d, false);
1517 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1520 static void its_unmask_irq(struct irq_data *d)
1522 if (irqd_is_forwarded_to_vcpu(d))
1523 its_vlpi_set_doorbell(d, true);
1525 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1528 static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1530 if (irqd_affinity_is_managed(d))
1531 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1533 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1536 static void its_inc_lpi_count(struct irq_data *d, int cpu)
1538 if (irqd_affinity_is_managed(d))
1539 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1541 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1544 static void its_dec_lpi_count(struct irq_data *d, int cpu)
1546 if (irqd_affinity_is_managed(d))
1547 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1549 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1552 static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1553 const struct cpumask *cpu_mask)
1555 unsigned int cpu = nr_cpu_ids, tmp;
1556 int count = S32_MAX;
1558 for_each_cpu(tmp, cpu_mask) {
1559 int this_count = its_read_lpi_count(d, tmp);
1560 if (this_count < count) {
1570 * As suggested by Thomas Gleixner in:
1571 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1573 static int its_select_cpu(struct irq_data *d,
1574 const struct cpumask *aff_mask)
1576 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1577 cpumask_var_t tmpmask;
1580 if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
1583 node = its_dev->its->numa_node;
1585 if (!irqd_affinity_is_managed(d)) {
1586 /* First try the NUMA node */
1587 if (node != NUMA_NO_NODE) {
1589 * Try the intersection of the affinity mask and the
1590 * node mask (and the online mask, just to be safe).
1592 cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1593 cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1596 * Ideally, we would check if the mask is empty, and
1597 * try again on the full node here.
1599 * But it turns out that the way ACPI describes the
1600 * affinity for ITSs only deals about memory, and
1601 * not target CPUs, so it cannot describe a single
1602 * ITS placed next to two NUMA nodes.
1604 * Instead, just fallback on the online mask. This
1605 * diverges from Thomas' suggestion above.
1607 cpu = cpumask_pick_least_loaded(d, tmpmask);
1608 if (cpu < nr_cpu_ids)
1611 /* If we can't cross sockets, give up */
1612 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1615 /* If the above failed, expand the search */
1618 /* Try the intersection of the affinity and online masks */
1619 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1621 /* If that doesn't fly, the online mask is the last resort */
1622 if (cpumask_empty(tmpmask))
1623 cpumask_copy(tmpmask, cpu_online_mask);
1625 cpu = cpumask_pick_least_loaded(d, tmpmask);
1627 cpumask_and(tmpmask, irq_data_get_affinity_mask(d), cpu_online_mask);
1629 /* If we cannot cross sockets, limit the search to that node */
1630 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1631 node != NUMA_NO_NODE)
1632 cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1634 cpu = cpumask_pick_least_loaded(d, tmpmask);
1637 free_cpumask_var(tmpmask);
1639 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1643 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1646 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1647 struct its_collection *target_col;
1648 u32 id = its_get_event_id(d);
1651 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1652 if (irqd_is_forwarded_to_vcpu(d))
1655 prev_cpu = its_dev->event_map.col_map[id];
1656 its_dec_lpi_count(d, prev_cpu);
1659 cpu = its_select_cpu(d, mask_val);
1661 cpu = cpumask_pick_least_loaded(d, mask_val);
1663 if (cpu < 0 || cpu >= nr_cpu_ids)
1666 /* don't set the affinity when the target cpu is same as current one */
1667 if (cpu != prev_cpu) {
1668 target_col = &its_dev->its->collections[cpu];
1669 its_send_movi(its_dev, target_col, id);
1670 its_dev->event_map.col_map[id] = cpu;
1671 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1674 its_inc_lpi_count(d, cpu);
1676 return IRQ_SET_MASK_OK_DONE;
1679 its_inc_lpi_count(d, prev_cpu);
1683 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1685 struct its_node *its = its_dev->its;
1687 return its->phys_base + GITS_TRANSLATER;
1690 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1692 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1693 struct its_node *its;
1697 addr = its->get_msi_base(its_dev);
1699 msg->address_lo = lower_32_bits(addr);
1700 msg->address_hi = upper_32_bits(addr);
1701 msg->data = its_get_event_id(d);
1703 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1706 static int its_irq_set_irqchip_state(struct irq_data *d,
1707 enum irqchip_irq_state which,
1710 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1711 u32 event = its_get_event_id(d);
1713 if (which != IRQCHIP_STATE_PENDING)
1716 if (irqd_is_forwarded_to_vcpu(d)) {
1718 its_send_vint(its_dev, event);
1720 its_send_vclear(its_dev, event);
1723 its_send_int(its_dev, event);
1725 its_send_clear(its_dev, event);
1731 static int its_irq_retrigger(struct irq_data *d)
1733 return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
1737 * Two favourable cases:
1739 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1742 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1743 * and we're better off mapping all VPEs always
1745 * If neither (a) nor (b) is true, then we map vPEs on demand.
1748 static bool gic_requires_eager_mapping(void)
1750 if (!its_list_map || gic_rdists->has_rvpeid)
1756 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1758 unsigned long flags;
1760 if (gic_requires_eager_mapping())
1763 raw_spin_lock_irqsave(&vmovp_lock, flags);
1766 * If the VM wasn't mapped yet, iterate over the vpes and get
1769 vm->vlpi_count[its->list_nr]++;
1771 if (vm->vlpi_count[its->list_nr] == 1) {
1774 for (i = 0; i < vm->nr_vpes; i++) {
1775 struct its_vpe *vpe = vm->vpes[i];
1776 struct irq_data *d = irq_get_irq_data(vpe->irq);
1778 /* Map the VPE to the first possible CPU */
1779 vpe->col_idx = cpumask_first(cpu_online_mask);
1780 its_send_vmapp(its, vpe, true);
1781 its_send_vinvall(its, vpe);
1782 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1786 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1789 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1791 unsigned long flags;
1793 /* Not using the ITS list? Everything is always mapped. */
1794 if (gic_requires_eager_mapping())
1797 raw_spin_lock_irqsave(&vmovp_lock, flags);
1799 if (!--vm->vlpi_count[its->list_nr]) {
1802 for (i = 0; i < vm->nr_vpes; i++)
1803 its_send_vmapp(its, vm->vpes[i], false);
1806 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1809 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1811 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1812 u32 event = its_get_event_id(d);
1818 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1820 if (!its_dev->event_map.vm) {
1821 struct its_vlpi_map *maps;
1823 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1830 its_dev->event_map.vm = info->map->vm;
1831 its_dev->event_map.vlpi_maps = maps;
1832 } else if (its_dev->event_map.vm != info->map->vm) {
1837 /* Get our private copy of the mapping information */
1838 its_dev->event_map.vlpi_maps[event] = *info->map;
1840 if (irqd_is_forwarded_to_vcpu(d)) {
1841 /* Already mapped, move it around */
1842 its_send_vmovi(its_dev, event);
1844 /* Ensure all the VPEs are mapped on this ITS */
1845 its_map_vm(its_dev->its, info->map->vm);
1848 * Flag the interrupt as forwarded so that we can
1849 * start poking the virtual property table.
1851 irqd_set_forwarded_to_vcpu(d);
1853 /* Write out the property to the prop table */
1854 lpi_write_config(d, 0xff, info->map->properties);
1856 /* Drop the physical mapping */
1857 its_send_discard(its_dev, event);
1859 /* and install the virtual one */
1860 its_send_vmapti(its_dev, event);
1862 /* Increment the number of VLPIs */
1863 its_dev->event_map.nr_vlpis++;
1867 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1871 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1873 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1874 struct its_vlpi_map *map;
1877 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1879 map = get_vlpi_map(d);
1881 if (!its_dev->event_map.vm || !map) {
1886 /* Copy our mapping information to the incoming request */
1890 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1894 static int its_vlpi_unmap(struct irq_data *d)
1896 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1897 u32 event = its_get_event_id(d);
1900 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1902 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1907 /* Drop the virtual mapping */
1908 its_send_discard(its_dev, event);
1910 /* and restore the physical one */
1911 irqd_clr_forwarded_to_vcpu(d);
1912 its_send_mapti(its_dev, d->hwirq, event);
1913 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1917 /* Potentially unmap the VM from this ITS */
1918 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1921 * Drop the refcount and make the device available again if
1922 * this was the last VLPI.
1924 if (!--its_dev->event_map.nr_vlpis) {
1925 its_dev->event_map.vm = NULL;
1926 kfree(its_dev->event_map.vlpi_maps);
1930 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1934 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1936 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1938 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1941 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1942 lpi_update_config(d, 0xff, info->config);
1944 lpi_write_config(d, 0xff, info->config);
1945 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1950 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1952 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1953 struct its_cmd_info *info = vcpu_info;
1956 if (!is_v4(its_dev->its))
1959 /* Unmap request? */
1961 return its_vlpi_unmap(d);
1963 switch (info->cmd_type) {
1965 return its_vlpi_map(d, info);
1968 return its_vlpi_get(d, info);
1970 case PROP_UPDATE_VLPI:
1971 case PROP_UPDATE_AND_INV_VLPI:
1972 return its_vlpi_prop_update(d, info);
1979 static struct irq_chip its_irq_chip = {
1981 .irq_mask = its_mask_irq,
1982 .irq_unmask = its_unmask_irq,
1983 .irq_eoi = irq_chip_eoi_parent,
1984 .irq_set_affinity = its_set_affinity,
1985 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1986 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1987 .irq_retrigger = its_irq_retrigger,
1988 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1993 * How we allocate LPIs:
1995 * lpi_range_list contains ranges of LPIs that are to available to
1996 * allocate from. To allocate LPIs, just pick the first range that
1997 * fits the required allocation, and reduce it by the required
1998 * amount. Once empty, remove the range from the list.
2000 * To free a range of LPIs, add a free range to the list, sort it and
2001 * merge the result if the new range happens to be adjacent to an
2002 * already free block.
2004 * The consequence of the above is that allocation is cost is low, but
2005 * freeing is expensive. We assumes that freeing rarely occurs.
2007 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
2009 static DEFINE_MUTEX(lpi_range_lock);
2010 static LIST_HEAD(lpi_range_list);
2013 struct list_head entry;
2018 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2020 struct lpi_range *range;
2022 range = kmalloc(sizeof(*range), GFP_KERNEL);
2024 range->base_id = base;
2031 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2033 struct lpi_range *range, *tmp;
2036 mutex_lock(&lpi_range_lock);
2038 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2039 if (range->span >= nr_lpis) {
2040 *base = range->base_id;
2041 range->base_id += nr_lpis;
2042 range->span -= nr_lpis;
2044 if (range->span == 0) {
2045 list_del(&range->entry);
2054 mutex_unlock(&lpi_range_lock);
2056 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2060 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2062 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2064 if (a->base_id + a->span != b->base_id)
2066 b->base_id = a->base_id;
2068 list_del(&a->entry);
2072 static int free_lpi_range(u32 base, u32 nr_lpis)
2074 struct lpi_range *new, *old;
2076 new = mk_lpi_range(base, nr_lpis);
2080 mutex_lock(&lpi_range_lock);
2082 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2083 if (old->base_id < base)
2087 * old is the last element with ->base_id smaller than base,
2088 * so new goes right after it. If there are no elements with
2089 * ->base_id smaller than base, &old->entry ends up pointing
2090 * at the head of the list, and inserting new it the start of
2091 * the list is the right thing to do in that case as well.
2093 list_add(&new->entry, &old->entry);
2095 * Now check if we can merge with the preceding and/or
2098 merge_lpi_ranges(old, new);
2099 merge_lpi_ranges(new, list_next_entry(new, entry));
2101 mutex_unlock(&lpi_range_lock);
2105 static int __init its_lpi_init(u32 id_bits)
2107 u32 lpis = (1UL << id_bits) - 8192;
2111 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2113 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2115 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2120 * Initializing the allocator is just the same as freeing the
2121 * full range of LPIs.
2123 err = free_lpi_range(8192, lpis);
2124 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2128 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2130 unsigned long *bitmap = NULL;
2134 err = alloc_lpi_range(nr_irqs, base);
2139 } while (nr_irqs > 0);
2147 bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC);
2155 *base = *nr_ids = 0;
2160 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2162 WARN_ON(free_lpi_range(base, nr_ids));
2163 bitmap_free(bitmap);
2166 static void gic_reset_prop_table(void *va)
2168 /* Priority 0xa0, Group-1, disabled */
2169 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2171 /* Make sure the GIC will observe the written configuration */
2172 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2175 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2177 struct page *prop_page;
2179 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2183 gic_reset_prop_table(page_address(prop_page));
2188 static void its_free_prop_table(struct page *prop_page)
2190 free_pages((unsigned long)page_address(prop_page),
2191 get_order(LPI_PROPBASE_SZ));
2194 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2196 phys_addr_t start, end, addr_end;
2200 * We don't bother checking for a kdump kernel as by
2201 * construction, the LPI tables are out of this kernel's
2204 if (is_kdump_kernel())
2207 addr_end = addr + size - 1;
2209 for_each_reserved_mem_range(i, &start, &end) {
2210 if (addr >= start && addr_end <= end)
2214 /* Not found, not a good sign... */
2215 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2217 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2221 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2223 if (efi_enabled(EFI_CONFIG_TABLES))
2224 return efi_mem_reserve_persistent(addr, size);
2229 static int __init its_setup_lpi_prop_table(void)
2231 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2234 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2235 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2237 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2238 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2241 gic_reset_prop_table(gic_rdists->prop_table_va);
2245 lpi_id_bits = min_t(u32,
2246 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2247 ITS_MAX_LPI_NRBITS);
2248 page = its_allocate_prop_table(GFP_NOWAIT);
2250 pr_err("Failed to allocate PROPBASE\n");
2254 gic_rdists->prop_table_pa = page_to_phys(page);
2255 gic_rdists->prop_table_va = page_address(page);
2256 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2260 pr_info("GICv3: using LPI property table @%pa\n",
2261 &gic_rdists->prop_table_pa);
2263 return its_lpi_init(lpi_id_bits);
2266 static const char *its_base_type_string[] = {
2267 [GITS_BASER_TYPE_DEVICE] = "Devices",
2268 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
2269 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
2270 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
2271 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
2272 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
2273 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
2276 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2278 u32 idx = baser - its->tables;
2280 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2283 static void its_write_baser(struct its_node *its, struct its_baser *baser,
2286 u32 idx = baser - its->tables;
2288 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2289 baser->val = its_read_baser(its, baser);
2292 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2293 u64 cache, u64 shr, u32 order, bool indirect)
2295 u64 val = its_read_baser(its, baser);
2296 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2297 u64 type = GITS_BASER_TYPE(val);
2298 u64 baser_phys, tmp;
2299 u32 alloc_pages, psz;
2304 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2305 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2306 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2307 &its->phys_base, its_base_type_string[type],
2308 alloc_pages, GITS_BASER_PAGES_MAX);
2309 alloc_pages = GITS_BASER_PAGES_MAX;
2310 order = get_order(GITS_BASER_PAGES_MAX * psz);
2313 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2317 base = (void *)page_address(page);
2318 baser_phys = virt_to_phys(base);
2320 /* Check if the physical address of the memory is above 48bits */
2321 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2323 /* 52bit PA is supported only when PageSize=64K */
2324 if (psz != SZ_64K) {
2325 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2326 free_pages((unsigned long)base, order);
2330 /* Convert 52bit PA to 48bit field */
2331 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2336 (type << GITS_BASER_TYPE_SHIFT) |
2337 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2338 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2343 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2347 val |= GITS_BASER_PAGE_SIZE_4K;
2350 val |= GITS_BASER_PAGE_SIZE_16K;
2353 val |= GITS_BASER_PAGE_SIZE_64K;
2357 its_write_baser(its, baser, val);
2360 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2362 * Shareability didn't stick. Just use
2363 * whatever the read reported, which is likely
2364 * to be the only thing this redistributor
2365 * supports. If that's zero, make it
2366 * non-cacheable as well.
2368 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2370 cache = GITS_BASER_nC;
2371 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2377 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2378 &its->phys_base, its_base_type_string[type],
2380 free_pages((unsigned long)base, order);
2384 baser->order = order;
2387 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2389 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2390 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2391 its_base_type_string[type],
2392 (unsigned long)virt_to_phys(base),
2393 indirect ? "indirect" : "flat", (int)esz,
2394 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2399 static bool its_parse_indirect_baser(struct its_node *its,
2400 struct its_baser *baser,
2401 u32 *order, u32 ids)
2403 u64 tmp = its_read_baser(its, baser);
2404 u64 type = GITS_BASER_TYPE(tmp);
2405 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2406 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2407 u32 new_order = *order;
2408 u32 psz = baser->psz;
2409 bool indirect = false;
2411 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2412 if ((esz << ids) > (psz * 2)) {
2414 * Find out whether hw supports a single or two-level table by
2415 * table by reading bit at offset '62' after writing '1' to it.
2417 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2418 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2422 * The size of the lvl2 table is equal to ITS page size
2423 * which is 'psz'. For computing lvl1 table size,
2424 * subtract ID bits that sparse lvl2 table from 'ids'
2425 * which is reported by ITS hardware times lvl1 table
2428 ids -= ilog2(psz / (int)esz);
2429 esz = GITS_LVL1_ENTRY_SIZE;
2434 * Allocate as many entries as required to fit the
2435 * range of device IDs that the ITS can grok... The ID
2436 * space being incredibly sparse, this results in a
2437 * massive waste of memory if two-level device table
2438 * feature is not supported by hardware.
2440 new_order = max_t(u32, get_order(esz << ids), new_order);
2441 if (new_order >= MAX_ORDER) {
2442 new_order = MAX_ORDER - 1;
2443 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2444 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2445 &its->phys_base, its_base_type_string[type],
2446 device_ids(its), ids);
2454 static u32 compute_common_aff(u64 val)
2458 aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2459 clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2461 return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2464 static u32 compute_its_aff(struct its_node *its)
2470 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2471 * the resulting affinity. We then use that to see if this match
2474 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2475 val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2476 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2477 return compute_common_aff(val);
2480 static struct its_node *find_sibling_its(struct its_node *cur_its)
2482 struct its_node *its;
2485 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2488 aff = compute_its_aff(cur_its);
2490 list_for_each_entry(its, &its_nodes, entry) {
2493 if (!is_v4_1(its) || its == cur_its)
2496 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2499 if (aff != compute_its_aff(its))
2502 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2503 baser = its->tables[2].val;
2504 if (!(baser & GITS_BASER_VALID))
2513 static void its_free_tables(struct its_node *its)
2517 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2518 if (its->tables[i].base) {
2519 free_pages((unsigned long)its->tables[i].base,
2520 its->tables[i].order);
2521 its->tables[i].base = NULL;
2526 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2533 val = its_read_baser(its, baser);
2534 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2538 gpsz = GITS_BASER_PAGE_SIZE_64K;
2541 gpsz = GITS_BASER_PAGE_SIZE_16K;
2545 gpsz = GITS_BASER_PAGE_SIZE_4K;
2549 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2551 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2552 its_write_baser(its, baser, val);
2554 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2574 static int its_alloc_tables(struct its_node *its)
2576 u64 shr = GITS_BASER_InnerShareable;
2577 u64 cache = GITS_BASER_RaWaWb;
2580 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2581 /* erratum 24313: ignore memory access type */
2582 cache = GITS_BASER_nCnB;
2584 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2585 struct its_baser *baser = its->tables + i;
2586 u64 val = its_read_baser(its, baser);
2587 u64 type = GITS_BASER_TYPE(val);
2588 bool indirect = false;
2591 if (type == GITS_BASER_TYPE_NONE)
2594 if (its_probe_baser_psz(its, baser)) {
2595 its_free_tables(its);
2599 order = get_order(baser->psz);
2602 case GITS_BASER_TYPE_DEVICE:
2603 indirect = its_parse_indirect_baser(its, baser, &order,
2607 case GITS_BASER_TYPE_VCPU:
2609 struct its_node *sibling;
2612 if ((sibling = find_sibling_its(its))) {
2613 *baser = sibling->tables[2];
2614 its_write_baser(its, baser, baser->val);
2619 indirect = its_parse_indirect_baser(its, baser, &order,
2620 ITS_MAX_VPEID_BITS);
2624 err = its_setup_baser(its, baser, cache, shr, order, indirect);
2626 its_free_tables(its);
2630 /* Update settings which will be used for next BASERn */
2631 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2632 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2638 static u64 inherit_vpe_l1_table_from_its(void)
2640 struct its_node *its;
2644 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2645 aff = compute_common_aff(val);
2647 list_for_each_entry(its, &its_nodes, entry) {
2653 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2656 if (aff != compute_its_aff(its))
2659 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2660 baser = its->tables[2].val;
2661 if (!(baser & GITS_BASER_VALID))
2664 /* We have a winner! */
2665 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2667 val = GICR_VPROPBASER_4_1_VALID;
2668 if (baser & GITS_BASER_INDIRECT)
2669 val |= GICR_VPROPBASER_4_1_INDIRECT;
2670 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2671 FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2672 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2673 case GIC_PAGE_SIZE_64K:
2674 addr = GITS_BASER_ADDR_48_to_52(baser);
2677 addr = baser & GENMASK_ULL(47, 12);
2680 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2681 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2682 FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2683 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2684 FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2685 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2693 static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2699 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2700 aff = compute_common_aff(val);
2702 for_each_possible_cpu(cpu) {
2703 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2705 if (!base || cpu == smp_processor_id())
2708 val = gic_read_typer(base + GICR_TYPER);
2709 if (aff != compute_common_aff(val))
2713 * At this point, we have a victim. This particular CPU
2714 * has already booted, and has an affinity that matches
2715 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2716 * Make sure we don't write the Z bit in that case.
2718 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2719 val &= ~GICR_VPROPBASER_4_1_Z;
2721 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2722 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2730 static bool allocate_vpe_l2_table(int cpu, u32 id)
2732 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2733 unsigned int psz, esz, idx, npg, gpsz;
2738 if (!gic_rdists->has_rvpeid)
2741 /* Skip non-present CPUs */
2745 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2747 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2748 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2749 npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2755 case GIC_PAGE_SIZE_4K:
2758 case GIC_PAGE_SIZE_16K:
2761 case GIC_PAGE_SIZE_64K:
2766 /* Don't allow vpe_id that exceeds single, flat table limit */
2767 if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2768 return (id < (npg * psz / (esz * SZ_8)));
2770 /* Compute 1st level table index & check if that exceeds table limit */
2771 idx = id >> ilog2(psz / (esz * SZ_8));
2772 if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2775 table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2777 /* Allocate memory for 2nd level table */
2779 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2783 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2784 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2785 gic_flush_dcache_to_poc(page_address(page), psz);
2787 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2789 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2790 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2791 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2793 /* Ensure updated table contents are visible to RD hardware */
2800 static int allocate_vpe_l1_table(void)
2802 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2803 u64 val, gpsz, npg, pa;
2804 unsigned int psz = SZ_64K;
2805 unsigned int np, epp, esz;
2808 if (!gic_rdists->has_rvpeid)
2812 * if VPENDBASER.Valid is set, disable any previously programmed
2813 * VPE by setting PendingLast while clearing Valid. This has the
2814 * effect of making sure no doorbell will be generated and we can
2815 * then safely clear VPROPBASER.Valid.
2817 if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2818 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2819 vlpi_base + GICR_VPENDBASER);
2822 * If we can inherit the configuration from another RD, let's do
2823 * so. Otherwise, we have to go through the allocation process. We
2824 * assume that all RDs have the exact same requirements, as
2825 * nothing will work otherwise.
2827 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2828 if (val & GICR_VPROPBASER_4_1_VALID)
2831 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2832 if (!gic_data_rdist()->vpe_table_mask)
2835 val = inherit_vpe_l1_table_from_its();
2836 if (val & GICR_VPROPBASER_4_1_VALID)
2839 /* First probe the page size */
2840 val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2841 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2842 val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2843 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2844 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2848 gpsz = GIC_PAGE_SIZE_4K;
2850 case GIC_PAGE_SIZE_4K:
2853 case GIC_PAGE_SIZE_16K:
2856 case GIC_PAGE_SIZE_64K:
2862 * Start populating the register from scratch, including RO fields
2863 * (which we want to print in debug cases...)
2866 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2867 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2869 /* How many entries per GIC page? */
2871 epp = psz / (esz * SZ_8);
2874 * If we need more than just a single L1 page, flag the table
2875 * as indirect and compute the number of required L1 pages.
2877 if (epp < ITS_MAX_VPEID) {
2880 val |= GICR_VPROPBASER_4_1_INDIRECT;
2882 /* Number of L2 pages required to cover the VPEID space */
2883 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2885 /* Number of L1 pages to point to the L2 pages */
2886 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2891 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2893 /* Right, that's the number of CPU pages we need for L1 */
2894 np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2896 pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2897 np, npg, psz, epp, esz);
2898 page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2902 gic_data_rdist()->vpe_l1_base = page_address(page);
2903 pa = virt_to_phys(page_address(page));
2904 WARN_ON(!IS_ALIGNED(pa, psz));
2906 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2907 val |= GICR_VPROPBASER_RaWb;
2908 val |= GICR_VPROPBASER_InnerShareable;
2909 val |= GICR_VPROPBASER_4_1_Z;
2910 val |= GICR_VPROPBASER_4_1_VALID;
2913 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2914 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2916 pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2917 smp_processor_id(), val,
2918 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2923 static int its_alloc_collections(struct its_node *its)
2927 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2929 if (!its->collections)
2932 for (i = 0; i < nr_cpu_ids; i++)
2933 its->collections[i].target_address = ~0ULL;
2938 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2940 struct page *pend_page;
2942 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2943 get_order(LPI_PENDBASE_SZ));
2947 /* Make sure the GIC will observe the zero-ed page */
2948 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2953 static void its_free_pending_table(struct page *pt)
2955 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2959 * Booting with kdump and LPIs enabled is generally fine. Any other
2960 * case is wrong in the absence of firmware/EFI support.
2962 static bool enabled_lpis_allowed(void)
2967 /* Check whether the property table is in a reserved region */
2968 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2969 addr = val & GENMASK_ULL(51, 12);
2971 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2974 static int __init allocate_lpi_tables(void)
2980 * If LPIs are enabled while we run this from the boot CPU,
2981 * flag the RD tables as pre-allocated if the stars do align.
2983 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2984 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2985 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2986 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2987 pr_info("GICv3: Using preallocated redistributor tables\n");
2990 err = its_setup_lpi_prop_table();
2995 * We allocate all the pending tables anyway, as we may have a
2996 * mix of RDs that have had LPIs enabled, and some that
2997 * don't. We'll free the unused ones as each CPU comes online.
2999 for_each_possible_cpu(cpu) {
3000 struct page *pend_page;
3002 pend_page = its_allocate_pending_table(GFP_NOWAIT);
3004 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
3008 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3014 static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3016 u32 count = 1000000; /* 1s! */
3020 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3021 val &= ~GICR_VPENDBASER_Valid;
3024 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3027 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3028 clean = !(val & GICR_VPENDBASER_Dirty);
3034 } while (!clean && count);
3036 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
3037 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3038 val |= GICR_VPENDBASER_PendingLast;
3044 static void its_cpu_init_lpis(void)
3046 void __iomem *rbase = gic_data_rdist_rd_base();
3047 struct page *pend_page;
3051 if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED)
3054 val = readl_relaxed(rbase + GICR_CTLR);
3055 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3056 (val & GICR_CTLR_ENABLE_LPIS)) {
3058 * Check that we get the same property table on all
3059 * RDs. If we don't, this is hopeless.
3061 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3062 paddr &= GENMASK_ULL(51, 12);
3063 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3064 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3066 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3067 paddr &= GENMASK_ULL(51, 16);
3069 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3070 gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED;
3075 pend_page = gic_data_rdist()->pend_page;
3076 paddr = page_to_phys(pend_page);
3079 val = (gic_rdists->prop_table_pa |
3080 GICR_PROPBASER_InnerShareable |
3081 GICR_PROPBASER_RaWaWb |
3082 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3084 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3085 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3087 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3088 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3090 * The HW reports non-shareable, we must
3091 * remove the cacheability attributes as
3094 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3095 GICR_PROPBASER_CACHEABILITY_MASK);
3096 val |= GICR_PROPBASER_nC;
3097 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3099 pr_info_once("GIC: using cache flushing for LPI property table\n");
3100 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3104 val = (page_to_phys(pend_page) |
3105 GICR_PENDBASER_InnerShareable |
3106 GICR_PENDBASER_RaWaWb);
3108 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3109 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3111 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3113 * The HW reports non-shareable, we must remove the
3114 * cacheability attributes as well.
3116 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3117 GICR_PENDBASER_CACHEABILITY_MASK);
3118 val |= GICR_PENDBASER_nC;
3119 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3123 val = readl_relaxed(rbase + GICR_CTLR);
3124 val |= GICR_CTLR_ENABLE_LPIS;
3125 writel_relaxed(val, rbase + GICR_CTLR);
3127 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3128 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3131 * It's possible for CPU to receive VLPIs before it is
3132 * scheduled as a vPE, especially for the first CPU, and the
3133 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3134 * as out of range and dropped by GIC.
3135 * So we initialize IDbits to known value to avoid VLPI drop.
3137 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3138 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3139 smp_processor_id(), val);
3140 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3143 * Also clear Valid bit of GICR_VPENDBASER, in case some
3144 * ancient programming gets left in and has possibility of
3145 * corrupting memory.
3147 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3150 if (allocate_vpe_l1_table()) {
3152 * If the allocation has failed, we're in massive trouble.
3153 * Disable direct injection, and pray that no VM was
3154 * already running...
3156 gic_rdists->has_rvpeid = false;
3157 gic_rdists->has_vlpis = false;
3160 /* Make sure the GIC has seen the above */
3163 gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED;
3164 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3166 gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ?
3167 "reserved" : "allocated",
3171 static void its_cpu_init_collection(struct its_node *its)
3173 int cpu = smp_processor_id();
3176 /* avoid cross node collections and its mapping */
3177 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3178 struct device_node *cpu_node;
3180 cpu_node = of_get_cpu_node(cpu, NULL);
3181 if (its->numa_node != NUMA_NO_NODE &&
3182 its->numa_node != of_node_to_nid(cpu_node))
3187 * We now have to bind each collection to its target
3190 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3192 * This ITS wants the physical address of the
3195 target = gic_data_rdist()->phys_base;
3197 /* This ITS wants a linear CPU number. */
3198 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3199 target = GICR_TYPER_CPU_NUMBER(target) << 16;
3202 /* Perform collection mapping */
3203 its->collections[cpu].target_address = target;
3204 its->collections[cpu].col_id = cpu;
3206 its_send_mapc(its, &its->collections[cpu], 1);
3207 its_send_invall(its, &its->collections[cpu]);
3210 static void its_cpu_init_collections(void)
3212 struct its_node *its;
3214 raw_spin_lock(&its_lock);
3216 list_for_each_entry(its, &its_nodes, entry)
3217 its_cpu_init_collection(its);
3219 raw_spin_unlock(&its_lock);
3222 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3224 struct its_device *its_dev = NULL, *tmp;
3225 unsigned long flags;
3227 raw_spin_lock_irqsave(&its->lock, flags);
3229 list_for_each_entry(tmp, &its->its_device_list, entry) {
3230 if (tmp->device_id == dev_id) {
3236 raw_spin_unlock_irqrestore(&its->lock, flags);
3241 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3245 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3246 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3247 return &its->tables[i];
3253 static bool its_alloc_table_entry(struct its_node *its,
3254 struct its_baser *baser, u32 id)
3260 /* Don't allow device id that exceeds single, flat table limit */
3261 esz = GITS_BASER_ENTRY_SIZE(baser->val);
3262 if (!(baser->val & GITS_BASER_INDIRECT))
3263 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3265 /* Compute 1st level table index & check if that exceeds table limit */
3266 idx = id >> ilog2(baser->psz / esz);
3267 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3270 table = baser->base;
3272 /* Allocate memory for 2nd level table */
3274 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3275 get_order(baser->psz));
3279 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3280 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3281 gic_flush_dcache_to_poc(page_address(page), baser->psz);
3283 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3285 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3286 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3287 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3289 /* Ensure updated table contents are visible to ITS hardware */
3296 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3298 struct its_baser *baser;
3300 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3302 /* Don't allow device id that exceeds ITS hardware limit */
3304 return (ilog2(dev_id) < device_ids(its));
3306 return its_alloc_table_entry(its, baser, dev_id);
3309 static bool its_alloc_vpe_table(u32 vpe_id)
3311 struct its_node *its;
3315 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3316 * could try and only do it on ITSs corresponding to devices
3317 * that have interrupts targeted at this VPE, but the
3318 * complexity becomes crazy (and you have tons of memory
3321 list_for_each_entry(its, &its_nodes, entry) {
3322 struct its_baser *baser;
3327 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3331 if (!its_alloc_table_entry(its, baser, vpe_id))
3335 /* Non v4.1? No need to iterate RDs and go back early. */
3336 if (!gic_rdists->has_rvpeid)
3340 * Make sure the L2 tables are allocated for all copies of
3341 * the L1 table on *all* v4.1 RDs.
3343 for_each_possible_cpu(cpu) {
3344 if (!allocate_vpe_l2_table(cpu, vpe_id))
3351 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3352 int nvecs, bool alloc_lpis)
3354 struct its_device *dev;
3355 unsigned long *lpi_map = NULL;
3356 unsigned long flags;
3357 u16 *col_map = NULL;
3364 if (!its_alloc_device_table(its, dev_id))
3367 if (WARN_ON(!is_power_of_2(nvecs)))
3368 nvecs = roundup_pow_of_two(nvecs);
3370 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3372 * Even if the device wants a single LPI, the ITT must be
3373 * sized as a power of two (and you need at least one bit...).
3375 nr_ites = max(2, nvecs);
3376 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3377 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3378 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3380 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3382 col_map = kcalloc(nr_lpis, sizeof(*col_map),
3385 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3390 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
3393 bitmap_free(lpi_map);
3398 gic_flush_dcache_to_poc(itt, sz);
3402 dev->nr_ites = nr_ites;
3403 dev->event_map.lpi_map = lpi_map;
3404 dev->event_map.col_map = col_map;
3405 dev->event_map.lpi_base = lpi_base;
3406 dev->event_map.nr_lpis = nr_lpis;
3407 raw_spin_lock_init(&dev->event_map.vlpi_lock);
3408 dev->device_id = dev_id;
3409 INIT_LIST_HEAD(&dev->entry);
3411 raw_spin_lock_irqsave(&its->lock, flags);
3412 list_add(&dev->entry, &its->its_device_list);
3413 raw_spin_unlock_irqrestore(&its->lock, flags);
3415 /* Map device to its ITT */
3416 its_send_mapd(dev, 1);
3421 static void its_free_device(struct its_device *its_dev)
3423 unsigned long flags;
3425 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3426 list_del(&its_dev->entry);
3427 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3428 kfree(its_dev->event_map.col_map);
3429 kfree(its_dev->itt);
3433 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3437 /* Find a free LPI region in lpi_map and allocate them. */
3438 idx = bitmap_find_free_region(dev->event_map.lpi_map,
3439 dev->event_map.nr_lpis,
3440 get_count_order(nvecs));
3444 *hwirq = dev->event_map.lpi_base + idx;
3449 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3450 int nvec, msi_alloc_info_t *info)
3452 struct its_node *its;
3453 struct its_device *its_dev;
3454 struct msi_domain_info *msi_info;
3459 * We ignore "dev" entirely, and rely on the dev_id that has
3460 * been passed via the scratchpad. This limits this domain's
3461 * usefulness to upper layers that definitely know that they
3462 * are built on top of the ITS.
3464 dev_id = info->scratchpad[0].ul;
3466 msi_info = msi_get_domain_info(domain);
3467 its = msi_info->data;
3469 if (!gic_rdists->has_direct_lpi &&
3471 vpe_proxy.dev->its == its &&
3472 dev_id == vpe_proxy.dev->device_id) {
3473 /* Bad luck. Get yourself a better implementation */
3474 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3479 mutex_lock(&its->dev_alloc_lock);
3480 its_dev = its_find_device(its, dev_id);
3483 * We already have seen this ID, probably through
3484 * another alias (PCI bridge of some sort). No need to
3485 * create the device.
3487 its_dev->shared = true;
3488 pr_debug("Reusing ITT for devID %x\n", dev_id);
3492 its_dev = its_create_device(its, dev_id, nvec, true);
3498 if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE)
3499 its_dev->shared = true;
3501 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3503 mutex_unlock(&its->dev_alloc_lock);
3504 info->scratchpad[0].ptr = its_dev;
3508 static struct msi_domain_ops its_msi_domain_ops = {
3509 .msi_prepare = its_msi_prepare,
3512 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3514 irq_hw_number_t hwirq)
3516 struct irq_fwspec fwspec;
3518 if (irq_domain_get_of_node(domain->parent)) {
3519 fwspec.fwnode = domain->parent->fwnode;
3520 fwspec.param_count = 3;
3521 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3522 fwspec.param[1] = hwirq;
3523 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3524 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3525 fwspec.fwnode = domain->parent->fwnode;
3526 fwspec.param_count = 2;
3527 fwspec.param[0] = hwirq;
3528 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3533 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3536 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3537 unsigned int nr_irqs, void *args)
3539 msi_alloc_info_t *info = args;
3540 struct its_device *its_dev = info->scratchpad[0].ptr;
3541 struct its_node *its = its_dev->its;
3542 struct irq_data *irqd;
3543 irq_hw_number_t hwirq;
3547 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3551 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3555 for (i = 0; i < nr_irqs; i++) {
3556 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3560 irq_domain_set_hwirq_and_chip(domain, virq + i,
3561 hwirq + i, &its_irq_chip, its_dev);
3562 irqd = irq_get_irq_data(virq + i);
3563 irqd_set_single_target(irqd);
3564 irqd_set_affinity_on_activate(irqd);
3565 pr_debug("ID:%d pID:%d vID:%d\n",
3566 (int)(hwirq + i - its_dev->event_map.lpi_base),
3567 (int)(hwirq + i), virq + i);
3573 static int its_irq_domain_activate(struct irq_domain *domain,
3574 struct irq_data *d, bool reserve)
3576 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3577 u32 event = its_get_event_id(d);
3580 cpu = its_select_cpu(d, cpu_online_mask);
3581 if (cpu < 0 || cpu >= nr_cpu_ids)
3584 its_inc_lpi_count(d, cpu);
3585 its_dev->event_map.col_map[event] = cpu;
3586 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3588 /* Map the GIC IRQ and event to the device */
3589 its_send_mapti(its_dev, d->hwirq, event);
3593 static void its_irq_domain_deactivate(struct irq_domain *domain,
3596 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3597 u32 event = its_get_event_id(d);
3599 its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3600 /* Stop the delivery of interrupts */
3601 its_send_discard(its_dev, event);
3604 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3605 unsigned int nr_irqs)
3607 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3608 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3609 struct its_node *its = its_dev->its;
3612 bitmap_release_region(its_dev->event_map.lpi_map,
3613 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3614 get_count_order(nr_irqs));
3616 for (i = 0; i < nr_irqs; i++) {
3617 struct irq_data *data = irq_domain_get_irq_data(domain,
3619 /* Nuke the entry in the domain */
3620 irq_domain_reset_irq_data(data);
3623 mutex_lock(&its->dev_alloc_lock);
3626 * If all interrupts have been freed, start mopping the
3627 * floor. This is conditioned on the device not being shared.
3629 if (!its_dev->shared &&
3630 bitmap_empty(its_dev->event_map.lpi_map,
3631 its_dev->event_map.nr_lpis)) {
3632 its_lpi_free(its_dev->event_map.lpi_map,
3633 its_dev->event_map.lpi_base,
3634 its_dev->event_map.nr_lpis);
3636 /* Unmap device/itt */
3637 its_send_mapd(its_dev, 0);
3638 its_free_device(its_dev);
3641 mutex_unlock(&its->dev_alloc_lock);
3643 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3646 static const struct irq_domain_ops its_domain_ops = {
3647 .alloc = its_irq_domain_alloc,
3648 .free = its_irq_domain_free,
3649 .activate = its_irq_domain_activate,
3650 .deactivate = its_irq_domain_deactivate,
3656 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3657 * likely), the only way to perform an invalidate is to use a fake
3658 * device to issue an INV command, implying that the LPI has first
3659 * been mapped to some event on that device. Since this is not exactly
3660 * cheap, we try to keep that mapping around as long as possible, and
3661 * only issue an UNMAP if we're short on available slots.
3663 * Broken by design(tm).
3665 * GICv4.1, on the other hand, mandates that we're able to invalidate
3666 * by writing to a MMIO register. It doesn't implement the whole of
3667 * DirectLPI, but that's good enough. And most of the time, we don't
3668 * even have to invalidate anything, as the redistributor can be told
3669 * whether to generate a doorbell or not (we thus leave it enabled,
3672 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3674 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3675 if (gic_rdists->has_rvpeid)
3678 /* Already unmapped? */
3679 if (vpe->vpe_proxy_event == -1)
3682 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3683 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3686 * We don't track empty slots at all, so let's move the
3687 * next_victim pointer if we can quickly reuse that slot
3688 * instead of nuking an existing entry. Not clear that this is
3689 * always a win though, and this might just generate a ripple
3690 * effect... Let's just hope VPEs don't migrate too often.
3692 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3693 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3695 vpe->vpe_proxy_event = -1;
3698 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3700 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3701 if (gic_rdists->has_rvpeid)
3704 if (!gic_rdists->has_direct_lpi) {
3705 unsigned long flags;
3707 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3708 its_vpe_db_proxy_unmap_locked(vpe);
3709 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3713 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3715 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3716 if (gic_rdists->has_rvpeid)
3719 /* Already mapped? */
3720 if (vpe->vpe_proxy_event != -1)
3723 /* This slot was already allocated. Kick the other VPE out. */
3724 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3725 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3727 /* Map the new VPE instead */
3728 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3729 vpe->vpe_proxy_event = vpe_proxy.next_victim;
3730 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3732 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3733 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3736 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3738 unsigned long flags;
3739 struct its_collection *target_col;
3741 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3742 if (gic_rdists->has_rvpeid)
3745 if (gic_rdists->has_direct_lpi) {
3746 void __iomem *rdbase;
3748 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3749 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3750 wait_for_syncr(rdbase);
3755 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3757 its_vpe_db_proxy_map_locked(vpe);
3759 target_col = &vpe_proxy.dev->its->collections[to];
3760 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3761 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3763 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3766 static int its_vpe_set_affinity(struct irq_data *d,
3767 const struct cpumask *mask_val,
3770 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3771 int from, cpu = cpumask_first(mask_val);
3772 unsigned long flags;
3775 * Changing affinity is mega expensive, so let's be as lazy as
3776 * we can and only do it if we really have to. Also, if mapped
3777 * into the proxy device, we need to move the doorbell
3778 * interrupt to its new location.
3780 * Another thing is that changing the affinity of a vPE affects
3781 * *other interrupts* such as all the vLPIs that are routed to
3782 * this vPE. This means that the irq_desc lock is not enough to
3783 * protect us, and that we must ensure nobody samples vpe->col_idx
3784 * during the update, hence the lock below which must also be
3785 * taken on any vLPI handling path that evaluates vpe->col_idx.
3787 from = vpe_to_cpuid_lock(vpe, &flags);
3794 * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3795 * is sharing its VPE table with the current one.
3797 if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3798 cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3801 its_send_vmovp(vpe);
3802 its_vpe_db_proxy_move(vpe, from, cpu);
3805 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3806 vpe_to_cpuid_unlock(vpe, flags);
3808 return IRQ_SET_MASK_OK_DONE;
3811 static void its_wait_vpt_parse_complete(void)
3813 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3816 if (!gic_rdists->has_vpend_valid_dirty)
3819 WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3821 !(val & GICR_VPENDBASER_Dirty),
3825 static void its_vpe_schedule(struct its_vpe *vpe)
3827 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3830 /* Schedule the VPE */
3831 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3832 GENMASK_ULL(51, 12);
3833 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3834 val |= GICR_VPROPBASER_RaWb;
3835 val |= GICR_VPROPBASER_InnerShareable;
3836 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3838 val = virt_to_phys(page_address(vpe->vpt_page)) &
3839 GENMASK_ULL(51, 16);
3840 val |= GICR_VPENDBASER_RaWaWb;
3841 val |= GICR_VPENDBASER_InnerShareable;
3843 * There is no good way of finding out if the pending table is
3844 * empty as we can race against the doorbell interrupt very
3845 * easily. So in the end, vpe->pending_last is only an
3846 * indication that the vcpu has something pending, not one
3847 * that the pending table is empty. A good implementation
3848 * would be able to read its coarse map pretty quickly anyway,
3849 * making this a tolerable issue.
3851 val |= GICR_VPENDBASER_PendingLast;
3852 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3853 val |= GICR_VPENDBASER_Valid;
3854 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3857 static void its_vpe_deschedule(struct its_vpe *vpe)
3859 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3862 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3864 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3865 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3868 static void its_vpe_invall(struct its_vpe *vpe)
3870 struct its_node *its;
3872 list_for_each_entry(its, &its_nodes, entry) {
3876 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3880 * Sending a VINVALL to a single ITS is enough, as all
3881 * we need is to reach the redistributors.
3883 its_send_vinvall(its, vpe);
3888 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3890 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3891 struct its_cmd_info *info = vcpu_info;
3893 switch (info->cmd_type) {
3895 its_vpe_schedule(vpe);
3898 case DESCHEDULE_VPE:
3899 its_vpe_deschedule(vpe);
3903 its_wait_vpt_parse_complete();
3907 its_vpe_invall(vpe);
3915 static void its_vpe_send_cmd(struct its_vpe *vpe,
3916 void (*cmd)(struct its_device *, u32))
3918 unsigned long flags;
3920 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3922 its_vpe_db_proxy_map_locked(vpe);
3923 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3925 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3928 static void its_vpe_send_inv(struct irq_data *d)
3930 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3932 if (gic_rdists->has_direct_lpi) {
3933 void __iomem *rdbase;
3935 /* Target the redistributor this VPE is currently known on */
3936 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3937 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3938 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
3939 wait_for_syncr(rdbase);
3940 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3942 its_vpe_send_cmd(vpe, its_send_inv);
3946 static void its_vpe_mask_irq(struct irq_data *d)
3949 * We need to unmask the LPI, which is described by the parent
3950 * irq_data. Instead of calling into the parent (which won't
3951 * exactly do the right thing, let's simply use the
3952 * parent_data pointer. Yes, I'm naughty.
3954 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3955 its_vpe_send_inv(d);
3958 static void its_vpe_unmask_irq(struct irq_data *d)
3960 /* Same hack as above... */
3961 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3962 its_vpe_send_inv(d);
3965 static int its_vpe_set_irqchip_state(struct irq_data *d,
3966 enum irqchip_irq_state which,
3969 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3971 if (which != IRQCHIP_STATE_PENDING)
3974 if (gic_rdists->has_direct_lpi) {
3975 void __iomem *rdbase;
3977 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3979 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3981 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3982 wait_for_syncr(rdbase);
3986 its_vpe_send_cmd(vpe, its_send_int);
3988 its_vpe_send_cmd(vpe, its_send_clear);
3994 static int its_vpe_retrigger(struct irq_data *d)
3996 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
3999 static struct irq_chip its_vpe_irq_chip = {
4000 .name = "GICv4-vpe",
4001 .irq_mask = its_vpe_mask_irq,
4002 .irq_unmask = its_vpe_unmask_irq,
4003 .irq_eoi = irq_chip_eoi_parent,
4004 .irq_set_affinity = its_vpe_set_affinity,
4005 .irq_retrigger = its_vpe_retrigger,
4006 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
4007 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
4010 static struct its_node *find_4_1_its(void)
4012 static struct its_node *its = NULL;
4015 list_for_each_entry(its, &its_nodes, entry) {
4027 static void its_vpe_4_1_send_inv(struct irq_data *d)
4029 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4030 struct its_node *its;
4033 * GICv4.1 wants doorbells to be invalidated using the
4034 * INVDB command in order to be broadcast to all RDs. Send
4035 * it to the first valid ITS, and let the HW do its magic.
4037 its = find_4_1_its();
4039 its_send_invdb(its, vpe);
4042 static void its_vpe_4_1_mask_irq(struct irq_data *d)
4044 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4045 its_vpe_4_1_send_inv(d);
4048 static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4050 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4051 its_vpe_4_1_send_inv(d);
4054 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4055 struct its_cmd_info *info)
4057 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4060 /* Schedule the VPE */
4061 val |= GICR_VPENDBASER_Valid;
4062 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4063 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4064 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4066 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4069 static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4070 struct its_cmd_info *info)
4072 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4076 unsigned long flags;
4079 * vPE is going to block: make the vPE non-resident with
4080 * PendingLast clear and DB set. The GIC guarantees that if
4081 * we read-back PendingLast clear, then a doorbell will be
4082 * delivered when an interrupt comes.
4084 * Note the locking to deal with the concurrent update of
4085 * pending_last from the doorbell interrupt handler that can
4088 raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4089 val = its_clear_vpend_valid(vlpi_base,
4090 GICR_VPENDBASER_PendingLast,
4091 GICR_VPENDBASER_4_1_DB);
4092 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4093 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4096 * We're not blocking, so just make the vPE non-resident
4097 * with PendingLast set, indicating that we'll be back.
4099 val = its_clear_vpend_valid(vlpi_base,
4101 GICR_VPENDBASER_PendingLast);
4102 vpe->pending_last = true;
4106 static void its_vpe_4_1_invall(struct its_vpe *vpe)
4108 void __iomem *rdbase;
4109 unsigned long flags;
4113 val = GICR_INVALLR_V;
4114 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4116 /* Target the redistributor this vPE is currently known on */
4117 cpu = vpe_to_cpuid_lock(vpe, &flags);
4118 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4119 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
4120 gic_write_lpir(val, rdbase + GICR_INVALLR);
4122 wait_for_syncr(rdbase);
4123 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4124 vpe_to_cpuid_unlock(vpe, flags);
4127 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4129 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4130 struct its_cmd_info *info = vcpu_info;
4132 switch (info->cmd_type) {
4134 its_vpe_4_1_schedule(vpe, info);
4137 case DESCHEDULE_VPE:
4138 its_vpe_4_1_deschedule(vpe, info);
4142 its_wait_vpt_parse_complete();
4146 its_vpe_4_1_invall(vpe);
4154 static struct irq_chip its_vpe_4_1_irq_chip = {
4155 .name = "GICv4.1-vpe",
4156 .irq_mask = its_vpe_4_1_mask_irq,
4157 .irq_unmask = its_vpe_4_1_unmask_irq,
4158 .irq_eoi = irq_chip_eoi_parent,
4159 .irq_set_affinity = its_vpe_set_affinity,
4160 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity,
4163 static void its_configure_sgi(struct irq_data *d, bool clear)
4165 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4166 struct its_cmd_desc desc;
4168 desc.its_vsgi_cmd.vpe = vpe;
4169 desc.its_vsgi_cmd.sgi = d->hwirq;
4170 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4171 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4172 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4173 desc.its_vsgi_cmd.clear = clear;
4176 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4177 * destination VPE is mapped there. Since we map them eagerly at
4178 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4180 its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4183 static void its_sgi_mask_irq(struct irq_data *d)
4185 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4187 vpe->sgi_config[d->hwirq].enabled = false;
4188 its_configure_sgi(d, false);
4191 static void its_sgi_unmask_irq(struct irq_data *d)
4193 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4195 vpe->sgi_config[d->hwirq].enabled = true;
4196 its_configure_sgi(d, false);
4199 static int its_sgi_set_affinity(struct irq_data *d,
4200 const struct cpumask *mask_val,
4204 * There is no notion of affinity for virtual SGIs, at least
4205 * not on the host (since they can only be targeting a vPE).
4206 * Tell the kernel we've done whatever it asked for.
4208 irq_data_update_effective_affinity(d, mask_val);
4209 return IRQ_SET_MASK_OK;
4212 static int its_sgi_set_irqchip_state(struct irq_data *d,
4213 enum irqchip_irq_state which,
4216 if (which != IRQCHIP_STATE_PENDING)
4220 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4221 struct its_node *its = find_4_1_its();
4224 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4225 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4226 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4228 its_configure_sgi(d, true);
4234 static int its_sgi_get_irqchip_state(struct irq_data *d,
4235 enum irqchip_irq_state which, bool *val)
4237 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4239 unsigned long flags;
4240 u32 count = 1000000; /* 1s! */
4244 if (which != IRQCHIP_STATE_PENDING)
4248 * Locking galore! We can race against two different events:
4250 * - Concurrent vPE affinity change: we must make sure it cannot
4251 * happen, or we'll talk to the wrong redistributor. This is
4252 * identical to what happens with vLPIs.
4254 * - Concurrent VSGIPENDR access: As it involves accessing two
4255 * MMIO registers, this must be made atomic one way or another.
4257 cpu = vpe_to_cpuid_lock(vpe, &flags);
4258 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4259 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4260 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4262 status = readl_relaxed(base + GICR_VSGIPENDR);
4263 if (!(status & GICR_VSGIPENDR_BUSY))
4268 pr_err_ratelimited("Unable to get SGI status\n");
4276 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4277 vpe_to_cpuid_unlock(vpe, flags);
4282 *val = !!(status & (1 << d->hwirq));
4287 static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4289 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4290 struct its_cmd_info *info = vcpu_info;
4292 switch (info->cmd_type) {
4293 case PROP_UPDATE_VSGI:
4294 vpe->sgi_config[d->hwirq].priority = info->priority;
4295 vpe->sgi_config[d->hwirq].group = info->group;
4296 its_configure_sgi(d, false);
4304 static struct irq_chip its_sgi_irq_chip = {
4305 .name = "GICv4.1-sgi",
4306 .irq_mask = its_sgi_mask_irq,
4307 .irq_unmask = its_sgi_unmask_irq,
4308 .irq_set_affinity = its_sgi_set_affinity,
4309 .irq_set_irqchip_state = its_sgi_set_irqchip_state,
4310 .irq_get_irqchip_state = its_sgi_get_irqchip_state,
4311 .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity,
4314 static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4315 unsigned int virq, unsigned int nr_irqs,
4318 struct its_vpe *vpe = args;
4321 /* Yes, we do want 16 SGIs */
4322 WARN_ON(nr_irqs != 16);
4324 for (i = 0; i < 16; i++) {
4325 vpe->sgi_config[i].priority = 0;
4326 vpe->sgi_config[i].enabled = false;
4327 vpe->sgi_config[i].group = false;
4329 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4330 &its_sgi_irq_chip, vpe);
4331 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4337 static void its_sgi_irq_domain_free(struct irq_domain *domain,
4339 unsigned int nr_irqs)
4344 static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4345 struct irq_data *d, bool reserve)
4347 /* Write out the initial SGI configuration */
4348 its_configure_sgi(d, false);
4352 static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4355 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4358 * The VSGI command is awkward:
4360 * - To change the configuration, CLEAR must be set to false,
4361 * leaving the pending bit unchanged.
4362 * - To clear the pending bit, CLEAR must be set to true, leaving
4363 * the configuration unchanged.
4365 * You just can't do both at once, hence the two commands below.
4367 vpe->sgi_config[d->hwirq].enabled = false;
4368 its_configure_sgi(d, false);
4369 its_configure_sgi(d, true);
4372 static const struct irq_domain_ops its_sgi_domain_ops = {
4373 .alloc = its_sgi_irq_domain_alloc,
4374 .free = its_sgi_irq_domain_free,
4375 .activate = its_sgi_irq_domain_activate,
4376 .deactivate = its_sgi_irq_domain_deactivate,
4379 static int its_vpe_id_alloc(void)
4381 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
4384 static void its_vpe_id_free(u16 id)
4386 ida_simple_remove(&its_vpeid_ida, id);
4389 static int its_vpe_init(struct its_vpe *vpe)
4391 struct page *vpt_page;
4394 /* Allocate vpe_id */
4395 vpe_id = its_vpe_id_alloc();
4400 vpt_page = its_allocate_pending_table(GFP_KERNEL);
4402 its_vpe_id_free(vpe_id);
4406 if (!its_alloc_vpe_table(vpe_id)) {
4407 its_vpe_id_free(vpe_id);
4408 its_free_pending_table(vpt_page);
4412 raw_spin_lock_init(&vpe->vpe_lock);
4413 vpe->vpe_id = vpe_id;
4414 vpe->vpt_page = vpt_page;
4415 if (gic_rdists->has_rvpeid)
4416 atomic_set(&vpe->vmapp_count, 0);
4418 vpe->vpe_proxy_event = -1;
4423 static void its_vpe_teardown(struct its_vpe *vpe)
4425 its_vpe_db_proxy_unmap(vpe);
4426 its_vpe_id_free(vpe->vpe_id);
4427 its_free_pending_table(vpe->vpt_page);
4430 static void its_vpe_irq_domain_free(struct irq_domain *domain,
4432 unsigned int nr_irqs)
4434 struct its_vm *vm = domain->host_data;
4437 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4439 for (i = 0; i < nr_irqs; i++) {
4440 struct irq_data *data = irq_domain_get_irq_data(domain,
4442 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4444 BUG_ON(vm != vpe->its_vm);
4446 clear_bit(data->hwirq, vm->db_bitmap);
4447 its_vpe_teardown(vpe);
4448 irq_domain_reset_irq_data(data);
4451 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4452 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4453 its_free_prop_table(vm->vprop_page);
4457 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4458 unsigned int nr_irqs, void *args)
4460 struct irq_chip *irqchip = &its_vpe_irq_chip;
4461 struct its_vm *vm = args;
4462 unsigned long *bitmap;
4463 struct page *vprop_page;
4464 int base, nr_ids, i, err = 0;
4468 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4472 if (nr_ids < nr_irqs) {
4473 its_lpi_free(bitmap, base, nr_ids);
4477 vprop_page = its_allocate_prop_table(GFP_KERNEL);
4479 its_lpi_free(bitmap, base, nr_ids);
4483 vm->db_bitmap = bitmap;
4484 vm->db_lpi_base = base;
4485 vm->nr_db_lpis = nr_ids;
4486 vm->vprop_page = vprop_page;
4488 if (gic_rdists->has_rvpeid)
4489 irqchip = &its_vpe_4_1_irq_chip;
4491 for (i = 0; i < nr_irqs; i++) {
4492 vm->vpes[i]->vpe_db_lpi = base + i;
4493 err = its_vpe_init(vm->vpes[i]);
4496 err = its_irq_gic_domain_alloc(domain, virq + i,
4497 vm->vpes[i]->vpe_db_lpi);
4500 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4501 irqchip, vm->vpes[i]);
4507 its_vpe_irq_domain_free(domain, virq, i);
4509 its_lpi_free(bitmap, base, nr_ids);
4510 its_free_prop_table(vprop_page);
4516 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4517 struct irq_data *d, bool reserve)
4519 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4520 struct its_node *its;
4523 * If we use the list map, we issue VMAPP on demand... Unless
4524 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4525 * so that VSGIs can work.
4527 if (!gic_requires_eager_mapping())
4530 /* Map the VPE to the first possible CPU */
4531 vpe->col_idx = cpumask_first(cpu_online_mask);
4533 list_for_each_entry(its, &its_nodes, entry) {
4537 its_send_vmapp(its, vpe, true);
4538 its_send_vinvall(its, vpe);
4541 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4546 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4549 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4550 struct its_node *its;
4553 * If we use the list map on GICv4.0, we unmap the VPE once no
4554 * VLPIs are associated with the VM.
4556 if (!gic_requires_eager_mapping())
4559 list_for_each_entry(its, &its_nodes, entry) {
4563 its_send_vmapp(its, vpe, false);
4567 * There may be a direct read to the VPT after unmapping the
4568 * vPE, to guarantee the validity of this, we make the VPT
4569 * memory coherent with the CPU caches here.
4571 if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))
4572 gic_flush_dcache_to_poc(page_address(vpe->vpt_page),
4576 static const struct irq_domain_ops its_vpe_domain_ops = {
4577 .alloc = its_vpe_irq_domain_alloc,
4578 .free = its_vpe_irq_domain_free,
4579 .activate = its_vpe_irq_domain_activate,
4580 .deactivate = its_vpe_irq_domain_deactivate,
4583 static int its_force_quiescent(void __iomem *base)
4585 u32 count = 1000000; /* 1s */
4588 val = readl_relaxed(base + GITS_CTLR);
4590 * GIC architecture specification requires the ITS to be both
4591 * disabled and quiescent for writes to GITS_BASER<n> or
4592 * GITS_CBASER to not have UNPREDICTABLE results.
4594 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4597 /* Disable the generation of all interrupts to this ITS */
4598 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4599 writel_relaxed(val, base + GITS_CTLR);
4601 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4603 val = readl_relaxed(base + GITS_CTLR);
4604 if (val & GITS_CTLR_QUIESCENT)
4616 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4618 struct its_node *its = data;
4620 /* erratum 22375: only alloc 8MB table size (20 bits) */
4621 its->typer &= ~GITS_TYPER_DEVBITS;
4622 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4623 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4628 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4630 struct its_node *its = data;
4632 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4637 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4639 struct its_node *its = data;
4641 /* On QDF2400, the size of the ITE is 16Bytes */
4642 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4643 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4648 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4650 struct its_node *its = its_dev->its;
4653 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4654 * which maps 32-bit writes targeted at a separate window of
4655 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4656 * with device ID taken from bits [device_id_bits + 1:2] of
4657 * the window offset.
4659 return its->pre_its_base + (its_dev->device_id << 2);
4662 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4664 struct its_node *its = data;
4665 u32 pre_its_window[2];
4668 if (!fwnode_property_read_u32_array(its->fwnode_handle,
4669 "socionext,synquacer-pre-its",
4671 ARRAY_SIZE(pre_its_window))) {
4673 its->pre_its_base = pre_its_window[0];
4674 its->get_msi_base = its_irq_get_msi_base_pre_its;
4676 ids = ilog2(pre_its_window[1]) - 2;
4677 if (device_ids(its) > ids) {
4678 its->typer &= ~GITS_TYPER_DEVBITS;
4679 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4682 /* the pre-ITS breaks isolation, so disable MSI remapping */
4683 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
4689 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4691 struct its_node *its = data;
4694 * Hip07 insists on using the wrong address for the VLPI
4695 * page. Trick it into doing the right thing...
4697 its->vlpi_redist_offset = SZ_128K;
4701 static const struct gic_quirk its_quirks[] = {
4702 #ifdef CONFIG_CAVIUM_ERRATUM_22375
4704 .desc = "ITS: Cavium errata 22375, 24313",
4705 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4707 .init = its_enable_quirk_cavium_22375,
4710 #ifdef CONFIG_CAVIUM_ERRATUM_23144
4712 .desc = "ITS: Cavium erratum 23144",
4713 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4715 .init = its_enable_quirk_cavium_23144,
4718 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4720 .desc = "ITS: QDF2400 erratum 0065",
4721 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4723 .init = its_enable_quirk_qdf2400_e0065,
4726 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4729 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4730 * implementation, but with a 'pre-ITS' added that requires
4731 * special handling in software.
4733 .desc = "ITS: Socionext Synquacer pre-ITS",
4736 .init = its_enable_quirk_socionext_synquacer,
4739 #ifdef CONFIG_HISILICON_ERRATUM_161600802
4741 .desc = "ITS: Hip07 erratum 161600802",
4744 .init = its_enable_quirk_hip07_161600802,
4751 static void its_enable_quirks(struct its_node *its)
4753 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4755 gic_enable_quirks(iidr, its_quirks, its);
4758 static int its_save_disable(void)
4760 struct its_node *its;
4763 raw_spin_lock(&its_lock);
4764 list_for_each_entry(its, &its_nodes, entry) {
4768 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4769 err = its_force_quiescent(base);
4771 pr_err("ITS@%pa: failed to quiesce: %d\n",
4772 &its->phys_base, err);
4773 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4777 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4782 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4786 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4789 raw_spin_unlock(&its_lock);
4794 static void its_restore_enable(void)
4796 struct its_node *its;
4799 raw_spin_lock(&its_lock);
4800 list_for_each_entry(its, &its_nodes, entry) {
4807 * Make sure that the ITS is disabled. If it fails to quiesce,
4808 * don't restore it since writing to CBASER or BASER<n>
4809 * registers is undefined according to the GIC v3 ITS
4812 * Firmware resuming with the ITS enabled is terminally broken.
4814 WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
4815 ret = its_force_quiescent(base);
4817 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4818 &its->phys_base, ret);
4822 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4825 * Writing CBASER resets CREADR to 0, so make CWRITER and
4826 * cmd_write line up with it.
4828 its->cmd_write = its->cmd_base;
4829 gits_write_cwriter(0, base + GITS_CWRITER);
4831 /* Restore GITS_BASER from the value cache. */
4832 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4833 struct its_baser *baser = &its->tables[i];
4835 if (!(baser->val & GITS_BASER_VALID))
4838 its_write_baser(its, baser, baser->val);
4840 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4843 * Reinit the collection if it's stored in the ITS. This is
4844 * indicated by the col_id being less than the HCC field.
4845 * CID < HCC as specified in the GIC v3 Documentation.
4847 if (its->collections[smp_processor_id()].col_id <
4848 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4849 its_cpu_init_collection(its);
4851 raw_spin_unlock(&its_lock);
4854 static struct syscore_ops its_syscore_ops = {
4855 .suspend = its_save_disable,
4856 .resume = its_restore_enable,
4859 static void __init __iomem *its_map_one(struct resource *res, int *err)
4861 void __iomem *its_base;
4864 its_base = ioremap(res->start, SZ_64K);
4866 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4871 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4872 if (val != 0x30 && val != 0x40) {
4873 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4878 *err = its_force_quiescent(its_base);
4880 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4891 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
4893 struct irq_domain *inner_domain;
4894 struct msi_domain_info *info;
4896 info = kzalloc(sizeof(*info), GFP_KERNEL);
4900 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
4901 if (!inner_domain) {
4906 inner_domain->parent = its_parent;
4907 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4908 inner_domain->flags |= its->msi_domain_flags;
4909 info->ops = &its_msi_domain_ops;
4911 inner_domain->host_data = info;
4916 static int its_init_vpe_domain(void)
4918 struct its_node *its;
4922 if (gic_rdists->has_direct_lpi) {
4923 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
4927 /* Any ITS will do, even if not v4 */
4928 its = list_first_entry(&its_nodes, struct its_node, entry);
4930 entries = roundup_pow_of_two(nr_cpu_ids);
4931 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
4933 if (!vpe_proxy.vpes)
4936 /* Use the last possible DevID */
4937 devid = GENMASK(device_ids(its) - 1, 0);
4938 vpe_proxy.dev = its_create_device(its, devid, entries, false);
4939 if (!vpe_proxy.dev) {
4940 kfree(vpe_proxy.vpes);
4941 pr_err("ITS: Can't allocate GICv4 proxy device\n");
4945 BUG_ON(entries > vpe_proxy.dev->nr_ites);
4947 raw_spin_lock_init(&vpe_proxy.lock);
4948 vpe_proxy.next_victim = 0;
4949 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
4950 devid, vpe_proxy.dev->nr_ites);
4955 static int __init its_compute_its_list_map(struct resource *res,
4956 void __iomem *its_base)
4962 * This is assumed to be done early enough that we're
4963 * guaranteed to be single-threaded, hence no
4964 * locking. Should this change, we should address
4967 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
4968 if (its_number >= GICv4_ITS_LIST_MAX) {
4969 pr_err("ITS@%pa: No ITSList entry available!\n",
4974 ctlr = readl_relaxed(its_base + GITS_CTLR);
4975 ctlr &= ~GITS_CTLR_ITS_NUMBER;
4976 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
4977 writel_relaxed(ctlr, its_base + GITS_CTLR);
4978 ctlr = readl_relaxed(its_base + GITS_CTLR);
4979 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
4980 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
4981 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
4984 if (test_and_set_bit(its_number, &its_list_map)) {
4985 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
4986 &res->start, its_number);
4993 static int __init its_probe_one(struct resource *res,
4994 struct fwnode_handle *handle, int numa_node)
4996 struct its_node *its;
4997 void __iomem *its_base;
4998 u64 baser, tmp, typer;
5003 its_base = its_map_one(res, &err);
5007 pr_info("ITS %pR\n", res);
5009 its = kzalloc(sizeof(*its), GFP_KERNEL);
5015 raw_spin_lock_init(&its->lock);
5016 mutex_init(&its->dev_alloc_lock);
5017 INIT_LIST_HEAD(&its->entry);
5018 INIT_LIST_HEAD(&its->its_device_list);
5019 typer = gic_read_typer(its_base + GITS_TYPER);
5021 its->base = its_base;
5022 its->phys_base = res->start;
5024 if (!(typer & GITS_TYPER_VMOVP)) {
5025 err = its_compute_its_list_map(res, its_base);
5031 pr_info("ITS@%pa: Using ITS number %d\n",
5034 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
5038 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer);
5040 its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K);
5041 if (!its->sgir_base) {
5046 its->mpidr = readl_relaxed(its_base + GITS_MPIDR);
5048 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5049 &res->start, its->mpidr, svpet);
5053 its->numa_node = numa_node;
5055 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5056 get_order(ITS_CMD_QUEUE_SZ));
5059 goto out_unmap_sgir;
5061 its->cmd_base = (void *)page_address(page);
5062 its->cmd_write = its->cmd_base;
5063 its->fwnode_handle = handle;
5064 its->get_msi_base = its_irq_get_msi_base;
5065 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
5067 its_enable_quirks(its);
5069 err = its_alloc_tables(its);
5073 err = its_alloc_collections(its);
5075 goto out_free_tables;
5077 baser = (virt_to_phys(its->cmd_base) |
5078 GITS_CBASER_RaWaWb |
5079 GITS_CBASER_InnerShareable |
5080 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5083 gits_write_cbaser(baser, its->base + GITS_CBASER);
5084 tmp = gits_read_cbaser(its->base + GITS_CBASER);
5086 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5087 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5089 * The HW reports non-shareable, we must
5090 * remove the cacheability attributes as
5093 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5094 GITS_CBASER_CACHEABILITY_MASK);
5095 baser |= GITS_CBASER_nC;
5096 gits_write_cbaser(baser, its->base + GITS_CBASER);
5098 pr_info("ITS: using cache flushing for cmd queue\n");
5099 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5102 gits_write_cwriter(0, its->base + GITS_CWRITER);
5103 ctlr = readl_relaxed(its->base + GITS_CTLR);
5104 ctlr |= GITS_CTLR_ENABLE;
5106 ctlr |= GITS_CTLR_ImDe;
5107 writel_relaxed(ctlr, its->base + GITS_CTLR);
5109 err = its_init_domain(handle, its);
5111 goto out_free_tables;
5113 raw_spin_lock(&its_lock);
5114 list_add(&its->entry, &its_nodes);
5115 raw_spin_unlock(&its_lock);
5120 its_free_tables(its);
5122 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5125 iounmap(its->sgir_base);
5130 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
5134 static bool gic_rdists_supports_plpis(void)
5136 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5139 static int redist_disable_lpis(void)
5141 void __iomem *rbase = gic_data_rdist_rd_base();
5142 u64 timeout = USEC_PER_SEC;
5145 if (!gic_rdists_supports_plpis()) {
5146 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5150 val = readl_relaxed(rbase + GICR_CTLR);
5151 if (!(val & GICR_CTLR_ENABLE_LPIS))
5155 * If coming via a CPU hotplug event, we don't need to disable
5156 * LPIs before trying to re-enable them. They are already
5157 * configured and all is well in the world.
5159 * If running with preallocated tables, there is nothing to do.
5161 if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) ||
5162 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5166 * From that point on, we only try to do some damage control.
5168 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5169 smp_processor_id());
5170 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5173 val &= ~GICR_CTLR_ENABLE_LPIS;
5174 writel_relaxed(val, rbase + GICR_CTLR);
5176 /* Make sure any change to GICR_CTLR is observable by the GIC */
5180 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5181 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5182 * Error out if we time out waiting for RWP to clear.
5184 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5186 pr_err("CPU%d: Timeout while disabling LPIs\n",
5187 smp_processor_id());
5195 * After it has been written to 1, it is IMPLEMENTATION
5196 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5197 * cleared to 0. Error out if clearing the bit failed.
5199 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5200 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5207 int its_cpu_init(void)
5209 if (!list_empty(&its_nodes)) {
5212 ret = redist_disable_lpis();
5216 its_cpu_init_lpis();
5217 its_cpu_init_collections();
5223 static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work)
5225 cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state);
5226 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5229 static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work,
5230 rdist_memreserve_cpuhp_cleanup_workfn);
5232 static int its_cpu_memreserve_lpi(unsigned int cpu)
5234 struct page *pend_page;
5237 /* This gets to run exactly once per CPU */
5238 if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE)
5241 pend_page = gic_data_rdist()->pend_page;
5242 if (WARN_ON(!pend_page)) {
5247 * If the pending table was pre-programmed, free the memory we
5248 * preemptively allocated. Otherwise, reserve that memory for
5251 if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) {
5252 its_free_pending_table(pend_page);
5253 gic_data_rdist()->pend_page = NULL;
5255 phys_addr_t paddr = page_to_phys(pend_page);
5256 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
5260 /* Last CPU being brought up gets to issue the cleanup */
5261 if (!IS_ENABLED(CONFIG_SMP) ||
5262 cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5263 schedule_work(&rdist_memreserve_cpuhp_cleanup_work);
5265 gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE;
5269 /* Mark all the BASER registers as invalid before they get reprogrammed */
5270 static int __init its_reset_one(struct resource *res)
5272 void __iomem *its_base;
5275 its_base = its_map_one(res, &err);
5279 for (i = 0; i < GITS_BASER_NR_REGS; i++)
5280 gits_write_baser(0, its_base + GITS_BASER + (i << 3));
5286 static const struct of_device_id its_device_id[] = {
5287 { .compatible = "arm,gic-v3-its", },
5291 static int __init its_of_probe(struct device_node *node)
5293 struct device_node *np;
5294 struct resource res;
5297 * Make sure *all* the ITS are reset before we probe any, as
5298 * they may be sharing memory. If any of the ITS fails to
5299 * reset, don't even try to go any further, as this could
5300 * result in something even worse.
5302 for (np = of_find_matching_node(node, its_device_id); np;
5303 np = of_find_matching_node(np, its_device_id)) {
5306 if (!of_device_is_available(np) ||
5307 !of_property_read_bool(np, "msi-controller") ||
5308 of_address_to_resource(np, 0, &res))
5311 err = its_reset_one(&res);
5316 for (np = of_find_matching_node(node, its_device_id); np;
5317 np = of_find_matching_node(np, its_device_id)) {
5318 if (!of_device_is_available(np))
5320 if (!of_property_read_bool(np, "msi-controller")) {
5321 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5326 if (of_address_to_resource(np, 0, &res)) {
5327 pr_warn("%pOF: no regs?\n", np);
5331 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
5338 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5340 #ifdef CONFIG_ACPI_NUMA
5341 struct its_srat_map {
5348 static struct its_srat_map *its_srat_maps __initdata;
5349 static int its_in_srat __initdata;
5351 static int __init acpi_get_its_numa_node(u32 its_id)
5355 for (i = 0; i < its_in_srat; i++) {
5356 if (its_id == its_srat_maps[i].its_id)
5357 return its_srat_maps[i].numa_node;
5359 return NUMA_NO_NODE;
5362 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5363 const unsigned long end)
5368 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5369 const unsigned long end)
5372 struct acpi_srat_gic_its_affinity *its_affinity;
5374 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5378 if (its_affinity->header.length < sizeof(*its_affinity)) {
5379 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5380 its_affinity->header.length);
5385 * Note that in theory a new proximity node could be created by this
5386 * entry as it is an SRAT resource allocation structure.
5387 * We do not currently support doing so.
5389 node = pxm_to_node(its_affinity->proximity_domain);
5391 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5392 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5396 its_srat_maps[its_in_srat].numa_node = node;
5397 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5399 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5400 its_affinity->proximity_domain, its_affinity->its_id, node);
5405 static void __init acpi_table_parse_srat_its(void)
5409 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5410 sizeof(struct acpi_table_srat),
5411 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5412 gic_acpi_match_srat_its, 0);
5416 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5421 acpi_table_parse_entries(ACPI_SIG_SRAT,
5422 sizeof(struct acpi_table_srat),
5423 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5424 gic_acpi_parse_srat_its, 0);
5427 /* free the its_srat_maps after ITS probing */
5428 static void __init acpi_its_srat_maps_free(void)
5430 kfree(its_srat_maps);
5433 static void __init acpi_table_parse_srat_its(void) { }
5434 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5435 static void __init acpi_its_srat_maps_free(void) { }
5438 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5439 const unsigned long end)
5441 struct acpi_madt_generic_translator *its_entry;
5442 struct fwnode_handle *dom_handle;
5443 struct resource res;
5446 its_entry = (struct acpi_madt_generic_translator *)header;
5447 memset(&res, 0, sizeof(res));
5448 res.start = its_entry->base_address;
5449 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5450 res.flags = IORESOURCE_MEM;
5452 dom_handle = irq_domain_alloc_fwnode(&res.start);
5454 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5459 err = iort_register_domain_token(its_entry->translation_id, res.start,
5462 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5463 &res.start, its_entry->translation_id);
5467 err = its_probe_one(&res, dom_handle,
5468 acpi_get_its_numa_node(its_entry->translation_id));
5472 iort_deregister_domain_token(its_entry->translation_id);
5474 irq_domain_free_fwnode(dom_handle);
5478 static int __init its_acpi_reset(union acpi_subtable_headers *header,
5479 const unsigned long end)
5481 struct acpi_madt_generic_translator *its_entry;
5482 struct resource res;
5484 its_entry = (struct acpi_madt_generic_translator *)header;
5485 res = (struct resource) {
5486 .start = its_entry->base_address,
5487 .end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1,
5488 .flags = IORESOURCE_MEM,
5491 return its_reset_one(&res);
5494 static void __init its_acpi_probe(void)
5496 acpi_table_parse_srat_its();
5498 * Make sure *all* the ITS are reset before we probe any, as
5499 * they may be sharing memory. If any of the ITS fails to
5500 * reset, don't even try to go any further, as this could
5501 * result in something even worse.
5503 if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5504 its_acpi_reset, 0) > 0)
5505 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5506 gic_acpi_parse_madt_its, 0);
5507 acpi_its_srat_maps_free();
5510 static void __init its_acpi_probe(void) { }
5513 int __init its_lpi_memreserve_init(void)
5517 if (!efi_enabled(EFI_CONFIG_TABLES))
5520 if (list_empty(&its_nodes))
5523 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
5524 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
5525 "irqchip/arm/gicv3/memreserve:online",
5526 its_cpu_memreserve_lpi,
5531 gic_rdists->cpuhp_memreserve_state = state;
5536 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5537 struct irq_domain *parent_domain)
5539 struct device_node *of_node;
5540 struct its_node *its;
5541 bool has_v4 = false;
5542 bool has_v4_1 = false;
5545 gic_rdists = rdists;
5547 its_parent = parent_domain;
5548 of_node = to_of_node(handle);
5550 its_of_probe(of_node);
5554 if (list_empty(&its_nodes)) {
5555 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5559 err = allocate_lpi_tables();
5563 list_for_each_entry(its, &its_nodes, entry) {
5564 has_v4 |= is_v4(its);
5565 has_v4_1 |= is_v4_1(its);
5568 /* Don't bother with inconsistent systems */
5569 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5570 rdists->has_rvpeid = false;
5572 if (has_v4 & rdists->has_vlpis) {
5573 const struct irq_domain_ops *sgi_ops;
5576 sgi_ops = &its_sgi_domain_ops;
5580 if (its_init_vpe_domain() ||
5581 its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5582 rdists->has_vlpis = false;
5583 pr_err("ITS: Disabling GICv4 support\n");
5587 register_syscore_ops(&its_syscore_ops);