2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/acpi.h>
19 #include <linux/acpi_iort.h>
20 #include <linux/bitmap.h>
21 #include <linux/cpu.h>
22 #include <linux/delay.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/log2.h>
28 #include <linux/msi.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_pci.h>
33 #include <linux/of_platform.h>
34 #include <linux/percpu.h>
35 #include <linux/slab.h>
37 #include <linux/irqchip.h>
38 #include <linux/irqchip/arm-gic-v3.h>
39 #include <linux/irqchip/arm-gic-v4.h>
41 #include <asm/cputype.h>
42 #include <asm/exception.h>
44 #include "irq-gic-common.h"
46 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
47 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
48 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
50 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
52 static u32 lpi_id_bits;
55 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
56 * deal with (one configuration byte per interrupt). PENDBASE has to
57 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
59 #define LPI_NRBITS lpi_id_bits
60 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
61 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
63 #define LPI_PROP_DEFAULT_PRIO 0xa0
66 * Collection structure - just an ID, and a redistributor address to
67 * ping. We use one per CPU as a bag of interrupts assigned to this
70 struct its_collection {
76 * The ITS_BASER structure - contains memory information, cached
77 * value of BASER register configuration and ITS page size.
87 * The ITS structure - contains most of the infrastructure, with the
88 * top-level MSI domain, the command queue, the collections, and the
89 * list of devices writing to it.
93 struct list_head entry;
95 phys_addr_t phys_base;
96 struct its_cmd_block *cmd_base;
97 struct its_cmd_block *cmd_write;
98 struct its_baser tables[GITS_BASER_NR_REGS];
99 struct its_collection *collections;
100 struct list_head its_device_list;
108 #define ITS_ITT_ALIGN SZ_256
110 /* The maximum number of VPEID bits supported by VLPI commands */
111 #define ITS_MAX_VPEID_BITS (16)
112 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
114 /* Convert page order to size in bytes */
115 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
117 struct event_lpi_map {
118 unsigned long *lpi_map;
120 irq_hw_number_t lpi_base;
122 struct mutex vlpi_lock;
124 struct its_vlpi_map *vlpi_maps;
129 * The ITS view of a device - belongs to an ITS, owns an interrupt
130 * translation table, and a list of interrupts. If it some of its
131 * LPIs are injected into a guest (GICv4), the event_map.vm field
132 * indicates which one.
135 struct list_head entry;
136 struct its_node *its;
137 struct event_lpi_map event_map;
145 struct its_device *dev;
146 struct its_vpe **vpes;
150 static LIST_HEAD(its_nodes);
151 static DEFINE_SPINLOCK(its_lock);
152 static struct rdists *gic_rdists;
153 static struct irq_domain *its_parent;
156 * We have a maximum number of 16 ITSs in the whole system if we're
157 * using the ITSList mechanism
159 #define ITS_LIST_MAX 16
161 static unsigned long its_list_map;
162 static u16 vmovp_seq_num;
163 static DEFINE_RAW_SPINLOCK(vmovp_lock);
165 static DEFINE_IDA(its_vpeid_ida);
167 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
168 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
169 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
171 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
174 struct its_node *its = its_dev->its;
176 return its->collections + its_dev->event_map.col_map[event];
180 * ITS command descriptors - parameters to be encoded in a command
183 struct its_cmd_desc {
186 struct its_device *dev;
191 struct its_device *dev;
196 struct its_device *dev;
201 struct its_device *dev;
206 struct its_collection *col;
211 struct its_device *dev;
217 struct its_device *dev;
218 struct its_collection *col;
223 struct its_device *dev;
228 struct its_collection *col;
237 struct its_collection *col;
243 struct its_device *dev;
251 struct its_device *dev;
258 struct its_collection *col;
266 * The ITS command block, which is what the ITS actually parses.
268 struct its_cmd_block {
272 #define ITS_CMD_QUEUE_SZ SZ_64K
273 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
275 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
276 struct its_cmd_desc *);
278 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_cmd_block *,
279 struct its_cmd_desc *);
281 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
283 u64 mask = GENMASK_ULL(h, l);
285 *raw_cmd |= (val << l) & mask;
288 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
290 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
293 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
295 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
298 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
300 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
303 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
305 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
308 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
310 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
313 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
315 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
318 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
320 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
323 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
325 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
328 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
330 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
333 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
335 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
338 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
340 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
343 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
345 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
348 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
350 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
353 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
355 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
358 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
360 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
363 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
365 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
368 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
370 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
373 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
375 /* Let's fixup BE commands */
376 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
377 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
378 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
379 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
382 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
383 struct its_cmd_desc *desc)
385 unsigned long itt_addr;
386 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
388 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
389 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
391 its_encode_cmd(cmd, GITS_CMD_MAPD);
392 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
393 its_encode_size(cmd, size - 1);
394 its_encode_itt(cmd, itt_addr);
395 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
402 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
403 struct its_cmd_desc *desc)
405 its_encode_cmd(cmd, GITS_CMD_MAPC);
406 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
407 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
408 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
412 return desc->its_mapc_cmd.col;
415 static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd,
416 struct its_cmd_desc *desc)
418 struct its_collection *col;
420 col = dev_event_to_col(desc->its_mapti_cmd.dev,
421 desc->its_mapti_cmd.event_id);
423 its_encode_cmd(cmd, GITS_CMD_MAPTI);
424 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
425 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
426 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
427 its_encode_collection(cmd, col->col_id);
434 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
435 struct its_cmd_desc *desc)
437 struct its_collection *col;
439 col = dev_event_to_col(desc->its_movi_cmd.dev,
440 desc->its_movi_cmd.event_id);
442 its_encode_cmd(cmd, GITS_CMD_MOVI);
443 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
444 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
445 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
452 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
453 struct its_cmd_desc *desc)
455 struct its_collection *col;
457 col = dev_event_to_col(desc->its_discard_cmd.dev,
458 desc->its_discard_cmd.event_id);
460 its_encode_cmd(cmd, GITS_CMD_DISCARD);
461 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
462 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
469 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
470 struct its_cmd_desc *desc)
472 struct its_collection *col;
474 col = dev_event_to_col(desc->its_inv_cmd.dev,
475 desc->its_inv_cmd.event_id);
477 its_encode_cmd(cmd, GITS_CMD_INV);
478 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
479 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
486 static struct its_collection *its_build_int_cmd(struct its_cmd_block *cmd,
487 struct its_cmd_desc *desc)
489 struct its_collection *col;
491 col = dev_event_to_col(desc->its_int_cmd.dev,
492 desc->its_int_cmd.event_id);
494 its_encode_cmd(cmd, GITS_CMD_INT);
495 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
496 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
503 static struct its_collection *its_build_clear_cmd(struct its_cmd_block *cmd,
504 struct its_cmd_desc *desc)
506 struct its_collection *col;
508 col = dev_event_to_col(desc->its_clear_cmd.dev,
509 desc->its_clear_cmd.event_id);
511 its_encode_cmd(cmd, GITS_CMD_CLEAR);
512 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
513 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
520 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
521 struct its_cmd_desc *desc)
523 its_encode_cmd(cmd, GITS_CMD_INVALL);
524 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
531 static struct its_vpe *its_build_vinvall_cmd(struct its_cmd_block *cmd,
532 struct its_cmd_desc *desc)
534 its_encode_cmd(cmd, GITS_CMD_VINVALL);
535 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
539 return desc->its_vinvall_cmd.vpe;
542 static struct its_vpe *its_build_vmapp_cmd(struct its_cmd_block *cmd,
543 struct its_cmd_desc *desc)
545 unsigned long vpt_addr;
547 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
549 its_encode_cmd(cmd, GITS_CMD_VMAPP);
550 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
551 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
552 its_encode_target(cmd, desc->its_vmapp_cmd.col->target_address);
553 its_encode_vpt_addr(cmd, vpt_addr);
554 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
558 return desc->its_vmapp_cmd.vpe;
561 static struct its_vpe *its_build_vmapti_cmd(struct its_cmd_block *cmd,
562 struct its_cmd_desc *desc)
566 if (desc->its_vmapti_cmd.db_enabled)
567 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
571 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
572 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
573 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
574 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
575 its_encode_db_phys_id(cmd, db);
576 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
580 return desc->its_vmapti_cmd.vpe;
583 static struct its_vpe *its_build_vmovi_cmd(struct its_cmd_block *cmd,
584 struct its_cmd_desc *desc)
588 if (desc->its_vmovi_cmd.db_enabled)
589 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
593 its_encode_cmd(cmd, GITS_CMD_VMOVI);
594 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
595 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
596 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
597 its_encode_db_phys_id(cmd, db);
598 its_encode_db_valid(cmd, true);
602 return desc->its_vmovi_cmd.vpe;
605 static struct its_vpe *its_build_vmovp_cmd(struct its_cmd_block *cmd,
606 struct its_cmd_desc *desc)
608 its_encode_cmd(cmd, GITS_CMD_VMOVP);
609 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
610 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
611 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
612 its_encode_target(cmd, desc->its_vmovp_cmd.col->target_address);
616 return desc->its_vmovp_cmd.vpe;
619 static u64 its_cmd_ptr_to_offset(struct its_node *its,
620 struct its_cmd_block *ptr)
622 return (ptr - its->cmd_base) * sizeof(*ptr);
625 static int its_queue_full(struct its_node *its)
630 widx = its->cmd_write - its->cmd_base;
631 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
633 /* This is incredibly unlikely to happen, unless the ITS locks up. */
634 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
640 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
642 struct its_cmd_block *cmd;
643 u32 count = 1000000; /* 1s! */
645 while (its_queue_full(its)) {
648 pr_err_ratelimited("ITS queue not draining\n");
655 cmd = its->cmd_write++;
657 /* Handle queue wrapping */
658 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
659 its->cmd_write = its->cmd_base;
670 static struct its_cmd_block *its_post_commands(struct its_node *its)
672 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
674 writel_relaxed(wr, its->base + GITS_CWRITER);
676 return its->cmd_write;
679 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
682 * Make sure the commands written to memory are observable by
685 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
686 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
691 static void its_wait_for_range_completion(struct its_node *its,
692 struct its_cmd_block *from,
693 struct its_cmd_block *to)
695 u64 rd_idx, from_idx, to_idx;
696 u32 count = 1000000; /* 1s! */
698 from_idx = its_cmd_ptr_to_offset(its, from);
699 to_idx = its_cmd_ptr_to_offset(its, to);
702 rd_idx = readl_relaxed(its->base + GITS_CREADR);
705 if (from_idx < to_idx && rd_idx >= to_idx)
709 if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx)
714 pr_err_ratelimited("ITS queue timeout\n");
722 /* Warning, macro hell follows */
723 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
724 void name(struct its_node *its, \
726 struct its_cmd_desc *desc) \
728 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
729 synctype *sync_obj; \
730 unsigned long flags; \
732 raw_spin_lock_irqsave(&its->lock, flags); \
734 cmd = its_allocate_entry(its); \
735 if (!cmd) { /* We're soooooo screewed... */ \
736 raw_spin_unlock_irqrestore(&its->lock, flags); \
739 sync_obj = builder(cmd, desc); \
740 its_flush_cmd(its, cmd); \
743 sync_cmd = its_allocate_entry(its); \
747 buildfn(sync_cmd, sync_obj); \
748 its_flush_cmd(its, sync_cmd); \
752 next_cmd = its_post_commands(its); \
753 raw_spin_unlock_irqrestore(&its->lock, flags); \
755 its_wait_for_range_completion(its, cmd, next_cmd); \
758 static void its_build_sync_cmd(struct its_cmd_block *sync_cmd,
759 struct its_collection *sync_col)
761 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
762 its_encode_target(sync_cmd, sync_col->target_address);
764 its_fixup_cmd(sync_cmd);
767 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
768 struct its_collection, its_build_sync_cmd)
770 static void its_build_vsync_cmd(struct its_cmd_block *sync_cmd,
771 struct its_vpe *sync_vpe)
773 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
774 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
776 its_fixup_cmd(sync_cmd);
779 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
780 struct its_vpe, its_build_vsync_cmd)
782 static void its_send_int(struct its_device *dev, u32 event_id)
784 struct its_cmd_desc desc;
786 desc.its_int_cmd.dev = dev;
787 desc.its_int_cmd.event_id = event_id;
789 its_send_single_command(dev->its, its_build_int_cmd, &desc);
792 static void its_send_clear(struct its_device *dev, u32 event_id)
794 struct its_cmd_desc desc;
796 desc.its_clear_cmd.dev = dev;
797 desc.its_clear_cmd.event_id = event_id;
799 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
802 static void its_send_inv(struct its_device *dev, u32 event_id)
804 struct its_cmd_desc desc;
806 desc.its_inv_cmd.dev = dev;
807 desc.its_inv_cmd.event_id = event_id;
809 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
812 static void its_send_mapd(struct its_device *dev, int valid)
814 struct its_cmd_desc desc;
816 desc.its_mapd_cmd.dev = dev;
817 desc.its_mapd_cmd.valid = !!valid;
819 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
822 static void its_send_mapc(struct its_node *its, struct its_collection *col,
825 struct its_cmd_desc desc;
827 desc.its_mapc_cmd.col = col;
828 desc.its_mapc_cmd.valid = !!valid;
830 its_send_single_command(its, its_build_mapc_cmd, &desc);
833 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
835 struct its_cmd_desc desc;
837 desc.its_mapti_cmd.dev = dev;
838 desc.its_mapti_cmd.phys_id = irq_id;
839 desc.its_mapti_cmd.event_id = id;
841 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
844 static void its_send_movi(struct its_device *dev,
845 struct its_collection *col, u32 id)
847 struct its_cmd_desc desc;
849 desc.its_movi_cmd.dev = dev;
850 desc.its_movi_cmd.col = col;
851 desc.its_movi_cmd.event_id = id;
853 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
856 static void its_send_discard(struct its_device *dev, u32 id)
858 struct its_cmd_desc desc;
860 desc.its_discard_cmd.dev = dev;
861 desc.its_discard_cmd.event_id = id;
863 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
866 static void its_send_invall(struct its_node *its, struct its_collection *col)
868 struct its_cmd_desc desc;
870 desc.its_invall_cmd.col = col;
872 its_send_single_command(its, its_build_invall_cmd, &desc);
875 static void its_send_vmapti(struct its_device *dev, u32 id)
877 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
878 struct its_cmd_desc desc;
880 desc.its_vmapti_cmd.vpe = map->vpe;
881 desc.its_vmapti_cmd.dev = dev;
882 desc.its_vmapti_cmd.virt_id = map->vintid;
883 desc.its_vmapti_cmd.event_id = id;
884 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
886 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
889 static void its_send_vmovi(struct its_device *dev, u32 id)
891 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
892 struct its_cmd_desc desc;
894 desc.its_vmovi_cmd.vpe = map->vpe;
895 desc.its_vmovi_cmd.dev = dev;
896 desc.its_vmovi_cmd.event_id = id;
897 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
899 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
902 static void its_send_vmapp(struct its_vpe *vpe, bool valid)
904 struct its_cmd_desc desc;
905 struct its_node *its;
907 desc.its_vmapp_cmd.vpe = vpe;
908 desc.its_vmapp_cmd.valid = valid;
910 list_for_each_entry(its, &its_nodes, entry) {
914 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
915 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
919 static void its_send_vmovp(struct its_vpe *vpe)
921 struct its_cmd_desc desc;
922 struct its_node *its;
924 int col_id = vpe->col_idx;
926 desc.its_vmovp_cmd.vpe = vpe;
927 desc.its_vmovp_cmd.its_list = (u16)its_list_map;
930 its = list_first_entry(&its_nodes, struct its_node, entry);
931 desc.its_vmovp_cmd.seq_num = 0;
932 desc.its_vmovp_cmd.col = &its->collections[col_id];
933 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
938 * Yet another marvel of the architecture. If using the
939 * its_list "feature", we need to make sure that all ITSs
940 * receive all VMOVP commands in the same order. The only way
941 * to guarantee this is to make vmovp a serialization point.
945 raw_spin_lock_irqsave(&vmovp_lock, flags);
947 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
950 list_for_each_entry(its, &its_nodes, entry) {
954 desc.its_vmovp_cmd.col = &its->collections[col_id];
955 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
958 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
961 static void its_send_vinvall(struct its_vpe *vpe)
963 struct its_cmd_desc desc;
964 struct its_node *its;
966 desc.its_vinvall_cmd.vpe = vpe;
968 list_for_each_entry(its, &its_nodes, entry) {
971 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
976 * irqchip functions - assumes MSI, mostly.
979 static inline u32 its_get_event_id(struct irq_data *d)
981 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
982 return d->hwirq - its_dev->event_map.lpi_base;
985 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
987 irq_hw_number_t hwirq;
988 struct page *prop_page;
991 if (irqd_is_forwarded_to_vcpu(d)) {
992 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
993 u32 event = its_get_event_id(d);
995 prop_page = its_dev->event_map.vm->vprop_page;
996 hwirq = its_dev->event_map.vlpi_maps[event].vintid;
998 prop_page = gic_rdists->prop_page;
1002 cfg = page_address(prop_page) + hwirq - 8192;
1004 *cfg |= set | LPI_PROP_GROUP1;
1007 * Make the above write visible to the redistributors.
1008 * And yes, we're flushing exactly: One. Single. Byte.
1011 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1012 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1017 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1019 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1021 lpi_write_config(d, clr, set);
1022 its_send_inv(its_dev, its_get_event_id(d));
1025 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1027 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1028 u32 event = its_get_event_id(d);
1030 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1033 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1036 * More fun with the architecture:
1038 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1039 * value or to 1023, depending on the enable bit. But that
1040 * would be issueing a mapping for an /existing/ DevID+EventID
1041 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1042 * to the /same/ vPE, using this opportunity to adjust the
1043 * doorbell. Mouahahahaha. We loves it, Precious.
1045 its_send_vmovi(its_dev, event);
1048 static void its_mask_irq(struct irq_data *d)
1050 if (irqd_is_forwarded_to_vcpu(d))
1051 its_vlpi_set_doorbell(d, false);
1053 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1056 static void its_unmask_irq(struct irq_data *d)
1058 if (irqd_is_forwarded_to_vcpu(d))
1059 its_vlpi_set_doorbell(d, true);
1061 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1064 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1068 const struct cpumask *cpu_mask = cpu_online_mask;
1069 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1070 struct its_collection *target_col;
1071 u32 id = its_get_event_id(d);
1073 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1074 if (irqd_is_forwarded_to_vcpu(d))
1077 /* lpi cannot be routed to a redistributor that is on a foreign node */
1078 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1079 if (its_dev->its->numa_node >= 0) {
1080 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1081 if (!cpumask_intersects(mask_val, cpu_mask))
1086 cpu = cpumask_any_and(mask_val, cpu_mask);
1088 if (cpu >= nr_cpu_ids)
1091 /* don't set the affinity when the target cpu is same as current one */
1092 if (cpu != its_dev->event_map.col_map[id]) {
1093 target_col = &its_dev->its->collections[cpu];
1094 its_send_movi(its_dev, target_col, id);
1095 its_dev->event_map.col_map[id] = cpu;
1096 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1099 return IRQ_SET_MASK_OK_DONE;
1102 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1104 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1105 struct its_node *its;
1109 addr = its->phys_base + GITS_TRANSLATER;
1111 msg->address_lo = lower_32_bits(addr);
1112 msg->address_hi = upper_32_bits(addr);
1113 msg->data = its_get_event_id(d);
1115 iommu_dma_map_msi_msg(d->irq, msg);
1118 static int its_irq_set_irqchip_state(struct irq_data *d,
1119 enum irqchip_irq_state which,
1122 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1123 u32 event = its_get_event_id(d);
1125 if (which != IRQCHIP_STATE_PENDING)
1129 its_send_int(its_dev, event);
1131 its_send_clear(its_dev, event);
1136 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1138 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1139 u32 event = its_get_event_id(d);
1145 mutex_lock(&its_dev->event_map.vlpi_lock);
1147 if (!its_dev->event_map.vm) {
1148 struct its_vlpi_map *maps;
1150 maps = kzalloc(sizeof(*maps) * its_dev->event_map.nr_lpis,
1157 its_dev->event_map.vm = info->map->vm;
1158 its_dev->event_map.vlpi_maps = maps;
1159 } else if (its_dev->event_map.vm != info->map->vm) {
1164 /* Get our private copy of the mapping information */
1165 its_dev->event_map.vlpi_maps[event] = *info->map;
1167 if (irqd_is_forwarded_to_vcpu(d)) {
1168 /* Already mapped, move it around */
1169 its_send_vmovi(its_dev, event);
1171 /* Drop the physical mapping */
1172 its_send_discard(its_dev, event);
1174 /* and install the virtual one */
1175 its_send_vmapti(its_dev, event);
1176 irqd_set_forwarded_to_vcpu(d);
1178 /* Increment the number of VLPIs */
1179 its_dev->event_map.nr_vlpis++;
1183 mutex_unlock(&its_dev->event_map.vlpi_lock);
1187 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1189 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1190 u32 event = its_get_event_id(d);
1193 mutex_lock(&its_dev->event_map.vlpi_lock);
1195 if (!its_dev->event_map.vm ||
1196 !its_dev->event_map.vlpi_maps[event].vm) {
1201 /* Copy our mapping information to the incoming request */
1202 *info->map = its_dev->event_map.vlpi_maps[event];
1205 mutex_unlock(&its_dev->event_map.vlpi_lock);
1209 static int its_vlpi_unmap(struct irq_data *d)
1211 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1212 u32 event = its_get_event_id(d);
1215 mutex_lock(&its_dev->event_map.vlpi_lock);
1217 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1222 /* Drop the virtual mapping */
1223 its_send_discard(its_dev, event);
1225 /* and restore the physical one */
1226 irqd_clr_forwarded_to_vcpu(d);
1227 its_send_mapti(its_dev, d->hwirq, event);
1228 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1233 * Drop the refcount and make the device available again if
1234 * this was the last VLPI.
1236 if (!--its_dev->event_map.nr_vlpis) {
1237 its_dev->event_map.vm = NULL;
1238 kfree(its_dev->event_map.vlpi_maps);
1242 mutex_unlock(&its_dev->event_map.vlpi_lock);
1246 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1248 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1250 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1253 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1254 lpi_update_config(d, 0xff, info->config);
1256 lpi_write_config(d, 0xff, info->config);
1257 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1262 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1264 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1265 struct its_cmd_info *info = vcpu_info;
1268 if (!its_dev->its->is_v4)
1271 /* Unmap request? */
1273 return its_vlpi_unmap(d);
1275 switch (info->cmd_type) {
1277 return its_vlpi_map(d, info);
1280 return its_vlpi_get(d, info);
1282 case PROP_UPDATE_VLPI:
1283 case PROP_UPDATE_AND_INV_VLPI:
1284 return its_vlpi_prop_update(d, info);
1291 static struct irq_chip its_irq_chip = {
1293 .irq_mask = its_mask_irq,
1294 .irq_unmask = its_unmask_irq,
1295 .irq_eoi = irq_chip_eoi_parent,
1296 .irq_set_affinity = its_set_affinity,
1297 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1298 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1299 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1303 * How we allocate LPIs:
1305 * The GIC has id_bits bits for interrupt identifiers. From there, we
1306 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
1307 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
1308 * bits to the right.
1310 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
1312 #define IRQS_PER_CHUNK_SHIFT 5
1313 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
1314 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1316 static unsigned long *lpi_bitmap;
1317 static u32 lpi_chunks;
1318 static DEFINE_SPINLOCK(lpi_lock);
1320 static int its_lpi_to_chunk(int lpi)
1322 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
1325 static int its_chunk_to_lpi(int chunk)
1327 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
1330 static int __init its_lpi_init(u32 id_bits)
1332 lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
1334 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
1341 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
1345 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
1347 unsigned long *bitmap = NULL;
1352 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
1354 spin_lock(&lpi_lock);
1357 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
1359 if (chunk_id < lpi_chunks)
1363 } while (nr_chunks > 0);
1368 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
1373 for (i = 0; i < nr_chunks; i++)
1374 set_bit(chunk_id + i, lpi_bitmap);
1376 *base = its_chunk_to_lpi(chunk_id);
1377 *nr_ids = nr_chunks * IRQS_PER_CHUNK;
1380 spin_unlock(&lpi_lock);
1383 *base = *nr_ids = 0;
1388 static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids)
1392 spin_lock(&lpi_lock);
1394 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
1395 int chunk = its_lpi_to_chunk(lpi);
1397 BUG_ON(chunk > lpi_chunks);
1398 if (test_bit(chunk, lpi_bitmap)) {
1399 clear_bit(chunk, lpi_bitmap);
1401 pr_err("Bad LPI chunk %d\n", chunk);
1405 spin_unlock(&lpi_lock);
1410 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1412 struct page *prop_page;
1414 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1418 /* Priority 0xa0, Group-1, disabled */
1419 memset(page_address(prop_page),
1420 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
1423 /* Make sure the GIC will observe the written configuration */
1424 gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ);
1429 static void its_free_prop_table(struct page *prop_page)
1431 free_pages((unsigned long)page_address(prop_page),
1432 get_order(LPI_PROPBASE_SZ));
1435 static int __init its_alloc_lpi_tables(void)
1439 lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
1440 gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT);
1441 if (!gic_rdists->prop_page) {
1442 pr_err("Failed to allocate PROPBASE\n");
1446 paddr = page_to_phys(gic_rdists->prop_page);
1447 pr_info("GIC: using LPI property table @%pa\n", &paddr);
1449 return its_lpi_init(lpi_id_bits);
1452 static const char *its_base_type_string[] = {
1453 [GITS_BASER_TYPE_DEVICE] = "Devices",
1454 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1455 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1456 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1457 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1458 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1459 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1462 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1464 u32 idx = baser - its->tables;
1466 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1469 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1472 u32 idx = baser - its->tables;
1474 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1475 baser->val = its_read_baser(its, baser);
1478 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1479 u64 cache, u64 shr, u32 psz, u32 order,
1482 u64 val = its_read_baser(its, baser);
1483 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1484 u64 type = GITS_BASER_TYPE(val);
1485 u64 baser_phys, tmp;
1490 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1491 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1492 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1493 &its->phys_base, its_base_type_string[type],
1494 alloc_pages, GITS_BASER_PAGES_MAX);
1495 alloc_pages = GITS_BASER_PAGES_MAX;
1496 order = get_order(GITS_BASER_PAGES_MAX * psz);
1499 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
1503 baser_phys = virt_to_phys(base);
1505 /* Check if the physical address of the memory is above 48bits */
1506 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1508 /* 52bit PA is supported only when PageSize=64K */
1509 if (psz != SZ_64K) {
1510 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1511 free_pages((unsigned long)base, order);
1515 /* Convert 52bit PA to 48bit field */
1516 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1521 (type << GITS_BASER_TYPE_SHIFT) |
1522 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1523 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1528 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1532 val |= GITS_BASER_PAGE_SIZE_4K;
1535 val |= GITS_BASER_PAGE_SIZE_16K;
1538 val |= GITS_BASER_PAGE_SIZE_64K;
1542 its_write_baser(its, baser, val);
1545 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1547 * Shareability didn't stick. Just use
1548 * whatever the read reported, which is likely
1549 * to be the only thing this redistributor
1550 * supports. If that's zero, make it
1551 * non-cacheable as well.
1553 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1555 cache = GITS_BASER_nC;
1556 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1561 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1563 * Page size didn't stick. Let's try a smaller
1564 * size and retry. If we reach 4K, then
1565 * something is horribly wrong...
1567 free_pages((unsigned long)base, order);
1573 goto retry_alloc_baser;
1576 goto retry_alloc_baser;
1581 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1582 &its->phys_base, its_base_type_string[type],
1584 free_pages((unsigned long)base, order);
1588 baser->order = order;
1591 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1593 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1594 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1595 its_base_type_string[type],
1596 (unsigned long)virt_to_phys(base),
1597 indirect ? "indirect" : "flat", (int)esz,
1598 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1603 static bool its_parse_indirect_baser(struct its_node *its,
1604 struct its_baser *baser,
1605 u32 psz, u32 *order, u32 ids)
1607 u64 tmp = its_read_baser(its, baser);
1608 u64 type = GITS_BASER_TYPE(tmp);
1609 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1610 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1611 u32 new_order = *order;
1612 bool indirect = false;
1614 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1615 if ((esz << ids) > (psz * 2)) {
1617 * Find out whether hw supports a single or two-level table by
1618 * table by reading bit at offset '62' after writing '1' to it.
1620 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1621 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1625 * The size of the lvl2 table is equal to ITS page size
1626 * which is 'psz'. For computing lvl1 table size,
1627 * subtract ID bits that sparse lvl2 table from 'ids'
1628 * which is reported by ITS hardware times lvl1 table
1631 ids -= ilog2(psz / (int)esz);
1632 esz = GITS_LVL1_ENTRY_SIZE;
1637 * Allocate as many entries as required to fit the
1638 * range of device IDs that the ITS can grok... The ID
1639 * space being incredibly sparse, this results in a
1640 * massive waste of memory if two-level device table
1641 * feature is not supported by hardware.
1643 new_order = max_t(u32, get_order(esz << ids), new_order);
1644 if (new_order >= MAX_ORDER) {
1645 new_order = MAX_ORDER - 1;
1646 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1647 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1648 &its->phys_base, its_base_type_string[type],
1649 its->device_ids, ids);
1657 static void its_free_tables(struct its_node *its)
1661 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1662 if (its->tables[i].base) {
1663 free_pages((unsigned long)its->tables[i].base,
1664 its->tables[i].order);
1665 its->tables[i].base = NULL;
1670 static int its_alloc_tables(struct its_node *its)
1672 u64 typer = gic_read_typer(its->base + GITS_TYPER);
1673 u32 ids = GITS_TYPER_DEVBITS(typer);
1674 u64 shr = GITS_BASER_InnerShareable;
1675 u64 cache = GITS_BASER_RaWaWb;
1679 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
1681 * erratum 22375: only alloc 8MB table size
1682 * erratum 24313: ignore memory access type
1684 cache = GITS_BASER_nCnB;
1685 ids = 0x14; /* 20 bits, 8MB */
1688 its->device_ids = ids;
1690 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1691 struct its_baser *baser = its->tables + i;
1692 u64 val = its_read_baser(its, baser);
1693 u64 type = GITS_BASER_TYPE(val);
1694 u32 order = get_order(psz);
1695 bool indirect = false;
1698 case GITS_BASER_TYPE_NONE:
1701 case GITS_BASER_TYPE_DEVICE:
1702 indirect = its_parse_indirect_baser(its, baser,
1705 case GITS_BASER_TYPE_VCPU:
1706 indirect = its_parse_indirect_baser(its, baser,
1708 ITS_MAX_VPEID_BITS);
1712 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1714 its_free_tables(its);
1718 /* Update settings which will be used for next BASERn */
1720 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1721 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1727 static int its_alloc_collections(struct its_node *its)
1729 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
1731 if (!its->collections)
1737 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
1739 struct page *pend_page;
1741 * The pending pages have to be at least 64kB aligned,
1742 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1744 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
1745 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1749 /* Make sure the GIC will observe the zero-ed page */
1750 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
1755 static void its_free_pending_table(struct page *pt)
1757 free_pages((unsigned long)page_address(pt),
1758 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1761 static void its_cpu_init_lpis(void)
1763 void __iomem *rbase = gic_data_rdist_rd_base();
1764 struct page *pend_page;
1767 /* If we didn't allocate the pending table yet, do it now */
1768 pend_page = gic_data_rdist()->pend_page;
1772 pend_page = its_allocate_pending_table(GFP_NOWAIT);
1774 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1775 smp_processor_id());
1779 paddr = page_to_phys(pend_page);
1780 pr_info("CPU%d: using LPI pending table @%pa\n",
1781 smp_processor_id(), &paddr);
1782 gic_data_rdist()->pend_page = pend_page;
1786 val = readl_relaxed(rbase + GICR_CTLR);
1787 val &= ~GICR_CTLR_ENABLE_LPIS;
1788 writel_relaxed(val, rbase + GICR_CTLR);
1791 * Make sure any change to the table is observable by the GIC.
1796 val = (page_to_phys(gic_rdists->prop_page) |
1797 GICR_PROPBASER_InnerShareable |
1798 GICR_PROPBASER_RaWaWb |
1799 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1801 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1802 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
1804 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1805 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1807 * The HW reports non-shareable, we must
1808 * remove the cacheability attributes as
1811 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1812 GICR_PROPBASER_CACHEABILITY_MASK);
1813 val |= GICR_PROPBASER_nC;
1814 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1816 pr_info_once("GIC: using cache flushing for LPI property table\n");
1817 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1821 val = (page_to_phys(pend_page) |
1822 GICR_PENDBASER_InnerShareable |
1823 GICR_PENDBASER_RaWaWb);
1825 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1826 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
1828 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1830 * The HW reports non-shareable, we must remove the
1831 * cacheability attributes as well.
1833 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1834 GICR_PENDBASER_CACHEABILITY_MASK);
1835 val |= GICR_PENDBASER_nC;
1836 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1840 val = readl_relaxed(rbase + GICR_CTLR);
1841 val |= GICR_CTLR_ENABLE_LPIS;
1842 writel_relaxed(val, rbase + GICR_CTLR);
1844 /* Make sure the GIC has seen the above */
1848 static void its_cpu_init_collection(void)
1850 struct its_node *its;
1853 spin_lock(&its_lock);
1854 cpu = smp_processor_id();
1856 list_for_each_entry(its, &its_nodes, entry) {
1859 /* avoid cross node collections and its mapping */
1860 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1861 struct device_node *cpu_node;
1863 cpu_node = of_get_cpu_node(cpu, NULL);
1864 if (its->numa_node != NUMA_NO_NODE &&
1865 its->numa_node != of_node_to_nid(cpu_node))
1870 * We now have to bind each collection to its target
1873 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1875 * This ITS wants the physical address of the
1878 target = gic_data_rdist()->phys_base;
1881 * This ITS wants a linear CPU number.
1883 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
1884 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1887 /* Perform collection mapping */
1888 its->collections[cpu].target_address = target;
1889 its->collections[cpu].col_id = cpu;
1891 its_send_mapc(its, &its->collections[cpu], 1);
1892 its_send_invall(its, &its->collections[cpu]);
1895 spin_unlock(&its_lock);
1898 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1900 struct its_device *its_dev = NULL, *tmp;
1901 unsigned long flags;
1903 raw_spin_lock_irqsave(&its->lock, flags);
1905 list_for_each_entry(tmp, &its->its_device_list, entry) {
1906 if (tmp->device_id == dev_id) {
1912 raw_spin_unlock_irqrestore(&its->lock, flags);
1917 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
1921 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1922 if (GITS_BASER_TYPE(its->tables[i].val) == type)
1923 return &its->tables[i];
1929 static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
1935 /* Don't allow device id that exceeds single, flat table limit */
1936 esz = GITS_BASER_ENTRY_SIZE(baser->val);
1937 if (!(baser->val & GITS_BASER_INDIRECT))
1938 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
1940 /* Compute 1st level table index & check if that exceeds table limit */
1941 idx = id >> ilog2(baser->psz / esz);
1942 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
1945 table = baser->base;
1947 /* Allocate memory for 2nd level table */
1949 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
1953 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
1954 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
1955 gic_flush_dcache_to_poc(page_address(page), baser->psz);
1957 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
1959 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
1960 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
1961 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
1963 /* Ensure updated table contents are visible to ITS hardware */
1970 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
1972 struct its_baser *baser;
1974 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
1976 /* Don't allow device id that exceeds ITS hardware limit */
1978 return (ilog2(dev_id) < its->device_ids);
1980 return its_alloc_table_entry(baser, dev_id);
1983 static bool its_alloc_vpe_table(u32 vpe_id)
1985 struct its_node *its;
1988 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
1989 * could try and only do it on ITSs corresponding to devices
1990 * that have interrupts targeted at this VPE, but the
1991 * complexity becomes crazy (and you have tons of memory
1994 list_for_each_entry(its, &its_nodes, entry) {
1995 struct its_baser *baser;
2000 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2004 if (!its_alloc_table_entry(baser, vpe_id))
2011 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2012 int nvecs, bool alloc_lpis)
2014 struct its_device *dev;
2015 unsigned long *lpi_map = NULL;
2016 unsigned long flags;
2017 u16 *col_map = NULL;
2024 if (!its_alloc_device_table(its, dev_id))
2027 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2029 * At least one bit of EventID is being used, hence a minimum
2030 * of two entries. No, the architecture doesn't let you
2031 * express an ITT with a single entry.
2033 nr_ites = max(2UL, roundup_pow_of_two(nvecs));
2034 sz = nr_ites * its->ite_size;
2035 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2036 itt = kzalloc(sz, GFP_KERNEL);
2038 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
2040 col_map = kzalloc(sizeof(*col_map) * nr_lpis,
2043 col_map = kzalloc(sizeof(*col_map) * nr_ites, GFP_KERNEL);
2048 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2056 gic_flush_dcache_to_poc(itt, sz);
2060 dev->nr_ites = nr_ites;
2061 dev->event_map.lpi_map = lpi_map;
2062 dev->event_map.col_map = col_map;
2063 dev->event_map.lpi_base = lpi_base;
2064 dev->event_map.nr_lpis = nr_lpis;
2065 mutex_init(&dev->event_map.vlpi_lock);
2066 dev->device_id = dev_id;
2067 INIT_LIST_HEAD(&dev->entry);
2069 raw_spin_lock_irqsave(&its->lock, flags);
2070 list_add(&dev->entry, &its->its_device_list);
2071 raw_spin_unlock_irqrestore(&its->lock, flags);
2073 /* Map device to its ITT */
2074 its_send_mapd(dev, 1);
2079 static void its_free_device(struct its_device *its_dev)
2081 unsigned long flags;
2083 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2084 list_del(&its_dev->entry);
2085 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2086 kfree(its_dev->itt);
2090 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
2094 idx = find_first_zero_bit(dev->event_map.lpi_map,
2095 dev->event_map.nr_lpis);
2096 if (idx == dev->event_map.nr_lpis)
2099 *hwirq = dev->event_map.lpi_base + idx;
2100 set_bit(idx, dev->event_map.lpi_map);
2105 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2106 int nvec, msi_alloc_info_t *info)
2108 struct its_node *its;
2109 struct its_device *its_dev;
2110 struct msi_domain_info *msi_info;
2114 * We ignore "dev" entierely, and rely on the dev_id that has
2115 * been passed via the scratchpad. This limits this domain's
2116 * usefulness to upper layers that definitely know that they
2117 * are built on top of the ITS.
2119 dev_id = info->scratchpad[0].ul;
2121 msi_info = msi_get_domain_info(domain);
2122 its = msi_info->data;
2124 if (!gic_rdists->has_direct_lpi &&
2126 vpe_proxy.dev->its == its &&
2127 dev_id == vpe_proxy.dev->device_id) {
2128 /* Bad luck. Get yourself a better implementation */
2129 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2134 its_dev = its_find_device(its, dev_id);
2137 * We already have seen this ID, probably through
2138 * another alias (PCI bridge of some sort). No need to
2139 * create the device.
2141 pr_debug("Reusing ITT for devID %x\n", dev_id);
2145 its_dev = its_create_device(its, dev_id, nvec, true);
2149 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2151 info->scratchpad[0].ptr = its_dev;
2155 static struct msi_domain_ops its_msi_domain_ops = {
2156 .msi_prepare = its_msi_prepare,
2159 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2161 irq_hw_number_t hwirq)
2163 struct irq_fwspec fwspec;
2165 if (irq_domain_get_of_node(domain->parent)) {
2166 fwspec.fwnode = domain->parent->fwnode;
2167 fwspec.param_count = 3;
2168 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2169 fwspec.param[1] = hwirq;
2170 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2171 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2172 fwspec.fwnode = domain->parent->fwnode;
2173 fwspec.param_count = 2;
2174 fwspec.param[0] = hwirq;
2175 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2180 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2183 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2184 unsigned int nr_irqs, void *args)
2186 msi_alloc_info_t *info = args;
2187 struct its_device *its_dev = info->scratchpad[0].ptr;
2188 irq_hw_number_t hwirq;
2192 for (i = 0; i < nr_irqs; i++) {
2193 err = its_alloc_device_irq(its_dev, &hwirq);
2197 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
2201 irq_domain_set_hwirq_and_chip(domain, virq + i,
2202 hwirq, &its_irq_chip, its_dev);
2203 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2204 pr_debug("ID:%d pID:%d vID:%d\n",
2205 (int)(hwirq - its_dev->event_map.lpi_base),
2206 (int) hwirq, virq + i);
2212 static void its_irq_domain_activate(struct irq_domain *domain,
2215 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2216 u32 event = its_get_event_id(d);
2217 const struct cpumask *cpu_mask = cpu_online_mask;
2220 /* get the cpu_mask of local node */
2221 if (its_dev->its->numa_node >= 0)
2222 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2224 /* Bind the LPI to the first possible CPU */
2225 cpu = cpumask_first(cpu_mask);
2226 its_dev->event_map.col_map[event] = cpu;
2227 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2229 /* Map the GIC IRQ and event to the device */
2230 its_send_mapti(its_dev, d->hwirq, event);
2233 static void its_irq_domain_deactivate(struct irq_domain *domain,
2236 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2237 u32 event = its_get_event_id(d);
2239 /* Stop the delivery of interrupts */
2240 its_send_discard(its_dev, event);
2243 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2244 unsigned int nr_irqs)
2246 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2247 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2250 for (i = 0; i < nr_irqs; i++) {
2251 struct irq_data *data = irq_domain_get_irq_data(domain,
2253 u32 event = its_get_event_id(data);
2255 /* Mark interrupt index as unused */
2256 clear_bit(event, its_dev->event_map.lpi_map);
2258 /* Nuke the entry in the domain */
2259 irq_domain_reset_irq_data(data);
2262 /* If all interrupts have been freed, start mopping the floor */
2263 if (bitmap_empty(its_dev->event_map.lpi_map,
2264 its_dev->event_map.nr_lpis)) {
2265 its_lpi_free_chunks(its_dev->event_map.lpi_map,
2266 its_dev->event_map.lpi_base,
2267 its_dev->event_map.nr_lpis);
2268 kfree(its_dev->event_map.col_map);
2270 /* Unmap device/itt */
2271 its_send_mapd(its_dev, 0);
2272 its_free_device(its_dev);
2275 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2278 static const struct irq_domain_ops its_domain_ops = {
2279 .alloc = its_irq_domain_alloc,
2280 .free = its_irq_domain_free,
2281 .activate = its_irq_domain_activate,
2282 .deactivate = its_irq_domain_deactivate,
2288 * If a GICv4 doesn't implement Direct LPIs (which is extremely
2289 * likely), the only way to perform an invalidate is to use a fake
2290 * device to issue an INV command, implying that the LPI has first
2291 * been mapped to some event on that device. Since this is not exactly
2292 * cheap, we try to keep that mapping around as long as possible, and
2293 * only issue an UNMAP if we're short on available slots.
2295 * Broken by design(tm).
2297 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2299 /* Already unmapped? */
2300 if (vpe->vpe_proxy_event == -1)
2303 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2304 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2307 * We don't track empty slots at all, so let's move the
2308 * next_victim pointer if we can quickly reuse that slot
2309 * instead of nuking an existing entry. Not clear that this is
2310 * always a win though, and this might just generate a ripple
2311 * effect... Let's just hope VPEs don't migrate too often.
2313 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2314 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2316 vpe->vpe_proxy_event = -1;
2319 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2321 if (!gic_rdists->has_direct_lpi) {
2322 unsigned long flags;
2324 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2325 its_vpe_db_proxy_unmap_locked(vpe);
2326 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2330 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2332 /* Already mapped? */
2333 if (vpe->vpe_proxy_event != -1)
2336 /* This slot was already allocated. Kick the other VPE out. */
2337 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2338 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2340 /* Map the new VPE instead */
2341 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2342 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2343 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2345 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2346 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2349 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2351 unsigned long flags;
2352 struct its_collection *target_col;
2354 if (gic_rdists->has_direct_lpi) {
2355 void __iomem *rdbase;
2357 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2358 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2359 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2365 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2367 its_vpe_db_proxy_map_locked(vpe);
2369 target_col = &vpe_proxy.dev->its->collections[to];
2370 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2371 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2373 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2376 static int its_vpe_set_affinity(struct irq_data *d,
2377 const struct cpumask *mask_val,
2380 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2381 int cpu = cpumask_first(mask_val);
2384 * Changing affinity is mega expensive, so let's be as lazy as
2385 * we can and only do it if we really have to. Also, if mapped
2386 * into the proxy device, we need to move the doorbell
2387 * interrupt to its new location.
2389 if (vpe->col_idx != cpu) {
2390 int from = vpe->col_idx;
2393 its_send_vmovp(vpe);
2394 its_vpe_db_proxy_move(vpe, from, cpu);
2397 return IRQ_SET_MASK_OK_DONE;
2400 static void its_vpe_schedule(struct its_vpe *vpe)
2402 void * __iomem vlpi_base = gic_data_rdist_vlpi_base();
2405 /* Schedule the VPE */
2406 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2407 GENMASK_ULL(51, 12);
2408 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2409 val |= GICR_VPROPBASER_RaWb;
2410 val |= GICR_VPROPBASER_InnerShareable;
2411 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2413 val = virt_to_phys(page_address(vpe->vpt_page)) &
2414 GENMASK_ULL(51, 16);
2415 val |= GICR_VPENDBASER_RaWaWb;
2416 val |= GICR_VPENDBASER_NonShareable;
2418 * There is no good way of finding out if the pending table is
2419 * empty as we can race against the doorbell interrupt very
2420 * easily. So in the end, vpe->pending_last is only an
2421 * indication that the vcpu has something pending, not one
2422 * that the pending table is empty. A good implementation
2423 * would be able to read its coarse map pretty quickly anyway,
2424 * making this a tolerable issue.
2426 val |= GICR_VPENDBASER_PendingLast;
2427 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2428 val |= GICR_VPENDBASER_Valid;
2429 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2432 static void its_vpe_deschedule(struct its_vpe *vpe)
2434 void * __iomem vlpi_base = gic_data_rdist_vlpi_base();
2435 u32 count = 1000000; /* 1s! */
2439 /* We're being scheduled out */
2440 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2441 val &= ~GICR_VPENDBASER_Valid;
2442 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2445 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2446 clean = !(val & GICR_VPENDBASER_Dirty);
2452 } while (!clean && count);
2454 if (unlikely(!clean && !count)) {
2455 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2457 vpe->pending_last = true;
2459 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2460 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2464 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2466 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2467 struct its_cmd_info *info = vcpu_info;
2469 switch (info->cmd_type) {
2471 its_vpe_schedule(vpe);
2474 case DESCHEDULE_VPE:
2475 its_vpe_deschedule(vpe);
2479 its_send_vinvall(vpe);
2487 static void its_vpe_send_cmd(struct its_vpe *vpe,
2488 void (*cmd)(struct its_device *, u32))
2490 unsigned long flags;
2492 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2494 its_vpe_db_proxy_map_locked(vpe);
2495 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2497 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2500 static void its_vpe_send_inv(struct irq_data *d)
2502 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2504 if (gic_rdists->has_direct_lpi) {
2505 void __iomem *rdbase;
2507 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2508 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2509 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2512 its_vpe_send_cmd(vpe, its_send_inv);
2516 static void its_vpe_mask_irq(struct irq_data *d)
2519 * We need to unmask the LPI, which is described by the parent
2520 * irq_data. Instead of calling into the parent (which won't
2521 * exactly do the right thing, let's simply use the
2522 * parent_data pointer. Yes, I'm naughty.
2524 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2525 its_vpe_send_inv(d);
2528 static void its_vpe_unmask_irq(struct irq_data *d)
2530 /* Same hack as above... */
2531 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2532 its_vpe_send_inv(d);
2535 static int its_vpe_set_irqchip_state(struct irq_data *d,
2536 enum irqchip_irq_state which,
2539 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2541 if (which != IRQCHIP_STATE_PENDING)
2544 if (gic_rdists->has_direct_lpi) {
2545 void __iomem *rdbase;
2547 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2549 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2551 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2552 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2557 its_vpe_send_cmd(vpe, its_send_int);
2559 its_vpe_send_cmd(vpe, its_send_clear);
2565 static struct irq_chip its_vpe_irq_chip = {
2566 .name = "GICv4-vpe",
2567 .irq_mask = its_vpe_mask_irq,
2568 .irq_unmask = its_vpe_unmask_irq,
2569 .irq_eoi = irq_chip_eoi_parent,
2570 .irq_set_affinity = its_vpe_set_affinity,
2571 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
2572 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
2575 static int its_vpe_id_alloc(void)
2577 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2580 static void its_vpe_id_free(u16 id)
2582 ida_simple_remove(&its_vpeid_ida, id);
2585 static int its_vpe_init(struct its_vpe *vpe)
2587 struct page *vpt_page;
2590 /* Allocate vpe_id */
2591 vpe_id = its_vpe_id_alloc();
2596 vpt_page = its_allocate_pending_table(GFP_KERNEL);
2598 its_vpe_id_free(vpe_id);
2602 if (!its_alloc_vpe_table(vpe_id)) {
2603 its_vpe_id_free(vpe_id);
2604 its_free_pending_table(vpe->vpt_page);
2608 vpe->vpe_id = vpe_id;
2609 vpe->vpt_page = vpt_page;
2610 vpe->vpe_proxy_event = -1;
2615 static void its_vpe_teardown(struct its_vpe *vpe)
2617 its_vpe_db_proxy_unmap(vpe);
2618 its_vpe_id_free(vpe->vpe_id);
2619 its_free_pending_table(vpe->vpt_page);
2622 static void its_vpe_irq_domain_free(struct irq_domain *domain,
2624 unsigned int nr_irqs)
2626 struct its_vm *vm = domain->host_data;
2629 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2631 for (i = 0; i < nr_irqs; i++) {
2632 struct irq_data *data = irq_domain_get_irq_data(domain,
2634 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
2636 BUG_ON(vm != vpe->its_vm);
2638 clear_bit(data->hwirq, vm->db_bitmap);
2639 its_vpe_teardown(vpe);
2640 irq_domain_reset_irq_data(data);
2643 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
2644 its_lpi_free_chunks(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
2645 its_free_prop_table(vm->vprop_page);
2649 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2650 unsigned int nr_irqs, void *args)
2652 struct its_vm *vm = args;
2653 unsigned long *bitmap;
2654 struct page *vprop_page;
2655 int base, nr_ids, i, err = 0;
2659 bitmap = its_lpi_alloc_chunks(nr_irqs, &base, &nr_ids);
2663 if (nr_ids < nr_irqs) {
2664 its_lpi_free_chunks(bitmap, base, nr_ids);
2668 vprop_page = its_allocate_prop_table(GFP_KERNEL);
2670 its_lpi_free_chunks(bitmap, base, nr_ids);
2674 vm->db_bitmap = bitmap;
2675 vm->db_lpi_base = base;
2676 vm->nr_db_lpis = nr_ids;
2677 vm->vprop_page = vprop_page;
2679 for (i = 0; i < nr_irqs; i++) {
2680 vm->vpes[i]->vpe_db_lpi = base + i;
2681 err = its_vpe_init(vm->vpes[i]);
2684 err = its_irq_gic_domain_alloc(domain, virq + i,
2685 vm->vpes[i]->vpe_db_lpi);
2688 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
2689 &its_vpe_irq_chip, vm->vpes[i]);
2695 its_vpe_irq_domain_free(domain, virq, i - 1);
2697 its_lpi_free_chunks(bitmap, base, nr_ids);
2698 its_free_prop_table(vprop_page);
2704 static void its_vpe_irq_domain_activate(struct irq_domain *domain,
2707 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2709 /* Map the VPE to the first possible CPU */
2710 vpe->col_idx = cpumask_first(cpu_online_mask);
2711 its_send_vmapp(vpe, true);
2712 its_send_vinvall(vpe);
2715 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
2718 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2720 its_send_vmapp(vpe, false);
2723 static const struct irq_domain_ops its_vpe_domain_ops = {
2724 .alloc = its_vpe_irq_domain_alloc,
2725 .free = its_vpe_irq_domain_free,
2726 .activate = its_vpe_irq_domain_activate,
2727 .deactivate = its_vpe_irq_domain_deactivate,
2730 static int its_force_quiescent(void __iomem *base)
2732 u32 count = 1000000; /* 1s */
2735 val = readl_relaxed(base + GITS_CTLR);
2737 * GIC architecture specification requires the ITS to be both
2738 * disabled and quiescent for writes to GITS_BASER<n> or
2739 * GITS_CBASER to not have UNPREDICTABLE results.
2741 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
2744 /* Disable the generation of all interrupts to this ITS */
2745 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
2746 writel_relaxed(val, base + GITS_CTLR);
2748 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
2750 val = readl_relaxed(base + GITS_CTLR);
2751 if (val & GITS_CTLR_QUIESCENT)
2763 static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
2765 struct its_node *its = data;
2767 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
2770 static void __maybe_unused its_enable_quirk_cavium_23144(void *data)
2772 struct its_node *its = data;
2774 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
2777 static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
2779 struct its_node *its = data;
2781 /* On QDF2400, the size of the ITE is 16Bytes */
2785 static const struct gic_quirk its_quirks[] = {
2786 #ifdef CONFIG_CAVIUM_ERRATUM_22375
2788 .desc = "ITS: Cavium errata 22375, 24313",
2789 .iidr = 0xa100034c, /* ThunderX pass 1.x */
2791 .init = its_enable_quirk_cavium_22375,
2794 #ifdef CONFIG_CAVIUM_ERRATUM_23144
2796 .desc = "ITS: Cavium erratum 23144",
2797 .iidr = 0xa100034c, /* ThunderX pass 1.x */
2799 .init = its_enable_quirk_cavium_23144,
2802 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
2804 .desc = "ITS: QDF2400 erratum 0065",
2805 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
2807 .init = its_enable_quirk_qdf2400_e0065,
2814 static void its_enable_quirks(struct its_node *its)
2816 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
2818 gic_enable_quirks(iidr, its_quirks, its);
2821 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
2823 struct irq_domain *inner_domain;
2824 struct msi_domain_info *info;
2826 info = kzalloc(sizeof(*info), GFP_KERNEL);
2830 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
2831 if (!inner_domain) {
2836 inner_domain->parent = its_parent;
2837 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
2838 inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP;
2839 info->ops = &its_msi_domain_ops;
2841 inner_domain->host_data = info;
2846 static int its_init_vpe_domain(void)
2848 struct its_node *its;
2852 if (gic_rdists->has_direct_lpi) {
2853 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
2857 /* Any ITS will do, even if not v4 */
2858 its = list_first_entry(&its_nodes, struct its_node, entry);
2860 entries = roundup_pow_of_two(nr_cpu_ids);
2861 vpe_proxy.vpes = kzalloc(sizeof(*vpe_proxy.vpes) * entries,
2863 if (!vpe_proxy.vpes) {
2864 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
2868 /* Use the last possible DevID */
2869 devid = GENMASK(its->device_ids - 1, 0);
2870 vpe_proxy.dev = its_create_device(its, devid, entries, false);
2871 if (!vpe_proxy.dev) {
2872 kfree(vpe_proxy.vpes);
2873 pr_err("ITS: Can't allocate GICv4 proxy device\n");
2877 BUG_ON(entries > vpe_proxy.dev->nr_ites);
2879 raw_spin_lock_init(&vpe_proxy.lock);
2880 vpe_proxy.next_victim = 0;
2881 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
2882 devid, vpe_proxy.dev->nr_ites);
2887 static int __init its_compute_its_list_map(struct resource *res,
2888 void __iomem *its_base)
2894 * This is assumed to be done early enough that we're
2895 * guaranteed to be single-threaded, hence no
2896 * locking. Should this change, we should address
2899 its_number = find_first_zero_bit(&its_list_map, ITS_LIST_MAX);
2900 if (its_number >= ITS_LIST_MAX) {
2901 pr_err("ITS@%pa: No ITSList entry available!\n",
2906 ctlr = readl_relaxed(its_base + GITS_CTLR);
2907 ctlr &= ~GITS_CTLR_ITS_NUMBER;
2908 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
2909 writel_relaxed(ctlr, its_base + GITS_CTLR);
2910 ctlr = readl_relaxed(its_base + GITS_CTLR);
2911 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
2912 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
2913 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
2916 if (test_and_set_bit(its_number, &its_list_map)) {
2917 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
2918 &res->start, its_number);
2925 static int __init its_probe_one(struct resource *res,
2926 struct fwnode_handle *handle, int numa_node)
2928 struct its_node *its;
2929 void __iomem *its_base;
2931 u64 baser, tmp, typer;
2934 its_base = ioremap(res->start, resource_size(res));
2936 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
2940 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
2941 if (val != 0x30 && val != 0x40) {
2942 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
2947 err = its_force_quiescent(its_base);
2949 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
2953 pr_info("ITS %pR\n", res);
2955 its = kzalloc(sizeof(*its), GFP_KERNEL);
2961 raw_spin_lock_init(&its->lock);
2962 INIT_LIST_HEAD(&its->entry);
2963 INIT_LIST_HEAD(&its->its_device_list);
2964 typer = gic_read_typer(its_base + GITS_TYPER);
2965 its->base = its_base;
2966 its->phys_base = res->start;
2967 its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
2968 its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
2970 if (!(typer & GITS_TYPER_VMOVP)) {
2971 err = its_compute_its_list_map(res, its_base);
2975 pr_info("ITS@%pa: Using ITS number %d\n",
2978 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
2982 its->numa_node = numa_node;
2984 its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2985 get_order(ITS_CMD_QUEUE_SZ));
2986 if (!its->cmd_base) {
2990 its->cmd_write = its->cmd_base;
2992 its_enable_quirks(its);
2994 err = its_alloc_tables(its);
2998 err = its_alloc_collections(its);
3000 goto out_free_tables;
3002 baser = (virt_to_phys(its->cmd_base) |
3003 GITS_CBASER_RaWaWb |
3004 GITS_CBASER_InnerShareable |
3005 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3008 gits_write_cbaser(baser, its->base + GITS_CBASER);
3009 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3011 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3012 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3014 * The HW reports non-shareable, we must
3015 * remove the cacheability attributes as
3018 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3019 GITS_CBASER_CACHEABILITY_MASK);
3020 baser |= GITS_CBASER_nC;
3021 gits_write_cbaser(baser, its->base + GITS_CBASER);
3023 pr_info("ITS: using cache flushing for cmd queue\n");
3024 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3027 gits_write_cwriter(0, its->base + GITS_CWRITER);
3028 ctlr = readl_relaxed(its->base + GITS_CTLR);
3029 ctlr |= GITS_CTLR_ENABLE;
3031 ctlr |= GITS_CTLR_ImDe;
3032 writel_relaxed(ctlr, its->base + GITS_CTLR);
3034 err = its_init_domain(handle, its);
3036 goto out_free_tables;
3038 spin_lock(&its_lock);
3039 list_add(&its->entry, &its_nodes);
3040 spin_unlock(&its_lock);
3045 its_free_tables(its);
3047 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3052 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3056 static bool gic_rdists_supports_plpis(void)
3058 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3061 int its_cpu_init(void)
3063 if (!list_empty(&its_nodes)) {
3064 if (!gic_rdists_supports_plpis()) {
3065 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3068 its_cpu_init_lpis();
3069 its_cpu_init_collection();
3075 static const struct of_device_id its_device_id[] = {
3076 { .compatible = "arm,gic-v3-its", },
3080 static int __init its_of_probe(struct device_node *node)
3082 struct device_node *np;
3083 struct resource res;
3085 for (np = of_find_matching_node(node, its_device_id); np;
3086 np = of_find_matching_node(np, its_device_id)) {
3087 if (!of_property_read_bool(np, "msi-controller")) {
3088 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3093 if (of_address_to_resource(np, 0, &res)) {
3094 pr_warn("%pOF: no regs?\n", np);
3098 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3105 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3107 #ifdef CONFIG_ACPI_NUMA
3108 struct its_srat_map {
3115 static struct its_srat_map *its_srat_maps __initdata;
3116 static int its_in_srat __initdata;
3118 static int __init acpi_get_its_numa_node(u32 its_id)
3122 for (i = 0; i < its_in_srat; i++) {
3123 if (its_id == its_srat_maps[i].its_id)
3124 return its_srat_maps[i].numa_node;
3126 return NUMA_NO_NODE;
3129 static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header,
3130 const unsigned long end)
3135 static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header,
3136 const unsigned long end)
3139 struct acpi_srat_gic_its_affinity *its_affinity;
3141 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3145 if (its_affinity->header.length < sizeof(*its_affinity)) {
3146 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3147 its_affinity->header.length);
3151 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3153 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3154 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3158 its_srat_maps[its_in_srat].numa_node = node;
3159 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3161 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3162 its_affinity->proximity_domain, its_affinity->its_id, node);
3167 static void __init acpi_table_parse_srat_its(void)
3171 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3172 sizeof(struct acpi_table_srat),
3173 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3174 gic_acpi_match_srat_its, 0);
3178 its_srat_maps = kmalloc(count * sizeof(struct its_srat_map),
3180 if (!its_srat_maps) {
3181 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3185 acpi_table_parse_entries(ACPI_SIG_SRAT,
3186 sizeof(struct acpi_table_srat),
3187 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3188 gic_acpi_parse_srat_its, 0);
3191 /* free the its_srat_maps after ITS probing */
3192 static void __init acpi_its_srat_maps_free(void)
3194 kfree(its_srat_maps);
3197 static void __init acpi_table_parse_srat_its(void) { }
3198 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3199 static void __init acpi_its_srat_maps_free(void) { }
3202 static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
3203 const unsigned long end)
3205 struct acpi_madt_generic_translator *its_entry;
3206 struct fwnode_handle *dom_handle;
3207 struct resource res;
3210 its_entry = (struct acpi_madt_generic_translator *)header;
3211 memset(&res, 0, sizeof(res));
3212 res.start = its_entry->base_address;
3213 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3214 res.flags = IORESOURCE_MEM;
3216 dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
3218 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3223 err = iort_register_domain_token(its_entry->translation_id, dom_handle);
3225 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3226 &res.start, its_entry->translation_id);
3230 err = its_probe_one(&res, dom_handle,
3231 acpi_get_its_numa_node(its_entry->translation_id));
3235 iort_deregister_domain_token(its_entry->translation_id);
3237 irq_domain_free_fwnode(dom_handle);
3241 static void __init its_acpi_probe(void)
3243 acpi_table_parse_srat_its();
3244 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3245 gic_acpi_parse_madt_its, 0);
3246 acpi_its_srat_maps_free();
3249 static void __init its_acpi_probe(void) { }
3252 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3253 struct irq_domain *parent_domain)
3255 struct device_node *of_node;
3256 struct its_node *its;
3257 bool has_v4 = false;
3260 its_parent = parent_domain;
3261 of_node = to_of_node(handle);
3263 its_of_probe(of_node);
3267 if (list_empty(&its_nodes)) {
3268 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3272 gic_rdists = rdists;
3273 err = its_alloc_lpi_tables();
3277 list_for_each_entry(its, &its_nodes, entry)
3278 has_v4 |= its->is_v4;
3280 if (has_v4 & rdists->has_vlpis) {
3281 if (its_init_vpe_domain() ||
3282 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3283 rdists->has_vlpis = false;
3284 pr_err("ITS: Disabling GICv4 support\n");