1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitfield.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/dma-iommu.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/irqdomain.h>
19 #include <linux/list.h>
20 #include <linux/log2.h>
21 #include <linux/memblock.h>
23 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/percpu.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
40 #include "irq-gic-common.h"
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
45 #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
47 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
48 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
50 static u32 lpi_id_bits;
53 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
54 * deal with (one configuration byte per interrupt). PENDBASE has to
55 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
57 #define LPI_NRBITS lpi_id_bits
58 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
59 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
61 #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
64 * Collection structure - just an ID, and a redistributor address to
65 * ping. We use one per CPU as a bag of interrupts assigned to this
68 struct its_collection {
74 * The ITS_BASER structure - contains memory information, cached
75 * value of BASER register configuration and ITS page size.
87 * The ITS structure - contains most of the infrastructure, with the
88 * top-level MSI domain, the command queue, the collections, and the
89 * list of devices writing to it.
91 * dev_alloc_lock has to be taken for device allocations, while the
92 * spinlock must be taken to parse data structures such as the device
97 struct mutex dev_alloc_lock;
98 struct list_head entry;
100 void __iomem *sgir_base;
101 phys_addr_t phys_base;
102 struct its_cmd_block *cmd_base;
103 struct its_cmd_block *cmd_write;
104 struct its_baser tables[GITS_BASER_NR_REGS];
105 struct its_collection *collections;
106 struct fwnode_handle *fwnode_handle;
107 u64 (*get_msi_base)(struct its_device *its_dev);
112 struct list_head its_device_list;
114 unsigned long list_nr;
116 unsigned int msi_domain_flags;
117 u32 pre_its_base; /* for Socionext Synquacer */
118 int vlpi_redist_offset;
121 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
122 #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
123 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
125 #define ITS_ITT_ALIGN SZ_256
127 /* The maximum number of VPEID bits supported by VLPI commands */
128 #define ITS_MAX_VPEID_BITS \
131 if (gic_rdists->has_rvpeid && \
132 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
133 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
138 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
140 /* Convert page order to size in bytes */
141 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
143 struct event_lpi_map {
144 unsigned long *lpi_map;
146 irq_hw_number_t lpi_base;
148 raw_spinlock_t vlpi_lock;
150 struct its_vlpi_map *vlpi_maps;
155 * The ITS view of a device - belongs to an ITS, owns an interrupt
156 * translation table, and a list of interrupts. If it some of its
157 * LPIs are injected into a guest (GICv4), the event_map.vm field
158 * indicates which one.
161 struct list_head entry;
162 struct its_node *its;
163 struct event_lpi_map event_map;
172 struct its_device *dev;
173 struct its_vpe **vpes;
177 struct cpu_lpi_count {
182 static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
184 static LIST_HEAD(its_nodes);
185 static DEFINE_RAW_SPINLOCK(its_lock);
186 static struct rdists *gic_rdists;
187 static struct irq_domain *its_parent;
189 static unsigned long its_list_map;
190 static u16 vmovp_seq_num;
191 static DEFINE_RAW_SPINLOCK(vmovp_lock);
193 static DEFINE_IDA(its_vpeid_ida);
195 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
196 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
197 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
198 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
201 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
202 * always have vSGIs mapped.
204 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
206 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
209 static u16 get_its_list(struct its_vm *vm)
211 struct its_node *its;
212 unsigned long its_list = 0;
214 list_for_each_entry(its, &its_nodes, entry) {
218 if (require_its_list_vmovp(vm, its))
219 __set_bit(its->list_nr, &its_list);
222 return (u16)its_list;
225 static inline u32 its_get_event_id(struct irq_data *d)
227 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
228 return d->hwirq - its_dev->event_map.lpi_base;
231 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
234 struct its_node *its = its_dev->its;
236 return its->collections + its_dev->event_map.col_map[event];
239 static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
242 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
245 return &its_dev->event_map.vlpi_maps[event];
248 static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
250 if (irqd_is_forwarded_to_vcpu(d)) {
251 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
252 u32 event = its_get_event_id(d);
254 return dev_event_to_vlpi_map(its_dev, event);
260 static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
262 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
266 static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
268 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
271 static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
273 struct its_vlpi_map *map = get_vlpi_map(d);
277 cpu = vpe_to_cpuid_lock(map->vpe, flags);
279 /* Physical LPIs are already locked via the irq_desc lock */
280 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
281 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
282 /* Keep GCC quiet... */
289 static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
291 struct its_vlpi_map *map = get_vlpi_map(d);
294 vpe_to_cpuid_unlock(map->vpe, flags);
297 static struct its_collection *valid_col(struct its_collection *col)
299 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
305 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
307 if (valid_col(its->collections + vpe->col_idx))
314 * ITS command descriptors - parameters to be encoded in a command
317 struct its_cmd_desc {
320 struct its_device *dev;
325 struct its_device *dev;
330 struct its_device *dev;
335 struct its_device *dev;
340 struct its_collection *col;
345 struct its_device *dev;
351 struct its_device *dev;
352 struct its_collection *col;
357 struct its_device *dev;
362 struct its_collection *col;
371 struct its_collection *col;
377 struct its_device *dev;
385 struct its_device *dev;
392 struct its_collection *col;
413 * The ITS command block, which is what the ITS actually parses.
415 struct its_cmd_block {
418 __le64 raw_cmd_le[4];
422 #define ITS_CMD_QUEUE_SZ SZ_64K
423 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
425 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
426 struct its_cmd_block *,
427 struct its_cmd_desc *);
429 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
430 struct its_cmd_block *,
431 struct its_cmd_desc *);
433 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
435 u64 mask = GENMASK_ULL(h, l);
437 *raw_cmd |= (val << l) & mask;
440 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
442 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
445 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
447 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
450 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
452 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
455 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
457 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
460 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
462 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
465 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
467 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
470 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
472 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
475 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
477 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
480 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
482 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
485 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
487 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
490 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
492 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
495 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
497 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
500 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
502 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
505 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
507 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
510 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
512 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
515 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
517 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
520 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
522 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
525 static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
527 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
530 static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
532 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
535 static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
537 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
540 static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
543 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
546 static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
549 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
552 static void its_encode_db(struct its_cmd_block *cmd, bool db)
554 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
557 static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
559 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
562 static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
564 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
567 static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
569 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
572 static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
574 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
577 static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
579 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
582 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
584 /* Let's fixup BE commands */
585 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
586 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
587 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
588 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
591 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
592 struct its_cmd_block *cmd,
593 struct its_cmd_desc *desc)
595 unsigned long itt_addr;
596 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
598 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
599 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
601 its_encode_cmd(cmd, GITS_CMD_MAPD);
602 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
603 its_encode_size(cmd, size - 1);
604 its_encode_itt(cmd, itt_addr);
605 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
612 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
613 struct its_cmd_block *cmd,
614 struct its_cmd_desc *desc)
616 its_encode_cmd(cmd, GITS_CMD_MAPC);
617 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
618 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
619 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
623 return desc->its_mapc_cmd.col;
626 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
627 struct its_cmd_block *cmd,
628 struct its_cmd_desc *desc)
630 struct its_collection *col;
632 col = dev_event_to_col(desc->its_mapti_cmd.dev,
633 desc->its_mapti_cmd.event_id);
635 its_encode_cmd(cmd, GITS_CMD_MAPTI);
636 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
637 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
638 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
639 its_encode_collection(cmd, col->col_id);
643 return valid_col(col);
646 static struct its_collection *its_build_movi_cmd(struct its_node *its,
647 struct its_cmd_block *cmd,
648 struct its_cmd_desc *desc)
650 struct its_collection *col;
652 col = dev_event_to_col(desc->its_movi_cmd.dev,
653 desc->its_movi_cmd.event_id);
655 its_encode_cmd(cmd, GITS_CMD_MOVI);
656 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
657 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
658 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
662 return valid_col(col);
665 static struct its_collection *its_build_discard_cmd(struct its_node *its,
666 struct its_cmd_block *cmd,
667 struct its_cmd_desc *desc)
669 struct its_collection *col;
671 col = dev_event_to_col(desc->its_discard_cmd.dev,
672 desc->its_discard_cmd.event_id);
674 its_encode_cmd(cmd, GITS_CMD_DISCARD);
675 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
676 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
680 return valid_col(col);
683 static struct its_collection *its_build_inv_cmd(struct its_node *its,
684 struct its_cmd_block *cmd,
685 struct its_cmd_desc *desc)
687 struct its_collection *col;
689 col = dev_event_to_col(desc->its_inv_cmd.dev,
690 desc->its_inv_cmd.event_id);
692 its_encode_cmd(cmd, GITS_CMD_INV);
693 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
694 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
698 return valid_col(col);
701 static struct its_collection *its_build_int_cmd(struct its_node *its,
702 struct its_cmd_block *cmd,
703 struct its_cmd_desc *desc)
705 struct its_collection *col;
707 col = dev_event_to_col(desc->its_int_cmd.dev,
708 desc->its_int_cmd.event_id);
710 its_encode_cmd(cmd, GITS_CMD_INT);
711 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
712 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
716 return valid_col(col);
719 static struct its_collection *its_build_clear_cmd(struct its_node *its,
720 struct its_cmd_block *cmd,
721 struct its_cmd_desc *desc)
723 struct its_collection *col;
725 col = dev_event_to_col(desc->its_clear_cmd.dev,
726 desc->its_clear_cmd.event_id);
728 its_encode_cmd(cmd, GITS_CMD_CLEAR);
729 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
730 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
734 return valid_col(col);
737 static struct its_collection *its_build_invall_cmd(struct its_node *its,
738 struct its_cmd_block *cmd,
739 struct its_cmd_desc *desc)
741 its_encode_cmd(cmd, GITS_CMD_INVALL);
742 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
749 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
750 struct its_cmd_block *cmd,
751 struct its_cmd_desc *desc)
753 its_encode_cmd(cmd, GITS_CMD_VINVALL);
754 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
758 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
761 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
762 struct its_cmd_block *cmd,
763 struct its_cmd_desc *desc)
765 unsigned long vpt_addr, vconf_addr;
769 its_encode_cmd(cmd, GITS_CMD_VMAPP);
770 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
771 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
773 if (!desc->its_vmapp_cmd.valid) {
775 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
776 its_encode_alloc(cmd, alloc);
782 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
783 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
785 its_encode_target(cmd, target);
786 its_encode_vpt_addr(cmd, vpt_addr);
787 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
792 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
794 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
796 its_encode_alloc(cmd, alloc);
798 /* We can only signal PTZ when alloc==1. Why do we have two bits? */
799 its_encode_ptz(cmd, alloc);
800 its_encode_vconf_addr(cmd, vconf_addr);
801 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
806 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
809 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
810 struct its_cmd_block *cmd,
811 struct its_cmd_desc *desc)
815 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
816 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
820 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
821 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
822 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
823 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
824 its_encode_db_phys_id(cmd, db);
825 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
829 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
832 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
833 struct its_cmd_block *cmd,
834 struct its_cmd_desc *desc)
838 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
839 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
843 its_encode_cmd(cmd, GITS_CMD_VMOVI);
844 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
845 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
846 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
847 its_encode_db_phys_id(cmd, db);
848 its_encode_db_valid(cmd, true);
852 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
855 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
856 struct its_cmd_block *cmd,
857 struct its_cmd_desc *desc)
861 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
862 its_encode_cmd(cmd, GITS_CMD_VMOVP);
863 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
864 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
865 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
866 its_encode_target(cmd, target);
869 its_encode_db(cmd, true);
870 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
875 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
878 static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
879 struct its_cmd_block *cmd,
880 struct its_cmd_desc *desc)
882 struct its_vlpi_map *map;
884 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
885 desc->its_inv_cmd.event_id);
887 its_encode_cmd(cmd, GITS_CMD_INV);
888 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
889 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
893 return valid_vpe(its, map->vpe);
896 static struct its_vpe *its_build_vint_cmd(struct its_node *its,
897 struct its_cmd_block *cmd,
898 struct its_cmd_desc *desc)
900 struct its_vlpi_map *map;
902 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
903 desc->its_int_cmd.event_id);
905 its_encode_cmd(cmd, GITS_CMD_INT);
906 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
907 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
911 return valid_vpe(its, map->vpe);
914 static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
915 struct its_cmd_block *cmd,
916 struct its_cmd_desc *desc)
918 struct its_vlpi_map *map;
920 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
921 desc->its_clear_cmd.event_id);
923 its_encode_cmd(cmd, GITS_CMD_CLEAR);
924 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
925 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
929 return valid_vpe(its, map->vpe);
932 static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
933 struct its_cmd_block *cmd,
934 struct its_cmd_desc *desc)
936 if (WARN_ON(!is_v4_1(its)))
939 its_encode_cmd(cmd, GITS_CMD_INVDB);
940 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
944 return valid_vpe(its, desc->its_invdb_cmd.vpe);
947 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
948 struct its_cmd_block *cmd,
949 struct its_cmd_desc *desc)
951 if (WARN_ON(!is_v4_1(its)))
954 its_encode_cmd(cmd, GITS_CMD_VSGI);
955 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
956 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
957 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
958 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
959 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
960 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
964 return valid_vpe(its, desc->its_vsgi_cmd.vpe);
967 static u64 its_cmd_ptr_to_offset(struct its_node *its,
968 struct its_cmd_block *ptr)
970 return (ptr - its->cmd_base) * sizeof(*ptr);
973 static int its_queue_full(struct its_node *its)
978 widx = its->cmd_write - its->cmd_base;
979 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
981 /* This is incredibly unlikely to happen, unless the ITS locks up. */
982 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
988 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
990 struct its_cmd_block *cmd;
991 u32 count = 1000000; /* 1s! */
993 while (its_queue_full(its)) {
996 pr_err_ratelimited("ITS queue not draining\n");
1003 cmd = its->cmd_write++;
1005 /* Handle queue wrapping */
1006 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1007 its->cmd_write = its->cmd_base;
1010 cmd->raw_cmd[0] = 0;
1011 cmd->raw_cmd[1] = 0;
1012 cmd->raw_cmd[2] = 0;
1013 cmd->raw_cmd[3] = 0;
1018 static struct its_cmd_block *its_post_commands(struct its_node *its)
1020 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1022 writel_relaxed(wr, its->base + GITS_CWRITER);
1024 return its->cmd_write;
1027 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1030 * Make sure the commands written to memory are observable by
1033 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1034 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1039 static int its_wait_for_range_completion(struct its_node *its,
1041 struct its_cmd_block *to)
1043 u64 rd_idx, to_idx, linear_idx;
1044 u32 count = 1000000; /* 1s! */
1046 /* Linearize to_idx if the command set has wrapped around */
1047 to_idx = its_cmd_ptr_to_offset(its, to);
1048 if (to_idx < prev_idx)
1049 to_idx += ITS_CMD_QUEUE_SZ;
1051 linear_idx = prev_idx;
1056 rd_idx = readl_relaxed(its->base + GITS_CREADR);
1059 * Compute the read pointer progress, taking the
1060 * potential wrap-around into account.
1062 delta = rd_idx - prev_idx;
1063 if (rd_idx < prev_idx)
1064 delta += ITS_CMD_QUEUE_SZ;
1066 linear_idx += delta;
1067 if (linear_idx >= to_idx)
1072 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1073 to_idx, linear_idx);
1084 /* Warning, macro hell follows */
1085 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
1086 void name(struct its_node *its, \
1087 buildtype builder, \
1088 struct its_cmd_desc *desc) \
1090 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
1091 synctype *sync_obj; \
1092 unsigned long flags; \
1095 raw_spin_lock_irqsave(&its->lock, flags); \
1097 cmd = its_allocate_entry(its); \
1098 if (!cmd) { /* We're soooooo screewed... */ \
1099 raw_spin_unlock_irqrestore(&its->lock, flags); \
1102 sync_obj = builder(its, cmd, desc); \
1103 its_flush_cmd(its, cmd); \
1106 sync_cmd = its_allocate_entry(its); \
1110 buildfn(its, sync_cmd, sync_obj); \
1111 its_flush_cmd(its, sync_cmd); \
1115 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1116 next_cmd = its_post_commands(its); \
1117 raw_spin_unlock_irqrestore(&its->lock, flags); \
1119 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1120 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1123 static void its_build_sync_cmd(struct its_node *its,
1124 struct its_cmd_block *sync_cmd,
1125 struct its_collection *sync_col)
1127 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1128 its_encode_target(sync_cmd, sync_col->target_address);
1130 its_fixup_cmd(sync_cmd);
1133 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1134 struct its_collection, its_build_sync_cmd)
1136 static void its_build_vsync_cmd(struct its_node *its,
1137 struct its_cmd_block *sync_cmd,
1138 struct its_vpe *sync_vpe)
1140 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1141 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1143 its_fixup_cmd(sync_cmd);
1146 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1147 struct its_vpe, its_build_vsync_cmd)
1149 static void its_send_int(struct its_device *dev, u32 event_id)
1151 struct its_cmd_desc desc;
1153 desc.its_int_cmd.dev = dev;
1154 desc.its_int_cmd.event_id = event_id;
1156 its_send_single_command(dev->its, its_build_int_cmd, &desc);
1159 static void its_send_clear(struct its_device *dev, u32 event_id)
1161 struct its_cmd_desc desc;
1163 desc.its_clear_cmd.dev = dev;
1164 desc.its_clear_cmd.event_id = event_id;
1166 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1169 static void its_send_inv(struct its_device *dev, u32 event_id)
1171 struct its_cmd_desc desc;
1173 desc.its_inv_cmd.dev = dev;
1174 desc.its_inv_cmd.event_id = event_id;
1176 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1179 static void its_send_mapd(struct its_device *dev, int valid)
1181 struct its_cmd_desc desc;
1183 desc.its_mapd_cmd.dev = dev;
1184 desc.its_mapd_cmd.valid = !!valid;
1186 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1189 static void its_send_mapc(struct its_node *its, struct its_collection *col,
1192 struct its_cmd_desc desc;
1194 desc.its_mapc_cmd.col = col;
1195 desc.its_mapc_cmd.valid = !!valid;
1197 its_send_single_command(its, its_build_mapc_cmd, &desc);
1200 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1202 struct its_cmd_desc desc;
1204 desc.its_mapti_cmd.dev = dev;
1205 desc.its_mapti_cmd.phys_id = irq_id;
1206 desc.its_mapti_cmd.event_id = id;
1208 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1211 static void its_send_movi(struct its_device *dev,
1212 struct its_collection *col, u32 id)
1214 struct its_cmd_desc desc;
1216 desc.its_movi_cmd.dev = dev;
1217 desc.its_movi_cmd.col = col;
1218 desc.its_movi_cmd.event_id = id;
1220 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1223 static void its_send_discard(struct its_device *dev, u32 id)
1225 struct its_cmd_desc desc;
1227 desc.its_discard_cmd.dev = dev;
1228 desc.its_discard_cmd.event_id = id;
1230 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1233 static void its_send_invall(struct its_node *its, struct its_collection *col)
1235 struct its_cmd_desc desc;
1237 desc.its_invall_cmd.col = col;
1239 its_send_single_command(its, its_build_invall_cmd, &desc);
1242 static void its_send_vmapti(struct its_device *dev, u32 id)
1244 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1245 struct its_cmd_desc desc;
1247 desc.its_vmapti_cmd.vpe = map->vpe;
1248 desc.its_vmapti_cmd.dev = dev;
1249 desc.its_vmapti_cmd.virt_id = map->vintid;
1250 desc.its_vmapti_cmd.event_id = id;
1251 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1253 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1256 static void its_send_vmovi(struct its_device *dev, u32 id)
1258 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1259 struct its_cmd_desc desc;
1261 desc.its_vmovi_cmd.vpe = map->vpe;
1262 desc.its_vmovi_cmd.dev = dev;
1263 desc.its_vmovi_cmd.event_id = id;
1264 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1266 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1269 static void its_send_vmapp(struct its_node *its,
1270 struct its_vpe *vpe, bool valid)
1272 struct its_cmd_desc desc;
1274 desc.its_vmapp_cmd.vpe = vpe;
1275 desc.its_vmapp_cmd.valid = valid;
1276 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1278 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1281 static void its_send_vmovp(struct its_vpe *vpe)
1283 struct its_cmd_desc desc = {};
1284 struct its_node *its;
1285 unsigned long flags;
1286 int col_id = vpe->col_idx;
1288 desc.its_vmovp_cmd.vpe = vpe;
1290 if (!its_list_map) {
1291 its = list_first_entry(&its_nodes, struct its_node, entry);
1292 desc.its_vmovp_cmd.col = &its->collections[col_id];
1293 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1298 * Yet another marvel of the architecture. If using the
1299 * its_list "feature", we need to make sure that all ITSs
1300 * receive all VMOVP commands in the same order. The only way
1301 * to guarantee this is to make vmovp a serialization point.
1305 raw_spin_lock_irqsave(&vmovp_lock, flags);
1307 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1308 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1311 list_for_each_entry(its, &its_nodes, entry) {
1315 if (!require_its_list_vmovp(vpe->its_vm, its))
1318 desc.its_vmovp_cmd.col = &its->collections[col_id];
1319 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1322 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1325 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1327 struct its_cmd_desc desc;
1329 desc.its_vinvall_cmd.vpe = vpe;
1330 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1333 static void its_send_vinv(struct its_device *dev, u32 event_id)
1335 struct its_cmd_desc desc;
1338 * There is no real VINV command. This is just a normal INV,
1339 * with a VSYNC instead of a SYNC.
1341 desc.its_inv_cmd.dev = dev;
1342 desc.its_inv_cmd.event_id = event_id;
1344 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1347 static void its_send_vint(struct its_device *dev, u32 event_id)
1349 struct its_cmd_desc desc;
1352 * There is no real VINT command. This is just a normal INT,
1353 * with a VSYNC instead of a SYNC.
1355 desc.its_int_cmd.dev = dev;
1356 desc.its_int_cmd.event_id = event_id;
1358 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1361 static void its_send_vclear(struct its_device *dev, u32 event_id)
1363 struct its_cmd_desc desc;
1366 * There is no real VCLEAR command. This is just a normal CLEAR,
1367 * with a VSYNC instead of a SYNC.
1369 desc.its_clear_cmd.dev = dev;
1370 desc.its_clear_cmd.event_id = event_id;
1372 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1375 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1377 struct its_cmd_desc desc;
1379 desc.its_invdb_cmd.vpe = vpe;
1380 its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1384 * irqchip functions - assumes MSI, mostly.
1386 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1388 struct its_vlpi_map *map = get_vlpi_map(d);
1389 irq_hw_number_t hwirq;
1394 va = page_address(map->vm->vprop_page);
1395 hwirq = map->vintid;
1397 /* Remember the updated property */
1398 map->properties &= ~clr;
1399 map->properties |= set | LPI_PROP_GROUP1;
1401 va = gic_rdists->prop_table_va;
1405 cfg = va + hwirq - 8192;
1407 *cfg |= set | LPI_PROP_GROUP1;
1410 * Make the above write visible to the redistributors.
1411 * And yes, we're flushing exactly: One. Single. Byte.
1414 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1415 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1420 static void wait_for_syncr(void __iomem *rdbase)
1422 while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1426 static void direct_lpi_inv(struct irq_data *d)
1428 struct its_vlpi_map *map = get_vlpi_map(d);
1429 void __iomem *rdbase;
1430 unsigned long flags;
1435 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1437 WARN_ON(!is_v4_1(its_dev->its));
1439 val = GICR_INVLPIR_V;
1440 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1441 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1446 /* Target the redistributor this LPI is currently routed to */
1447 cpu = irq_to_cpuid_lock(d, &flags);
1448 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1449 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1450 gic_write_lpir(val, rdbase + GICR_INVLPIR);
1452 wait_for_syncr(rdbase);
1453 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1454 irq_to_cpuid_unlock(d, flags);
1457 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1459 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1461 lpi_write_config(d, clr, set);
1462 if (gic_rdists->has_direct_lpi &&
1463 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1465 else if (!irqd_is_forwarded_to_vcpu(d))
1466 its_send_inv(its_dev, its_get_event_id(d));
1468 its_send_vinv(its_dev, its_get_event_id(d));
1471 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1473 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1474 u32 event = its_get_event_id(d);
1475 struct its_vlpi_map *map;
1478 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1481 if (is_v4_1(its_dev->its))
1484 map = dev_event_to_vlpi_map(its_dev, event);
1486 if (map->db_enabled == enable)
1489 map->db_enabled = enable;
1492 * More fun with the architecture:
1494 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1495 * value or to 1023, depending on the enable bit. But that
1496 * would be issueing a mapping for an /existing/ DevID+EventID
1497 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1498 * to the /same/ vPE, using this opportunity to adjust the
1499 * doorbell. Mouahahahaha. We loves it, Precious.
1501 its_send_vmovi(its_dev, event);
1504 static void its_mask_irq(struct irq_data *d)
1506 if (irqd_is_forwarded_to_vcpu(d))
1507 its_vlpi_set_doorbell(d, false);
1509 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1512 static void its_unmask_irq(struct irq_data *d)
1514 if (irqd_is_forwarded_to_vcpu(d))
1515 its_vlpi_set_doorbell(d, true);
1517 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1520 static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1522 if (irqd_affinity_is_managed(d))
1523 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1525 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1528 static void its_inc_lpi_count(struct irq_data *d, int cpu)
1530 if (irqd_affinity_is_managed(d))
1531 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1533 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1536 static void its_dec_lpi_count(struct irq_data *d, int cpu)
1538 if (irqd_affinity_is_managed(d))
1539 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1541 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1544 static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1545 const struct cpumask *cpu_mask)
1547 unsigned int cpu = nr_cpu_ids, tmp;
1548 int count = S32_MAX;
1550 for_each_cpu(tmp, cpu_mask) {
1551 int this_count = its_read_lpi_count(d, tmp);
1552 if (this_count < count) {
1562 * As suggested by Thomas Gleixner in:
1563 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1565 static int its_select_cpu(struct irq_data *d,
1566 const struct cpumask *aff_mask)
1568 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1569 cpumask_var_t tmpmask;
1572 if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
1575 node = its_dev->its->numa_node;
1577 if (!irqd_affinity_is_managed(d)) {
1578 /* First try the NUMA node */
1579 if (node != NUMA_NO_NODE) {
1581 * Try the intersection of the affinity mask and the
1582 * node mask (and the online mask, just to be safe).
1584 cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1585 cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1588 * Ideally, we would check if the mask is empty, and
1589 * try again on the full node here.
1591 * But it turns out that the way ACPI describes the
1592 * affinity for ITSs only deals about memory, and
1593 * not target CPUs, so it cannot describe a single
1594 * ITS placed next to two NUMA nodes.
1596 * Instead, just fallback on the online mask. This
1597 * diverges from Thomas' suggestion above.
1599 cpu = cpumask_pick_least_loaded(d, tmpmask);
1600 if (cpu < nr_cpu_ids)
1603 /* If we can't cross sockets, give up */
1604 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1607 /* If the above failed, expand the search */
1610 /* Try the intersection of the affinity and online masks */
1611 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1613 /* If that doesn't fly, the online mask is the last resort */
1614 if (cpumask_empty(tmpmask))
1615 cpumask_copy(tmpmask, cpu_online_mask);
1617 cpu = cpumask_pick_least_loaded(d, tmpmask);
1619 cpumask_and(tmpmask, irq_data_get_affinity_mask(d), cpu_online_mask);
1621 /* If we cannot cross sockets, limit the search to that node */
1622 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1623 node != NUMA_NO_NODE)
1624 cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1626 cpu = cpumask_pick_least_loaded(d, tmpmask);
1629 free_cpumask_var(tmpmask);
1631 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1635 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1638 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1639 struct its_collection *target_col;
1640 u32 id = its_get_event_id(d);
1643 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1644 if (irqd_is_forwarded_to_vcpu(d))
1647 prev_cpu = its_dev->event_map.col_map[id];
1648 its_dec_lpi_count(d, prev_cpu);
1651 cpu = its_select_cpu(d, mask_val);
1653 cpu = cpumask_pick_least_loaded(d, mask_val);
1655 if (cpu < 0 || cpu >= nr_cpu_ids)
1658 /* don't set the affinity when the target cpu is same as current one */
1659 if (cpu != prev_cpu) {
1660 target_col = &its_dev->its->collections[cpu];
1661 its_send_movi(its_dev, target_col, id);
1662 its_dev->event_map.col_map[id] = cpu;
1663 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1666 its_inc_lpi_count(d, cpu);
1668 return IRQ_SET_MASK_OK_DONE;
1671 its_inc_lpi_count(d, prev_cpu);
1675 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1677 struct its_node *its = its_dev->its;
1679 return its->phys_base + GITS_TRANSLATER;
1682 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1684 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1685 struct its_node *its;
1689 addr = its->get_msi_base(its_dev);
1691 msg->address_lo = lower_32_bits(addr);
1692 msg->address_hi = upper_32_bits(addr);
1693 msg->data = its_get_event_id(d);
1695 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1698 static int its_irq_set_irqchip_state(struct irq_data *d,
1699 enum irqchip_irq_state which,
1702 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1703 u32 event = its_get_event_id(d);
1705 if (which != IRQCHIP_STATE_PENDING)
1708 if (irqd_is_forwarded_to_vcpu(d)) {
1710 its_send_vint(its_dev, event);
1712 its_send_vclear(its_dev, event);
1715 its_send_int(its_dev, event);
1717 its_send_clear(its_dev, event);
1724 * Two favourable cases:
1726 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1729 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1730 * and we're better off mapping all VPEs always
1732 * If neither (a) nor (b) is true, then we map vPEs on demand.
1735 static bool gic_requires_eager_mapping(void)
1737 if (!its_list_map || gic_rdists->has_rvpeid)
1743 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1745 unsigned long flags;
1747 if (gic_requires_eager_mapping())
1750 raw_spin_lock_irqsave(&vmovp_lock, flags);
1753 * If the VM wasn't mapped yet, iterate over the vpes and get
1756 vm->vlpi_count[its->list_nr]++;
1758 if (vm->vlpi_count[its->list_nr] == 1) {
1761 for (i = 0; i < vm->nr_vpes; i++) {
1762 struct its_vpe *vpe = vm->vpes[i];
1763 struct irq_data *d = irq_get_irq_data(vpe->irq);
1765 /* Map the VPE to the first possible CPU */
1766 vpe->col_idx = cpumask_first(cpu_online_mask);
1767 its_send_vmapp(its, vpe, true);
1768 its_send_vinvall(its, vpe);
1769 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1773 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1776 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1778 unsigned long flags;
1780 /* Not using the ITS list? Everything is always mapped. */
1781 if (gic_requires_eager_mapping())
1784 raw_spin_lock_irqsave(&vmovp_lock, flags);
1786 if (!--vm->vlpi_count[its->list_nr]) {
1789 for (i = 0; i < vm->nr_vpes; i++)
1790 its_send_vmapp(its, vm->vpes[i], false);
1793 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1796 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1798 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1799 u32 event = its_get_event_id(d);
1805 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1807 if (!its_dev->event_map.vm) {
1808 struct its_vlpi_map *maps;
1810 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1817 its_dev->event_map.vm = info->map->vm;
1818 its_dev->event_map.vlpi_maps = maps;
1819 } else if (its_dev->event_map.vm != info->map->vm) {
1824 /* Get our private copy of the mapping information */
1825 its_dev->event_map.vlpi_maps[event] = *info->map;
1827 if (irqd_is_forwarded_to_vcpu(d)) {
1828 /* Already mapped, move it around */
1829 its_send_vmovi(its_dev, event);
1831 /* Ensure all the VPEs are mapped on this ITS */
1832 its_map_vm(its_dev->its, info->map->vm);
1835 * Flag the interrupt as forwarded so that we can
1836 * start poking the virtual property table.
1838 irqd_set_forwarded_to_vcpu(d);
1840 /* Write out the property to the prop table */
1841 lpi_write_config(d, 0xff, info->map->properties);
1843 /* Drop the physical mapping */
1844 its_send_discard(its_dev, event);
1846 /* and install the virtual one */
1847 its_send_vmapti(its_dev, event);
1849 /* Increment the number of VLPIs */
1850 its_dev->event_map.nr_vlpis++;
1854 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1858 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1860 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1861 struct its_vlpi_map *map;
1864 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1866 map = get_vlpi_map(d);
1868 if (!its_dev->event_map.vm || !map) {
1873 /* Copy our mapping information to the incoming request */
1877 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1881 static int its_vlpi_unmap(struct irq_data *d)
1883 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1884 u32 event = its_get_event_id(d);
1887 raw_spin_lock(&its_dev->event_map.vlpi_lock);
1889 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1894 /* Drop the virtual mapping */
1895 its_send_discard(its_dev, event);
1897 /* and restore the physical one */
1898 irqd_clr_forwarded_to_vcpu(d);
1899 its_send_mapti(its_dev, d->hwirq, event);
1900 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1904 /* Potentially unmap the VM from this ITS */
1905 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1908 * Drop the refcount and make the device available again if
1909 * this was the last VLPI.
1911 if (!--its_dev->event_map.nr_vlpis) {
1912 its_dev->event_map.vm = NULL;
1913 kfree(its_dev->event_map.vlpi_maps);
1917 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1921 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1923 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1925 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1928 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1929 lpi_update_config(d, 0xff, info->config);
1931 lpi_write_config(d, 0xff, info->config);
1932 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1937 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1939 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1940 struct its_cmd_info *info = vcpu_info;
1943 if (!is_v4(its_dev->its))
1946 /* Unmap request? */
1948 return its_vlpi_unmap(d);
1950 switch (info->cmd_type) {
1952 return its_vlpi_map(d, info);
1955 return its_vlpi_get(d, info);
1957 case PROP_UPDATE_VLPI:
1958 case PROP_UPDATE_AND_INV_VLPI:
1959 return its_vlpi_prop_update(d, info);
1966 static struct irq_chip its_irq_chip = {
1968 .irq_mask = its_mask_irq,
1969 .irq_unmask = its_unmask_irq,
1970 .irq_eoi = irq_chip_eoi_parent,
1971 .irq_set_affinity = its_set_affinity,
1972 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1973 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1974 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1979 * How we allocate LPIs:
1981 * lpi_range_list contains ranges of LPIs that are to available to
1982 * allocate from. To allocate LPIs, just pick the first range that
1983 * fits the required allocation, and reduce it by the required
1984 * amount. Once empty, remove the range from the list.
1986 * To free a range of LPIs, add a free range to the list, sort it and
1987 * merge the result if the new range happens to be adjacent to an
1988 * already free block.
1990 * The consequence of the above is that allocation is cost is low, but
1991 * freeing is expensive. We assumes that freeing rarely occurs.
1993 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1995 static DEFINE_MUTEX(lpi_range_lock);
1996 static LIST_HEAD(lpi_range_list);
1999 struct list_head entry;
2004 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2006 struct lpi_range *range;
2008 range = kmalloc(sizeof(*range), GFP_KERNEL);
2010 range->base_id = base;
2017 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2019 struct lpi_range *range, *tmp;
2022 mutex_lock(&lpi_range_lock);
2024 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2025 if (range->span >= nr_lpis) {
2026 *base = range->base_id;
2027 range->base_id += nr_lpis;
2028 range->span -= nr_lpis;
2030 if (range->span == 0) {
2031 list_del(&range->entry);
2040 mutex_unlock(&lpi_range_lock);
2042 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2046 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2048 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2050 if (a->base_id + a->span != b->base_id)
2052 b->base_id = a->base_id;
2054 list_del(&a->entry);
2058 static int free_lpi_range(u32 base, u32 nr_lpis)
2060 struct lpi_range *new, *old;
2062 new = mk_lpi_range(base, nr_lpis);
2066 mutex_lock(&lpi_range_lock);
2068 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2069 if (old->base_id < base)
2073 * old is the last element with ->base_id smaller than base,
2074 * so new goes right after it. If there are no elements with
2075 * ->base_id smaller than base, &old->entry ends up pointing
2076 * at the head of the list, and inserting new it the start of
2077 * the list is the right thing to do in that case as well.
2079 list_add(&new->entry, &old->entry);
2081 * Now check if we can merge with the preceding and/or
2084 merge_lpi_ranges(old, new);
2085 merge_lpi_ranges(new, list_next_entry(new, entry));
2087 mutex_unlock(&lpi_range_lock);
2091 static int __init its_lpi_init(u32 id_bits)
2093 u32 lpis = (1UL << id_bits) - 8192;
2097 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2099 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2101 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2106 * Initializing the allocator is just the same as freeing the
2107 * full range of LPIs.
2109 err = free_lpi_range(8192, lpis);
2110 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2114 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2116 unsigned long *bitmap = NULL;
2120 err = alloc_lpi_range(nr_irqs, base);
2125 } while (nr_irqs > 0);
2133 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
2141 *base = *nr_ids = 0;
2146 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2148 WARN_ON(free_lpi_range(base, nr_ids));
2152 static void gic_reset_prop_table(void *va)
2154 /* Priority 0xa0, Group-1, disabled */
2155 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2157 /* Make sure the GIC will observe the written configuration */
2158 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2161 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2163 struct page *prop_page;
2165 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2169 gic_reset_prop_table(page_address(prop_page));
2174 static void its_free_prop_table(struct page *prop_page)
2176 free_pages((unsigned long)page_address(prop_page),
2177 get_order(LPI_PROPBASE_SZ));
2180 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2182 phys_addr_t start, end, addr_end;
2186 * We don't bother checking for a kdump kernel as by
2187 * construction, the LPI tables are out of this kernel's
2190 if (is_kdump_kernel())
2193 addr_end = addr + size - 1;
2195 for_each_reserved_mem_region(i, &start, &end) {
2196 if (addr >= start && addr_end <= end)
2200 /* Not found, not a good sign... */
2201 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2203 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2207 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2209 if (efi_enabled(EFI_CONFIG_TABLES))
2210 return efi_mem_reserve_persistent(addr, size);
2215 static int __init its_setup_lpi_prop_table(void)
2217 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2220 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2221 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2223 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2224 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2227 gic_reset_prop_table(gic_rdists->prop_table_va);
2231 lpi_id_bits = min_t(u32,
2232 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2233 ITS_MAX_LPI_NRBITS);
2234 page = its_allocate_prop_table(GFP_NOWAIT);
2236 pr_err("Failed to allocate PROPBASE\n");
2240 gic_rdists->prop_table_pa = page_to_phys(page);
2241 gic_rdists->prop_table_va = page_address(page);
2242 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2246 pr_info("GICv3: using LPI property table @%pa\n",
2247 &gic_rdists->prop_table_pa);
2249 return its_lpi_init(lpi_id_bits);
2252 static const char *its_base_type_string[] = {
2253 [GITS_BASER_TYPE_DEVICE] = "Devices",
2254 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
2255 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
2256 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
2257 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
2258 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
2259 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
2262 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2264 u32 idx = baser - its->tables;
2266 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2269 static void its_write_baser(struct its_node *its, struct its_baser *baser,
2272 u32 idx = baser - its->tables;
2274 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2275 baser->val = its_read_baser(its, baser);
2278 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2279 u64 cache, u64 shr, u32 order, bool indirect)
2281 u64 val = its_read_baser(its, baser);
2282 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2283 u64 type = GITS_BASER_TYPE(val);
2284 u64 baser_phys, tmp;
2285 u32 alloc_pages, psz;
2290 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2291 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2292 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2293 &its->phys_base, its_base_type_string[type],
2294 alloc_pages, GITS_BASER_PAGES_MAX);
2295 alloc_pages = GITS_BASER_PAGES_MAX;
2296 order = get_order(GITS_BASER_PAGES_MAX * psz);
2299 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2303 base = (void *)page_address(page);
2304 baser_phys = virt_to_phys(base);
2306 /* Check if the physical address of the memory is above 48bits */
2307 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2309 /* 52bit PA is supported only when PageSize=64K */
2310 if (psz != SZ_64K) {
2311 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2312 free_pages((unsigned long)base, order);
2316 /* Convert 52bit PA to 48bit field */
2317 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2322 (type << GITS_BASER_TYPE_SHIFT) |
2323 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2324 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2329 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2333 val |= GITS_BASER_PAGE_SIZE_4K;
2336 val |= GITS_BASER_PAGE_SIZE_16K;
2339 val |= GITS_BASER_PAGE_SIZE_64K;
2343 its_write_baser(its, baser, val);
2346 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2348 * Shareability didn't stick. Just use
2349 * whatever the read reported, which is likely
2350 * to be the only thing this redistributor
2351 * supports. If that's zero, make it
2352 * non-cacheable as well.
2354 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2356 cache = GITS_BASER_nC;
2357 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2363 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2364 &its->phys_base, its_base_type_string[type],
2366 free_pages((unsigned long)base, order);
2370 baser->order = order;
2373 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2375 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2376 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2377 its_base_type_string[type],
2378 (unsigned long)virt_to_phys(base),
2379 indirect ? "indirect" : "flat", (int)esz,
2380 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2385 static bool its_parse_indirect_baser(struct its_node *its,
2386 struct its_baser *baser,
2387 u32 *order, u32 ids)
2389 u64 tmp = its_read_baser(its, baser);
2390 u64 type = GITS_BASER_TYPE(tmp);
2391 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2392 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2393 u32 new_order = *order;
2394 u32 psz = baser->psz;
2395 bool indirect = false;
2397 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2398 if ((esz << ids) > (psz * 2)) {
2400 * Find out whether hw supports a single or two-level table by
2401 * table by reading bit at offset '62' after writing '1' to it.
2403 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2404 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2408 * The size of the lvl2 table is equal to ITS page size
2409 * which is 'psz'. For computing lvl1 table size,
2410 * subtract ID bits that sparse lvl2 table from 'ids'
2411 * which is reported by ITS hardware times lvl1 table
2414 ids -= ilog2(psz / (int)esz);
2415 esz = GITS_LVL1_ENTRY_SIZE;
2420 * Allocate as many entries as required to fit the
2421 * range of device IDs that the ITS can grok... The ID
2422 * space being incredibly sparse, this results in a
2423 * massive waste of memory if two-level device table
2424 * feature is not supported by hardware.
2426 new_order = max_t(u32, get_order(esz << ids), new_order);
2427 if (new_order >= MAX_ORDER) {
2428 new_order = MAX_ORDER - 1;
2429 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2430 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2431 &its->phys_base, its_base_type_string[type],
2432 device_ids(its), ids);
2440 static u32 compute_common_aff(u64 val)
2444 aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2445 clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2447 return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2450 static u32 compute_its_aff(struct its_node *its)
2456 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2457 * the resulting affinity. We then use that to see if this match
2460 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2461 val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2462 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2463 return compute_common_aff(val);
2466 static struct its_node *find_sibling_its(struct its_node *cur_its)
2468 struct its_node *its;
2471 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2474 aff = compute_its_aff(cur_its);
2476 list_for_each_entry(its, &its_nodes, entry) {
2479 if (!is_v4_1(its) || its == cur_its)
2482 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2485 if (aff != compute_its_aff(its))
2488 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2489 baser = its->tables[2].val;
2490 if (!(baser & GITS_BASER_VALID))
2499 static void its_free_tables(struct its_node *its)
2503 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2504 if (its->tables[i].base) {
2505 free_pages((unsigned long)its->tables[i].base,
2506 its->tables[i].order);
2507 its->tables[i].base = NULL;
2512 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2519 val = its_read_baser(its, baser);
2520 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2524 gpsz = GITS_BASER_PAGE_SIZE_64K;
2527 gpsz = GITS_BASER_PAGE_SIZE_16K;
2531 gpsz = GITS_BASER_PAGE_SIZE_4K;
2535 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2537 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2538 its_write_baser(its, baser, val);
2540 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2560 static int its_alloc_tables(struct its_node *its)
2562 u64 shr = GITS_BASER_InnerShareable;
2563 u64 cache = GITS_BASER_RaWaWb;
2566 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2567 /* erratum 24313: ignore memory access type */
2568 cache = GITS_BASER_nCnB;
2570 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2571 struct its_baser *baser = its->tables + i;
2572 u64 val = its_read_baser(its, baser);
2573 u64 type = GITS_BASER_TYPE(val);
2574 bool indirect = false;
2577 if (type == GITS_BASER_TYPE_NONE)
2580 if (its_probe_baser_psz(its, baser)) {
2581 its_free_tables(its);
2585 order = get_order(baser->psz);
2588 case GITS_BASER_TYPE_DEVICE:
2589 indirect = its_parse_indirect_baser(its, baser, &order,
2593 case GITS_BASER_TYPE_VCPU:
2595 struct its_node *sibling;
2598 if ((sibling = find_sibling_its(its))) {
2599 *baser = sibling->tables[2];
2600 its_write_baser(its, baser, baser->val);
2605 indirect = its_parse_indirect_baser(its, baser, &order,
2606 ITS_MAX_VPEID_BITS);
2610 err = its_setup_baser(its, baser, cache, shr, order, indirect);
2612 its_free_tables(its);
2616 /* Update settings which will be used for next BASERn */
2617 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2618 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2624 static u64 inherit_vpe_l1_table_from_its(void)
2626 struct its_node *its;
2630 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2631 aff = compute_common_aff(val);
2633 list_for_each_entry(its, &its_nodes, entry) {
2639 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2642 if (aff != compute_its_aff(its))
2645 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2646 baser = its->tables[2].val;
2647 if (!(baser & GITS_BASER_VALID))
2650 /* We have a winner! */
2651 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2653 val = GICR_VPROPBASER_4_1_VALID;
2654 if (baser & GITS_BASER_INDIRECT)
2655 val |= GICR_VPROPBASER_4_1_INDIRECT;
2656 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2657 FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2658 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2659 case GIC_PAGE_SIZE_64K:
2660 addr = GITS_BASER_ADDR_48_to_52(baser);
2663 addr = baser & GENMASK_ULL(47, 12);
2666 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2667 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2668 FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2669 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2670 FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2671 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2679 static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2685 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2686 aff = compute_common_aff(val);
2688 for_each_possible_cpu(cpu) {
2689 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2691 if (!base || cpu == smp_processor_id())
2694 val = gic_read_typer(base + GICR_TYPER);
2695 if (aff != compute_common_aff(val))
2699 * At this point, we have a victim. This particular CPU
2700 * has already booted, and has an affinity that matches
2701 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2702 * Make sure we don't write the Z bit in that case.
2704 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2705 val &= ~GICR_VPROPBASER_4_1_Z;
2707 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2708 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2716 static bool allocate_vpe_l2_table(int cpu, u32 id)
2718 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2719 unsigned int psz, esz, idx, npg, gpsz;
2724 if (!gic_rdists->has_rvpeid)
2727 /* Skip non-present CPUs */
2731 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2733 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2734 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2735 npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2741 case GIC_PAGE_SIZE_4K:
2744 case GIC_PAGE_SIZE_16K:
2747 case GIC_PAGE_SIZE_64K:
2752 /* Don't allow vpe_id that exceeds single, flat table limit */
2753 if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2754 return (id < (npg * psz / (esz * SZ_8)));
2756 /* Compute 1st level table index & check if that exceeds table limit */
2757 idx = id >> ilog2(psz / (esz * SZ_8));
2758 if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2761 table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2763 /* Allocate memory for 2nd level table */
2765 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2769 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2770 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2771 gic_flush_dcache_to_poc(page_address(page), psz);
2773 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2775 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2776 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2777 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2779 /* Ensure updated table contents are visible to RD hardware */
2786 static int allocate_vpe_l1_table(void)
2788 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2789 u64 val, gpsz, npg, pa;
2790 unsigned int psz = SZ_64K;
2791 unsigned int np, epp, esz;
2794 if (!gic_rdists->has_rvpeid)
2798 * if VPENDBASER.Valid is set, disable any previously programmed
2799 * VPE by setting PendingLast while clearing Valid. This has the
2800 * effect of making sure no doorbell will be generated and we can
2801 * then safely clear VPROPBASER.Valid.
2803 if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2804 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2805 vlpi_base + GICR_VPENDBASER);
2808 * If we can inherit the configuration from another RD, let's do
2809 * so. Otherwise, we have to go through the allocation process. We
2810 * assume that all RDs have the exact same requirements, as
2811 * nothing will work otherwise.
2813 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2814 if (val & GICR_VPROPBASER_4_1_VALID)
2817 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_KERNEL);
2818 if (!gic_data_rdist()->vpe_table_mask)
2821 val = inherit_vpe_l1_table_from_its();
2822 if (val & GICR_VPROPBASER_4_1_VALID)
2825 /* First probe the page size */
2826 val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2827 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2828 val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2829 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2830 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2834 gpsz = GIC_PAGE_SIZE_4K;
2836 case GIC_PAGE_SIZE_4K:
2839 case GIC_PAGE_SIZE_16K:
2842 case GIC_PAGE_SIZE_64K:
2848 * Start populating the register from scratch, including RO fields
2849 * (which we want to print in debug cases...)
2852 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2853 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2855 /* How many entries per GIC page? */
2857 epp = psz / (esz * SZ_8);
2860 * If we need more than just a single L1 page, flag the table
2861 * as indirect and compute the number of required L1 pages.
2863 if (epp < ITS_MAX_VPEID) {
2866 val |= GICR_VPROPBASER_4_1_INDIRECT;
2868 /* Number of L2 pages required to cover the VPEID space */
2869 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2871 /* Number of L1 pages to point to the L2 pages */
2872 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2877 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2879 /* Right, that's the number of CPU pages we need for L1 */
2880 np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2882 pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2883 np, npg, psz, epp, esz);
2884 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(np * PAGE_SIZE));
2888 gic_data_rdist()->vpe_l1_base = page_address(page);
2889 pa = virt_to_phys(page_address(page));
2890 WARN_ON(!IS_ALIGNED(pa, psz));
2892 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2893 val |= GICR_VPROPBASER_RaWb;
2894 val |= GICR_VPROPBASER_InnerShareable;
2895 val |= GICR_VPROPBASER_4_1_Z;
2896 val |= GICR_VPROPBASER_4_1_VALID;
2899 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2900 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2902 pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2903 smp_processor_id(), val,
2904 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2909 static int its_alloc_collections(struct its_node *its)
2913 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2915 if (!its->collections)
2918 for (i = 0; i < nr_cpu_ids; i++)
2919 its->collections[i].target_address = ~0ULL;
2924 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2926 struct page *pend_page;
2928 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2929 get_order(LPI_PENDBASE_SZ));
2933 /* Make sure the GIC will observe the zero-ed page */
2934 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2939 static void its_free_pending_table(struct page *pt)
2941 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2945 * Booting with kdump and LPIs enabled is generally fine. Any other
2946 * case is wrong in the absence of firmware/EFI support.
2948 static bool enabled_lpis_allowed(void)
2953 /* Check whether the property table is in a reserved region */
2954 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2955 addr = val & GENMASK_ULL(51, 12);
2957 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2960 static int __init allocate_lpi_tables(void)
2966 * If LPIs are enabled while we run this from the boot CPU,
2967 * flag the RD tables as pre-allocated if the stars do align.
2969 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2970 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2971 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2972 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2973 pr_info("GICv3: Using preallocated redistributor tables\n");
2976 err = its_setup_lpi_prop_table();
2981 * We allocate all the pending tables anyway, as we may have a
2982 * mix of RDs that have had LPIs enabled, and some that
2983 * don't. We'll free the unused ones as each CPU comes online.
2985 for_each_possible_cpu(cpu) {
2986 struct page *pend_page;
2988 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2990 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2994 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3000 static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3002 u32 count = 1000000; /* 1s! */
3006 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3007 val &= ~GICR_VPENDBASER_Valid;
3010 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3013 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3014 clean = !(val & GICR_VPENDBASER_Dirty);
3020 } while (!clean && count);
3022 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
3023 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3024 val |= GICR_VPENDBASER_PendingLast;
3030 static void its_cpu_init_lpis(void)
3032 void __iomem *rbase = gic_data_rdist_rd_base();
3033 struct page *pend_page;
3037 if (gic_data_rdist()->lpi_enabled)
3040 val = readl_relaxed(rbase + GICR_CTLR);
3041 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3042 (val & GICR_CTLR_ENABLE_LPIS)) {
3044 * Check that we get the same property table on all
3045 * RDs. If we don't, this is hopeless.
3047 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3048 paddr &= GENMASK_ULL(51, 12);
3049 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3050 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3052 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3053 paddr &= GENMASK_ULL(51, 16);
3055 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3056 its_free_pending_table(gic_data_rdist()->pend_page);
3057 gic_data_rdist()->pend_page = NULL;
3062 pend_page = gic_data_rdist()->pend_page;
3063 paddr = page_to_phys(pend_page);
3064 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
3067 val = (gic_rdists->prop_table_pa |
3068 GICR_PROPBASER_InnerShareable |
3069 GICR_PROPBASER_RaWaWb |
3070 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3072 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3073 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3075 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3076 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3078 * The HW reports non-shareable, we must
3079 * remove the cacheability attributes as
3082 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3083 GICR_PROPBASER_CACHEABILITY_MASK);
3084 val |= GICR_PROPBASER_nC;
3085 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3087 pr_info_once("GIC: using cache flushing for LPI property table\n");
3088 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3092 val = (page_to_phys(pend_page) |
3093 GICR_PENDBASER_InnerShareable |
3094 GICR_PENDBASER_RaWaWb);
3096 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3097 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3099 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3101 * The HW reports non-shareable, we must remove the
3102 * cacheability attributes as well.
3104 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3105 GICR_PENDBASER_CACHEABILITY_MASK);
3106 val |= GICR_PENDBASER_nC;
3107 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3111 val = readl_relaxed(rbase + GICR_CTLR);
3112 val |= GICR_CTLR_ENABLE_LPIS;
3113 writel_relaxed(val, rbase + GICR_CTLR);
3115 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3116 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3119 * It's possible for CPU to receive VLPIs before it is
3120 * sheduled as a vPE, especially for the first CPU, and the
3121 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3122 * as out of range and dropped by GIC.
3123 * So we initialize IDbits to known value to avoid VLPI drop.
3125 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3126 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3127 smp_processor_id(), val);
3128 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3131 * Also clear Valid bit of GICR_VPENDBASER, in case some
3132 * ancient programming gets left in and has possibility of
3133 * corrupting memory.
3135 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3138 if (allocate_vpe_l1_table()) {
3140 * If the allocation has failed, we're in massive trouble.
3141 * Disable direct injection, and pray that no VM was
3142 * already running...
3144 gic_rdists->has_rvpeid = false;
3145 gic_rdists->has_vlpis = false;
3148 /* Make sure the GIC has seen the above */
3151 gic_data_rdist()->lpi_enabled = true;
3152 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3154 gic_data_rdist()->pend_page ? "allocated" : "reserved",
3158 static void its_cpu_init_collection(struct its_node *its)
3160 int cpu = smp_processor_id();
3163 /* avoid cross node collections and its mapping */
3164 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3165 struct device_node *cpu_node;
3167 cpu_node = of_get_cpu_node(cpu, NULL);
3168 if (its->numa_node != NUMA_NO_NODE &&
3169 its->numa_node != of_node_to_nid(cpu_node))
3174 * We now have to bind each collection to its target
3177 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3179 * This ITS wants the physical address of the
3182 target = gic_data_rdist()->phys_base;
3184 /* This ITS wants a linear CPU number. */
3185 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3186 target = GICR_TYPER_CPU_NUMBER(target) << 16;
3189 /* Perform collection mapping */
3190 its->collections[cpu].target_address = target;
3191 its->collections[cpu].col_id = cpu;
3193 its_send_mapc(its, &its->collections[cpu], 1);
3194 its_send_invall(its, &its->collections[cpu]);
3197 static void its_cpu_init_collections(void)
3199 struct its_node *its;
3201 raw_spin_lock(&its_lock);
3203 list_for_each_entry(its, &its_nodes, entry)
3204 its_cpu_init_collection(its);
3206 raw_spin_unlock(&its_lock);
3209 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3211 struct its_device *its_dev = NULL, *tmp;
3212 unsigned long flags;
3214 raw_spin_lock_irqsave(&its->lock, flags);
3216 list_for_each_entry(tmp, &its->its_device_list, entry) {
3217 if (tmp->device_id == dev_id) {
3223 raw_spin_unlock_irqrestore(&its->lock, flags);
3228 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3232 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3233 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3234 return &its->tables[i];
3240 static bool its_alloc_table_entry(struct its_node *its,
3241 struct its_baser *baser, u32 id)
3247 /* Don't allow device id that exceeds single, flat table limit */
3248 esz = GITS_BASER_ENTRY_SIZE(baser->val);
3249 if (!(baser->val & GITS_BASER_INDIRECT))
3250 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3252 /* Compute 1st level table index & check if that exceeds table limit */
3253 idx = id >> ilog2(baser->psz / esz);
3254 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3257 table = baser->base;
3259 /* Allocate memory for 2nd level table */
3261 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3262 get_order(baser->psz));
3266 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3267 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3268 gic_flush_dcache_to_poc(page_address(page), baser->psz);
3270 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3272 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3273 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3274 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3276 /* Ensure updated table contents are visible to ITS hardware */
3283 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3285 struct its_baser *baser;
3287 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3289 /* Don't allow device id that exceeds ITS hardware limit */
3291 return (ilog2(dev_id) < device_ids(its));
3293 return its_alloc_table_entry(its, baser, dev_id);
3296 static bool its_alloc_vpe_table(u32 vpe_id)
3298 struct its_node *its;
3302 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3303 * could try and only do it on ITSs corresponding to devices
3304 * that have interrupts targeted at this VPE, but the
3305 * complexity becomes crazy (and you have tons of memory
3308 list_for_each_entry(its, &its_nodes, entry) {
3309 struct its_baser *baser;
3314 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3318 if (!its_alloc_table_entry(its, baser, vpe_id))
3322 /* Non v4.1? No need to iterate RDs and go back early. */
3323 if (!gic_rdists->has_rvpeid)
3327 * Make sure the L2 tables are allocated for all copies of
3328 * the L1 table on *all* v4.1 RDs.
3330 for_each_possible_cpu(cpu) {
3331 if (!allocate_vpe_l2_table(cpu, vpe_id))
3338 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3339 int nvecs, bool alloc_lpis)
3341 struct its_device *dev;
3342 unsigned long *lpi_map = NULL;
3343 unsigned long flags;
3344 u16 *col_map = NULL;
3351 if (!its_alloc_device_table(its, dev_id))
3354 if (WARN_ON(!is_power_of_2(nvecs)))
3355 nvecs = roundup_pow_of_two(nvecs);
3357 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3359 * Even if the device wants a single LPI, the ITT must be
3360 * sized as a power of two (and you need at least one bit...).
3362 nr_ites = max(2, nvecs);
3363 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3364 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3365 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3367 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3369 col_map = kcalloc(nr_lpis, sizeof(*col_map),
3372 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3377 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
3385 gic_flush_dcache_to_poc(itt, sz);
3389 dev->nr_ites = nr_ites;
3390 dev->event_map.lpi_map = lpi_map;
3391 dev->event_map.col_map = col_map;
3392 dev->event_map.lpi_base = lpi_base;
3393 dev->event_map.nr_lpis = nr_lpis;
3394 raw_spin_lock_init(&dev->event_map.vlpi_lock);
3395 dev->device_id = dev_id;
3396 INIT_LIST_HEAD(&dev->entry);
3398 raw_spin_lock_irqsave(&its->lock, flags);
3399 list_add(&dev->entry, &its->its_device_list);
3400 raw_spin_unlock_irqrestore(&its->lock, flags);
3402 /* Map device to its ITT */
3403 its_send_mapd(dev, 1);
3408 static void its_free_device(struct its_device *its_dev)
3410 unsigned long flags;
3412 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3413 list_del(&its_dev->entry);
3414 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3415 kfree(its_dev->event_map.col_map);
3416 kfree(its_dev->itt);
3420 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3424 /* Find a free LPI region in lpi_map and allocate them. */
3425 idx = bitmap_find_free_region(dev->event_map.lpi_map,
3426 dev->event_map.nr_lpis,
3427 get_count_order(nvecs));
3431 *hwirq = dev->event_map.lpi_base + idx;
3436 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3437 int nvec, msi_alloc_info_t *info)
3439 struct its_node *its;
3440 struct its_device *its_dev;
3441 struct msi_domain_info *msi_info;
3446 * We ignore "dev" entirely, and rely on the dev_id that has
3447 * been passed via the scratchpad. This limits this domain's
3448 * usefulness to upper layers that definitely know that they
3449 * are built on top of the ITS.
3451 dev_id = info->scratchpad[0].ul;
3453 msi_info = msi_get_domain_info(domain);
3454 its = msi_info->data;
3456 if (!gic_rdists->has_direct_lpi &&
3458 vpe_proxy.dev->its == its &&
3459 dev_id == vpe_proxy.dev->device_id) {
3460 /* Bad luck. Get yourself a better implementation */
3461 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3466 mutex_lock(&its->dev_alloc_lock);
3467 its_dev = its_find_device(its, dev_id);
3470 * We already have seen this ID, probably through
3471 * another alias (PCI bridge of some sort). No need to
3472 * create the device.
3474 its_dev->shared = true;
3475 pr_debug("Reusing ITT for devID %x\n", dev_id);
3479 its_dev = its_create_device(its, dev_id, nvec, true);
3485 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3487 mutex_unlock(&its->dev_alloc_lock);
3488 info->scratchpad[0].ptr = its_dev;
3492 static struct msi_domain_ops its_msi_domain_ops = {
3493 .msi_prepare = its_msi_prepare,
3496 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3498 irq_hw_number_t hwirq)
3500 struct irq_fwspec fwspec;
3502 if (irq_domain_get_of_node(domain->parent)) {
3503 fwspec.fwnode = domain->parent->fwnode;
3504 fwspec.param_count = 3;
3505 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3506 fwspec.param[1] = hwirq;
3507 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3508 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3509 fwspec.fwnode = domain->parent->fwnode;
3510 fwspec.param_count = 2;
3511 fwspec.param[0] = hwirq;
3512 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3517 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3520 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3521 unsigned int nr_irqs, void *args)
3523 msi_alloc_info_t *info = args;
3524 struct its_device *its_dev = info->scratchpad[0].ptr;
3525 struct its_node *its = its_dev->its;
3526 irq_hw_number_t hwirq;
3530 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3534 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3538 for (i = 0; i < nr_irqs; i++) {
3539 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3543 irq_domain_set_hwirq_and_chip(domain, virq + i,
3544 hwirq + i, &its_irq_chip, its_dev);
3545 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
3546 pr_debug("ID:%d pID:%d vID:%d\n",
3547 (int)(hwirq + i - its_dev->event_map.lpi_base),
3548 (int)(hwirq + i), virq + i);
3554 static int its_irq_domain_activate(struct irq_domain *domain,
3555 struct irq_data *d, bool reserve)
3557 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3558 u32 event = its_get_event_id(d);
3561 cpu = its_select_cpu(d, cpu_online_mask);
3562 if (cpu < 0 || cpu >= nr_cpu_ids)
3565 its_inc_lpi_count(d, cpu);
3566 its_dev->event_map.col_map[event] = cpu;
3567 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3569 /* Map the GIC IRQ and event to the device */
3570 its_send_mapti(its_dev, d->hwirq, event);
3574 static void its_irq_domain_deactivate(struct irq_domain *domain,
3577 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3578 u32 event = its_get_event_id(d);
3580 its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3581 /* Stop the delivery of interrupts */
3582 its_send_discard(its_dev, event);
3585 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3586 unsigned int nr_irqs)
3588 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3589 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3590 struct its_node *its = its_dev->its;
3593 bitmap_release_region(its_dev->event_map.lpi_map,
3594 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3595 get_count_order(nr_irqs));
3597 for (i = 0; i < nr_irqs; i++) {
3598 struct irq_data *data = irq_domain_get_irq_data(domain,
3600 /* Nuke the entry in the domain */
3601 irq_domain_reset_irq_data(data);
3604 mutex_lock(&its->dev_alloc_lock);
3607 * If all interrupts have been freed, start mopping the
3608 * floor. This is conditionned on the device not being shared.
3610 if (!its_dev->shared &&
3611 bitmap_empty(its_dev->event_map.lpi_map,
3612 its_dev->event_map.nr_lpis)) {
3613 its_lpi_free(its_dev->event_map.lpi_map,
3614 its_dev->event_map.lpi_base,
3615 its_dev->event_map.nr_lpis);
3617 /* Unmap device/itt */
3618 its_send_mapd(its_dev, 0);
3619 its_free_device(its_dev);
3622 mutex_unlock(&its->dev_alloc_lock);
3624 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3627 static const struct irq_domain_ops its_domain_ops = {
3628 .alloc = its_irq_domain_alloc,
3629 .free = its_irq_domain_free,
3630 .activate = its_irq_domain_activate,
3631 .deactivate = its_irq_domain_deactivate,
3637 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3638 * likely), the only way to perform an invalidate is to use a fake
3639 * device to issue an INV command, implying that the LPI has first
3640 * been mapped to some event on that device. Since this is not exactly
3641 * cheap, we try to keep that mapping around as long as possible, and
3642 * only issue an UNMAP if we're short on available slots.
3644 * Broken by design(tm).
3646 * GICv4.1, on the other hand, mandates that we're able to invalidate
3647 * by writing to a MMIO register. It doesn't implement the whole of
3648 * DirectLPI, but that's good enough. And most of the time, we don't
3649 * even have to invalidate anything, as the redistributor can be told
3650 * whether to generate a doorbell or not (we thus leave it enabled,
3653 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3655 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3656 if (gic_rdists->has_rvpeid)
3659 /* Already unmapped? */
3660 if (vpe->vpe_proxy_event == -1)
3663 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3664 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3667 * We don't track empty slots at all, so let's move the
3668 * next_victim pointer if we can quickly reuse that slot
3669 * instead of nuking an existing entry. Not clear that this is
3670 * always a win though, and this might just generate a ripple
3671 * effect... Let's just hope VPEs don't migrate too often.
3673 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3674 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3676 vpe->vpe_proxy_event = -1;
3679 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3681 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3682 if (gic_rdists->has_rvpeid)
3685 if (!gic_rdists->has_direct_lpi) {
3686 unsigned long flags;
3688 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3689 its_vpe_db_proxy_unmap_locked(vpe);
3690 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3694 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3696 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3697 if (gic_rdists->has_rvpeid)
3700 /* Already mapped? */
3701 if (vpe->vpe_proxy_event != -1)
3704 /* This slot was already allocated. Kick the other VPE out. */
3705 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3706 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3708 /* Map the new VPE instead */
3709 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3710 vpe->vpe_proxy_event = vpe_proxy.next_victim;
3711 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3713 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3714 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3717 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3719 unsigned long flags;
3720 struct its_collection *target_col;
3722 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3723 if (gic_rdists->has_rvpeid)
3726 if (gic_rdists->has_direct_lpi) {
3727 void __iomem *rdbase;
3729 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3730 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3731 wait_for_syncr(rdbase);
3736 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3738 its_vpe_db_proxy_map_locked(vpe);
3740 target_col = &vpe_proxy.dev->its->collections[to];
3741 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3742 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3744 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3747 static int its_vpe_set_affinity(struct irq_data *d,
3748 const struct cpumask *mask_val,
3751 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3752 int from, cpu = cpumask_first(mask_val);
3753 unsigned long flags;
3756 * Changing affinity is mega expensive, so let's be as lazy as
3757 * we can and only do it if we really have to. Also, if mapped
3758 * into the proxy device, we need to move the doorbell
3759 * interrupt to its new location.
3761 * Another thing is that changing the affinity of a vPE affects
3762 * *other interrupts* such as all the vLPIs that are routed to
3763 * this vPE. This means that the irq_desc lock is not enough to
3764 * protect us, and that we must ensure nobody samples vpe->col_idx
3765 * during the update, hence the lock below which must also be
3766 * taken on any vLPI handling path that evaluates vpe->col_idx.
3768 from = vpe_to_cpuid_lock(vpe, &flags);
3775 * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3776 * is sharing its VPE table with the current one.
3778 if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3779 cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3782 its_send_vmovp(vpe);
3783 its_vpe_db_proxy_move(vpe, from, cpu);
3786 irq_data_update_effective_affinity(d, cpumask_of(cpu));
3787 vpe_to_cpuid_unlock(vpe, flags);
3789 return IRQ_SET_MASK_OK_DONE;
3792 static void its_wait_vpt_parse_complete(void)
3794 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3797 if (!gic_rdists->has_vpend_valid_dirty)
3800 WARN_ON_ONCE(readq_relaxed_poll_timeout(vlpi_base + GICR_VPENDBASER,
3802 !(val & GICR_VPENDBASER_Dirty),
3806 static void its_vpe_schedule(struct its_vpe *vpe)
3808 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3811 /* Schedule the VPE */
3812 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3813 GENMASK_ULL(51, 12);
3814 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3815 val |= GICR_VPROPBASER_RaWb;
3816 val |= GICR_VPROPBASER_InnerShareable;
3817 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3819 val = virt_to_phys(page_address(vpe->vpt_page)) &
3820 GENMASK_ULL(51, 16);
3821 val |= GICR_VPENDBASER_RaWaWb;
3822 val |= GICR_VPENDBASER_InnerShareable;
3824 * There is no good way of finding out if the pending table is
3825 * empty as we can race against the doorbell interrupt very
3826 * easily. So in the end, vpe->pending_last is only an
3827 * indication that the vcpu has something pending, not one
3828 * that the pending table is empty. A good implementation
3829 * would be able to read its coarse map pretty quickly anyway,
3830 * making this a tolerable issue.
3832 val |= GICR_VPENDBASER_PendingLast;
3833 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3834 val |= GICR_VPENDBASER_Valid;
3835 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3837 its_wait_vpt_parse_complete();
3840 static void its_vpe_deschedule(struct its_vpe *vpe)
3842 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3845 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3847 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3848 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3851 static void its_vpe_invall(struct its_vpe *vpe)
3853 struct its_node *its;
3855 list_for_each_entry(its, &its_nodes, entry) {
3859 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3863 * Sending a VINVALL to a single ITS is enough, as all
3864 * we need is to reach the redistributors.
3866 its_send_vinvall(its, vpe);
3871 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3873 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3874 struct its_cmd_info *info = vcpu_info;
3876 switch (info->cmd_type) {
3878 its_vpe_schedule(vpe);
3881 case DESCHEDULE_VPE:
3882 its_vpe_deschedule(vpe);
3886 its_vpe_invall(vpe);
3894 static void its_vpe_send_cmd(struct its_vpe *vpe,
3895 void (*cmd)(struct its_device *, u32))
3897 unsigned long flags;
3899 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3901 its_vpe_db_proxy_map_locked(vpe);
3902 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3904 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3907 static void its_vpe_send_inv(struct irq_data *d)
3909 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3911 if (gic_rdists->has_direct_lpi) {
3912 void __iomem *rdbase;
3914 /* Target the redistributor this VPE is currently known on */
3915 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3916 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3917 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
3918 wait_for_syncr(rdbase);
3919 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3921 its_vpe_send_cmd(vpe, its_send_inv);
3925 static void its_vpe_mask_irq(struct irq_data *d)
3928 * We need to unmask the LPI, which is described by the parent
3929 * irq_data. Instead of calling into the parent (which won't
3930 * exactly do the right thing, let's simply use the
3931 * parent_data pointer. Yes, I'm naughty.
3933 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3934 its_vpe_send_inv(d);
3937 static void its_vpe_unmask_irq(struct irq_data *d)
3939 /* Same hack as above... */
3940 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3941 its_vpe_send_inv(d);
3944 static int its_vpe_set_irqchip_state(struct irq_data *d,
3945 enum irqchip_irq_state which,
3948 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3950 if (which != IRQCHIP_STATE_PENDING)
3953 if (gic_rdists->has_direct_lpi) {
3954 void __iomem *rdbase;
3956 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3958 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3960 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3961 wait_for_syncr(rdbase);
3965 its_vpe_send_cmd(vpe, its_send_int);
3967 its_vpe_send_cmd(vpe, its_send_clear);
3973 static int its_vpe_retrigger(struct irq_data *d)
3975 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
3978 static struct irq_chip its_vpe_irq_chip = {
3979 .name = "GICv4-vpe",
3980 .irq_mask = its_vpe_mask_irq,
3981 .irq_unmask = its_vpe_unmask_irq,
3982 .irq_eoi = irq_chip_eoi_parent,
3983 .irq_set_affinity = its_vpe_set_affinity,
3984 .irq_retrigger = its_vpe_retrigger,
3985 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
3986 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
3989 static struct its_node *find_4_1_its(void)
3991 static struct its_node *its = NULL;
3994 list_for_each_entry(its, &its_nodes, entry) {
4006 static void its_vpe_4_1_send_inv(struct irq_data *d)
4008 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4009 struct its_node *its;
4012 * GICv4.1 wants doorbells to be invalidated using the
4013 * INVDB command in order to be broadcast to all RDs. Send
4014 * it to the first valid ITS, and let the HW do its magic.
4016 its = find_4_1_its();
4018 its_send_invdb(its, vpe);
4021 static void its_vpe_4_1_mask_irq(struct irq_data *d)
4023 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4024 its_vpe_4_1_send_inv(d);
4027 static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4029 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4030 its_vpe_4_1_send_inv(d);
4033 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4034 struct its_cmd_info *info)
4036 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4039 /* Schedule the VPE */
4040 val |= GICR_VPENDBASER_Valid;
4041 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4042 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4043 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4045 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4047 its_wait_vpt_parse_complete();
4050 static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4051 struct its_cmd_info *info)
4053 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4058 * vPE is going to block: make the vPE non-resident with
4059 * PendingLast clear and DB set. The GIC guarantees that if
4060 * we read-back PendingLast clear, then a doorbell will be
4061 * delivered when an interrupt comes.
4063 val = its_clear_vpend_valid(vlpi_base,
4064 GICR_VPENDBASER_PendingLast,
4065 GICR_VPENDBASER_4_1_DB);
4066 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4069 * We're not blocking, so just make the vPE non-resident
4070 * with PendingLast set, indicating that we'll be back.
4072 val = its_clear_vpend_valid(vlpi_base,
4074 GICR_VPENDBASER_PendingLast);
4075 vpe->pending_last = true;
4079 static void its_vpe_4_1_invall(struct its_vpe *vpe)
4081 void __iomem *rdbase;
4084 val = GICR_INVALLR_V;
4085 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4087 /* Target the redistributor this vPE is currently known on */
4088 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
4089 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
4090 gic_write_lpir(val, rdbase + GICR_INVALLR);
4092 wait_for_syncr(rdbase);
4093 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
4096 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4098 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4099 struct its_cmd_info *info = vcpu_info;
4101 switch (info->cmd_type) {
4103 its_vpe_4_1_schedule(vpe, info);
4106 case DESCHEDULE_VPE:
4107 its_vpe_4_1_deschedule(vpe, info);
4111 its_vpe_4_1_invall(vpe);
4119 static struct irq_chip its_vpe_4_1_irq_chip = {
4120 .name = "GICv4.1-vpe",
4121 .irq_mask = its_vpe_4_1_mask_irq,
4122 .irq_unmask = its_vpe_4_1_unmask_irq,
4123 .irq_eoi = irq_chip_eoi_parent,
4124 .irq_set_affinity = its_vpe_set_affinity,
4125 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity,
4128 static void its_configure_sgi(struct irq_data *d, bool clear)
4130 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4131 struct its_cmd_desc desc;
4133 desc.its_vsgi_cmd.vpe = vpe;
4134 desc.its_vsgi_cmd.sgi = d->hwirq;
4135 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4136 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4137 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4138 desc.its_vsgi_cmd.clear = clear;
4141 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4142 * destination VPE is mapped there. Since we map them eagerly at
4143 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4145 its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4148 static void its_sgi_mask_irq(struct irq_data *d)
4150 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4152 vpe->sgi_config[d->hwirq].enabled = false;
4153 its_configure_sgi(d, false);
4156 static void its_sgi_unmask_irq(struct irq_data *d)
4158 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4160 vpe->sgi_config[d->hwirq].enabled = true;
4161 its_configure_sgi(d, false);
4164 static int its_sgi_set_affinity(struct irq_data *d,
4165 const struct cpumask *mask_val,
4169 * There is no notion of affinity for virtual SGIs, at least
4170 * not on the host (since they can only be targetting a vPE).
4171 * Tell the kernel we've done whatever it asked for.
4173 irq_data_update_effective_affinity(d, mask_val);
4174 return IRQ_SET_MASK_OK;
4177 static int its_sgi_set_irqchip_state(struct irq_data *d,
4178 enum irqchip_irq_state which,
4181 if (which != IRQCHIP_STATE_PENDING)
4185 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4186 struct its_node *its = find_4_1_its();
4189 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4190 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4191 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4193 its_configure_sgi(d, true);
4199 static int its_sgi_get_irqchip_state(struct irq_data *d,
4200 enum irqchip_irq_state which, bool *val)
4202 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4204 unsigned long flags;
4205 u32 count = 1000000; /* 1s! */
4209 if (which != IRQCHIP_STATE_PENDING)
4213 * Locking galore! We can race against two different events:
4215 * - Concurent vPE affinity change: we must make sure it cannot
4216 * happen, or we'll talk to the wrong redistributor. This is
4217 * identical to what happens with vLPIs.
4219 * - Concurrent VSGIPENDR access: As it involves accessing two
4220 * MMIO registers, this must be made atomic one way or another.
4222 cpu = vpe_to_cpuid_lock(vpe, &flags);
4223 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4224 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4225 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4227 status = readl_relaxed(base + GICR_VSGIPENDR);
4228 if (!(status & GICR_VSGIPENDR_BUSY))
4233 pr_err_ratelimited("Unable to get SGI status\n");
4241 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4242 vpe_to_cpuid_unlock(vpe, flags);
4247 *val = !!(status & (1 << d->hwirq));
4252 static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4254 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4255 struct its_cmd_info *info = vcpu_info;
4257 switch (info->cmd_type) {
4258 case PROP_UPDATE_VSGI:
4259 vpe->sgi_config[d->hwirq].priority = info->priority;
4260 vpe->sgi_config[d->hwirq].group = info->group;
4261 its_configure_sgi(d, false);
4269 static struct irq_chip its_sgi_irq_chip = {
4270 .name = "GICv4.1-sgi",
4271 .irq_mask = its_sgi_mask_irq,
4272 .irq_unmask = its_sgi_unmask_irq,
4273 .irq_set_affinity = its_sgi_set_affinity,
4274 .irq_set_irqchip_state = its_sgi_set_irqchip_state,
4275 .irq_get_irqchip_state = its_sgi_get_irqchip_state,
4276 .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity,
4279 static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4280 unsigned int virq, unsigned int nr_irqs,
4283 struct its_vpe *vpe = args;
4286 /* Yes, we do want 16 SGIs */
4287 WARN_ON(nr_irqs != 16);
4289 for (i = 0; i < 16; i++) {
4290 vpe->sgi_config[i].priority = 0;
4291 vpe->sgi_config[i].enabled = false;
4292 vpe->sgi_config[i].group = false;
4294 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4295 &its_sgi_irq_chip, vpe);
4296 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4302 static void its_sgi_irq_domain_free(struct irq_domain *domain,
4304 unsigned int nr_irqs)
4309 static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4310 struct irq_data *d, bool reserve)
4312 /* Write out the initial SGI configuration */
4313 its_configure_sgi(d, false);
4317 static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4320 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4323 * The VSGI command is awkward:
4325 * - To change the configuration, CLEAR must be set to false,
4326 * leaving the pending bit unchanged.
4327 * - To clear the pending bit, CLEAR must be set to true, leaving
4328 * the configuration unchanged.
4330 * You just can't do both at once, hence the two commands below.
4332 vpe->sgi_config[d->hwirq].enabled = false;
4333 its_configure_sgi(d, false);
4334 its_configure_sgi(d, true);
4337 static const struct irq_domain_ops its_sgi_domain_ops = {
4338 .alloc = its_sgi_irq_domain_alloc,
4339 .free = its_sgi_irq_domain_free,
4340 .activate = its_sgi_irq_domain_activate,
4341 .deactivate = its_sgi_irq_domain_deactivate,
4344 static int its_vpe_id_alloc(void)
4346 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
4349 static void its_vpe_id_free(u16 id)
4351 ida_simple_remove(&its_vpeid_ida, id);
4354 static int its_vpe_init(struct its_vpe *vpe)
4356 struct page *vpt_page;
4359 /* Allocate vpe_id */
4360 vpe_id = its_vpe_id_alloc();
4365 vpt_page = its_allocate_pending_table(GFP_KERNEL);
4367 its_vpe_id_free(vpe_id);
4371 if (!its_alloc_vpe_table(vpe_id)) {
4372 its_vpe_id_free(vpe_id);
4373 its_free_pending_table(vpt_page);
4377 raw_spin_lock_init(&vpe->vpe_lock);
4378 vpe->vpe_id = vpe_id;
4379 vpe->vpt_page = vpt_page;
4380 if (gic_rdists->has_rvpeid)
4381 atomic_set(&vpe->vmapp_count, 0);
4383 vpe->vpe_proxy_event = -1;
4388 static void its_vpe_teardown(struct its_vpe *vpe)
4390 its_vpe_db_proxy_unmap(vpe);
4391 its_vpe_id_free(vpe->vpe_id);
4392 its_free_pending_table(vpe->vpt_page);
4395 static void its_vpe_irq_domain_free(struct irq_domain *domain,
4397 unsigned int nr_irqs)
4399 struct its_vm *vm = domain->host_data;
4402 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4404 for (i = 0; i < nr_irqs; i++) {
4405 struct irq_data *data = irq_domain_get_irq_data(domain,
4407 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4409 BUG_ON(vm != vpe->its_vm);
4411 clear_bit(data->hwirq, vm->db_bitmap);
4412 its_vpe_teardown(vpe);
4413 irq_domain_reset_irq_data(data);
4416 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4417 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4418 its_free_prop_table(vm->vprop_page);
4422 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4423 unsigned int nr_irqs, void *args)
4425 struct irq_chip *irqchip = &its_vpe_irq_chip;
4426 struct its_vm *vm = args;
4427 unsigned long *bitmap;
4428 struct page *vprop_page;
4429 int base, nr_ids, i, err = 0;
4433 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4437 if (nr_ids < nr_irqs) {
4438 its_lpi_free(bitmap, base, nr_ids);
4442 vprop_page = its_allocate_prop_table(GFP_KERNEL);
4444 its_lpi_free(bitmap, base, nr_ids);
4448 vm->db_bitmap = bitmap;
4449 vm->db_lpi_base = base;
4450 vm->nr_db_lpis = nr_ids;
4451 vm->vprop_page = vprop_page;
4453 if (gic_rdists->has_rvpeid)
4454 irqchip = &its_vpe_4_1_irq_chip;
4456 for (i = 0; i < nr_irqs; i++) {
4457 vm->vpes[i]->vpe_db_lpi = base + i;
4458 err = its_vpe_init(vm->vpes[i]);
4461 err = its_irq_gic_domain_alloc(domain, virq + i,
4462 vm->vpes[i]->vpe_db_lpi);
4465 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4466 irqchip, vm->vpes[i]);
4472 its_vpe_irq_domain_free(domain, virq, i - 1);
4474 its_lpi_free(bitmap, base, nr_ids);
4475 its_free_prop_table(vprop_page);
4481 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4482 struct irq_data *d, bool reserve)
4484 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4485 struct its_node *its;
4488 * If we use the list map, we issue VMAPP on demand... Unless
4489 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4490 * so that VSGIs can work.
4492 if (!gic_requires_eager_mapping())
4495 /* Map the VPE to the first possible CPU */
4496 vpe->col_idx = cpumask_first(cpu_online_mask);
4498 list_for_each_entry(its, &its_nodes, entry) {
4502 its_send_vmapp(its, vpe, true);
4503 its_send_vinvall(its, vpe);
4506 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4511 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4514 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4515 struct its_node *its;
4518 * If we use the list map on GICv4.0, we unmap the VPE once no
4519 * VLPIs are associated with the VM.
4521 if (!gic_requires_eager_mapping())
4524 list_for_each_entry(its, &its_nodes, entry) {
4528 its_send_vmapp(its, vpe, false);
4532 static const struct irq_domain_ops its_vpe_domain_ops = {
4533 .alloc = its_vpe_irq_domain_alloc,
4534 .free = its_vpe_irq_domain_free,
4535 .activate = its_vpe_irq_domain_activate,
4536 .deactivate = its_vpe_irq_domain_deactivate,
4539 static int its_force_quiescent(void __iomem *base)
4541 u32 count = 1000000; /* 1s */
4544 val = readl_relaxed(base + GITS_CTLR);
4546 * GIC architecture specification requires the ITS to be both
4547 * disabled and quiescent for writes to GITS_BASER<n> or
4548 * GITS_CBASER to not have UNPREDICTABLE results.
4550 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4553 /* Disable the generation of all interrupts to this ITS */
4554 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4555 writel_relaxed(val, base + GITS_CTLR);
4557 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4559 val = readl_relaxed(base + GITS_CTLR);
4560 if (val & GITS_CTLR_QUIESCENT)
4572 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4574 struct its_node *its = data;
4576 /* erratum 22375: only alloc 8MB table size (20 bits) */
4577 its->typer &= ~GITS_TYPER_DEVBITS;
4578 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4579 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4584 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4586 struct its_node *its = data;
4588 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4593 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4595 struct its_node *its = data;
4597 /* On QDF2400, the size of the ITE is 16Bytes */
4598 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4599 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4604 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4606 struct its_node *its = its_dev->its;
4609 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4610 * which maps 32-bit writes targeted at a separate window of
4611 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4612 * with device ID taken from bits [device_id_bits + 1:2] of
4613 * the window offset.
4615 return its->pre_its_base + (its_dev->device_id << 2);
4618 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4620 struct its_node *its = data;
4621 u32 pre_its_window[2];
4624 if (!fwnode_property_read_u32_array(its->fwnode_handle,
4625 "socionext,synquacer-pre-its",
4627 ARRAY_SIZE(pre_its_window))) {
4629 its->pre_its_base = pre_its_window[0];
4630 its->get_msi_base = its_irq_get_msi_base_pre_its;
4632 ids = ilog2(pre_its_window[1]) - 2;
4633 if (device_ids(its) > ids) {
4634 its->typer &= ~GITS_TYPER_DEVBITS;
4635 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4638 /* the pre-ITS breaks isolation, so disable MSI remapping */
4639 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
4645 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4647 struct its_node *its = data;
4650 * Hip07 insists on using the wrong address for the VLPI
4651 * page. Trick it into doing the right thing...
4653 its->vlpi_redist_offset = SZ_128K;
4657 static const struct gic_quirk its_quirks[] = {
4658 #ifdef CONFIG_CAVIUM_ERRATUM_22375
4660 .desc = "ITS: Cavium errata 22375, 24313",
4661 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4663 .init = its_enable_quirk_cavium_22375,
4666 #ifdef CONFIG_CAVIUM_ERRATUM_23144
4668 .desc = "ITS: Cavium erratum 23144",
4669 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4671 .init = its_enable_quirk_cavium_23144,
4674 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4676 .desc = "ITS: QDF2400 erratum 0065",
4677 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4679 .init = its_enable_quirk_qdf2400_e0065,
4682 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4685 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4686 * implementation, but with a 'pre-ITS' added that requires
4687 * special handling in software.
4689 .desc = "ITS: Socionext Synquacer pre-ITS",
4692 .init = its_enable_quirk_socionext_synquacer,
4695 #ifdef CONFIG_HISILICON_ERRATUM_161600802
4697 .desc = "ITS: Hip07 erratum 161600802",
4700 .init = its_enable_quirk_hip07_161600802,
4707 static void its_enable_quirks(struct its_node *its)
4709 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4711 gic_enable_quirks(iidr, its_quirks, its);
4714 static int its_save_disable(void)
4716 struct its_node *its;
4719 raw_spin_lock(&its_lock);
4720 list_for_each_entry(its, &its_nodes, entry) {
4723 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4727 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4728 err = its_force_quiescent(base);
4730 pr_err("ITS@%pa: failed to quiesce: %d\n",
4731 &its->phys_base, err);
4732 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4736 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4741 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4744 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4748 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4751 raw_spin_unlock(&its_lock);
4756 static void its_restore_enable(void)
4758 struct its_node *its;
4761 raw_spin_lock(&its_lock);
4762 list_for_each_entry(its, &its_nodes, entry) {
4766 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4772 * Make sure that the ITS is disabled. If it fails to quiesce,
4773 * don't restore it since writing to CBASER or BASER<n>
4774 * registers is undefined according to the GIC v3 ITS
4777 ret = its_force_quiescent(base);
4779 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4780 &its->phys_base, ret);
4784 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4787 * Writing CBASER resets CREADR to 0, so make CWRITER and
4788 * cmd_write line up with it.
4790 its->cmd_write = its->cmd_base;
4791 gits_write_cwriter(0, base + GITS_CWRITER);
4793 /* Restore GITS_BASER from the value cache. */
4794 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4795 struct its_baser *baser = &its->tables[i];
4797 if (!(baser->val & GITS_BASER_VALID))
4800 its_write_baser(its, baser, baser->val);
4802 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4805 * Reinit the collection if it's stored in the ITS. This is
4806 * indicated by the col_id being less than the HCC field.
4807 * CID < HCC as specified in the GIC v3 Documentation.
4809 if (its->collections[smp_processor_id()].col_id <
4810 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4811 its_cpu_init_collection(its);
4813 raw_spin_unlock(&its_lock);
4816 static struct syscore_ops its_syscore_ops = {
4817 .suspend = its_save_disable,
4818 .resume = its_restore_enable,
4821 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
4823 struct irq_domain *inner_domain;
4824 struct msi_domain_info *info;
4826 info = kzalloc(sizeof(*info), GFP_KERNEL);
4830 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
4831 if (!inner_domain) {
4836 inner_domain->parent = its_parent;
4837 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4838 inner_domain->flags |= its->msi_domain_flags;
4839 info->ops = &its_msi_domain_ops;
4841 inner_domain->host_data = info;
4846 static int its_init_vpe_domain(void)
4848 struct its_node *its;
4852 if (gic_rdists->has_direct_lpi) {
4853 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
4857 /* Any ITS will do, even if not v4 */
4858 its = list_first_entry(&its_nodes, struct its_node, entry);
4860 entries = roundup_pow_of_two(nr_cpu_ids);
4861 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
4863 if (!vpe_proxy.vpes) {
4864 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
4868 /* Use the last possible DevID */
4869 devid = GENMASK(device_ids(its) - 1, 0);
4870 vpe_proxy.dev = its_create_device(its, devid, entries, false);
4871 if (!vpe_proxy.dev) {
4872 kfree(vpe_proxy.vpes);
4873 pr_err("ITS: Can't allocate GICv4 proxy device\n");
4877 BUG_ON(entries > vpe_proxy.dev->nr_ites);
4879 raw_spin_lock_init(&vpe_proxy.lock);
4880 vpe_proxy.next_victim = 0;
4881 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
4882 devid, vpe_proxy.dev->nr_ites);
4887 static int __init its_compute_its_list_map(struct resource *res,
4888 void __iomem *its_base)
4894 * This is assumed to be done early enough that we're
4895 * guaranteed to be single-threaded, hence no
4896 * locking. Should this change, we should address
4899 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
4900 if (its_number >= GICv4_ITS_LIST_MAX) {
4901 pr_err("ITS@%pa: No ITSList entry available!\n",
4906 ctlr = readl_relaxed(its_base + GITS_CTLR);
4907 ctlr &= ~GITS_CTLR_ITS_NUMBER;
4908 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
4909 writel_relaxed(ctlr, its_base + GITS_CTLR);
4910 ctlr = readl_relaxed(its_base + GITS_CTLR);
4911 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
4912 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
4913 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
4916 if (test_and_set_bit(its_number, &its_list_map)) {
4917 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
4918 &res->start, its_number);
4925 static int __init its_probe_one(struct resource *res,
4926 struct fwnode_handle *handle, int numa_node)
4928 struct its_node *its;
4929 void __iomem *its_base;
4931 u64 baser, tmp, typer;
4935 its_base = ioremap(res->start, SZ_64K);
4937 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4941 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4942 if (val != 0x30 && val != 0x40) {
4943 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4948 err = its_force_quiescent(its_base);
4950 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4954 pr_info("ITS %pR\n", res);
4956 its = kzalloc(sizeof(*its), GFP_KERNEL);
4962 raw_spin_lock_init(&its->lock);
4963 mutex_init(&its->dev_alloc_lock);
4964 INIT_LIST_HEAD(&its->entry);
4965 INIT_LIST_HEAD(&its->its_device_list);
4966 typer = gic_read_typer(its_base + GITS_TYPER);
4968 its->base = its_base;
4969 its->phys_base = res->start;
4971 if (!(typer & GITS_TYPER_VMOVP)) {
4972 err = its_compute_its_list_map(res, its_base);
4978 pr_info("ITS@%pa: Using ITS number %d\n",
4981 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
4985 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer);
4987 its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K);
4988 if (!its->sgir_base) {
4993 its->mpidr = readl_relaxed(its_base + GITS_MPIDR);
4995 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
4996 &res->start, its->mpidr, svpet);
5000 its->numa_node = numa_node;
5002 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5003 get_order(ITS_CMD_QUEUE_SZ));
5006 goto out_unmap_sgir;
5008 its->cmd_base = (void *)page_address(page);
5009 its->cmd_write = its->cmd_base;
5010 its->fwnode_handle = handle;
5011 its->get_msi_base = its_irq_get_msi_base;
5012 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
5014 its_enable_quirks(its);
5016 err = its_alloc_tables(its);
5020 err = its_alloc_collections(its);
5022 goto out_free_tables;
5024 baser = (virt_to_phys(its->cmd_base) |
5025 GITS_CBASER_RaWaWb |
5026 GITS_CBASER_InnerShareable |
5027 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5030 gits_write_cbaser(baser, its->base + GITS_CBASER);
5031 tmp = gits_read_cbaser(its->base + GITS_CBASER);
5033 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5034 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5036 * The HW reports non-shareable, we must
5037 * remove the cacheability attributes as
5040 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5041 GITS_CBASER_CACHEABILITY_MASK);
5042 baser |= GITS_CBASER_nC;
5043 gits_write_cbaser(baser, its->base + GITS_CBASER);
5045 pr_info("ITS: using cache flushing for cmd queue\n");
5046 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5049 gits_write_cwriter(0, its->base + GITS_CWRITER);
5050 ctlr = readl_relaxed(its->base + GITS_CTLR);
5051 ctlr |= GITS_CTLR_ENABLE;
5053 ctlr |= GITS_CTLR_ImDe;
5054 writel_relaxed(ctlr, its->base + GITS_CTLR);
5056 if (GITS_TYPER_HCC(typer))
5057 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
5059 err = its_init_domain(handle, its);
5061 goto out_free_tables;
5063 raw_spin_lock(&its_lock);
5064 list_add(&its->entry, &its_nodes);
5065 raw_spin_unlock(&its_lock);
5070 its_free_tables(its);
5072 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5075 iounmap(its->sgir_base);
5080 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
5084 static bool gic_rdists_supports_plpis(void)
5086 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5089 static int redist_disable_lpis(void)
5091 void __iomem *rbase = gic_data_rdist_rd_base();
5092 u64 timeout = USEC_PER_SEC;
5095 if (!gic_rdists_supports_plpis()) {
5096 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5100 val = readl_relaxed(rbase + GICR_CTLR);
5101 if (!(val & GICR_CTLR_ENABLE_LPIS))
5105 * If coming via a CPU hotplug event, we don't need to disable
5106 * LPIs before trying to re-enable them. They are already
5107 * configured and all is well in the world.
5109 * If running with preallocated tables, there is nothing to do.
5111 if (gic_data_rdist()->lpi_enabled ||
5112 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5116 * From that point on, we only try to do some damage control.
5118 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5119 smp_processor_id());
5120 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5123 val &= ~GICR_CTLR_ENABLE_LPIS;
5124 writel_relaxed(val, rbase + GICR_CTLR);
5126 /* Make sure any change to GICR_CTLR is observable by the GIC */
5130 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5131 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5132 * Error out if we time out waiting for RWP to clear.
5134 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5136 pr_err("CPU%d: Timeout while disabling LPIs\n",
5137 smp_processor_id());
5145 * After it has been written to 1, it is IMPLEMENTATION
5146 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5147 * cleared to 0. Error out if clearing the bit failed.
5149 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5150 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5157 int its_cpu_init(void)
5159 if (!list_empty(&its_nodes)) {
5162 ret = redist_disable_lpis();
5166 its_cpu_init_lpis();
5167 its_cpu_init_collections();
5173 static const struct of_device_id its_device_id[] = {
5174 { .compatible = "arm,gic-v3-its", },
5178 static int __init its_of_probe(struct device_node *node)
5180 struct device_node *np;
5181 struct resource res;
5183 for (np = of_find_matching_node(node, its_device_id); np;
5184 np = of_find_matching_node(np, its_device_id)) {
5185 if (!of_device_is_available(np))
5187 if (!of_property_read_bool(np, "msi-controller")) {
5188 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5193 if (of_address_to_resource(np, 0, &res)) {
5194 pr_warn("%pOF: no regs?\n", np);
5198 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
5205 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5207 #ifdef CONFIG_ACPI_NUMA
5208 struct its_srat_map {
5215 static struct its_srat_map *its_srat_maps __initdata;
5216 static int its_in_srat __initdata;
5218 static int __init acpi_get_its_numa_node(u32 its_id)
5222 for (i = 0; i < its_in_srat; i++) {
5223 if (its_id == its_srat_maps[i].its_id)
5224 return its_srat_maps[i].numa_node;
5226 return NUMA_NO_NODE;
5229 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5230 const unsigned long end)
5235 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5236 const unsigned long end)
5239 struct acpi_srat_gic_its_affinity *its_affinity;
5241 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5245 if (its_affinity->header.length < sizeof(*its_affinity)) {
5246 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5247 its_affinity->header.length);
5251 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
5253 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5254 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5258 its_srat_maps[its_in_srat].numa_node = node;
5259 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5261 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5262 its_affinity->proximity_domain, its_affinity->its_id, node);
5267 static void __init acpi_table_parse_srat_its(void)
5271 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5272 sizeof(struct acpi_table_srat),
5273 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5274 gic_acpi_match_srat_its, 0);
5278 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5280 if (!its_srat_maps) {
5281 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
5285 acpi_table_parse_entries(ACPI_SIG_SRAT,
5286 sizeof(struct acpi_table_srat),
5287 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5288 gic_acpi_parse_srat_its, 0);
5291 /* free the its_srat_maps after ITS probing */
5292 static void __init acpi_its_srat_maps_free(void)
5294 kfree(its_srat_maps);
5297 static void __init acpi_table_parse_srat_its(void) { }
5298 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5299 static void __init acpi_its_srat_maps_free(void) { }
5302 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5303 const unsigned long end)
5305 struct acpi_madt_generic_translator *its_entry;
5306 struct fwnode_handle *dom_handle;
5307 struct resource res;
5310 its_entry = (struct acpi_madt_generic_translator *)header;
5311 memset(&res, 0, sizeof(res));
5312 res.start = its_entry->base_address;
5313 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5314 res.flags = IORESOURCE_MEM;
5316 dom_handle = irq_domain_alloc_fwnode(&res.start);
5318 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5323 err = iort_register_domain_token(its_entry->translation_id, res.start,
5326 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5327 &res.start, its_entry->translation_id);
5331 err = its_probe_one(&res, dom_handle,
5332 acpi_get_its_numa_node(its_entry->translation_id));
5336 iort_deregister_domain_token(its_entry->translation_id);
5338 irq_domain_free_fwnode(dom_handle);
5342 static void __init its_acpi_probe(void)
5344 acpi_table_parse_srat_its();
5345 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5346 gic_acpi_parse_madt_its, 0);
5347 acpi_its_srat_maps_free();
5350 static void __init its_acpi_probe(void) { }
5353 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5354 struct irq_domain *parent_domain)
5356 struct device_node *of_node;
5357 struct its_node *its;
5358 bool has_v4 = false;
5359 bool has_v4_1 = false;
5362 gic_rdists = rdists;
5364 its_parent = parent_domain;
5365 of_node = to_of_node(handle);
5367 its_of_probe(of_node);
5371 if (list_empty(&its_nodes)) {
5372 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5376 err = allocate_lpi_tables();
5380 list_for_each_entry(its, &its_nodes, entry) {
5381 has_v4 |= is_v4(its);
5382 has_v4_1 |= is_v4_1(its);
5385 /* Don't bother with inconsistent systems */
5386 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5387 rdists->has_rvpeid = false;
5389 if (has_v4 & rdists->has_vlpis) {
5390 const struct irq_domain_ops *sgi_ops;
5393 sgi_ops = &its_sgi_domain_ops;
5397 if (its_init_vpe_domain() ||
5398 its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5399 rdists->has_vlpis = false;
5400 pr_err("ITS: Disabling GICv4 support\n");
5404 register_syscore_ops(&its_syscore_ops);