1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitfield.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/dma-iommu.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/irqdomain.h>
18 #include <linux/list.h>
19 #include <linux/log2.h>
20 #include <linux/memblock.h>
22 #include <linux/msi.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/of_platform.h>
28 #include <linux/percpu.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
32 #include <linux/irqchip.h>
33 #include <linux/irqchip/arm-gic-v3.h>
34 #include <linux/irqchip/arm-gic-v4.h>
36 #include <asm/cputype.h>
37 #include <asm/exception.h>
39 #include "irq-gic-common.h"
41 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
42 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
44 #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
46 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
47 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
49 static u32 lpi_id_bits;
52 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
53 * deal with (one configuration byte per interrupt). PENDBASE has to
54 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
56 #define LPI_NRBITS lpi_id_bits
57 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
58 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
60 #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
63 * Collection structure - just an ID, and a redistributor address to
64 * ping. We use one per CPU as a bag of interrupts assigned to this
67 struct its_collection {
73 * The ITS_BASER structure - contains memory information, cached
74 * value of BASER register configuration and ITS page size.
86 * The ITS structure - contains most of the infrastructure, with the
87 * top-level MSI domain, the command queue, the collections, and the
88 * list of devices writing to it.
90 * dev_alloc_lock has to be taken for device allocations, while the
91 * spinlock must be taken to parse data structures such as the device
96 struct mutex dev_alloc_lock;
97 struct list_head entry;
99 phys_addr_t phys_base;
100 struct its_cmd_block *cmd_base;
101 struct its_cmd_block *cmd_write;
102 struct its_baser tables[GITS_BASER_NR_REGS];
103 struct its_collection *collections;
104 struct fwnode_handle *fwnode_handle;
105 u64 (*get_msi_base)(struct its_device *its_dev);
109 struct list_head its_device_list;
111 unsigned long list_nr;
113 unsigned int msi_domain_flags;
114 u32 pre_its_base; /* for Socionext Synquacer */
115 int vlpi_redist_offset;
118 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
119 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
121 #define ITS_ITT_ALIGN SZ_256
123 /* The maximum number of VPEID bits supported by VLPI commands */
124 #define ITS_MAX_VPEID_BITS (16)
125 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
127 /* Convert page order to size in bytes */
128 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
130 struct event_lpi_map {
131 unsigned long *lpi_map;
133 irq_hw_number_t lpi_base;
135 struct mutex vlpi_lock;
137 struct its_vlpi_map *vlpi_maps;
142 * The ITS view of a device - belongs to an ITS, owns an interrupt
143 * translation table, and a list of interrupts. If it some of its
144 * LPIs are injected into a guest (GICv4), the event_map.vm field
145 * indicates which one.
148 struct list_head entry;
149 struct its_node *its;
150 struct event_lpi_map event_map;
159 struct its_device *dev;
160 struct its_vpe **vpes;
164 static LIST_HEAD(its_nodes);
165 static DEFINE_RAW_SPINLOCK(its_lock);
166 static struct rdists *gic_rdists;
167 static struct irq_domain *its_parent;
169 static unsigned long its_list_map;
170 static u16 vmovp_seq_num;
171 static DEFINE_RAW_SPINLOCK(vmovp_lock);
173 static DEFINE_IDA(its_vpeid_ida);
175 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
176 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
177 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
178 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
180 static u16 get_its_list(struct its_vm *vm)
182 struct its_node *its;
183 unsigned long its_list = 0;
185 list_for_each_entry(its, &its_nodes, entry) {
189 if (vm->vlpi_count[its->list_nr])
190 __set_bit(its->list_nr, &its_list);
193 return (u16)its_list;
196 static inline u32 its_get_event_id(struct irq_data *d)
198 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
199 return d->hwirq - its_dev->event_map.lpi_base;
202 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
205 struct its_node *its = its_dev->its;
207 return its->collections + its_dev->event_map.col_map[event];
210 static struct its_collection *irq_to_col(struct irq_data *d)
212 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
214 return dev_event_to_col(its_dev, its_get_event_id(d));
217 static struct its_collection *valid_col(struct its_collection *col)
219 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
225 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
227 if (valid_col(its->collections + vpe->col_idx))
234 * ITS command descriptors - parameters to be encoded in a command
237 struct its_cmd_desc {
240 struct its_device *dev;
245 struct its_device *dev;
250 struct its_device *dev;
255 struct its_device *dev;
260 struct its_collection *col;
265 struct its_device *dev;
271 struct its_device *dev;
272 struct its_collection *col;
277 struct its_device *dev;
282 struct its_collection *col;
291 struct its_collection *col;
297 struct its_device *dev;
305 struct its_device *dev;
312 struct its_collection *col;
320 * The ITS command block, which is what the ITS actually parses.
322 struct its_cmd_block {
325 __le64 raw_cmd_le[4];
329 #define ITS_CMD_QUEUE_SZ SZ_64K
330 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
332 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
333 struct its_cmd_block *,
334 struct its_cmd_desc *);
336 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
337 struct its_cmd_block *,
338 struct its_cmd_desc *);
340 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
342 u64 mask = GENMASK_ULL(h, l);
344 *raw_cmd |= (val << l) & mask;
347 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
349 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
352 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
354 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
357 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
359 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
362 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
364 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
367 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
369 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
372 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
374 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
377 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
379 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
382 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
384 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
387 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
389 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
392 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
394 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
397 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
399 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
402 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
404 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
407 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
409 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
412 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
414 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
417 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
419 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
422 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
424 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
427 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
429 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
432 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
434 /* Let's fixup BE commands */
435 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
436 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
437 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
438 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
441 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
442 struct its_cmd_block *cmd,
443 struct its_cmd_desc *desc)
445 unsigned long itt_addr;
446 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
448 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
449 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
451 its_encode_cmd(cmd, GITS_CMD_MAPD);
452 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
453 its_encode_size(cmd, size - 1);
454 its_encode_itt(cmd, itt_addr);
455 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
462 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
463 struct its_cmd_block *cmd,
464 struct its_cmd_desc *desc)
466 its_encode_cmd(cmd, GITS_CMD_MAPC);
467 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
468 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
469 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
473 return desc->its_mapc_cmd.col;
476 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
477 struct its_cmd_block *cmd,
478 struct its_cmd_desc *desc)
480 struct its_collection *col;
482 col = dev_event_to_col(desc->its_mapti_cmd.dev,
483 desc->its_mapti_cmd.event_id);
485 its_encode_cmd(cmd, GITS_CMD_MAPTI);
486 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
487 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
488 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
489 its_encode_collection(cmd, col->col_id);
493 return valid_col(col);
496 static struct its_collection *its_build_movi_cmd(struct its_node *its,
497 struct its_cmd_block *cmd,
498 struct its_cmd_desc *desc)
500 struct its_collection *col;
502 col = dev_event_to_col(desc->its_movi_cmd.dev,
503 desc->its_movi_cmd.event_id);
505 its_encode_cmd(cmd, GITS_CMD_MOVI);
506 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
507 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
508 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
512 return valid_col(col);
515 static struct its_collection *its_build_discard_cmd(struct its_node *its,
516 struct its_cmd_block *cmd,
517 struct its_cmd_desc *desc)
519 struct its_collection *col;
521 col = dev_event_to_col(desc->its_discard_cmd.dev,
522 desc->its_discard_cmd.event_id);
524 its_encode_cmd(cmd, GITS_CMD_DISCARD);
525 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
526 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
530 return valid_col(col);
533 static struct its_collection *its_build_inv_cmd(struct its_node *its,
534 struct its_cmd_block *cmd,
535 struct its_cmd_desc *desc)
537 struct its_collection *col;
539 col = dev_event_to_col(desc->its_inv_cmd.dev,
540 desc->its_inv_cmd.event_id);
542 its_encode_cmd(cmd, GITS_CMD_INV);
543 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
544 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
548 return valid_col(col);
551 static struct its_collection *its_build_int_cmd(struct its_node *its,
552 struct its_cmd_block *cmd,
553 struct its_cmd_desc *desc)
555 struct its_collection *col;
557 col = dev_event_to_col(desc->its_int_cmd.dev,
558 desc->its_int_cmd.event_id);
560 its_encode_cmd(cmd, GITS_CMD_INT);
561 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
562 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
566 return valid_col(col);
569 static struct its_collection *its_build_clear_cmd(struct its_node *its,
570 struct its_cmd_block *cmd,
571 struct its_cmd_desc *desc)
573 struct its_collection *col;
575 col = dev_event_to_col(desc->its_clear_cmd.dev,
576 desc->its_clear_cmd.event_id);
578 its_encode_cmd(cmd, GITS_CMD_CLEAR);
579 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
580 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
584 return valid_col(col);
587 static struct its_collection *its_build_invall_cmd(struct its_node *its,
588 struct its_cmd_block *cmd,
589 struct its_cmd_desc *desc)
591 its_encode_cmd(cmd, GITS_CMD_INVALL);
592 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
599 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
600 struct its_cmd_block *cmd,
601 struct its_cmd_desc *desc)
603 its_encode_cmd(cmd, GITS_CMD_VINVALL);
604 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
608 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
611 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
612 struct its_cmd_block *cmd,
613 struct its_cmd_desc *desc)
615 unsigned long vpt_addr;
618 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
619 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
621 its_encode_cmd(cmd, GITS_CMD_VMAPP);
622 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
623 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
624 its_encode_target(cmd, target);
625 its_encode_vpt_addr(cmd, vpt_addr);
626 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
630 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
633 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
634 struct its_cmd_block *cmd,
635 struct its_cmd_desc *desc)
639 if (desc->its_vmapti_cmd.db_enabled)
640 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
644 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
645 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
646 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
647 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
648 its_encode_db_phys_id(cmd, db);
649 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
653 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
656 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
657 struct its_cmd_block *cmd,
658 struct its_cmd_desc *desc)
662 if (desc->its_vmovi_cmd.db_enabled)
663 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
667 its_encode_cmd(cmd, GITS_CMD_VMOVI);
668 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
669 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
670 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
671 its_encode_db_phys_id(cmd, db);
672 its_encode_db_valid(cmd, true);
676 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
679 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
680 struct its_cmd_block *cmd,
681 struct its_cmd_desc *desc)
685 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
686 its_encode_cmd(cmd, GITS_CMD_VMOVP);
687 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
688 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
689 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
690 its_encode_target(cmd, target);
694 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
697 static u64 its_cmd_ptr_to_offset(struct its_node *its,
698 struct its_cmd_block *ptr)
700 return (ptr - its->cmd_base) * sizeof(*ptr);
703 static int its_queue_full(struct its_node *its)
708 widx = its->cmd_write - its->cmd_base;
709 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
711 /* This is incredibly unlikely to happen, unless the ITS locks up. */
712 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
718 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
720 struct its_cmd_block *cmd;
721 u32 count = 1000000; /* 1s! */
723 while (its_queue_full(its)) {
726 pr_err_ratelimited("ITS queue not draining\n");
733 cmd = its->cmd_write++;
735 /* Handle queue wrapping */
736 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
737 its->cmd_write = its->cmd_base;
748 static struct its_cmd_block *its_post_commands(struct its_node *its)
750 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
752 writel_relaxed(wr, its->base + GITS_CWRITER);
754 return its->cmd_write;
757 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
760 * Make sure the commands written to memory are observable by
763 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
764 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
769 static int its_wait_for_range_completion(struct its_node *its,
771 struct its_cmd_block *to)
773 u64 rd_idx, to_idx, linear_idx;
774 u32 count = 1000000; /* 1s! */
776 /* Linearize to_idx if the command set has wrapped around */
777 to_idx = its_cmd_ptr_to_offset(its, to);
778 if (to_idx < prev_idx)
779 to_idx += ITS_CMD_QUEUE_SZ;
781 linear_idx = prev_idx;
786 rd_idx = readl_relaxed(its->base + GITS_CREADR);
789 * Compute the read pointer progress, taking the
790 * potential wrap-around into account.
792 delta = rd_idx - prev_idx;
793 if (rd_idx < prev_idx)
794 delta += ITS_CMD_QUEUE_SZ;
797 if (linear_idx >= to_idx)
802 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
814 /* Warning, macro hell follows */
815 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
816 void name(struct its_node *its, \
818 struct its_cmd_desc *desc) \
820 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
821 synctype *sync_obj; \
822 unsigned long flags; \
825 raw_spin_lock_irqsave(&its->lock, flags); \
827 cmd = its_allocate_entry(its); \
828 if (!cmd) { /* We're soooooo screewed... */ \
829 raw_spin_unlock_irqrestore(&its->lock, flags); \
832 sync_obj = builder(its, cmd, desc); \
833 its_flush_cmd(its, cmd); \
836 sync_cmd = its_allocate_entry(its); \
840 buildfn(its, sync_cmd, sync_obj); \
841 its_flush_cmd(its, sync_cmd); \
845 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
846 next_cmd = its_post_commands(its); \
847 raw_spin_unlock_irqrestore(&its->lock, flags); \
849 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
850 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
853 static void its_build_sync_cmd(struct its_node *its,
854 struct its_cmd_block *sync_cmd,
855 struct its_collection *sync_col)
857 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
858 its_encode_target(sync_cmd, sync_col->target_address);
860 its_fixup_cmd(sync_cmd);
863 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
864 struct its_collection, its_build_sync_cmd)
866 static void its_build_vsync_cmd(struct its_node *its,
867 struct its_cmd_block *sync_cmd,
868 struct its_vpe *sync_vpe)
870 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
871 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
873 its_fixup_cmd(sync_cmd);
876 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
877 struct its_vpe, its_build_vsync_cmd)
879 static void its_send_int(struct its_device *dev, u32 event_id)
881 struct its_cmd_desc desc;
883 desc.its_int_cmd.dev = dev;
884 desc.its_int_cmd.event_id = event_id;
886 its_send_single_command(dev->its, its_build_int_cmd, &desc);
889 static void its_send_clear(struct its_device *dev, u32 event_id)
891 struct its_cmd_desc desc;
893 desc.its_clear_cmd.dev = dev;
894 desc.its_clear_cmd.event_id = event_id;
896 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
899 static void its_send_inv(struct its_device *dev, u32 event_id)
901 struct its_cmd_desc desc;
903 desc.its_inv_cmd.dev = dev;
904 desc.its_inv_cmd.event_id = event_id;
906 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
909 static void its_send_mapd(struct its_device *dev, int valid)
911 struct its_cmd_desc desc;
913 desc.its_mapd_cmd.dev = dev;
914 desc.its_mapd_cmd.valid = !!valid;
916 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
919 static void its_send_mapc(struct its_node *its, struct its_collection *col,
922 struct its_cmd_desc desc;
924 desc.its_mapc_cmd.col = col;
925 desc.its_mapc_cmd.valid = !!valid;
927 its_send_single_command(its, its_build_mapc_cmd, &desc);
930 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
932 struct its_cmd_desc desc;
934 desc.its_mapti_cmd.dev = dev;
935 desc.its_mapti_cmd.phys_id = irq_id;
936 desc.its_mapti_cmd.event_id = id;
938 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
941 static void its_send_movi(struct its_device *dev,
942 struct its_collection *col, u32 id)
944 struct its_cmd_desc desc;
946 desc.its_movi_cmd.dev = dev;
947 desc.its_movi_cmd.col = col;
948 desc.its_movi_cmd.event_id = id;
950 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
953 static void its_send_discard(struct its_device *dev, u32 id)
955 struct its_cmd_desc desc;
957 desc.its_discard_cmd.dev = dev;
958 desc.its_discard_cmd.event_id = id;
960 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
963 static void its_send_invall(struct its_node *its, struct its_collection *col)
965 struct its_cmd_desc desc;
967 desc.its_invall_cmd.col = col;
969 its_send_single_command(its, its_build_invall_cmd, &desc);
972 static void its_send_vmapti(struct its_device *dev, u32 id)
974 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
975 struct its_cmd_desc desc;
977 desc.its_vmapti_cmd.vpe = map->vpe;
978 desc.its_vmapti_cmd.dev = dev;
979 desc.its_vmapti_cmd.virt_id = map->vintid;
980 desc.its_vmapti_cmd.event_id = id;
981 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
983 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
986 static void its_send_vmovi(struct its_device *dev, u32 id)
988 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
989 struct its_cmd_desc desc;
991 desc.its_vmovi_cmd.vpe = map->vpe;
992 desc.its_vmovi_cmd.dev = dev;
993 desc.its_vmovi_cmd.event_id = id;
994 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
996 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
999 static void its_send_vmapp(struct its_node *its,
1000 struct its_vpe *vpe, bool valid)
1002 struct its_cmd_desc desc;
1004 desc.its_vmapp_cmd.vpe = vpe;
1005 desc.its_vmapp_cmd.valid = valid;
1006 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1008 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1011 static void its_send_vmovp(struct its_vpe *vpe)
1013 struct its_cmd_desc desc = {};
1014 struct its_node *its;
1015 unsigned long flags;
1016 int col_id = vpe->col_idx;
1018 desc.its_vmovp_cmd.vpe = vpe;
1020 if (!its_list_map) {
1021 its = list_first_entry(&its_nodes, struct its_node, entry);
1022 desc.its_vmovp_cmd.col = &its->collections[col_id];
1023 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1028 * Yet another marvel of the architecture. If using the
1029 * its_list "feature", we need to make sure that all ITSs
1030 * receive all VMOVP commands in the same order. The only way
1031 * to guarantee this is to make vmovp a serialization point.
1035 raw_spin_lock_irqsave(&vmovp_lock, flags);
1037 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1038 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1041 list_for_each_entry(its, &its_nodes, entry) {
1045 if (!vpe->its_vm->vlpi_count[its->list_nr])
1048 desc.its_vmovp_cmd.col = &its->collections[col_id];
1049 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1052 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1055 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1057 struct its_cmd_desc desc;
1059 desc.its_vinvall_cmd.vpe = vpe;
1060 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1064 * irqchip functions - assumes MSI, mostly.
1067 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1069 irq_hw_number_t hwirq;
1073 if (irqd_is_forwarded_to_vcpu(d)) {
1074 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1075 u32 event = its_get_event_id(d);
1076 struct its_vlpi_map *map;
1078 va = page_address(its_dev->event_map.vm->vprop_page);
1079 map = &its_dev->event_map.vlpi_maps[event];
1080 hwirq = map->vintid;
1082 /* Remember the updated property */
1083 map->properties &= ~clr;
1084 map->properties |= set | LPI_PROP_GROUP1;
1086 va = gic_rdists->prop_table_va;
1090 cfg = va + hwirq - 8192;
1092 *cfg |= set | LPI_PROP_GROUP1;
1095 * Make the above write visible to the redistributors.
1096 * And yes, we're flushing exactly: One. Single. Byte.
1099 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1100 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1105 static void wait_for_syncr(void __iomem *rdbase)
1107 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
1111 static void direct_lpi_inv(struct irq_data *d)
1113 struct its_collection *col;
1114 void __iomem *rdbase;
1116 /* Target the redistributor this LPI is currently routed to */
1117 col = irq_to_col(d);
1118 rdbase = per_cpu_ptr(gic_rdists->rdist, col->col_id)->rd_base;
1119 gic_write_lpir(d->hwirq, rdbase + GICR_INVLPIR);
1121 wait_for_syncr(rdbase);
1124 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1126 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1128 lpi_write_config(d, clr, set);
1129 if (gic_rdists->has_direct_lpi && !irqd_is_forwarded_to_vcpu(d))
1132 its_send_inv(its_dev, its_get_event_id(d));
1135 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1137 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1138 u32 event = its_get_event_id(d);
1140 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1143 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1146 * More fun with the architecture:
1148 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1149 * value or to 1023, depending on the enable bit. But that
1150 * would be issueing a mapping for an /existing/ DevID+EventID
1151 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1152 * to the /same/ vPE, using this opportunity to adjust the
1153 * doorbell. Mouahahahaha. We loves it, Precious.
1155 its_send_vmovi(its_dev, event);
1158 static void its_mask_irq(struct irq_data *d)
1160 if (irqd_is_forwarded_to_vcpu(d))
1161 its_vlpi_set_doorbell(d, false);
1163 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1166 static void its_unmask_irq(struct irq_data *d)
1168 if (irqd_is_forwarded_to_vcpu(d))
1169 its_vlpi_set_doorbell(d, true);
1171 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1174 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1178 const struct cpumask *cpu_mask = cpu_online_mask;
1179 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1180 struct its_collection *target_col;
1181 u32 id = its_get_event_id(d);
1183 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1184 if (irqd_is_forwarded_to_vcpu(d))
1187 /* lpi cannot be routed to a redistributor that is on a foreign node */
1188 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1189 if (its_dev->its->numa_node >= 0) {
1190 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1191 if (!cpumask_intersects(mask_val, cpu_mask))
1196 cpu = cpumask_any_and(mask_val, cpu_mask);
1198 if (cpu >= nr_cpu_ids)
1201 /* don't set the affinity when the target cpu is same as current one */
1202 if (cpu != its_dev->event_map.col_map[id]) {
1203 target_col = &its_dev->its->collections[cpu];
1204 its_send_movi(its_dev, target_col, id);
1205 its_dev->event_map.col_map[id] = cpu;
1206 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1209 return IRQ_SET_MASK_OK_DONE;
1212 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1214 struct its_node *its = its_dev->its;
1216 return its->phys_base + GITS_TRANSLATER;
1219 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1221 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1222 struct its_node *its;
1226 addr = its->get_msi_base(its_dev);
1228 msg->address_lo = lower_32_bits(addr);
1229 msg->address_hi = upper_32_bits(addr);
1230 msg->data = its_get_event_id(d);
1232 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1235 static int its_irq_set_irqchip_state(struct irq_data *d,
1236 enum irqchip_irq_state which,
1239 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1240 u32 event = its_get_event_id(d);
1242 if (which != IRQCHIP_STATE_PENDING)
1246 its_send_int(its_dev, event);
1248 its_send_clear(its_dev, event);
1253 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1255 unsigned long flags;
1257 /* Not using the ITS list? Everything is always mapped. */
1261 raw_spin_lock_irqsave(&vmovp_lock, flags);
1264 * If the VM wasn't mapped yet, iterate over the vpes and get
1267 vm->vlpi_count[its->list_nr]++;
1269 if (vm->vlpi_count[its->list_nr] == 1) {
1272 for (i = 0; i < vm->nr_vpes; i++) {
1273 struct its_vpe *vpe = vm->vpes[i];
1274 struct irq_data *d = irq_get_irq_data(vpe->irq);
1276 /* Map the VPE to the first possible CPU */
1277 vpe->col_idx = cpumask_first(cpu_online_mask);
1278 its_send_vmapp(its, vpe, true);
1279 its_send_vinvall(its, vpe);
1280 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1284 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1287 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1289 unsigned long flags;
1291 /* Not using the ITS list? Everything is always mapped. */
1295 raw_spin_lock_irqsave(&vmovp_lock, flags);
1297 if (!--vm->vlpi_count[its->list_nr]) {
1300 for (i = 0; i < vm->nr_vpes; i++)
1301 its_send_vmapp(its, vm->vpes[i], false);
1304 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1307 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1309 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1310 u32 event = its_get_event_id(d);
1316 mutex_lock(&its_dev->event_map.vlpi_lock);
1318 if (!its_dev->event_map.vm) {
1319 struct its_vlpi_map *maps;
1321 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1328 its_dev->event_map.vm = info->map->vm;
1329 its_dev->event_map.vlpi_maps = maps;
1330 } else if (its_dev->event_map.vm != info->map->vm) {
1335 /* Get our private copy of the mapping information */
1336 its_dev->event_map.vlpi_maps[event] = *info->map;
1338 if (irqd_is_forwarded_to_vcpu(d)) {
1339 /* Already mapped, move it around */
1340 its_send_vmovi(its_dev, event);
1342 /* Ensure all the VPEs are mapped on this ITS */
1343 its_map_vm(its_dev->its, info->map->vm);
1346 * Flag the interrupt as forwarded so that we can
1347 * start poking the virtual property table.
1349 irqd_set_forwarded_to_vcpu(d);
1351 /* Write out the property to the prop table */
1352 lpi_write_config(d, 0xff, info->map->properties);
1354 /* Drop the physical mapping */
1355 its_send_discard(its_dev, event);
1357 /* and install the virtual one */
1358 its_send_vmapti(its_dev, event);
1360 /* Increment the number of VLPIs */
1361 its_dev->event_map.nr_vlpis++;
1365 mutex_unlock(&its_dev->event_map.vlpi_lock);
1369 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1371 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1372 u32 event = its_get_event_id(d);
1375 mutex_lock(&its_dev->event_map.vlpi_lock);
1377 if (!its_dev->event_map.vm ||
1378 !its_dev->event_map.vlpi_maps[event].vm) {
1383 /* Copy our mapping information to the incoming request */
1384 *info->map = its_dev->event_map.vlpi_maps[event];
1387 mutex_unlock(&its_dev->event_map.vlpi_lock);
1391 static int its_vlpi_unmap(struct irq_data *d)
1393 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1394 u32 event = its_get_event_id(d);
1397 mutex_lock(&its_dev->event_map.vlpi_lock);
1399 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1404 /* Drop the virtual mapping */
1405 its_send_discard(its_dev, event);
1407 /* and restore the physical one */
1408 irqd_clr_forwarded_to_vcpu(d);
1409 its_send_mapti(its_dev, d->hwirq, event);
1410 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1414 /* Potentially unmap the VM from this ITS */
1415 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1418 * Drop the refcount and make the device available again if
1419 * this was the last VLPI.
1421 if (!--its_dev->event_map.nr_vlpis) {
1422 its_dev->event_map.vm = NULL;
1423 kfree(its_dev->event_map.vlpi_maps);
1427 mutex_unlock(&its_dev->event_map.vlpi_lock);
1431 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1433 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1435 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1438 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1439 lpi_update_config(d, 0xff, info->config);
1441 lpi_write_config(d, 0xff, info->config);
1442 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1447 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1449 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1450 struct its_cmd_info *info = vcpu_info;
1453 if (!is_v4(its_dev->its))
1456 /* Unmap request? */
1458 return its_vlpi_unmap(d);
1460 switch (info->cmd_type) {
1462 return its_vlpi_map(d, info);
1465 return its_vlpi_get(d, info);
1467 case PROP_UPDATE_VLPI:
1468 case PROP_UPDATE_AND_INV_VLPI:
1469 return its_vlpi_prop_update(d, info);
1476 static struct irq_chip its_irq_chip = {
1478 .irq_mask = its_mask_irq,
1479 .irq_unmask = its_unmask_irq,
1480 .irq_eoi = irq_chip_eoi_parent,
1481 .irq_set_affinity = its_set_affinity,
1482 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1483 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1484 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1489 * How we allocate LPIs:
1491 * lpi_range_list contains ranges of LPIs that are to available to
1492 * allocate from. To allocate LPIs, just pick the first range that
1493 * fits the required allocation, and reduce it by the required
1494 * amount. Once empty, remove the range from the list.
1496 * To free a range of LPIs, add a free range to the list, sort it and
1497 * merge the result if the new range happens to be adjacent to an
1498 * already free block.
1500 * The consequence of the above is that allocation is cost is low, but
1501 * freeing is expensive. We assumes that freeing rarely occurs.
1503 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1505 static DEFINE_MUTEX(lpi_range_lock);
1506 static LIST_HEAD(lpi_range_list);
1509 struct list_head entry;
1514 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1516 struct lpi_range *range;
1518 range = kmalloc(sizeof(*range), GFP_KERNEL);
1520 range->base_id = base;
1527 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1529 struct lpi_range *range, *tmp;
1532 mutex_lock(&lpi_range_lock);
1534 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1535 if (range->span >= nr_lpis) {
1536 *base = range->base_id;
1537 range->base_id += nr_lpis;
1538 range->span -= nr_lpis;
1540 if (range->span == 0) {
1541 list_del(&range->entry);
1550 mutex_unlock(&lpi_range_lock);
1552 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1556 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1558 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1560 if (a->base_id + a->span != b->base_id)
1562 b->base_id = a->base_id;
1564 list_del(&a->entry);
1568 static int free_lpi_range(u32 base, u32 nr_lpis)
1570 struct lpi_range *new, *old;
1572 new = mk_lpi_range(base, nr_lpis);
1576 mutex_lock(&lpi_range_lock);
1578 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1579 if (old->base_id < base)
1583 * old is the last element with ->base_id smaller than base,
1584 * so new goes right after it. If there are no elements with
1585 * ->base_id smaller than base, &old->entry ends up pointing
1586 * at the head of the list, and inserting new it the start of
1587 * the list is the right thing to do in that case as well.
1589 list_add(&new->entry, &old->entry);
1591 * Now check if we can merge with the preceding and/or
1594 merge_lpi_ranges(old, new);
1595 merge_lpi_ranges(new, list_next_entry(new, entry));
1597 mutex_unlock(&lpi_range_lock);
1601 static int __init its_lpi_init(u32 id_bits)
1603 u32 lpis = (1UL << id_bits) - 8192;
1607 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1609 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1611 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1616 * Initializing the allocator is just the same as freeing the
1617 * full range of LPIs.
1619 err = free_lpi_range(8192, lpis);
1620 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1624 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1626 unsigned long *bitmap = NULL;
1630 err = alloc_lpi_range(nr_irqs, base);
1635 } while (nr_irqs > 0);
1643 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1651 *base = *nr_ids = 0;
1656 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1658 WARN_ON(free_lpi_range(base, nr_ids));
1662 static void gic_reset_prop_table(void *va)
1664 /* Priority 0xa0, Group-1, disabled */
1665 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1667 /* Make sure the GIC will observe the written configuration */
1668 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1671 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1673 struct page *prop_page;
1675 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1679 gic_reset_prop_table(page_address(prop_page));
1684 static void its_free_prop_table(struct page *prop_page)
1686 free_pages((unsigned long)page_address(prop_page),
1687 get_order(LPI_PROPBASE_SZ));
1690 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1692 phys_addr_t start, end, addr_end;
1696 * We don't bother checking for a kdump kernel as by
1697 * construction, the LPI tables are out of this kernel's
1700 if (is_kdump_kernel())
1703 addr_end = addr + size - 1;
1705 for_each_reserved_mem_region(i, &start, &end) {
1706 if (addr >= start && addr_end <= end)
1710 /* Not found, not a good sign... */
1711 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1713 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1717 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1719 if (efi_enabled(EFI_CONFIG_TABLES))
1720 return efi_mem_reserve_persistent(addr, size);
1725 static int __init its_setup_lpi_prop_table(void)
1727 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1730 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1731 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1733 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1734 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1737 gic_reset_prop_table(gic_rdists->prop_table_va);
1741 lpi_id_bits = min_t(u32,
1742 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1743 ITS_MAX_LPI_NRBITS);
1744 page = its_allocate_prop_table(GFP_NOWAIT);
1746 pr_err("Failed to allocate PROPBASE\n");
1750 gic_rdists->prop_table_pa = page_to_phys(page);
1751 gic_rdists->prop_table_va = page_address(page);
1752 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
1756 pr_info("GICv3: using LPI property table @%pa\n",
1757 &gic_rdists->prop_table_pa);
1759 return its_lpi_init(lpi_id_bits);
1762 static const char *its_base_type_string[] = {
1763 [GITS_BASER_TYPE_DEVICE] = "Devices",
1764 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1765 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1766 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1767 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1768 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1769 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1772 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1774 u32 idx = baser - its->tables;
1776 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1779 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1782 u32 idx = baser - its->tables;
1784 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1785 baser->val = its_read_baser(its, baser);
1788 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1789 u64 cache, u64 shr, u32 psz, u32 order,
1792 u64 val = its_read_baser(its, baser);
1793 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1794 u64 type = GITS_BASER_TYPE(val);
1795 u64 baser_phys, tmp;
1801 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1802 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1803 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1804 &its->phys_base, its_base_type_string[type],
1805 alloc_pages, GITS_BASER_PAGES_MAX);
1806 alloc_pages = GITS_BASER_PAGES_MAX;
1807 order = get_order(GITS_BASER_PAGES_MAX * psz);
1810 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
1814 base = (void *)page_address(page);
1815 baser_phys = virt_to_phys(base);
1817 /* Check if the physical address of the memory is above 48bits */
1818 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1820 /* 52bit PA is supported only when PageSize=64K */
1821 if (psz != SZ_64K) {
1822 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1823 free_pages((unsigned long)base, order);
1827 /* Convert 52bit PA to 48bit field */
1828 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1833 (type << GITS_BASER_TYPE_SHIFT) |
1834 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1835 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1840 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1844 val |= GITS_BASER_PAGE_SIZE_4K;
1847 val |= GITS_BASER_PAGE_SIZE_16K;
1850 val |= GITS_BASER_PAGE_SIZE_64K;
1854 its_write_baser(its, baser, val);
1857 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1859 * Shareability didn't stick. Just use
1860 * whatever the read reported, which is likely
1861 * to be the only thing this redistributor
1862 * supports. If that's zero, make it
1863 * non-cacheable as well.
1865 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1867 cache = GITS_BASER_nC;
1868 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1873 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1875 * Page size didn't stick. Let's try a smaller
1876 * size and retry. If we reach 4K, then
1877 * something is horribly wrong...
1879 free_pages((unsigned long)base, order);
1885 goto retry_alloc_baser;
1888 goto retry_alloc_baser;
1893 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1894 &its->phys_base, its_base_type_string[type],
1896 free_pages((unsigned long)base, order);
1900 baser->order = order;
1903 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1905 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1906 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1907 its_base_type_string[type],
1908 (unsigned long)virt_to_phys(base),
1909 indirect ? "indirect" : "flat", (int)esz,
1910 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1915 static bool its_parse_indirect_baser(struct its_node *its,
1916 struct its_baser *baser,
1917 u32 psz, u32 *order, u32 ids)
1919 u64 tmp = its_read_baser(its, baser);
1920 u64 type = GITS_BASER_TYPE(tmp);
1921 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1922 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1923 u32 new_order = *order;
1924 bool indirect = false;
1926 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1927 if ((esz << ids) > (psz * 2)) {
1929 * Find out whether hw supports a single or two-level table by
1930 * table by reading bit at offset '62' after writing '1' to it.
1932 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1933 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1937 * The size of the lvl2 table is equal to ITS page size
1938 * which is 'psz'. For computing lvl1 table size,
1939 * subtract ID bits that sparse lvl2 table from 'ids'
1940 * which is reported by ITS hardware times lvl1 table
1943 ids -= ilog2(psz / (int)esz);
1944 esz = GITS_LVL1_ENTRY_SIZE;
1949 * Allocate as many entries as required to fit the
1950 * range of device IDs that the ITS can grok... The ID
1951 * space being incredibly sparse, this results in a
1952 * massive waste of memory if two-level device table
1953 * feature is not supported by hardware.
1955 new_order = max_t(u32, get_order(esz << ids), new_order);
1956 if (new_order >= MAX_ORDER) {
1957 new_order = MAX_ORDER - 1;
1958 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1959 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
1960 &its->phys_base, its_base_type_string[type],
1961 device_ids(its), ids);
1969 static void its_free_tables(struct its_node *its)
1973 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1974 if (its->tables[i].base) {
1975 free_pages((unsigned long)its->tables[i].base,
1976 its->tables[i].order);
1977 its->tables[i].base = NULL;
1982 static int its_alloc_tables(struct its_node *its)
1984 u64 shr = GITS_BASER_InnerShareable;
1985 u64 cache = GITS_BASER_RaWaWb;
1989 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1990 /* erratum 24313: ignore memory access type */
1991 cache = GITS_BASER_nCnB;
1993 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1994 struct its_baser *baser = its->tables + i;
1995 u64 val = its_read_baser(its, baser);
1996 u64 type = GITS_BASER_TYPE(val);
1997 u32 order = get_order(psz);
1998 bool indirect = false;
2001 case GITS_BASER_TYPE_NONE:
2004 case GITS_BASER_TYPE_DEVICE:
2005 indirect = its_parse_indirect_baser(its, baser,
2010 case GITS_BASER_TYPE_VCPU:
2011 indirect = its_parse_indirect_baser(its, baser,
2013 ITS_MAX_VPEID_BITS);
2017 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
2019 its_free_tables(its);
2023 /* Update settings which will be used for next BASERn */
2025 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2026 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2032 static int its_alloc_collections(struct its_node *its)
2036 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2038 if (!its->collections)
2041 for (i = 0; i < nr_cpu_ids; i++)
2042 its->collections[i].target_address = ~0ULL;
2047 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2049 struct page *pend_page;
2051 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2052 get_order(LPI_PENDBASE_SZ));
2056 /* Make sure the GIC will observe the zero-ed page */
2057 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2062 static void its_free_pending_table(struct page *pt)
2064 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2068 * Booting with kdump and LPIs enabled is generally fine. Any other
2069 * case is wrong in the absence of firmware/EFI support.
2071 static bool enabled_lpis_allowed(void)
2076 /* Check whether the property table is in a reserved region */
2077 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2078 addr = val & GENMASK_ULL(51, 12);
2080 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2083 static int __init allocate_lpi_tables(void)
2089 * If LPIs are enabled while we run this from the boot CPU,
2090 * flag the RD tables as pre-allocated if the stars do align.
2092 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2093 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2094 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2095 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2096 pr_info("GICv3: Using preallocated redistributor tables\n");
2099 err = its_setup_lpi_prop_table();
2104 * We allocate all the pending tables anyway, as we may have a
2105 * mix of RDs that have had LPIs enabled, and some that
2106 * don't. We'll free the unused ones as each CPU comes online.
2108 for_each_possible_cpu(cpu) {
2109 struct page *pend_page;
2111 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2113 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2117 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2123 static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
2125 u32 count = 1000000; /* 1s! */
2129 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2130 val &= ~GICR_VPENDBASER_Valid;
2131 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2134 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2135 clean = !(val & GICR_VPENDBASER_Dirty);
2141 } while (!clean && count);
2146 static void its_cpu_init_lpis(void)
2148 void __iomem *rbase = gic_data_rdist_rd_base();
2149 struct page *pend_page;
2153 if (gic_data_rdist()->lpi_enabled)
2156 val = readl_relaxed(rbase + GICR_CTLR);
2157 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2158 (val & GICR_CTLR_ENABLE_LPIS)) {
2160 * Check that we get the same property table on all
2161 * RDs. If we don't, this is hopeless.
2163 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2164 paddr &= GENMASK_ULL(51, 12);
2165 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2166 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2168 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2169 paddr &= GENMASK_ULL(51, 16);
2171 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2172 its_free_pending_table(gic_data_rdist()->pend_page);
2173 gic_data_rdist()->pend_page = NULL;
2178 pend_page = gic_data_rdist()->pend_page;
2179 paddr = page_to_phys(pend_page);
2180 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2183 val = (gic_rdists->prop_table_pa |
2184 GICR_PROPBASER_InnerShareable |
2185 GICR_PROPBASER_RaWaWb |
2186 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2188 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2189 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2191 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2192 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2194 * The HW reports non-shareable, we must
2195 * remove the cacheability attributes as
2198 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2199 GICR_PROPBASER_CACHEABILITY_MASK);
2200 val |= GICR_PROPBASER_nC;
2201 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2203 pr_info_once("GIC: using cache flushing for LPI property table\n");
2204 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2208 val = (page_to_phys(pend_page) |
2209 GICR_PENDBASER_InnerShareable |
2210 GICR_PENDBASER_RaWaWb);
2212 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2213 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2215 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2217 * The HW reports non-shareable, we must remove the
2218 * cacheability attributes as well.
2220 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2221 GICR_PENDBASER_CACHEABILITY_MASK);
2222 val |= GICR_PENDBASER_nC;
2223 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2227 val = readl_relaxed(rbase + GICR_CTLR);
2228 val |= GICR_CTLR_ENABLE_LPIS;
2229 writel_relaxed(val, rbase + GICR_CTLR);
2231 if (gic_rdists->has_vlpis) {
2232 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2235 * It's possible for CPU to receive VLPIs before it is
2236 * sheduled as a vPE, especially for the first CPU, and the
2237 * VLPI with INTID larger than 2^(IDbits+1) will be considered
2238 * as out of range and dropped by GIC.
2239 * So we initialize IDbits to known value to avoid VLPI drop.
2241 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2242 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2243 smp_processor_id(), val);
2244 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2247 * Also clear Valid bit of GICR_VPENDBASER, in case some
2248 * ancient programming gets left in and has possibility of
2249 * corrupting memory.
2251 val = its_clear_vpend_valid(vlpi_base);
2252 WARN_ON(val & GICR_VPENDBASER_Dirty);
2255 /* Make sure the GIC has seen the above */
2258 gic_data_rdist()->lpi_enabled = true;
2259 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2261 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2265 static void its_cpu_init_collection(struct its_node *its)
2267 int cpu = smp_processor_id();
2270 /* avoid cross node collections and its mapping */
2271 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2272 struct device_node *cpu_node;
2274 cpu_node = of_get_cpu_node(cpu, NULL);
2275 if (its->numa_node != NUMA_NO_NODE &&
2276 its->numa_node != of_node_to_nid(cpu_node))
2281 * We now have to bind each collection to its target
2284 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2286 * This ITS wants the physical address of the
2289 target = gic_data_rdist()->phys_base;
2291 /* This ITS wants a linear CPU number. */
2292 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2293 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2296 /* Perform collection mapping */
2297 its->collections[cpu].target_address = target;
2298 its->collections[cpu].col_id = cpu;
2300 its_send_mapc(its, &its->collections[cpu], 1);
2301 its_send_invall(its, &its->collections[cpu]);
2304 static void its_cpu_init_collections(void)
2306 struct its_node *its;
2308 raw_spin_lock(&its_lock);
2310 list_for_each_entry(its, &its_nodes, entry)
2311 its_cpu_init_collection(its);
2313 raw_spin_unlock(&its_lock);
2316 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2318 struct its_device *its_dev = NULL, *tmp;
2319 unsigned long flags;
2321 raw_spin_lock_irqsave(&its->lock, flags);
2323 list_for_each_entry(tmp, &its->its_device_list, entry) {
2324 if (tmp->device_id == dev_id) {
2330 raw_spin_unlock_irqrestore(&its->lock, flags);
2335 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2339 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2340 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2341 return &its->tables[i];
2347 static bool its_alloc_table_entry(struct its_node *its,
2348 struct its_baser *baser, u32 id)
2354 /* Don't allow device id that exceeds single, flat table limit */
2355 esz = GITS_BASER_ENTRY_SIZE(baser->val);
2356 if (!(baser->val & GITS_BASER_INDIRECT))
2357 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2359 /* Compute 1st level table index & check if that exceeds table limit */
2360 idx = id >> ilog2(baser->psz / esz);
2361 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2364 table = baser->base;
2366 /* Allocate memory for 2nd level table */
2368 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2369 get_order(baser->psz));
2373 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2374 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2375 gic_flush_dcache_to_poc(page_address(page), baser->psz);
2377 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2379 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2380 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2381 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2383 /* Ensure updated table contents are visible to ITS hardware */
2390 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2392 struct its_baser *baser;
2394 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2396 /* Don't allow device id that exceeds ITS hardware limit */
2398 return (ilog2(dev_id) < device_ids(its));
2400 return its_alloc_table_entry(its, baser, dev_id);
2403 static bool its_alloc_vpe_table(u32 vpe_id)
2405 struct its_node *its;
2408 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2409 * could try and only do it on ITSs corresponding to devices
2410 * that have interrupts targeted at this VPE, but the
2411 * complexity becomes crazy (and you have tons of memory
2414 list_for_each_entry(its, &its_nodes, entry) {
2415 struct its_baser *baser;
2420 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2424 if (!its_alloc_table_entry(its, baser, vpe_id))
2431 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2432 int nvecs, bool alloc_lpis)
2434 struct its_device *dev;
2435 unsigned long *lpi_map = NULL;
2436 unsigned long flags;
2437 u16 *col_map = NULL;
2444 if (!its_alloc_device_table(its, dev_id))
2447 if (WARN_ON(!is_power_of_2(nvecs)))
2448 nvecs = roundup_pow_of_two(nvecs);
2450 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2452 * Even if the device wants a single LPI, the ITT must be
2453 * sized as a power of two (and you need at least one bit...).
2455 nr_ites = max(2, nvecs);
2456 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
2457 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2458 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
2460 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2462 col_map = kcalloc(nr_lpis, sizeof(*col_map),
2465 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2470 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2478 gic_flush_dcache_to_poc(itt, sz);
2482 dev->nr_ites = nr_ites;
2483 dev->event_map.lpi_map = lpi_map;
2484 dev->event_map.col_map = col_map;
2485 dev->event_map.lpi_base = lpi_base;
2486 dev->event_map.nr_lpis = nr_lpis;
2487 mutex_init(&dev->event_map.vlpi_lock);
2488 dev->device_id = dev_id;
2489 INIT_LIST_HEAD(&dev->entry);
2491 raw_spin_lock_irqsave(&its->lock, flags);
2492 list_add(&dev->entry, &its->its_device_list);
2493 raw_spin_unlock_irqrestore(&its->lock, flags);
2495 /* Map device to its ITT */
2496 its_send_mapd(dev, 1);
2501 static void its_free_device(struct its_device *its_dev)
2503 unsigned long flags;
2505 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2506 list_del(&its_dev->entry);
2507 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2508 kfree(its_dev->event_map.col_map);
2509 kfree(its_dev->itt);
2513 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2517 /* Find a free LPI region in lpi_map and allocate them. */
2518 idx = bitmap_find_free_region(dev->event_map.lpi_map,
2519 dev->event_map.nr_lpis,
2520 get_count_order(nvecs));
2524 *hwirq = dev->event_map.lpi_base + idx;
2529 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2530 int nvec, msi_alloc_info_t *info)
2532 struct its_node *its;
2533 struct its_device *its_dev;
2534 struct msi_domain_info *msi_info;
2539 * We ignore "dev" entirely, and rely on the dev_id that has
2540 * been passed via the scratchpad. This limits this domain's
2541 * usefulness to upper layers that definitely know that they
2542 * are built on top of the ITS.
2544 dev_id = info->scratchpad[0].ul;
2546 msi_info = msi_get_domain_info(domain);
2547 its = msi_info->data;
2549 if (!gic_rdists->has_direct_lpi &&
2551 vpe_proxy.dev->its == its &&
2552 dev_id == vpe_proxy.dev->device_id) {
2553 /* Bad luck. Get yourself a better implementation */
2554 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2559 mutex_lock(&its->dev_alloc_lock);
2560 its_dev = its_find_device(its, dev_id);
2563 * We already have seen this ID, probably through
2564 * another alias (PCI bridge of some sort). No need to
2565 * create the device.
2567 its_dev->shared = true;
2568 pr_debug("Reusing ITT for devID %x\n", dev_id);
2572 its_dev = its_create_device(its, dev_id, nvec, true);
2578 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2580 mutex_unlock(&its->dev_alloc_lock);
2581 info->scratchpad[0].ptr = its_dev;
2585 static struct msi_domain_ops its_msi_domain_ops = {
2586 .msi_prepare = its_msi_prepare,
2589 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2591 irq_hw_number_t hwirq)
2593 struct irq_fwspec fwspec;
2595 if (irq_domain_get_of_node(domain->parent)) {
2596 fwspec.fwnode = domain->parent->fwnode;
2597 fwspec.param_count = 3;
2598 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2599 fwspec.param[1] = hwirq;
2600 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2601 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2602 fwspec.fwnode = domain->parent->fwnode;
2603 fwspec.param_count = 2;
2604 fwspec.param[0] = hwirq;
2605 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2610 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2613 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2614 unsigned int nr_irqs, void *args)
2616 msi_alloc_info_t *info = args;
2617 struct its_device *its_dev = info->scratchpad[0].ptr;
2618 struct its_node *its = its_dev->its;
2619 irq_hw_number_t hwirq;
2623 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2627 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
2631 for (i = 0; i < nr_irqs; i++) {
2632 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2636 irq_domain_set_hwirq_and_chip(domain, virq + i,
2637 hwirq + i, &its_irq_chip, its_dev);
2638 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2639 pr_debug("ID:%d pID:%d vID:%d\n",
2640 (int)(hwirq + i - its_dev->event_map.lpi_base),
2641 (int)(hwirq + i), virq + i);
2647 static int its_irq_domain_activate(struct irq_domain *domain,
2648 struct irq_data *d, bool reserve)
2650 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2651 u32 event = its_get_event_id(d);
2652 const struct cpumask *cpu_mask = cpu_online_mask;
2655 /* get the cpu_mask of local node */
2656 if (its_dev->its->numa_node >= 0)
2657 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2659 /* Bind the LPI to the first possible CPU */
2660 cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2661 if (cpu >= nr_cpu_ids) {
2662 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2665 cpu = cpumask_first(cpu_online_mask);
2668 its_dev->event_map.col_map[event] = cpu;
2669 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2671 /* Map the GIC IRQ and event to the device */
2672 its_send_mapti(its_dev, d->hwirq, event);
2676 static void its_irq_domain_deactivate(struct irq_domain *domain,
2679 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2680 u32 event = its_get_event_id(d);
2682 /* Stop the delivery of interrupts */
2683 its_send_discard(its_dev, event);
2686 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2687 unsigned int nr_irqs)
2689 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2690 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2691 struct its_node *its = its_dev->its;
2694 bitmap_release_region(its_dev->event_map.lpi_map,
2695 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
2696 get_count_order(nr_irqs));
2698 for (i = 0; i < nr_irqs; i++) {
2699 struct irq_data *data = irq_domain_get_irq_data(domain,
2701 /* Nuke the entry in the domain */
2702 irq_domain_reset_irq_data(data);
2705 mutex_lock(&its->dev_alloc_lock);
2708 * If all interrupts have been freed, start mopping the
2709 * floor. This is conditionned on the device not being shared.
2711 if (!its_dev->shared &&
2712 bitmap_empty(its_dev->event_map.lpi_map,
2713 its_dev->event_map.nr_lpis)) {
2714 its_lpi_free(its_dev->event_map.lpi_map,
2715 its_dev->event_map.lpi_base,
2716 its_dev->event_map.nr_lpis);
2718 /* Unmap device/itt */
2719 its_send_mapd(its_dev, 0);
2720 its_free_device(its_dev);
2723 mutex_unlock(&its->dev_alloc_lock);
2725 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2728 static const struct irq_domain_ops its_domain_ops = {
2729 .alloc = its_irq_domain_alloc,
2730 .free = its_irq_domain_free,
2731 .activate = its_irq_domain_activate,
2732 .deactivate = its_irq_domain_deactivate,
2738 * If a GICv4 doesn't implement Direct LPIs (which is extremely
2739 * likely), the only way to perform an invalidate is to use a fake
2740 * device to issue an INV command, implying that the LPI has first
2741 * been mapped to some event on that device. Since this is not exactly
2742 * cheap, we try to keep that mapping around as long as possible, and
2743 * only issue an UNMAP if we're short on available slots.
2745 * Broken by design(tm).
2747 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2749 /* Already unmapped? */
2750 if (vpe->vpe_proxy_event == -1)
2753 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2754 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2757 * We don't track empty slots at all, so let's move the
2758 * next_victim pointer if we can quickly reuse that slot
2759 * instead of nuking an existing entry. Not clear that this is
2760 * always a win though, and this might just generate a ripple
2761 * effect... Let's just hope VPEs don't migrate too often.
2763 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2764 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2766 vpe->vpe_proxy_event = -1;
2769 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2771 if (!gic_rdists->has_direct_lpi) {
2772 unsigned long flags;
2774 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2775 its_vpe_db_proxy_unmap_locked(vpe);
2776 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2780 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2782 /* Already mapped? */
2783 if (vpe->vpe_proxy_event != -1)
2786 /* This slot was already allocated. Kick the other VPE out. */
2787 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2788 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2790 /* Map the new VPE instead */
2791 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2792 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2793 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2795 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2796 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2799 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2801 unsigned long flags;
2802 struct its_collection *target_col;
2804 if (gic_rdists->has_direct_lpi) {
2805 void __iomem *rdbase;
2807 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2808 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2809 wait_for_syncr(rdbase);
2814 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2816 its_vpe_db_proxy_map_locked(vpe);
2818 target_col = &vpe_proxy.dev->its->collections[to];
2819 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2820 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2822 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2825 static int its_vpe_set_affinity(struct irq_data *d,
2826 const struct cpumask *mask_val,
2829 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2830 int cpu = cpumask_first(mask_val);
2833 * Changing affinity is mega expensive, so let's be as lazy as
2834 * we can and only do it if we really have to. Also, if mapped
2835 * into the proxy device, we need to move the doorbell
2836 * interrupt to its new location.
2838 if (vpe->col_idx != cpu) {
2839 int from = vpe->col_idx;
2842 its_send_vmovp(vpe);
2843 its_vpe_db_proxy_move(vpe, from, cpu);
2846 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2848 return IRQ_SET_MASK_OK_DONE;
2851 static void its_vpe_schedule(struct its_vpe *vpe)
2853 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2856 /* Schedule the VPE */
2857 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2858 GENMASK_ULL(51, 12);
2859 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2860 val |= GICR_VPROPBASER_RaWb;
2861 val |= GICR_VPROPBASER_InnerShareable;
2862 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2864 val = virt_to_phys(page_address(vpe->vpt_page)) &
2865 GENMASK_ULL(51, 16);
2866 val |= GICR_VPENDBASER_RaWaWb;
2867 val |= GICR_VPENDBASER_NonShareable;
2869 * There is no good way of finding out if the pending table is
2870 * empty as we can race against the doorbell interrupt very
2871 * easily. So in the end, vpe->pending_last is only an
2872 * indication that the vcpu has something pending, not one
2873 * that the pending table is empty. A good implementation
2874 * would be able to read its coarse map pretty quickly anyway,
2875 * making this a tolerable issue.
2877 val |= GICR_VPENDBASER_PendingLast;
2878 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2879 val |= GICR_VPENDBASER_Valid;
2880 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2883 static void its_vpe_deschedule(struct its_vpe *vpe)
2885 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2888 val = its_clear_vpend_valid(vlpi_base);
2890 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2891 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2893 vpe->pending_last = true;
2895 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2896 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2900 static void its_vpe_invall(struct its_vpe *vpe)
2902 struct its_node *its;
2904 list_for_each_entry(its, &its_nodes, entry) {
2908 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2912 * Sending a VINVALL to a single ITS is enough, as all
2913 * we need is to reach the redistributors.
2915 its_send_vinvall(its, vpe);
2920 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2922 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2923 struct its_cmd_info *info = vcpu_info;
2925 switch (info->cmd_type) {
2927 its_vpe_schedule(vpe);
2930 case DESCHEDULE_VPE:
2931 its_vpe_deschedule(vpe);
2935 its_vpe_invall(vpe);
2943 static void its_vpe_send_cmd(struct its_vpe *vpe,
2944 void (*cmd)(struct its_device *, u32))
2946 unsigned long flags;
2948 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2950 its_vpe_db_proxy_map_locked(vpe);
2951 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2953 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2956 static void its_vpe_send_inv(struct irq_data *d)
2958 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2960 if (gic_rdists->has_direct_lpi) {
2961 void __iomem *rdbase;
2963 /* Target the redistributor this VPE is currently known on */
2964 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2965 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
2966 wait_for_syncr(rdbase);
2968 its_vpe_send_cmd(vpe, its_send_inv);
2972 static void its_vpe_mask_irq(struct irq_data *d)
2975 * We need to unmask the LPI, which is described by the parent
2976 * irq_data. Instead of calling into the parent (which won't
2977 * exactly do the right thing, let's simply use the
2978 * parent_data pointer. Yes, I'm naughty.
2980 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2981 its_vpe_send_inv(d);
2984 static void its_vpe_unmask_irq(struct irq_data *d)
2986 /* Same hack as above... */
2987 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2988 its_vpe_send_inv(d);
2991 static int its_vpe_set_irqchip_state(struct irq_data *d,
2992 enum irqchip_irq_state which,
2995 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2997 if (which != IRQCHIP_STATE_PENDING)
3000 if (gic_rdists->has_direct_lpi) {
3001 void __iomem *rdbase;
3003 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3005 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3007 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3008 wait_for_syncr(rdbase);
3012 its_vpe_send_cmd(vpe, its_send_int);
3014 its_vpe_send_cmd(vpe, its_send_clear);
3020 static struct irq_chip its_vpe_irq_chip = {
3021 .name = "GICv4-vpe",
3022 .irq_mask = its_vpe_mask_irq,
3023 .irq_unmask = its_vpe_unmask_irq,
3024 .irq_eoi = irq_chip_eoi_parent,
3025 .irq_set_affinity = its_vpe_set_affinity,
3026 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
3027 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
3030 static int its_vpe_id_alloc(void)
3032 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
3035 static void its_vpe_id_free(u16 id)
3037 ida_simple_remove(&its_vpeid_ida, id);
3040 static int its_vpe_init(struct its_vpe *vpe)
3042 struct page *vpt_page;
3045 /* Allocate vpe_id */
3046 vpe_id = its_vpe_id_alloc();
3051 vpt_page = its_allocate_pending_table(GFP_KERNEL);
3053 its_vpe_id_free(vpe_id);
3057 if (!its_alloc_vpe_table(vpe_id)) {
3058 its_vpe_id_free(vpe_id);
3059 its_free_pending_table(vpt_page);
3063 vpe->vpe_id = vpe_id;
3064 vpe->vpt_page = vpt_page;
3065 vpe->vpe_proxy_event = -1;
3070 static void its_vpe_teardown(struct its_vpe *vpe)
3072 its_vpe_db_proxy_unmap(vpe);
3073 its_vpe_id_free(vpe->vpe_id);
3074 its_free_pending_table(vpe->vpt_page);
3077 static void its_vpe_irq_domain_free(struct irq_domain *domain,
3079 unsigned int nr_irqs)
3081 struct its_vm *vm = domain->host_data;
3084 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3086 for (i = 0; i < nr_irqs; i++) {
3087 struct irq_data *data = irq_domain_get_irq_data(domain,
3089 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3091 BUG_ON(vm != vpe->its_vm);
3093 clear_bit(data->hwirq, vm->db_bitmap);
3094 its_vpe_teardown(vpe);
3095 irq_domain_reset_irq_data(data);
3098 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3099 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3100 its_free_prop_table(vm->vprop_page);
3104 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3105 unsigned int nr_irqs, void *args)
3107 struct its_vm *vm = args;
3108 unsigned long *bitmap;
3109 struct page *vprop_page;
3110 int base, nr_ids, i, err = 0;
3114 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3118 if (nr_ids < nr_irqs) {
3119 its_lpi_free(bitmap, base, nr_ids);
3123 vprop_page = its_allocate_prop_table(GFP_KERNEL);
3125 its_lpi_free(bitmap, base, nr_ids);
3129 vm->db_bitmap = bitmap;
3130 vm->db_lpi_base = base;
3131 vm->nr_db_lpis = nr_ids;
3132 vm->vprop_page = vprop_page;
3134 for (i = 0; i < nr_irqs; i++) {
3135 vm->vpes[i]->vpe_db_lpi = base + i;
3136 err = its_vpe_init(vm->vpes[i]);
3139 err = its_irq_gic_domain_alloc(domain, virq + i,
3140 vm->vpes[i]->vpe_db_lpi);
3143 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3144 &its_vpe_irq_chip, vm->vpes[i]);
3150 its_vpe_irq_domain_free(domain, virq, i - 1);
3152 its_lpi_free(bitmap, base, nr_ids);
3153 its_free_prop_table(vprop_page);
3159 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3160 struct irq_data *d, bool reserve)
3162 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3163 struct its_node *its;
3165 /* If we use the list map, we issue VMAPP on demand... */
3169 /* Map the VPE to the first possible CPU */
3170 vpe->col_idx = cpumask_first(cpu_online_mask);
3172 list_for_each_entry(its, &its_nodes, entry) {
3176 its_send_vmapp(its, vpe, true);
3177 its_send_vinvall(its, vpe);
3180 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3185 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3188 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3189 struct its_node *its;
3192 * If we use the list map, we unmap the VPE once no VLPIs are
3193 * associated with the VM.
3198 list_for_each_entry(its, &its_nodes, entry) {
3202 its_send_vmapp(its, vpe, false);
3206 static const struct irq_domain_ops its_vpe_domain_ops = {
3207 .alloc = its_vpe_irq_domain_alloc,
3208 .free = its_vpe_irq_domain_free,
3209 .activate = its_vpe_irq_domain_activate,
3210 .deactivate = its_vpe_irq_domain_deactivate,
3213 static int its_force_quiescent(void __iomem *base)
3215 u32 count = 1000000; /* 1s */
3218 val = readl_relaxed(base + GITS_CTLR);
3220 * GIC architecture specification requires the ITS to be both
3221 * disabled and quiescent for writes to GITS_BASER<n> or
3222 * GITS_CBASER to not have UNPREDICTABLE results.
3224 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3227 /* Disable the generation of all interrupts to this ITS */
3228 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3229 writel_relaxed(val, base + GITS_CTLR);
3231 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3233 val = readl_relaxed(base + GITS_CTLR);
3234 if (val & GITS_CTLR_QUIESCENT)
3246 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3248 struct its_node *its = data;
3250 /* erratum 22375: only alloc 8MB table size (20 bits) */
3251 its->typer &= ~GITS_TYPER_DEVBITS;
3252 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
3253 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3258 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3260 struct its_node *its = data;
3262 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3267 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3269 struct its_node *its = data;
3271 /* On QDF2400, the size of the ITE is 16Bytes */
3272 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
3273 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
3278 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3280 struct its_node *its = its_dev->its;
3283 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
3284 * which maps 32-bit writes targeted at a separate window of
3285 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
3286 * with device ID taken from bits [device_id_bits + 1:2] of
3287 * the window offset.
3289 return its->pre_its_base + (its_dev->device_id << 2);
3292 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3294 struct its_node *its = data;
3295 u32 pre_its_window[2];
3298 if (!fwnode_property_read_u32_array(its->fwnode_handle,
3299 "socionext,synquacer-pre-its",
3301 ARRAY_SIZE(pre_its_window))) {
3303 its->pre_its_base = pre_its_window[0];
3304 its->get_msi_base = its_irq_get_msi_base_pre_its;
3306 ids = ilog2(pre_its_window[1]) - 2;
3307 if (device_ids(its) > ids) {
3308 its->typer &= ~GITS_TYPER_DEVBITS;
3309 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
3312 /* the pre-ITS breaks isolation, so disable MSI remapping */
3313 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3319 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3321 struct its_node *its = data;
3324 * Hip07 insists on using the wrong address for the VLPI
3325 * page. Trick it into doing the right thing...
3327 its->vlpi_redist_offset = SZ_128K;
3331 static const struct gic_quirk its_quirks[] = {
3332 #ifdef CONFIG_CAVIUM_ERRATUM_22375
3334 .desc = "ITS: Cavium errata 22375, 24313",
3335 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3337 .init = its_enable_quirk_cavium_22375,
3340 #ifdef CONFIG_CAVIUM_ERRATUM_23144
3342 .desc = "ITS: Cavium erratum 23144",
3343 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3345 .init = its_enable_quirk_cavium_23144,
3348 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3350 .desc = "ITS: QDF2400 erratum 0065",
3351 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
3353 .init = its_enable_quirk_qdf2400_e0065,
3356 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3359 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3360 * implementation, but with a 'pre-ITS' added that requires
3361 * special handling in software.
3363 .desc = "ITS: Socionext Synquacer pre-ITS",
3366 .init = its_enable_quirk_socionext_synquacer,
3369 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3371 .desc = "ITS: Hip07 erratum 161600802",
3374 .init = its_enable_quirk_hip07_161600802,
3381 static void its_enable_quirks(struct its_node *its)
3383 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3385 gic_enable_quirks(iidr, its_quirks, its);
3388 static int its_save_disable(void)
3390 struct its_node *its;
3393 raw_spin_lock(&its_lock);
3394 list_for_each_entry(its, &its_nodes, entry) {
3397 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3401 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3402 err = its_force_quiescent(base);
3404 pr_err("ITS@%pa: failed to quiesce: %d\n",
3405 &its->phys_base, err);
3406 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3410 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3415 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3418 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3422 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3425 raw_spin_unlock(&its_lock);
3430 static void its_restore_enable(void)
3432 struct its_node *its;
3435 raw_spin_lock(&its_lock);
3436 list_for_each_entry(its, &its_nodes, entry) {
3440 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3446 * Make sure that the ITS is disabled. If it fails to quiesce,
3447 * don't restore it since writing to CBASER or BASER<n>
3448 * registers is undefined according to the GIC v3 ITS
3451 ret = its_force_quiescent(base);
3453 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3454 &its->phys_base, ret);
3458 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3461 * Writing CBASER resets CREADR to 0, so make CWRITER and
3462 * cmd_write line up with it.
3464 its->cmd_write = its->cmd_base;
3465 gits_write_cwriter(0, base + GITS_CWRITER);
3467 /* Restore GITS_BASER from the value cache. */
3468 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3469 struct its_baser *baser = &its->tables[i];
3471 if (!(baser->val & GITS_BASER_VALID))
3474 its_write_baser(its, baser, baser->val);
3476 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3479 * Reinit the collection if it's stored in the ITS. This is
3480 * indicated by the col_id being less than the HCC field.
3481 * CID < HCC as specified in the GIC v3 Documentation.
3483 if (its->collections[smp_processor_id()].col_id <
3484 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3485 its_cpu_init_collection(its);
3487 raw_spin_unlock(&its_lock);
3490 static struct syscore_ops its_syscore_ops = {
3491 .suspend = its_save_disable,
3492 .resume = its_restore_enable,
3495 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3497 struct irq_domain *inner_domain;
3498 struct msi_domain_info *info;
3500 info = kzalloc(sizeof(*info), GFP_KERNEL);
3504 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3505 if (!inner_domain) {
3510 inner_domain->parent = its_parent;
3511 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3512 inner_domain->flags |= its->msi_domain_flags;
3513 info->ops = &its_msi_domain_ops;
3515 inner_domain->host_data = info;
3520 static int its_init_vpe_domain(void)
3522 struct its_node *its;
3526 if (gic_rdists->has_direct_lpi) {
3527 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3531 /* Any ITS will do, even if not v4 */
3532 its = list_first_entry(&its_nodes, struct its_node, entry);
3534 entries = roundup_pow_of_two(nr_cpu_ids);
3535 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3537 if (!vpe_proxy.vpes) {
3538 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3542 /* Use the last possible DevID */
3543 devid = GENMASK(device_ids(its) - 1, 0);
3544 vpe_proxy.dev = its_create_device(its, devid, entries, false);
3545 if (!vpe_proxy.dev) {
3546 kfree(vpe_proxy.vpes);
3547 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3551 BUG_ON(entries > vpe_proxy.dev->nr_ites);
3553 raw_spin_lock_init(&vpe_proxy.lock);
3554 vpe_proxy.next_victim = 0;
3555 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3556 devid, vpe_proxy.dev->nr_ites);
3561 static int __init its_compute_its_list_map(struct resource *res,
3562 void __iomem *its_base)
3568 * This is assumed to be done early enough that we're
3569 * guaranteed to be single-threaded, hence no
3570 * locking. Should this change, we should address
3573 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3574 if (its_number >= GICv4_ITS_LIST_MAX) {
3575 pr_err("ITS@%pa: No ITSList entry available!\n",
3580 ctlr = readl_relaxed(its_base + GITS_CTLR);
3581 ctlr &= ~GITS_CTLR_ITS_NUMBER;
3582 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3583 writel_relaxed(ctlr, its_base + GITS_CTLR);
3584 ctlr = readl_relaxed(its_base + GITS_CTLR);
3585 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3586 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3587 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3590 if (test_and_set_bit(its_number, &its_list_map)) {
3591 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3592 &res->start, its_number);
3599 static int __init its_probe_one(struct resource *res,
3600 struct fwnode_handle *handle, int numa_node)
3602 struct its_node *its;
3603 void __iomem *its_base;
3605 u64 baser, tmp, typer;
3609 its_base = ioremap(res->start, resource_size(res));
3611 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3615 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3616 if (val != 0x30 && val != 0x40) {
3617 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3622 err = its_force_quiescent(its_base);
3624 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3628 pr_info("ITS %pR\n", res);
3630 its = kzalloc(sizeof(*its), GFP_KERNEL);
3636 raw_spin_lock_init(&its->lock);
3637 mutex_init(&its->dev_alloc_lock);
3638 INIT_LIST_HEAD(&its->entry);
3639 INIT_LIST_HEAD(&its->its_device_list);
3640 typer = gic_read_typer(its_base + GITS_TYPER);
3642 its->base = its_base;
3643 its->phys_base = res->start;
3645 if (!(typer & GITS_TYPER_VMOVP)) {
3646 err = its_compute_its_list_map(res, its_base);
3652 pr_info("ITS@%pa: Using ITS number %d\n",
3655 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3659 its->numa_node = numa_node;
3661 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3662 get_order(ITS_CMD_QUEUE_SZ));
3667 its->cmd_base = (void *)page_address(page);
3668 its->cmd_write = its->cmd_base;
3669 its->fwnode_handle = handle;
3670 its->get_msi_base = its_irq_get_msi_base;
3671 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3673 its_enable_quirks(its);
3675 err = its_alloc_tables(its);
3679 err = its_alloc_collections(its);
3681 goto out_free_tables;
3683 baser = (virt_to_phys(its->cmd_base) |
3684 GITS_CBASER_RaWaWb |
3685 GITS_CBASER_InnerShareable |
3686 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3689 gits_write_cbaser(baser, its->base + GITS_CBASER);
3690 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3692 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3693 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3695 * The HW reports non-shareable, we must
3696 * remove the cacheability attributes as
3699 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3700 GITS_CBASER_CACHEABILITY_MASK);
3701 baser |= GITS_CBASER_nC;
3702 gits_write_cbaser(baser, its->base + GITS_CBASER);
3704 pr_info("ITS: using cache flushing for cmd queue\n");
3705 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3708 gits_write_cwriter(0, its->base + GITS_CWRITER);
3709 ctlr = readl_relaxed(its->base + GITS_CTLR);
3710 ctlr |= GITS_CTLR_ENABLE;
3712 ctlr |= GITS_CTLR_ImDe;
3713 writel_relaxed(ctlr, its->base + GITS_CTLR);
3715 if (GITS_TYPER_HCC(typer))
3716 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3718 err = its_init_domain(handle, its);
3720 goto out_free_tables;
3722 raw_spin_lock(&its_lock);
3723 list_add(&its->entry, &its_nodes);
3724 raw_spin_unlock(&its_lock);
3729 its_free_tables(its);
3731 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3736 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3740 static bool gic_rdists_supports_plpis(void)
3742 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3745 static int redist_disable_lpis(void)
3747 void __iomem *rbase = gic_data_rdist_rd_base();
3748 u64 timeout = USEC_PER_SEC;
3751 if (!gic_rdists_supports_plpis()) {
3752 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3756 val = readl_relaxed(rbase + GICR_CTLR);
3757 if (!(val & GICR_CTLR_ENABLE_LPIS))
3761 * If coming via a CPU hotplug event, we don't need to disable
3762 * LPIs before trying to re-enable them. They are already
3763 * configured and all is well in the world.
3765 * If running with preallocated tables, there is nothing to do.
3767 if (gic_data_rdist()->lpi_enabled ||
3768 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
3772 * From that point on, we only try to do some damage control.
3774 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3775 smp_processor_id());
3776 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3779 val &= ~GICR_CTLR_ENABLE_LPIS;
3780 writel_relaxed(val, rbase + GICR_CTLR);
3782 /* Make sure any change to GICR_CTLR is observable by the GIC */
3786 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3787 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3788 * Error out if we time out waiting for RWP to clear.
3790 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3792 pr_err("CPU%d: Timeout while disabling LPIs\n",
3793 smp_processor_id());
3801 * After it has been written to 1, it is IMPLEMENTATION
3802 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3803 * cleared to 0. Error out if clearing the bit failed.
3805 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3806 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3813 int its_cpu_init(void)
3815 if (!list_empty(&its_nodes)) {
3818 ret = redist_disable_lpis();
3822 its_cpu_init_lpis();
3823 its_cpu_init_collections();
3829 static const struct of_device_id its_device_id[] = {
3830 { .compatible = "arm,gic-v3-its", },
3834 static int __init its_of_probe(struct device_node *node)
3836 struct device_node *np;
3837 struct resource res;
3839 for (np = of_find_matching_node(node, its_device_id); np;
3840 np = of_find_matching_node(np, its_device_id)) {
3841 if (!of_device_is_available(np))
3843 if (!of_property_read_bool(np, "msi-controller")) {
3844 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3849 if (of_address_to_resource(np, 0, &res)) {
3850 pr_warn("%pOF: no regs?\n", np);
3854 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3861 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3863 #ifdef CONFIG_ACPI_NUMA
3864 struct its_srat_map {
3871 static struct its_srat_map *its_srat_maps __initdata;
3872 static int its_in_srat __initdata;
3874 static int __init acpi_get_its_numa_node(u32 its_id)
3878 for (i = 0; i < its_in_srat; i++) {
3879 if (its_id == its_srat_maps[i].its_id)
3880 return its_srat_maps[i].numa_node;
3882 return NUMA_NO_NODE;
3885 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
3886 const unsigned long end)
3891 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
3892 const unsigned long end)
3895 struct acpi_srat_gic_its_affinity *its_affinity;
3897 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3901 if (its_affinity->header.length < sizeof(*its_affinity)) {
3902 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3903 its_affinity->header.length);
3907 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3909 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3910 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3914 its_srat_maps[its_in_srat].numa_node = node;
3915 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3917 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3918 its_affinity->proximity_domain, its_affinity->its_id, node);
3923 static void __init acpi_table_parse_srat_its(void)
3927 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3928 sizeof(struct acpi_table_srat),
3929 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3930 gic_acpi_match_srat_its, 0);
3934 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3936 if (!its_srat_maps) {
3937 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3941 acpi_table_parse_entries(ACPI_SIG_SRAT,
3942 sizeof(struct acpi_table_srat),
3943 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3944 gic_acpi_parse_srat_its, 0);
3947 /* free the its_srat_maps after ITS probing */
3948 static void __init acpi_its_srat_maps_free(void)
3950 kfree(its_srat_maps);
3953 static void __init acpi_table_parse_srat_its(void) { }
3954 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3955 static void __init acpi_its_srat_maps_free(void) { }
3958 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
3959 const unsigned long end)
3961 struct acpi_madt_generic_translator *its_entry;
3962 struct fwnode_handle *dom_handle;
3963 struct resource res;
3966 its_entry = (struct acpi_madt_generic_translator *)header;
3967 memset(&res, 0, sizeof(res));
3968 res.start = its_entry->base_address;
3969 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3970 res.flags = IORESOURCE_MEM;
3972 dom_handle = irq_domain_alloc_fwnode(&res.start);
3974 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3979 err = iort_register_domain_token(its_entry->translation_id, res.start,
3982 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3983 &res.start, its_entry->translation_id);
3987 err = its_probe_one(&res, dom_handle,
3988 acpi_get_its_numa_node(its_entry->translation_id));
3992 iort_deregister_domain_token(its_entry->translation_id);
3994 irq_domain_free_fwnode(dom_handle);
3998 static void __init its_acpi_probe(void)
4000 acpi_table_parse_srat_its();
4001 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
4002 gic_acpi_parse_madt_its, 0);
4003 acpi_its_srat_maps_free();
4006 static void __init its_acpi_probe(void) { }
4009 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
4010 struct irq_domain *parent_domain)
4012 struct device_node *of_node;
4013 struct its_node *its;
4014 bool has_v4 = false;
4017 its_parent = parent_domain;
4018 of_node = to_of_node(handle);
4020 its_of_probe(of_node);
4024 if (list_empty(&its_nodes)) {
4025 pr_warn("ITS: No ITS available, not enabling LPIs\n");
4029 gic_rdists = rdists;
4031 err = allocate_lpi_tables();
4035 list_for_each_entry(its, &its_nodes, entry)
4036 has_v4 |= is_v4(its);
4038 if (has_v4 & rdists->has_vlpis) {
4039 if (its_init_vpe_domain() ||
4040 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
4041 rdists->has_vlpis = false;
4042 pr_err("ITS: Disabling GICv4 support\n");
4046 register_syscore_ops(&its_syscore_ops);