drivers/irqchip/irq-gic-v3-its.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/acpi_iort.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/bitmap.h>
  11 #include <linux/cpu.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/delay.h>
  14 #include <linux/dma-iommu.h>
  15 #include <linux/efi.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/list.h>
  20 #include <linux/log2.h>
  21 #include <linux/memblock.h>
  22 #include <linux/mm.h>
  23 #include <linux/msi.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_pci.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/percpu.h>
  30 #include <linux/slab.h>
  31 #include <linux/syscore_ops.h>
  32
  33 #include <linux/irqchip.h>
  34 #include <linux/irqchip/arm-gic-v3.h>
  35 #include <linux/irqchip/arm-gic-v4.h>
  36
  37 #include <asm/cputype.h>
  38 #include <asm/exception.h>
  39
  40 #include "irq-gic-common.h"
  41
  42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  44 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144       (1ULL << 2)
  45 #define ITS_FLAGS_SAVE_SUSPEND_STATE            (1ULL << 3)
  46
  47 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  48 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED      (1 << 1)
  49
  50 static u32 lpi_id_bits;
  51
  52 /*
  53  * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
  54  * deal with (one configuration byte per interrupt). PENDBASE has to
  55  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
  56  */
  57 #define LPI_NRBITS              lpi_id_bits
  58 #define LPI_PROPBASE_SZ         ALIGN(BIT(LPI_NRBITS), SZ_64K)
  59 #define LPI_PENDBASE_SZ         ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
  60
  61 #define LPI_PROP_DEFAULT_PRIO   GICD_INT_DEF_PRI
  62
  63 /*
  64  * Collection structure - just an ID, and a redistributor address to
  65  * ping. We use one per CPU as a bag of interrupts assigned to this
  66  * CPU.
  67  */
  68 struct its_collection {
  69         u64                     target_address;
  70         u16                     col_id;
  71 };
  72
  73 /*
  74  * The ITS_BASER structure - contains memory information, cached
  75  * value of BASER register configuration and ITS page size.
  76  */
  77 struct its_baser {
  78         void            *base;
  79         u64             val;
  80         u32             order;
  81         u32             psz;
  82 };
  83
  84 struct its_device;
  85
  86 /*
  87  * The ITS structure - contains most of the infrastructure, with the
  88  * top-level MSI domain, the command queue, the collections, and the
  89  * list of devices writing to it.
  90  *
  91  * dev_alloc_lock has to be taken for device allocations, while the
  92  * spinlock must be taken to parse data structures such as the device
  93  * list.
  94  */
  95 struct its_node {
  96         raw_spinlock_t          lock;
  97         struct mutex            dev_alloc_lock;
  98         struct list_head        entry;
  99         void __iomem            *base;
 100         void __iomem            *sgir_base;
 101         phys_addr_t             phys_base;
 102         struct its_cmd_block    *cmd_base;
 103         struct its_cmd_block    *cmd_write;
 104         struct its_baser        tables[GITS_BASER_NR_REGS];
 105         struct its_collection   *collections;
 106         struct fwnode_handle    *fwnode_handle;
 107         u64                     (*get_msi_base)(struct its_device *its_dev);
 108         u64                     typer;
 109         u64                     cbaser_save;
 110         u32                     ctlr_save;
 111         u32                     mpidr;
 112         struct list_head        its_device_list;
 113         u64                     flags;
 114         unsigned long           list_nr;
 115         int                     numa_node;
 116         unsigned int            msi_domain_flags;
 117         u32                     pre_its_base; /* for Socionext Synquacer */
 118         int                     vlpi_redist_offset;
 119 };
 120
 121 #define is_v4(its)              (!!((its)->typer & GITS_TYPER_VLPIS))
 122 #define is_v4_1(its)            (!!((its)->typer & GITS_TYPER_VMAPP))
 123 #define device_ids(its)         (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
 124
 125 #define ITS_ITT_ALIGN           SZ_256
 126
 127 /* The maximum number of VPEID bits supported by VLPI commands */
 128 #define ITS_MAX_VPEID_BITS                                              \
 129         ({                                                              \
 130                 int nvpeid = 16;                                        \
 131                 if (gic_rdists->has_rvpeid &&                           \
 132                     gic_rdists->gicd_typer2 & GICD_TYPER2_VIL)          \
 133                         nvpeid = 1 + (gic_rdists->gicd_typer2 &         \
 134                                       GICD_TYPER2_VID);                 \
 135                                                                         \
 136                 nvpeid;                                                 \
 137         })
 138 #define ITS_MAX_VPEID           (1 << (ITS_MAX_VPEID_BITS))
 139
 140 /* Convert page order to size in bytes */
 141 #define PAGE_ORDER_TO_SIZE(o)   (PAGE_SIZE << (o))
 142
 143 struct event_lpi_map {
 144         unsigned long           *lpi_map;
 145         u16                     *col_map;
 146         irq_hw_number_t         lpi_base;
 147         int                     nr_lpis;
 148         raw_spinlock_t          vlpi_lock;
 149         struct its_vm           *vm;
 150         struct its_vlpi_map     *vlpi_maps;
 151         int                     nr_vlpis;
 152 };
 153
 154 /*
 155  * The ITS view of a device - belongs to an ITS, owns an interrupt
 156  * translation table, and a list of interrupts.  If it some of its
 157  * LPIs are injected into a guest (GICv4), the event_map.vm field
 158  * indicates which one.
 159  */
 160 struct its_device {
 161         struct list_head        entry;
 162         struct its_node         *its;
 163         struct event_lpi_map    event_map;
 164         void                    *itt;
 165         u32                     nr_ites;
 166         u32                     device_id;
 167         bool                    shared;
 168 };
 169
 170 static struct {
 171         raw_spinlock_t          lock;
 172         struct its_device       *dev;
 173         struct its_vpe          **vpes;
 174         int                     next_victim;
 175 } vpe_proxy;
 176
 177 struct cpu_lpi_count {
 178         atomic_t        managed;
 179         atomic_t        unmanaged;
 180 };
 181
 182 static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
 183
 184 static LIST_HEAD(its_nodes);
 185 static DEFINE_RAW_SPINLOCK(its_lock);
 186 static struct rdists *gic_rdists;
 187 static struct irq_domain *its_parent;
 188
 189 static unsigned long its_list_map;
 190 static u16 vmovp_seq_num;
 191 static DEFINE_RAW_SPINLOCK(vmovp_lock);
 192
 193 static DEFINE_IDA(its_vpeid_ida);
 194
 195 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 196 #define gic_data_rdist_cpu(cpu)         (per_cpu_ptr(gic_rdists->rdist, cpu))
 197 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 198 #define gic_data_rdist_vlpi_base()      (gic_data_rdist_rd_base() + SZ_128K)
 199
 200 /*
 201  * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
 202  * always have vSGIs mapped.
 203  */
 204 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
 205 {
 206         return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
 207 }
 208
 209 static u16 get_its_list(struct its_vm *vm)
 210 {
 211         struct its_node *its;
 212         unsigned long its_list = 0;
 213
 214         list_for_each_entry(its, &its_nodes, entry) {
 215                 if (!is_v4(its))
 216                         continue;
 217
 218                 if (require_its_list_vmovp(vm, its))
 219                         __set_bit(its->list_nr, &its_list);
 220         }
 221
 222         return (u16)its_list;
 223 }
 224
 225 static inline u32 its_get_event_id(struct irq_data *d)
 226 {
 227         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 228         return d->hwirq - its_dev->event_map.lpi_base;
 229 }
 230
 231 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 232                                                u32 event)
 233 {
 234         struct its_node *its = its_dev->its;
 235
 236         return its->collections + its_dev->event_map.col_map[event];
 237 }
 238
 239 static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
 240                                                u32 event)
 241 {
 242         if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
 243                 return NULL;
 244
 245         return &its_dev->event_map.vlpi_maps[event];
 246 }
 247
 248 static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
 249 {
 250         if (irqd_is_forwarded_to_vcpu(d)) {
 251                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 252                 u32 event = its_get_event_id(d);
 253
 254                 return dev_event_to_vlpi_map(its_dev, event);
 255         }
 256
 257         return NULL;
 258 }
 259
 260 static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
 261 {
 262         raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
 263         return vpe->col_idx;
 264 }
 265
 266 static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
 267 {
 268         raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
 269 }
 270
 271 static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
 272 {
 273         struct its_vlpi_map *map = get_vlpi_map(d);
 274         int cpu;
 275
 276         if (map) {
 277                 cpu = vpe_to_cpuid_lock(map->vpe, flags);
 278         } else {
 279                 /* Physical LPIs are already locked via the irq_desc lock */
 280                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 281                 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
 282                 /* Keep GCC quiet... */
 283                 *flags = 0;
 284         }
 285
 286         return cpu;
 287 }
 288
 289 static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
 290 {
 291         struct its_vlpi_map *map = get_vlpi_map(d);
 292
 293         if (map)
 294                 vpe_to_cpuid_unlock(map->vpe, flags);
 295 }
 296
 297 static struct its_collection *valid_col(struct its_collection *col)
 298 {
 299         if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
 300                 return NULL;
 301
 302         return col;
 303 }
 304
 305 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
 306 {
 307         if (valid_col(its->collections + vpe->col_idx))
 308                 return vpe;
 309
 310         return NULL;
 311 }
 312
 313 /*
 314  * ITS command descriptors - parameters to be encoded in a command
 315  * block.
 316  */
 317 struct its_cmd_desc {
 318         union {
 319                 struct {
 320                         struct its_device *dev;
 321                         u32 event_id;
 322                 } its_inv_cmd;
 323
 324                 struct {
 325                         struct its_device *dev;
 326                         u32 event_id;
 327                 } its_clear_cmd;
 328
 329                 struct {
 330                         struct its_device *dev;
 331                         u32 event_id;
 332                 } its_int_cmd;
 333
 334                 struct {
 335                         struct its_device *dev;
 336                         int valid;
 337                 } its_mapd_cmd;
 338
 339                 struct {
 340                         struct its_collection *col;
 341                         int valid;
 342                 } its_mapc_cmd;
 343
 344                 struct {
 345                         struct its_device *dev;
 346                         u32 phys_id;
 347                         u32 event_id;
 348                 } its_mapti_cmd;
 349
 350                 struct {
 351                         struct its_device *dev;
 352                         struct its_collection *col;
 353                         u32 event_id;
 354                 } its_movi_cmd;
 355
 356                 struct {
 357                         struct its_device *dev;
 358                         u32 event_id;
 359                 } its_discard_cmd;
 360
 361                 struct {
 362                         struct its_collection *col;
 363                 } its_invall_cmd;
 364
 365                 struct {
 366                         struct its_vpe *vpe;
 367                 } its_vinvall_cmd;
 368
 369                 struct {
 370                         struct its_vpe *vpe;
 371                         struct its_collection *col;
 372                         bool valid;
 373                 } its_vmapp_cmd;
 374
 375                 struct {
 376                         struct its_vpe *vpe;
 377                         struct its_device *dev;
 378                         u32 virt_id;
 379                         u32 event_id;
 380                         bool db_enabled;
 381                 } its_vmapti_cmd;
 382
 383                 struct {
 384                         struct its_vpe *vpe;
 385                         struct its_device *dev;
 386                         u32 event_id;
 387                         bool db_enabled;
 388                 } its_vmovi_cmd;
 389
 390                 struct {
 391                         struct its_vpe *vpe;
 392                         struct its_collection *col;
 393                         u16 seq_num;
 394                         u16 its_list;
 395                 } its_vmovp_cmd;
 396
 397                 struct {
 398                         struct its_vpe *vpe;
 399                 } its_invdb_cmd;
 400
 401                 struct {
 402                         struct its_vpe *vpe;
 403                         u8 sgi;
 404                         u8 priority;
 405                         bool enable;
 406                         bool group;
 407                         bool clear;
 408                 } its_vsgi_cmd;
 409         };
 410 };
 411
 412 /*
 413  * The ITS command block, which is what the ITS actually parses.
 414  */
 415 struct its_cmd_block {
 416         union {
 417                 u64     raw_cmd[4];
 418                 __le64  raw_cmd_le[4];
 419         };
 420 };
 421
 422 #define ITS_CMD_QUEUE_SZ                SZ_64K
 423 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 424
 425 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
 426                                                     struct its_cmd_block *,
 427                                                     struct its_cmd_desc *);
 428
 429 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
 430                                               struct its_cmd_block *,
 431                                               struct its_cmd_desc *);
 432
 433 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
 434 {
 435         u64 mask = GENMASK_ULL(h, l);
 436         *raw_cmd &= ~mask;
 437         *raw_cmd |= (val << l) & mask;
 438 }
 439
 440 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 441 {
 442         its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
 443 }
 444
 445 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 446 {
 447         its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
 448 }
 449
 450 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 451 {
 452         its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
 453 }
 454
 455 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 456 {
 457         its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
 458 }
 459
 460 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 461 {
 462         its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
 463 }
 464
 465 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 466 {
 467         its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
 468 }
 469
 470 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 471 {
 472         its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
 473 }
 474
 475 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 476 {
 477         its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
 478 }
 479
 480 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 481 {
 482         its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
 483 }
 484
 485 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
 486 {
 487         its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
 488 }
 489
 490 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
 491 {
 492         its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
 493 }
 494
 495 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
 496 {
 497         its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
 498 }
 499
 500 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
 501 {
 502         its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
 503 }
 504
 505 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
 506 {
 507         its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
 508 }
 509
 510 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
 511 {
 512         its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
 513 }
 514
 515 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
 516 {
 517         its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
 518 }
 519
 520 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
 521 {
 522         its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
 523 }
 524
 525 static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
 526 {
 527         its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
 528 }
 529
 530 static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
 531 {
 532         its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
 533 }
 534
 535 static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
 536 {
 537         its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
 538 }
 539
 540 static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
 541                                         u32 vpe_db_lpi)
 542 {
 543         its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
 544 }
 545
 546 static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
 547                                         u32 vpe_db_lpi)
 548 {
 549         its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
 550 }
 551
 552 static void its_encode_db(struct its_cmd_block *cmd, bool db)
 553 {
 554         its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
 555 }
 556
 557 static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
 558 {
 559         its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
 560 }
 561
 562 static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
 563 {
 564         its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
 565 }
 566
 567 static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
 568 {
 569         its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
 570 }
 571
 572 static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
 573 {
 574         its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
 575 }
 576
 577 static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
 578 {
 579         its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
 580 }
 581
 582 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 583 {
 584         /* Let's fixup BE commands */
 585         cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
 586         cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
 587         cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
 588         cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
 589 }
 590
 591 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
 592                                                  struct its_cmd_block *cmd,
 593                                                  struct its_cmd_desc *desc)
 594 {
 595         unsigned long itt_addr;
 596         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 597
 598         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 599         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 600
 601         its_encode_cmd(cmd, GITS_CMD_MAPD);
 602         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 603         its_encode_size(cmd, size - 1);
 604         its_encode_itt(cmd, itt_addr);
 605         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 606
 607         its_fixup_cmd(cmd);
 608
 609         return NULL;
 610 }
 611
 612 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
 613                                                  struct its_cmd_block *cmd,
 614                                                  struct its_cmd_desc *desc)
 615 {
 616         its_encode_cmd(cmd, GITS_CMD_MAPC);
 617         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 618         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 619         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 620
 621         its_fixup_cmd(cmd);
 622
 623         return desc->its_mapc_cmd.col;
 624 }
 625
 626 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
 627                                                   struct its_cmd_block *cmd,
 628                                                   struct its_cmd_desc *desc)
 629 {
 630         struct its_collection *col;
 631
 632         col = dev_event_to_col(desc->its_mapti_cmd.dev,
 633                                desc->its_mapti_cmd.event_id);
 634
 635         its_encode_cmd(cmd, GITS_CMD_MAPTI);
 636         its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
 637         its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
 638         its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
 639         its_encode_collection(cmd, col->col_id);
 640
 641         its_fixup_cmd(cmd);
 642
 643         return valid_col(col);
 644 }
 645
 646 static struct its_collection *its_build_movi_cmd(struct its_node *its,
 647                                                  struct its_cmd_block *cmd,
 648                                                  struct its_cmd_desc *desc)
 649 {
 650         struct its_collection *col;
 651
 652         col = dev_event_to_col(desc->its_movi_cmd.dev,
 653                                desc->its_movi_cmd.event_id);
 654
 655         its_encode_cmd(cmd, GITS_CMD_MOVI);
 656         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 657         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 658         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 659
 660         its_fixup_cmd(cmd);
 661
 662         return valid_col(col);
 663 }
 664
 665 static struct its_collection *its_build_discard_cmd(struct its_node *its,
 666                                                     struct its_cmd_block *cmd,
 667                                                     struct its_cmd_desc *desc)
 668 {
 669         struct its_collection *col;
 670
 671         col = dev_event_to_col(desc->its_discard_cmd.dev,
 672                                desc->its_discard_cmd.event_id);
 673
 674         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 675         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 676         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 677
 678         its_fixup_cmd(cmd);
 679
 680         return valid_col(col);
 681 }
 682
 683 static struct its_collection *its_build_inv_cmd(struct its_node *its,
 684                                                 struct its_cmd_block *cmd,
 685                                                 struct its_cmd_desc *desc)
 686 {
 687         struct its_collection *col;
 688
 689         col = dev_event_to_col(desc->its_inv_cmd.dev,
 690                                desc->its_inv_cmd.event_id);
 691
 692         its_encode_cmd(cmd, GITS_CMD_INV);
 693         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 694         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 695
 696         its_fixup_cmd(cmd);
 697
 698         return valid_col(col);
 699 }
 700
 701 static struct its_collection *its_build_int_cmd(struct its_node *its,
 702                                                 struct its_cmd_block *cmd,
 703                                                 struct its_cmd_desc *desc)
 704 {
 705         struct its_collection *col;
 706
 707         col = dev_event_to_col(desc->its_int_cmd.dev,
 708                                desc->its_int_cmd.event_id);
 709
 710         its_encode_cmd(cmd, GITS_CMD_INT);
 711         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
 712         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
 713
 714         its_fixup_cmd(cmd);
 715
 716         return valid_col(col);
 717 }
 718
 719 static struct its_collection *its_build_clear_cmd(struct its_node *its,
 720                                                   struct its_cmd_block *cmd,
 721                                                   struct its_cmd_desc *desc)
 722 {
 723         struct its_collection *col;
 724
 725         col = dev_event_to_col(desc->its_clear_cmd.dev,
 726                                desc->its_clear_cmd.event_id);
 727
 728         its_encode_cmd(cmd, GITS_CMD_CLEAR);
 729         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
 730         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
 731
 732         its_fixup_cmd(cmd);
 733
 734         return valid_col(col);
 735 }
 736
 737 static struct its_collection *its_build_invall_cmd(struct its_node *its,
 738                                                    struct its_cmd_block *cmd,
 739                                                    struct its_cmd_desc *desc)
 740 {
 741         its_encode_cmd(cmd, GITS_CMD_INVALL);
 742         its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
 743
 744         its_fixup_cmd(cmd);
 745
 746         return NULL;
 747 }
 748
 749 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
 750                                              struct its_cmd_block *cmd,
 751                                              struct its_cmd_desc *desc)
 752 {
 753         its_encode_cmd(cmd, GITS_CMD_VINVALL);
 754         its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
 755
 756         its_fixup_cmd(cmd);
 757
 758         return valid_vpe(its, desc->its_vinvall_cmd.vpe);
 759 }
 760
 761 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
 762                                            struct its_cmd_block *cmd,
 763                                            struct its_cmd_desc *desc)
 764 {
 765         unsigned long vpt_addr, vconf_addr;
 766         u64 target;
 767         bool alloc;
 768
 769         its_encode_cmd(cmd, GITS_CMD_VMAPP);
 770         its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
 771         its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
 772
 773         if (!desc->its_vmapp_cmd.valid) {
 774                 if (is_v4_1(its)) {
 775                         alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
 776                         its_encode_alloc(cmd, alloc);
 777                 }
 778
 779                 goto out;
 780         }
 781
 782         vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
 783         target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
 784
 785         its_encode_target(cmd, target);
 786         its_encode_vpt_addr(cmd, vpt_addr);
 787         its_encode_vpt_size(cmd, LPI_NRBITS - 1);
 788
 789         if (!is_v4_1(its))
 790                 goto out;
 791
 792         vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
 793
 794         alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
 795
 796         its_encode_alloc(cmd, alloc);
 797
 798         /* We can only signal PTZ when alloc==1. Why do we have two bits? */
 799         its_encode_ptz(cmd, alloc);
 800         its_encode_vconf_addr(cmd, vconf_addr);
 801         its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
 802
 803 out:
 804         its_fixup_cmd(cmd);
 805
 806         return valid_vpe(its, desc->its_vmapp_cmd.vpe);
 807 }
 808
 809 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
 810                                             struct its_cmd_block *cmd,
 811                                             struct its_cmd_desc *desc)
 812 {
 813         u32 db;
 814
 815         if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
 816                 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
 817         else
 818                 db = 1023;
 819
 820         its_encode_cmd(cmd, GITS_CMD_VMAPTI);
 821         its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
 822         its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
 823         its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
 824         its_encode_db_phys_id(cmd, db);
 825         its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
 826
 827         its_fixup_cmd(cmd);
 828
 829         return valid_vpe(its, desc->its_vmapti_cmd.vpe);
 830 }
 831
 832 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
 833                                            struct its_cmd_block *cmd,
 834                                            struct its_cmd_desc *desc)
 835 {
 836         u32 db;
 837
 838         if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
 839                 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
 840         else
 841                 db = 1023;
 842
 843         its_encode_cmd(cmd, GITS_CMD_VMOVI);
 844         its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
 845         its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
 846         its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
 847         its_encode_db_phys_id(cmd, db);
 848         its_encode_db_valid(cmd, true);
 849
 850         its_fixup_cmd(cmd);
 851
 852         return valid_vpe(its, desc->its_vmovi_cmd.vpe);
 853 }
 854
 855 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
 856                                            struct its_cmd_block *cmd,
 857                                            struct its_cmd_desc *desc)
 858 {
 859         u64 target;
 860
 861         target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
 862         its_encode_cmd(cmd, GITS_CMD_VMOVP);
 863         its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
 864         its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
 865         its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
 866         its_encode_target(cmd, target);
 867
 868         if (is_v4_1(its)) {
 869                 its_encode_db(cmd, true);
 870                 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
 871         }
 872
 873         its_fixup_cmd(cmd);
 874
 875         return valid_vpe(its, desc->its_vmovp_cmd.vpe);
 876 }
 877
 878 static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
 879                                           struct its_cmd_block *cmd,
 880                                           struct its_cmd_desc *desc)
 881 {
 882         struct its_vlpi_map *map;
 883
 884         map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
 885                                     desc->its_inv_cmd.event_id);
 886
 887         its_encode_cmd(cmd, GITS_CMD_INV);
 888         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 889         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 890
 891         its_fixup_cmd(cmd);
 892
 893         return valid_vpe(its, map->vpe);
 894 }
 895
 896 static struct its_vpe *its_build_vint_cmd(struct its_node *its,
 897                                           struct its_cmd_block *cmd,
 898                                           struct its_cmd_desc *desc)
 899 {
 900         struct its_vlpi_map *map;
 901
 902         map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
 903                                     desc->its_int_cmd.event_id);
 904
 905         its_encode_cmd(cmd, GITS_CMD_INT);
 906         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
 907         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
 908
 909         its_fixup_cmd(cmd);
 910
 911         return valid_vpe(its, map->vpe);
 912 }
 913
 914 static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
 915                                             struct its_cmd_block *cmd,
 916                                             struct its_cmd_desc *desc)
 917 {
 918         struct its_vlpi_map *map;
 919
 920         map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
 921                                     desc->its_clear_cmd.event_id);
 922
 923         its_encode_cmd(cmd, GITS_CMD_CLEAR);
 924         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
 925         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
 926
 927         its_fixup_cmd(cmd);
 928
 929         return valid_vpe(its, map->vpe);
 930 }
 931
 932 static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
 933                                            struct its_cmd_block *cmd,
 934                                            struct its_cmd_desc *desc)
 935 {
 936         if (WARN_ON(!is_v4_1(its)))
 937                 return NULL;
 938
 939         its_encode_cmd(cmd, GITS_CMD_INVDB);
 940         its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
 941
 942         its_fixup_cmd(cmd);
 943
 944         return valid_vpe(its, desc->its_invdb_cmd.vpe);
 945 }
 946
 947 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
 948                                           struct its_cmd_block *cmd,
 949                                           struct its_cmd_desc *desc)
 950 {
 951         if (WARN_ON(!is_v4_1(its)))
 952                 return NULL;
 953
 954         its_encode_cmd(cmd, GITS_CMD_VSGI);
 955         its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
 956         its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
 957         its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
 958         its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
 959         its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
 960         its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
 961
 962         its_fixup_cmd(cmd);
 963
 964         return valid_vpe(its, desc->its_vsgi_cmd.vpe);
 965 }
 966
 967 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 968                                  struct its_cmd_block *ptr)
 969 {
 970         return (ptr - its->cmd_base) * sizeof(*ptr);
 971 }
 972
 973 static int its_queue_full(struct its_node *its)
 974 {
 975         int widx;
 976         int ridx;
 977
 978         widx = its->cmd_write - its->cmd_base;
 979         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 980
 981         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 982         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 983                 return 1;
 984
 985         return 0;
 986 }
 987
 988 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 989 {
 990         struct its_cmd_block *cmd;
 991         u32 count = 1000000;    /* 1s! */
 992
 993         while (its_queue_full(its)) {
 994                 count--;
 995                 if (!count) {
 996                         pr_err_ratelimited("ITS queue not draining\n");
 997                         return NULL;
 998                 }
 999                 cpu_relax();
1000                 udelay(1);
1001         }
1002
1003         cmd = its->cmd_write++;
1004
1005         /* Handle queue wrapping */
1006         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1007                 its->cmd_write = its->cmd_base;
1008
1009         /* Clear command  */
1010         cmd->raw_cmd[0] = 0;
1011         cmd->raw_cmd[1] = 0;
1012         cmd->raw_cmd[2] = 0;
1013         cmd->raw_cmd[3] = 0;
1014
1015         return cmd;
1016 }
1017
1018 static struct its_cmd_block *its_post_commands(struct its_node *its)
1019 {
1020         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1021
1022         writel_relaxed(wr, its->base + GITS_CWRITER);
1023
1024         return its->cmd_write;
1025 }
1026
1027 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1028 {
1029         /*
1030          * Make sure the commands written to memory are observable by
1031          * the ITS.
1032          */
1033         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
1034                 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
1035         else
1036                 dsb(ishst);
1037 }
1038
1039 static int its_wait_for_range_completion(struct its_node *its,
1040                                          u64    prev_idx,
1041                                          struct its_cmd_block *to)
1042 {
1043         u64 rd_idx, to_idx, linear_idx;
1044         u32 count = 1000000;    /* 1s! */
1045
1046         /* Linearize to_idx if the command set has wrapped around */
1047         to_idx = its_cmd_ptr_to_offset(its, to);
1048         if (to_idx < prev_idx)
1049                 to_idx += ITS_CMD_QUEUE_SZ;
1050
1051         linear_idx = prev_idx;
1052
1053         while (1) {
1054                 s64 delta;
1055
1056                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
1057
1058                 /*
1059                  * Compute the read pointer progress, taking the
1060                  * potential wrap-around into account.
1061                  */
1062                 delta = rd_idx - prev_idx;
1063                 if (rd_idx < prev_idx)
1064                         delta += ITS_CMD_QUEUE_SZ;
1065
1066                 linear_idx += delta;
1067                 if (linear_idx >= to_idx)
1068                         break;
1069
1070                 count--;
1071                 if (!count) {
1072                         pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1073                                            to_idx, linear_idx);
1074                         return -1;
1075                 }
1076                 prev_idx = rd_idx;
1077                 cpu_relax();
1078                 udelay(1);
1079         }
1080
1081         return 0;
1082 }
1083
1084 /* Warning, macro hell follows */
1085 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)       \
1086 void name(struct its_node *its,                                         \
1087           buildtype builder,                                            \
1088           struct its_cmd_desc *desc)                                    \
1089 {                                                                       \
1090         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;                \
1091         synctype *sync_obj;                                             \
1092         unsigned long flags;                                            \
1093         u64 rd_idx;                                                     \
1094                                                                         \
1095         raw_spin_lock_irqsave(&its->lock, flags);                       \
1096                                                                         \
1097         cmd = its_allocate_entry(its);                                  \
1098         if (!cmd) {             /* We're soooooo screewed... */         \
1099                 raw_spin_unlock_irqrestore(&its->lock, flags);          \
1100                 return;                                                 \
1101         }                                                               \
1102         sync_obj = builder(its, cmd, desc);                             \
1103         its_flush_cmd(its, cmd);                                        \
1104                                                                         \
1105         if (sync_obj) {                                                 \
1106                 sync_cmd = its_allocate_entry(its);                     \
1107                 if (!sync_cmd)                                          \
1108                         goto post;                                      \
1109                                                                         \
1110                 buildfn(its, sync_cmd, sync_obj);                       \
1111                 its_flush_cmd(its, sync_cmd);                           \
1112         }                                                               \
1113                                                                         \
1114 post:                                                                   \
1115         rd_idx = readl_relaxed(its->base + GITS_CREADR);                \
1116         next_cmd = its_post_commands(its);                              \
1117         raw_spin_unlock_irqrestore(&its->lock, flags);                  \
1118                                                                         \
1119         if (its_wait_for_range_completion(its, rd_idx, next_cmd))       \
1120                 pr_err_ratelimited("ITS cmd %ps failed\n", builder);    \
1121 }
1122
1123 static void its_build_sync_cmd(struct its_node *its,
1124                                struct its_cmd_block *sync_cmd,
1125                                struct its_collection *sync_col)
1126 {
1127         its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1128         its_encode_target(sync_cmd, sync_col->target_address);
1129
1130         its_fixup_cmd(sync_cmd);
1131 }
1132
1133 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1134                              struct its_collection, its_build_sync_cmd)
1135
1136 static void its_build_vsync_cmd(struct its_node *its,
1137                                 struct its_cmd_block *sync_cmd,
1138                                 struct its_vpe *sync_vpe)
1139 {
1140         its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1141         its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
1142
1143         its_fixup_cmd(sync_cmd);
1144 }
1145
1146 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1147                              struct its_vpe, its_build_vsync_cmd)
1148
1149 static void its_send_int(struct its_device *dev, u32 event_id)
1150 {
1151         struct its_cmd_desc desc;
1152
1153         desc.its_int_cmd.dev = dev;
1154         desc.its_int_cmd.event_id = event_id;
1155
1156         its_send_single_command(dev->its, its_build_int_cmd, &desc);
1157 }
1158
1159 static void its_send_clear(struct its_device *dev, u32 event_id)
1160 {
1161         struct its_cmd_desc desc;
1162
1163         desc.its_clear_cmd.dev = dev;
1164         desc.its_clear_cmd.event_id = event_id;
1165
1166         its_send_single_command(dev->its, its_build_clear_cmd, &desc);
1167 }
1168
1169 static void its_send_inv(struct its_device *dev, u32 event_id)
1170 {
1171         struct its_cmd_desc desc;
1172
1173         desc.its_inv_cmd.dev = dev;
1174         desc.its_inv_cmd.event_id = event_id;
1175
1176         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1177 }
1178
1179 static void its_send_mapd(struct its_device *dev, int valid)
1180 {
1181         struct its_cmd_desc desc;
1182
1183         desc.its_mapd_cmd.dev = dev;
1184         desc.its_mapd_cmd.valid = !!valid;
1185
1186         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1187 }
1188
1189 static void its_send_mapc(struct its_node *its, struct its_collection *col,
1190                           int valid)
1191 {
1192         struct its_cmd_desc desc;
1193
1194         desc.its_mapc_cmd.col = col;
1195         desc.its_mapc_cmd.valid = !!valid;
1196
1197         its_send_single_command(its, its_build_mapc_cmd, &desc);
1198 }
1199
1200 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
1201 {
1202         struct its_cmd_desc desc;
1203
1204         desc.its_mapti_cmd.dev = dev;
1205         desc.its_mapti_cmd.phys_id = irq_id;
1206         desc.its_mapti_cmd.event_id = id;
1207
1208         its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
1209 }
1210
1211 static void its_send_movi(struct its_device *dev,
1212                           struct its_collection *col, u32 id)
1213 {
1214         struct its_cmd_desc desc;
1215
1216         desc.its_movi_cmd.dev = dev;
1217         desc.its_movi_cmd.col = col;
1218         desc.its_movi_cmd.event_id = id;
1219
1220         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1221 }
1222
1223 static void its_send_discard(struct its_device *dev, u32 id)
1224 {
1225         struct its_cmd_desc desc;
1226
1227         desc.its_discard_cmd.dev = dev;
1228         desc.its_discard_cmd.event_id = id;
1229
1230         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1231 }
1232
1233 static void its_send_invall(struct its_node *its, struct its_collection *col)
1234 {
1235         struct its_cmd_desc desc;
1236
1237         desc.its_invall_cmd.col = col;
1238
1239         its_send_single_command(its, its_build_invall_cmd, &desc);
1240 }
1241
1242 static void its_send_vmapti(struct its_device *dev, u32 id)
1243 {
1244         struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1245         struct its_cmd_desc desc;
1246
1247         desc.its_vmapti_cmd.vpe = map->vpe;
1248         desc.its_vmapti_cmd.dev = dev;
1249         desc.its_vmapti_cmd.virt_id = map->vintid;
1250         desc.its_vmapti_cmd.event_id = id;
1251         desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1252
1253         its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1254 }
1255
1256 static void its_send_vmovi(struct its_device *dev, u32 id)
1257 {
1258         struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
1259         struct its_cmd_desc desc;
1260
1261         desc.its_vmovi_cmd.vpe = map->vpe;
1262         desc.its_vmovi_cmd.dev = dev;
1263         desc.its_vmovi_cmd.event_id = id;
1264         desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1265
1266         its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1267 }
1268
1269 static void its_send_vmapp(struct its_node *its,
1270                            struct its_vpe *vpe, bool valid)
1271 {
1272         struct its_cmd_desc desc;
1273
1274         desc.its_vmapp_cmd.vpe = vpe;
1275         desc.its_vmapp_cmd.valid = valid;
1276         desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
1277
1278         its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
1279 }
1280
1281 static void its_send_vmovp(struct its_vpe *vpe)
1282 {
1283         struct its_cmd_desc desc = {};
1284         struct its_node *its;
1285         unsigned long flags;
1286         int col_id = vpe->col_idx;
1287
1288         desc.its_vmovp_cmd.vpe = vpe;
1289
1290         if (!its_list_map) {
1291                 its = list_first_entry(&its_nodes, struct its_node, entry);
1292                 desc.its_vmovp_cmd.col = &its->collections[col_id];
1293                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1294                 return;
1295         }
1296
1297         /*
1298          * Yet another marvel of the architecture. If using the
1299          * its_list "feature", we need to make sure that all ITSs
1300          * receive all VMOVP commands in the same order. The only way
1301          * to guarantee this is to make vmovp a serialization point.
1302          *
1303          * Wall <-- Head.
1304          */
1305         raw_spin_lock_irqsave(&vmovp_lock, flags);
1306
1307         desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1308         desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
1309
1310         /* Emit VMOVPs */
1311         list_for_each_entry(its, &its_nodes, entry) {
1312                 if (!is_v4(its))
1313                         continue;
1314
1315                 if (!require_its_list_vmovp(vpe->its_vm, its))
1316                         continue;
1317
1318                 desc.its_vmovp_cmd.col = &its->collections[col_id];
1319                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1320         }
1321
1322         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1323 }
1324
1325 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1326 {
1327         struct its_cmd_desc desc;
1328
1329         desc.its_vinvall_cmd.vpe = vpe;
1330         its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1331 }
1332
1333 static void its_send_vinv(struct its_device *dev, u32 event_id)
1334 {
1335         struct its_cmd_desc desc;
1336
1337         /*
1338          * There is no real VINV command. This is just a normal INV,
1339          * with a VSYNC instead of a SYNC.
1340          */
1341         desc.its_inv_cmd.dev = dev;
1342         desc.its_inv_cmd.event_id = event_id;
1343
1344         its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1345 }
1346
1347 static void its_send_vint(struct its_device *dev, u32 event_id)
1348 {
1349         struct its_cmd_desc desc;
1350
1351         /*
1352          * There is no real VINT command. This is just a normal INT,
1353          * with a VSYNC instead of a SYNC.
1354          */
1355         desc.its_int_cmd.dev = dev;
1356         desc.its_int_cmd.event_id = event_id;
1357
1358         its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1359 }
1360
1361 static void its_send_vclear(struct its_device *dev, u32 event_id)
1362 {
1363         struct its_cmd_desc desc;
1364
1365         /*
1366          * There is no real VCLEAR command. This is just a normal CLEAR,
1367          * with a VSYNC instead of a SYNC.
1368          */
1369         desc.its_clear_cmd.dev = dev;
1370         desc.its_clear_cmd.event_id = event_id;
1371
1372         its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1373 }
1374
1375 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1376 {
1377         struct its_cmd_desc desc;
1378
1379         desc.its_invdb_cmd.vpe = vpe;
1380         its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1381 }
1382
1383 /*
1384  * irqchip functions - assumes MSI, mostly.
1385  */
1386 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1387 {
1388         struct its_vlpi_map *map = get_vlpi_map(d);
1389         irq_hw_number_t hwirq;
1390         void *va;
1391         u8 *cfg;
1392
1393         if (map) {
1394                 va = page_address(map->vm->vprop_page);
1395                 hwirq = map->vintid;
1396
1397                 /* Remember the updated property */
1398                 map->properties &= ~clr;
1399                 map->properties |= set | LPI_PROP_GROUP1;
1400         } else {
1401                 va = gic_rdists->prop_table_va;
1402                 hwirq = d->hwirq;
1403         }
1404
1405         cfg = va + hwirq - 8192;
1406         *cfg &= ~clr;
1407         *cfg |= set | LPI_PROP_GROUP1;
1408
1409         /*
1410          * Make the above write visible to the redistributors.
1411          * And yes, we're flushing exactly: One. Single. Byte.
1412          * Humpf...
1413          */
1414         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1415                 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1416         else
1417                 dsb(ishst);
1418 }
1419
1420 static void wait_for_syncr(void __iomem *rdbase)
1421 {
1422         while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
1423                 cpu_relax();
1424 }
1425
1426 static void direct_lpi_inv(struct irq_data *d)
1427 {
1428         struct its_vlpi_map *map = get_vlpi_map(d);
1429         void __iomem *rdbase;
1430         unsigned long flags;
1431         u64 val;
1432         int cpu;
1433
1434         if (map) {
1435                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1436
1437                 WARN_ON(!is_v4_1(its_dev->its));
1438
1439                 val  = GICR_INVLPIR_V;
1440                 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1441                 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1442         } else {
1443                 val = d->hwirq;
1444         }
1445
1446         /* Target the redistributor this LPI is currently routed to */
1447         cpu = irq_to_cpuid_lock(d, &flags);
1448         raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
1449         rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
1450         gic_write_lpir(val, rdbase + GICR_INVLPIR);
1451
1452         wait_for_syncr(rdbase);
1453         raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
1454         irq_to_cpuid_unlock(d, flags);
1455 }
1456
1457 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1458 {
1459         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1460
1461         lpi_write_config(d, clr, set);
1462         if (gic_rdists->has_direct_lpi &&
1463             (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
1464                 direct_lpi_inv(d);
1465         else if (!irqd_is_forwarded_to_vcpu(d))
1466                 its_send_inv(its_dev, its_get_event_id(d));
1467         else
1468                 its_send_vinv(its_dev, its_get_event_id(d));
1469 }
1470
1471 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1472 {
1473         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1474         u32 event = its_get_event_id(d);
1475         struct its_vlpi_map *map;
1476
1477         /*
1478          * GICv4.1 does away with the per-LPI nonsense, nothing to do
1479          * here.
1480          */
1481         if (is_v4_1(its_dev->its))
1482                 return;
1483
1484         map = dev_event_to_vlpi_map(its_dev, event);
1485
1486         if (map->db_enabled == enable)
1487                 return;
1488
1489         map->db_enabled = enable;
1490
1491         /*
1492          * More fun with the architecture:
1493          *
1494          * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1495          * value or to 1023, depending on the enable bit. But that
1496          * would be issueing a mapping for an /existing/ DevID+EventID
1497          * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1498          * to the /same/ vPE, using this opportunity to adjust the
1499          * doorbell. Mouahahahaha. We loves it, Precious.
1500          */
1501         its_send_vmovi(its_dev, event);
1502 }
1503
1504 static void its_mask_irq(struct irq_data *d)
1505 {
1506         if (irqd_is_forwarded_to_vcpu(d))
1507                 its_vlpi_set_doorbell(d, false);
1508
1509         lpi_update_config(d, LPI_PROP_ENABLED, 0);
1510 }
1511
1512 static void its_unmask_irq(struct irq_data *d)
1513 {
1514         if (irqd_is_forwarded_to_vcpu(d))
1515                 its_vlpi_set_doorbell(d, true);
1516
1517         lpi_update_config(d, 0, LPI_PROP_ENABLED);
1518 }
1519
1520 static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1521 {
1522         if (irqd_affinity_is_managed(d))
1523                 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1524
1525         return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1526 }
1527
1528 static void its_inc_lpi_count(struct irq_data *d, int cpu)
1529 {
1530         if (irqd_affinity_is_managed(d))
1531                 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1532         else
1533                 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1534 }
1535
1536 static void its_dec_lpi_count(struct irq_data *d, int cpu)
1537 {
1538         if (irqd_affinity_is_managed(d))
1539                 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1540         else
1541                 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1542 }
1543
1544 static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1545                                               const struct cpumask *cpu_mask)
1546 {
1547         unsigned int cpu = nr_cpu_ids, tmp;
1548         int count = S32_MAX;
1549
1550         for_each_cpu(tmp, cpu_mask) {
1551                 int this_count = its_read_lpi_count(d, tmp);
1552                 if (this_count < count) {
1553                         cpu = tmp;
1554                         count = this_count;
1555                 }
1556         }
1557
1558         return cpu;
1559 }
1560
1561 /*
1562  * As suggested by Thomas Gleixner in:
1563  * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1564  */
1565 static int its_select_cpu(struct irq_data *d,
1566                           const struct cpumask *aff_mask)
1567 {
1568         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1569         cpumask_var_t tmpmask;
1570         int cpu, node;
1571
1572         if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
1573                 return -ENOMEM;
1574
1575         node = its_dev->its->numa_node;
1576
1577         if (!irqd_affinity_is_managed(d)) {
1578                 /* First try the NUMA node */
1579                 if (node != NUMA_NO_NODE) {
1580                         /*
1581                          * Try the intersection of the affinity mask and the
1582                          * node mask (and the online mask, just to be safe).
1583                          */
1584                         cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1585                         cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1586
1587                         /*
1588                          * Ideally, we would check if the mask is empty, and
1589                          * try again on the full node here.
1590                          *
1591                          * But it turns out that the way ACPI describes the
1592                          * affinity for ITSs only deals about memory, and
1593                          * not target CPUs, so it cannot describe a single
1594                          * ITS placed next to two NUMA nodes.
1595                          *
1596                          * Instead, just fallback on the online mask. This
1597                          * diverges from Thomas' suggestion above.
1598                          */
1599                         cpu = cpumask_pick_least_loaded(d, tmpmask);
1600                         if (cpu < nr_cpu_ids)
1601                                 goto out;
1602
1603                         /* If we can't cross sockets, give up */
1604                         if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1605                                 goto out;
1606
1607                         /* If the above failed, expand the search */
1608                 }
1609
1610                 /* Try the intersection of the affinity and online masks */
1611                 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1612
1613                 /* If that doesn't fly, the online mask is the last resort */
1614                 if (cpumask_empty(tmpmask))
1615                         cpumask_copy(tmpmask, cpu_online_mask);
1616
1617                 cpu = cpumask_pick_least_loaded(d, tmpmask);
1618         } else {
1619                 cpumask_and(tmpmask, irq_data_get_affinity_mask(d), cpu_online_mask);
1620
1621                 /* If we cannot cross sockets, limit the search to that node */
1622                 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1623                     node != NUMA_NO_NODE)
1624                         cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1625
1626                 cpu = cpumask_pick_least_loaded(d, tmpmask);
1627         }
1628 out:
1629         free_cpumask_var(tmpmask);
1630
1631         pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1632         return cpu;
1633 }
1634
1635 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1636                             bool force)
1637 {
1638         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1639         struct its_collection *target_col;
1640         u32 id = its_get_event_id(d);
1641         int cpu, prev_cpu;
1642
1643         /* A forwarded interrupt should use irq_set_vcpu_affinity */
1644         if (irqd_is_forwarded_to_vcpu(d))
1645                 return -EINVAL;
1646
1647         prev_cpu = its_dev->event_map.col_map[id];
1648         its_dec_lpi_count(d, prev_cpu);
1649
1650         if (!force)
1651                 cpu = its_select_cpu(d, mask_val);
1652         else
1653                 cpu = cpumask_pick_least_loaded(d, mask_val);
1654
1655         if (cpu < 0 || cpu >= nr_cpu_ids)
1656                 goto err;
1657
1658         /* don't set the affinity when the target cpu is same as current one */
1659         if (cpu != prev_cpu) {
1660                 target_col = &its_dev->its->collections[cpu];
1661                 its_send_movi(its_dev, target_col, id);
1662                 its_dev->event_map.col_map[id] = cpu;
1663                 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1664         }
1665
1666         its_inc_lpi_count(d, cpu);
1667
1668         return IRQ_SET_MASK_OK_DONE;
1669
1670 err:
1671         its_inc_lpi_count(d, prev_cpu);
1672         return -EINVAL;
1673 }
1674
1675 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1676 {
1677         struct its_node *its = its_dev->its;
1678
1679         return its->phys_base + GITS_TRANSLATER;
1680 }
1681
1682 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1683 {
1684         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1685         struct its_node *its;
1686         u64 addr;
1687
1688         its = its_dev->its;
1689         addr = its->get_msi_base(its_dev);
1690
1691         msg->address_lo         = lower_32_bits(addr);
1692         msg->address_hi         = upper_32_bits(addr);
1693         msg->data               = its_get_event_id(d);
1694
1695         iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1696 }
1697
1698 static int its_irq_set_irqchip_state(struct irq_data *d,
1699                                      enum irqchip_irq_state which,
1700                                      bool state)
1701 {
1702         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1703         u32 event = its_get_event_id(d);
1704
1705         if (which != IRQCHIP_STATE_PENDING)
1706                 return -EINVAL;
1707
1708         if (irqd_is_forwarded_to_vcpu(d)) {
1709                 if (state)
1710                         its_send_vint(its_dev, event);
1711                 else
1712                         its_send_vclear(its_dev, event);
1713         } else {
1714                 if (state)
1715                         its_send_int(its_dev, event);
1716                 else
1717                         its_send_clear(its_dev, event);
1718         }
1719
1720         return 0;
1721 }
1722
1723 static int its_irq_retrigger(struct irq_data *d)
1724 {
1725         return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
1726 }
1727
1728 /*
1729  * Two favourable cases:
1730  *
1731  * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1732  *     for vSGI delivery
1733  *
1734  * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1735  *     and we're better off mapping all VPEs always
1736  *
1737  * If neither (a) nor (b) is true, then we map vPEs on demand.
1738  *
1739  */
1740 static bool gic_requires_eager_mapping(void)
1741 {
1742         if (!its_list_map || gic_rdists->has_rvpeid)
1743                 return true;
1744
1745         return false;
1746 }
1747
1748 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1749 {
1750         unsigned long flags;
1751
1752         if (gic_requires_eager_mapping())
1753                 return;
1754
1755         raw_spin_lock_irqsave(&vmovp_lock, flags);
1756
1757         /*
1758          * If the VM wasn't mapped yet, iterate over the vpes and get
1759          * them mapped now.
1760          */
1761         vm->vlpi_count[its->list_nr]++;
1762
1763         if (vm->vlpi_count[its->list_nr] == 1) {
1764                 int i;
1765
1766                 for (i = 0; i < vm->nr_vpes; i++) {
1767                         struct its_vpe *vpe = vm->vpes[i];
1768                         struct irq_data *d = irq_get_irq_data(vpe->irq);
1769
1770                         /* Map the VPE to the first possible CPU */
1771                         vpe->col_idx = cpumask_first(cpu_online_mask);
1772                         its_send_vmapp(its, vpe, true);
1773                         its_send_vinvall(its, vpe);
1774                         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1775                 }
1776         }
1777
1778         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1779 }
1780
1781 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1782 {
1783         unsigned long flags;
1784
1785         /* Not using the ITS list? Everything is always mapped. */
1786         if (gic_requires_eager_mapping())
1787                 return;
1788
1789         raw_spin_lock_irqsave(&vmovp_lock, flags);
1790
1791         if (!--vm->vlpi_count[its->list_nr]) {
1792                 int i;
1793
1794                 for (i = 0; i < vm->nr_vpes; i++)
1795                         its_send_vmapp(its, vm->vpes[i], false);
1796         }
1797
1798         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1799 }
1800
1801 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1802 {
1803         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1804         u32 event = its_get_event_id(d);
1805         int ret = 0;
1806
1807         if (!info->map)
1808                 return -EINVAL;
1809
1810         raw_spin_lock(&its_dev->event_map.vlpi_lock);
1811
1812         if (!its_dev->event_map.vm) {
1813                 struct its_vlpi_map *maps;
1814
1815                 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1816                                GFP_ATOMIC);
1817                 if (!maps) {
1818                         ret = -ENOMEM;
1819                         goto out;
1820                 }
1821
1822                 its_dev->event_map.vm = info->map->vm;
1823                 its_dev->event_map.vlpi_maps = maps;
1824         } else if (its_dev->event_map.vm != info->map->vm) {
1825                 ret = -EINVAL;
1826                 goto out;
1827         }
1828
1829         /* Get our private copy of the mapping information */
1830         its_dev->event_map.vlpi_maps[event] = *info->map;
1831
1832         if (irqd_is_forwarded_to_vcpu(d)) {
1833                 /* Already mapped, move it around */
1834                 its_send_vmovi(its_dev, event);
1835         } else {
1836                 /* Ensure all the VPEs are mapped on this ITS */
1837                 its_map_vm(its_dev->its, info->map->vm);
1838
1839                 /*
1840                  * Flag the interrupt as forwarded so that we can
1841                  * start poking the virtual property table.
1842                  */
1843                 irqd_set_forwarded_to_vcpu(d);
1844
1845                 /* Write out the property to the prop table */
1846                 lpi_write_config(d, 0xff, info->map->properties);
1847
1848                 /* Drop the physical mapping */
1849                 its_send_discard(its_dev, event);
1850
1851                 /* and install the virtual one */
1852                 its_send_vmapti(its_dev, event);
1853
1854                 /* Increment the number of VLPIs */
1855                 its_dev->event_map.nr_vlpis++;
1856         }
1857
1858 out:
1859         raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1860         return ret;
1861 }
1862
1863 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1864 {
1865         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1866         struct its_vlpi_map *map;
1867         int ret = 0;
1868
1869         raw_spin_lock(&its_dev->event_map.vlpi_lock);
1870
1871         map = get_vlpi_map(d);
1872
1873         if (!its_dev->event_map.vm || !map) {
1874                 ret = -EINVAL;
1875                 goto out;
1876         }
1877
1878         /* Copy our mapping information to the incoming request */
1879         *info->map = *map;
1880
1881 out:
1882         raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1883         return ret;
1884 }
1885
1886 static int its_vlpi_unmap(struct irq_data *d)
1887 {
1888         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1889         u32 event = its_get_event_id(d);
1890         int ret = 0;
1891
1892         raw_spin_lock(&its_dev->event_map.vlpi_lock);
1893
1894         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1895                 ret = -EINVAL;
1896                 goto out;
1897         }
1898
1899         /* Drop the virtual mapping */
1900         its_send_discard(its_dev, event);
1901
1902         /* and restore the physical one */
1903         irqd_clr_forwarded_to_vcpu(d);
1904         its_send_mapti(its_dev, d->hwirq, event);
1905         lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1906                                     LPI_PROP_ENABLED |
1907                                     LPI_PROP_GROUP1));
1908
1909         /* Potentially unmap the VM from this ITS */
1910         its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1911
1912         /*
1913          * Drop the refcount and make the device available again if
1914          * this was the last VLPI.
1915          */
1916         if (!--its_dev->event_map.nr_vlpis) {
1917                 its_dev->event_map.vm = NULL;
1918                 kfree(its_dev->event_map.vlpi_maps);
1919         }
1920
1921 out:
1922         raw_spin_unlock(&its_dev->event_map.vlpi_lock);
1923         return ret;
1924 }
1925
1926 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1927 {
1928         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1929
1930         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1931                 return -EINVAL;
1932
1933         if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1934                 lpi_update_config(d, 0xff, info->config);
1935         else
1936                 lpi_write_config(d, 0xff, info->config);
1937         its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1938
1939         return 0;
1940 }
1941
1942 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1943 {
1944         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1945         struct its_cmd_info *info = vcpu_info;
1946
1947         /* Need a v4 ITS */
1948         if (!is_v4(its_dev->its))
1949                 return -EINVAL;
1950
1951         /* Unmap request? */
1952         if (!info)
1953                 return its_vlpi_unmap(d);
1954
1955         switch (info->cmd_type) {
1956         case MAP_VLPI:
1957                 return its_vlpi_map(d, info);
1958
1959         case GET_VLPI:
1960                 return its_vlpi_get(d, info);
1961
1962         case PROP_UPDATE_VLPI:
1963         case PROP_UPDATE_AND_INV_VLPI:
1964                 return its_vlpi_prop_update(d, info);
1965
1966         default:
1967                 return -EINVAL;
1968         }
1969 }
1970
1971 static struct irq_chip its_irq_chip = {
1972         .name                   = "ITS",
1973         .irq_mask               = its_mask_irq,
1974         .irq_unmask             = its_unmask_irq,
1975         .irq_eoi                = irq_chip_eoi_parent,
1976         .irq_set_affinity       = its_set_affinity,
1977         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
1978         .irq_set_irqchip_state  = its_irq_set_irqchip_state,
1979         .irq_retrigger          = its_irq_retrigger,
1980         .irq_set_vcpu_affinity  = its_irq_set_vcpu_affinity,
1981 };
1982
1983
1984 /*
1985  * How we allocate LPIs:
1986  *
1987  * lpi_range_list contains ranges of LPIs that are to available to
1988  * allocate from. To allocate LPIs, just pick the first range that
1989  * fits the required allocation, and reduce it by the required
1990  * amount. Once empty, remove the range from the list.
1991  *
1992  * To free a range of LPIs, add a free range to the list, sort it and
1993  * merge the result if the new range happens to be adjacent to an
1994  * already free block.
1995  *
1996  * The consequence of the above is that allocation is cost is low, but
1997  * freeing is expensive. We assumes that freeing rarely occurs.
1998  */
1999 #define ITS_MAX_LPI_NRBITS      16 /* 64K LPIs */
2000
2001 static DEFINE_MUTEX(lpi_range_lock);
2002 static LIST_HEAD(lpi_range_list);
2003
2004 struct lpi_range {
2005         struct list_head        entry;
2006         u32                     base_id;
2007         u32                     span;
2008 };
2009
2010 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
2011 {
2012         struct lpi_range *range;
2013
2014         range = kmalloc(sizeof(*range), GFP_KERNEL);
2015         if (range) {
2016                 range->base_id = base;
2017                 range->span = span;
2018         }
2019
2020         return range;
2021 }
2022
2023 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2024 {
2025         struct lpi_range *range, *tmp;
2026         int err = -ENOSPC;
2027
2028         mutex_lock(&lpi_range_lock);
2029
2030         list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2031                 if (range->span >= nr_lpis) {
2032                         *base = range->base_id;
2033                         range->base_id += nr_lpis;
2034                         range->span -= nr_lpis;
2035
2036                         if (range->span == 0) {
2037                                 list_del(&range->entry);
2038                                 kfree(range);
2039                         }
2040
2041                         err = 0;
2042                         break;
2043                 }
2044         }
2045
2046         mutex_unlock(&lpi_range_lock);
2047
2048         pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2049         return err;
2050 }
2051
2052 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2053 {
2054         if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2055                 return;
2056         if (a->base_id + a->span != b->base_id)
2057                 return;
2058         b->base_id = a->base_id;
2059         b->span += a->span;
2060         list_del(&a->entry);
2061         kfree(a);
2062 }
2063
2064 static int free_lpi_range(u32 base, u32 nr_lpis)
2065 {
2066         struct lpi_range *new, *old;
2067
2068         new = mk_lpi_range(base, nr_lpis);
2069         if (!new)
2070                 return -ENOMEM;
2071
2072         mutex_lock(&lpi_range_lock);
2073
2074         list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2075                 if (old->base_id < base)
2076                         break;
2077         }
2078         /*
2079          * old is the last element with ->base_id smaller than base,
2080          * so new goes right after it. If there are no elements with
2081          * ->base_id smaller than base, &old->entry ends up pointing
2082          * at the head of the list, and inserting new it the start of
2083          * the list is the right thing to do in that case as well.
2084          */
2085         list_add(&new->entry, &old->entry);
2086         /*
2087          * Now check if we can merge with the preceding and/or
2088          * following ranges.
2089          */
2090         merge_lpi_ranges(old, new);
2091         merge_lpi_ranges(new, list_next_entry(new, entry));
2092
2093         mutex_unlock(&lpi_range_lock);
2094         return 0;
2095 }
2096
2097 static int __init its_lpi_init(u32 id_bits)
2098 {
2099         u32 lpis = (1UL << id_bits) - 8192;
2100         u32 numlpis;
2101         int err;
2102
2103         numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2104
2105         if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2106                 lpis = numlpis;
2107                 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2108                         lpis);
2109         }
2110
2111         /*
2112          * Initializing the allocator is just the same as freeing the
2113          * full range of LPIs.
2114          */
2115         err = free_lpi_range(8192, lpis);
2116         pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2117         return err;
2118 }
2119
2120 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
2121 {
2122         unsigned long *bitmap = NULL;
2123         int err = 0;
2124
2125         do {
2126                 err = alloc_lpi_range(nr_irqs, base);
2127                 if (!err)
2128                         break;
2129
2130                 nr_irqs /= 2;
2131         } while (nr_irqs > 0);
2132
2133         if (!nr_irqs)
2134                 err = -ENOSPC;
2135
2136         if (err)
2137                 goto out;
2138
2139         bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
2140         if (!bitmap)
2141                 goto out;
2142
2143         *nr_ids = nr_irqs;
2144
2145 out:
2146         if (!bitmap)
2147                 *base = *nr_ids = 0;
2148
2149         return bitmap;
2150 }
2151
2152 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
2153 {
2154         WARN_ON(free_lpi_range(base, nr_ids));
2155         kfree(bitmap);
2156 }
2157
2158 static void gic_reset_prop_table(void *va)
2159 {
2160         /* Priority 0xa0, Group-1, disabled */
2161         memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2162
2163         /* Make sure the GIC will observe the written configuration */
2164         gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2165 }
2166
2167 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2168 {
2169         struct page *prop_page;
2170
2171         prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2172         if (!prop_page)
2173                 return NULL;
2174
2175         gic_reset_prop_table(page_address(prop_page));
2176
2177         return prop_page;
2178 }
2179
2180 static void its_free_prop_table(struct page *prop_page)
2181 {
2182         free_pages((unsigned long)page_address(prop_page),
2183                    get_order(LPI_PROPBASE_SZ));
2184 }
2185
2186 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2187 {
2188         phys_addr_t start, end, addr_end;
2189         u64 i;
2190
2191         /*
2192          * We don't bother checking for a kdump kernel as by
2193          * construction, the LPI tables are out of this kernel's
2194          * memory map.
2195          */
2196         if (is_kdump_kernel())
2197                 return true;
2198
2199         addr_end = addr + size - 1;
2200
2201         for_each_reserved_mem_range(i, &start, &end) {
2202                 if (addr >= start && addr_end <= end)
2203                         return true;
2204         }
2205
2206         /* Not found, not a good sign... */
2207         pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2208                 &addr, &addr_end);
2209         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2210         return false;
2211 }
2212
2213 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2214 {
2215         if (efi_enabled(EFI_CONFIG_TABLES))
2216                 return efi_mem_reserve_persistent(addr, size);
2217
2218         return 0;
2219 }
2220
2221 static int __init its_setup_lpi_prop_table(void)
2222 {
2223         if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2224                 u64 val;
2225
2226                 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2227                 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2228
2229                 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2230                 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2231                                                      LPI_PROPBASE_SZ,
2232                                                      MEMREMAP_WB);
2233                 gic_reset_prop_table(gic_rdists->prop_table_va);
2234         } else {
2235                 struct page *page;
2236
2237                 lpi_id_bits = min_t(u32,
2238                                     GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2239                                     ITS_MAX_LPI_NRBITS);
2240                 page = its_allocate_prop_table(GFP_NOWAIT);
2241                 if (!page) {
2242                         pr_err("Failed to allocate PROPBASE\n");
2243                         return -ENOMEM;
2244                 }
2245
2246                 gic_rdists->prop_table_pa = page_to_phys(page);
2247                 gic_rdists->prop_table_va = page_address(page);
2248                 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2249                                           LPI_PROPBASE_SZ));
2250         }
2251
2252         pr_info("GICv3: using LPI property table @%pa\n",
2253                 &gic_rdists->prop_table_pa);
2254
2255         return its_lpi_init(lpi_id_bits);
2256 }
2257
2258 static const char *its_base_type_string[] = {
2259         [GITS_BASER_TYPE_DEVICE]        = "Devices",
2260         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
2261         [GITS_BASER_TYPE_RESERVED3]     = "Reserved (3)",
2262         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
2263         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
2264         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
2265         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
2266 };
2267
2268 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2269 {
2270         u32 idx = baser - its->tables;
2271
2272         return gits_read_baser(its->base + GITS_BASER + (idx << 3));
2273 }
2274
2275 static void its_write_baser(struct its_node *its, struct its_baser *baser,
2276                             u64 val)
2277 {
2278         u32 idx = baser - its->tables;
2279
2280         gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
2281         baser->val = its_read_baser(its, baser);
2282 }
2283
2284 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
2285                            u64 cache, u64 shr, u32 order, bool indirect)
2286 {
2287         u64 val = its_read_baser(its, baser);
2288         u64 esz = GITS_BASER_ENTRY_SIZE(val);
2289         u64 type = GITS_BASER_TYPE(val);
2290         u64 baser_phys, tmp;
2291         u32 alloc_pages, psz;
2292         struct page *page;
2293         void *base;
2294
2295         psz = baser->psz;
2296         alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2297         if (alloc_pages > GITS_BASER_PAGES_MAX) {
2298                 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2299                         &its->phys_base, its_base_type_string[type],
2300                         alloc_pages, GITS_BASER_PAGES_MAX);
2301                 alloc_pages = GITS_BASER_PAGES_MAX;
2302                 order = get_order(GITS_BASER_PAGES_MAX * psz);
2303         }
2304
2305         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2306         if (!page)
2307                 return -ENOMEM;
2308
2309         base = (void *)page_address(page);
2310         baser_phys = virt_to_phys(base);
2311
2312         /* Check if the physical address of the memory is above 48bits */
2313         if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2314
2315                 /* 52bit PA is supported only when PageSize=64K */
2316                 if (psz != SZ_64K) {
2317                         pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2318                         free_pages((unsigned long)base, order);
2319                         return -ENXIO;
2320                 }
2321
2322                 /* Convert 52bit PA to 48bit field */
2323                 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2324         }
2325
2326 retry_baser:
2327         val = (baser_phys                                        |
2328                 (type << GITS_BASER_TYPE_SHIFT)                  |
2329                 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)       |
2330                 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)    |
2331                 cache                                            |
2332                 shr                                              |
2333                 GITS_BASER_VALID);
2334
2335         val |=  indirect ? GITS_BASER_INDIRECT : 0x0;
2336
2337         switch (psz) {
2338         case SZ_4K:
2339                 val |= GITS_BASER_PAGE_SIZE_4K;
2340                 break;
2341         case SZ_16K:
2342                 val |= GITS_BASER_PAGE_SIZE_16K;
2343                 break;
2344         case SZ_64K:
2345                 val |= GITS_BASER_PAGE_SIZE_64K;
2346                 break;
2347         }
2348
2349         its_write_baser(its, baser, val);
2350         tmp = baser->val;
2351
2352         if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2353                 /*
2354                  * Shareability didn't stick. Just use
2355                  * whatever the read reported, which is likely
2356                  * to be the only thing this redistributor
2357                  * supports. If that's zero, make it
2358                  * non-cacheable as well.
2359                  */
2360                 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2361                 if (!shr) {
2362                         cache = GITS_BASER_nC;
2363                         gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
2364                 }
2365                 goto retry_baser;
2366         }
2367
2368         if (val != tmp) {
2369                 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
2370                        &its->phys_base, its_base_type_string[type],
2371                        val, tmp);
2372                 free_pages((unsigned long)base, order);
2373                 return -ENXIO;
2374         }
2375
2376         baser->order = order;
2377         baser->base = base;
2378         baser->psz = psz;
2379         tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
2380
2381         pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
2382                 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
2383                 its_base_type_string[type],
2384                 (unsigned long)virt_to_phys(base),
2385                 indirect ? "indirect" : "flat", (int)esz,
2386                 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2387
2388         return 0;
2389 }
2390
2391 static bool its_parse_indirect_baser(struct its_node *its,
2392                                      struct its_baser *baser,
2393                                      u32 *order, u32 ids)
2394 {
2395         u64 tmp = its_read_baser(its, baser);
2396         u64 type = GITS_BASER_TYPE(tmp);
2397         u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
2398         u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
2399         u32 new_order = *order;
2400         u32 psz = baser->psz;
2401         bool indirect = false;
2402
2403         /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2404         if ((esz << ids) > (psz * 2)) {
2405                 /*
2406                  * Find out whether hw supports a single or two-level table by
2407                  * table by reading bit at offset '62' after writing '1' to it.
2408                  */
2409                 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2410                 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2411
2412                 if (indirect) {
2413                         /*
2414                          * The size of the lvl2 table is equal to ITS page size
2415                          * which is 'psz'. For computing lvl1 table size,
2416                          * subtract ID bits that sparse lvl2 table from 'ids'
2417                          * which is reported by ITS hardware times lvl1 table
2418                          * entry size.
2419                          */
2420                         ids -= ilog2(psz / (int)esz);
2421                         esz = GITS_LVL1_ENTRY_SIZE;
2422                 }
2423         }
2424
2425         /*
2426          * Allocate as many entries as required to fit the
2427          * range of device IDs that the ITS can grok... The ID
2428          * space being incredibly sparse, this results in a
2429          * massive waste of memory if two-level device table
2430          * feature is not supported by hardware.
2431          */
2432         new_order = max_t(u32, get_order(esz << ids), new_order);
2433         if (new_order >= MAX_ORDER) {
2434                 new_order = MAX_ORDER - 1;
2435                 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
2436                 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
2437                         &its->phys_base, its_base_type_string[type],
2438                         device_ids(its), ids);
2439         }
2440
2441         *order = new_order;
2442
2443         return indirect;
2444 }
2445
2446 static u32 compute_common_aff(u64 val)
2447 {
2448         u32 aff, clpiaff;
2449
2450         aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2451         clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2452
2453         return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2454 }
2455
2456 static u32 compute_its_aff(struct its_node *its)
2457 {
2458         u64 val;
2459         u32 svpet;
2460
2461         /*
2462          * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2463          * the resulting affinity. We then use that to see if this match
2464          * our own affinity.
2465          */
2466         svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2467         val  = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2468         val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2469         return compute_common_aff(val);
2470 }
2471
2472 static struct its_node *find_sibling_its(struct its_node *cur_its)
2473 {
2474         struct its_node *its;
2475         u32 aff;
2476
2477         if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2478                 return NULL;
2479
2480         aff = compute_its_aff(cur_its);
2481
2482         list_for_each_entry(its, &its_nodes, entry) {
2483                 u64 baser;
2484
2485                 if (!is_v4_1(its) || its == cur_its)
2486                         continue;
2487
2488                 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2489                         continue;
2490
2491                 if (aff != compute_its_aff(its))
2492                         continue;
2493
2494                 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2495                 baser = its->tables[2].val;
2496                 if (!(baser & GITS_BASER_VALID))
2497                         continue;
2498
2499                 return its;
2500         }
2501
2502         return NULL;
2503 }
2504
2505 static void its_free_tables(struct its_node *its)
2506 {
2507         int i;
2508
2509         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2510                 if (its->tables[i].base) {
2511                         free_pages((unsigned long)its->tables[i].base,
2512                                    its->tables[i].order);
2513                         its->tables[i].base = NULL;
2514                 }
2515         }
2516 }
2517
2518 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2519 {
2520         u64 psz = SZ_64K;
2521
2522         while (psz) {
2523                 u64 val, gpsz;
2524
2525                 val = its_read_baser(its, baser);
2526                 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2527
2528                 switch (psz) {
2529                 case SZ_64K:
2530                         gpsz = GITS_BASER_PAGE_SIZE_64K;
2531                         break;
2532                 case SZ_16K:
2533                         gpsz = GITS_BASER_PAGE_SIZE_16K;
2534                         break;
2535                 case SZ_4K:
2536                 default:
2537                         gpsz = GITS_BASER_PAGE_SIZE_4K;
2538                         break;
2539                 }
2540
2541                 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2542
2543                 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2544                 its_write_baser(its, baser, val);
2545
2546                 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2547                         break;
2548
2549                 switch (psz) {
2550                 case SZ_64K:
2551                         psz = SZ_16K;
2552                         break;
2553                 case SZ_16K:
2554                         psz = SZ_4K;
2555                         break;
2556                 case SZ_4K:
2557                 default:
2558                         return -1;
2559                 }
2560         }
2561
2562         baser->psz = psz;
2563         return 0;
2564 }
2565
2566 static int its_alloc_tables(struct its_node *its)
2567 {
2568         u64 shr = GITS_BASER_InnerShareable;
2569         u64 cache = GITS_BASER_RaWaWb;
2570         int err, i;
2571
2572         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2573                 /* erratum 24313: ignore memory access type */
2574                 cache = GITS_BASER_nCnB;
2575
2576         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2577                 struct its_baser *baser = its->tables + i;
2578                 u64 val = its_read_baser(its, baser);
2579                 u64 type = GITS_BASER_TYPE(val);
2580                 bool indirect = false;
2581                 u32 order;
2582
2583                 if (type == GITS_BASER_TYPE_NONE)
2584                         continue;
2585
2586                 if (its_probe_baser_psz(its, baser)) {
2587                         its_free_tables(its);
2588                         return -ENXIO;
2589                 }
2590
2591                 order = get_order(baser->psz);
2592
2593                 switch (type) {
2594                 case GITS_BASER_TYPE_DEVICE:
2595                         indirect = its_parse_indirect_baser(its, baser, &order,
2596                                                             device_ids(its));
2597                         break;
2598
2599                 case GITS_BASER_TYPE_VCPU:
2600                         if (is_v4_1(its)) {
2601                                 struct its_node *sibling;
2602
2603                                 WARN_ON(i != 2);
2604                                 if ((sibling = find_sibling_its(its))) {
2605                                         *baser = sibling->tables[2];
2606                                         its_write_baser(its, baser, baser->val);
2607                                         continue;
2608                                 }
2609                         }
2610
2611                         indirect = its_parse_indirect_baser(its, baser, &order,
2612                                                             ITS_MAX_VPEID_BITS);
2613                         break;
2614                 }
2615
2616                 err = its_setup_baser(its, baser, cache, shr, order, indirect);
2617                 if (err < 0) {
2618                         its_free_tables(its);
2619                         return err;
2620                 }
2621
2622                 /* Update settings which will be used for next BASERn */
2623                 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2624                 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
2625         }
2626
2627         return 0;
2628 }
2629
2630 static u64 inherit_vpe_l1_table_from_its(void)
2631 {
2632         struct its_node *its;
2633         u64 val;
2634         u32 aff;
2635
2636         val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2637         aff = compute_common_aff(val);
2638
2639         list_for_each_entry(its, &its_nodes, entry) {
2640                 u64 baser, addr;
2641
2642                 if (!is_v4_1(its))
2643                         continue;
2644
2645                 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2646                         continue;
2647
2648                 if (aff != compute_its_aff(its))
2649                         continue;
2650
2651                 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2652                 baser = its->tables[2].val;
2653                 if (!(baser & GITS_BASER_VALID))
2654                         continue;
2655
2656                 /* We have a winner! */
2657                 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2658
2659                 val  = GICR_VPROPBASER_4_1_VALID;
2660                 if (baser & GITS_BASER_INDIRECT)
2661                         val |= GICR_VPROPBASER_4_1_INDIRECT;
2662                 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2663                                   FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2664                 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2665                 case GIC_PAGE_SIZE_64K:
2666                         addr = GITS_BASER_ADDR_48_to_52(baser);
2667                         break;
2668                 default:
2669                         addr = baser & GENMASK_ULL(47, 12);
2670                         break;
2671                 }
2672                 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2673                 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2674                                   FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2675                 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2676                                   FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2677                 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2678
2679                 return val;
2680         }
2681
2682         return 0;
2683 }
2684
2685 static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2686 {
2687         u32 aff;
2688         u64 val;
2689         int cpu;
2690
2691         val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2692         aff = compute_common_aff(val);
2693
2694         for_each_possible_cpu(cpu) {
2695                 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2696
2697                 if (!base || cpu == smp_processor_id())
2698                         continue;
2699
2700                 val = gic_read_typer(base + GICR_TYPER);
2701                 if (aff != compute_common_aff(val))
2702                         continue;
2703
2704                 /*
2705                  * At this point, we have a victim. This particular CPU
2706                  * has already booted, and has an affinity that matches
2707                  * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2708                  * Make sure we don't write the Z bit in that case.
2709                  */
2710                 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2711                 val &= ~GICR_VPROPBASER_4_1_Z;
2712
2713                 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2714                 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2715
2716                 return val;
2717         }
2718
2719         return 0;
2720 }
2721
2722 static bool allocate_vpe_l2_table(int cpu, u32 id)
2723 {
2724         void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
2725         unsigned int psz, esz, idx, npg, gpsz;
2726         u64 val;
2727         struct page *page;
2728         __le64 *table;
2729
2730         if (!gic_rdists->has_rvpeid)
2731                 return true;
2732
2733         /* Skip non-present CPUs */
2734         if (!base)
2735                 return true;
2736
2737         val  = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
2738
2739         esz  = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2740         gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2741         npg  = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2742
2743         switch (gpsz) {
2744         default:
2745                 WARN_ON(1);
2746                 fallthrough;
2747         case GIC_PAGE_SIZE_4K:
2748                 psz = SZ_4K;
2749                 break;
2750         case GIC_PAGE_SIZE_16K:
2751                 psz = SZ_16K;
2752                 break;
2753         case GIC_PAGE_SIZE_64K:
2754                 psz = SZ_64K;
2755                 break;
2756         }
2757
2758         /* Don't allow vpe_id that exceeds single, flat table limit */
2759         if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2760                 return (id < (npg * psz / (esz * SZ_8)));
2761
2762         /* Compute 1st level table index & check if that exceeds table limit */
2763         idx = id >> ilog2(psz / (esz * SZ_8));
2764         if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2765                 return false;
2766
2767         table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2768
2769         /* Allocate memory for 2nd level table */
2770         if (!table[idx]) {
2771                 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2772                 if (!page)
2773                         return false;
2774
2775                 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2776                 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2777                         gic_flush_dcache_to_poc(page_address(page), psz);
2778
2779                 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2780
2781                 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2782                 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2783                         gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2784
2785                 /* Ensure updated table contents are visible to RD hardware */
2786                 dsb(sy);
2787         }
2788
2789         return true;
2790 }
2791
2792 static int allocate_vpe_l1_table(void)
2793 {
2794         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2795         u64 val, gpsz, npg, pa;
2796         unsigned int psz = SZ_64K;
2797         unsigned int np, epp, esz;
2798         struct page *page;
2799
2800         if (!gic_rdists->has_rvpeid)
2801                 return 0;
2802
2803         /*
2804          * if VPENDBASER.Valid is set, disable any previously programmed
2805          * VPE by setting PendingLast while clearing Valid. This has the
2806          * effect of making sure no doorbell will be generated and we can
2807          * then safely clear VPROPBASER.Valid.
2808          */
2809         if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2810                 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
2811                                       vlpi_base + GICR_VPENDBASER);
2812
2813         /*
2814          * If we can inherit the configuration from another RD, let's do
2815          * so. Otherwise, we have to go through the allocation process. We
2816          * assume that all RDs have the exact same requirements, as
2817          * nothing will work otherwise.
2818          */
2819         val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2820         if (val & GICR_VPROPBASER_4_1_VALID)
2821                 goto out;
2822
2823         gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
2824         if (!gic_data_rdist()->vpe_table_mask)
2825                 return -ENOMEM;
2826
2827         val = inherit_vpe_l1_table_from_its();
2828         if (val & GICR_VPROPBASER_4_1_VALID)
2829                 goto out;
2830
2831         /* First probe the page size */
2832         val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
2833         gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2834         val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
2835         gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2836         esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2837
2838         switch (gpsz) {
2839         default:
2840                 gpsz = GIC_PAGE_SIZE_4K;
2841                 fallthrough;
2842         case GIC_PAGE_SIZE_4K:
2843                 psz = SZ_4K;
2844                 break;
2845         case GIC_PAGE_SIZE_16K:
2846                 psz = SZ_16K;
2847                 break;
2848         case GIC_PAGE_SIZE_64K:
2849                 psz = SZ_64K;
2850                 break;
2851         }
2852
2853         /*
2854          * Start populating the register from scratch, including RO fields
2855          * (which we want to print in debug cases...)
2856          */
2857         val = 0;
2858         val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2859         val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2860
2861         /* How many entries per GIC page? */
2862         esz++;
2863         epp = psz / (esz * SZ_8);
2864
2865         /*
2866          * If we need more than just a single L1 page, flag the table
2867          * as indirect and compute the number of required L1 pages.
2868          */
2869         if (epp < ITS_MAX_VPEID) {
2870                 int nl2;
2871
2872                 val |= GICR_VPROPBASER_4_1_INDIRECT;
2873
2874                 /* Number of L2 pages required to cover the VPEID space */
2875                 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2876
2877                 /* Number of L1 pages to point to the L2 pages */
2878                 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2879         } else {
2880                 npg = 1;
2881         }
2882
2883         val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
2884
2885         /* Right, that's the number of CPU pages we need for L1 */
2886         np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2887
2888         pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2889                  np, npg, psz, epp, esz);
2890         page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
2891         if (!page)
2892                 return -ENOMEM;
2893
2894         gic_data_rdist()->vpe_l1_base = page_address(page);
2895         pa = virt_to_phys(page_address(page));
2896         WARN_ON(!IS_ALIGNED(pa, psz));
2897
2898         val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2899         val |= GICR_VPROPBASER_RaWb;
2900         val |= GICR_VPROPBASER_InnerShareable;
2901         val |= GICR_VPROPBASER_4_1_Z;
2902         val |= GICR_VPROPBASER_4_1_VALID;
2903
2904 out:
2905         gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2906         cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2907
2908         pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2909                  smp_processor_id(), val,
2910                  cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2911
2912         return 0;
2913 }
2914
2915 static int its_alloc_collections(struct its_node *its)
2916 {
2917         int i;
2918
2919         its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
2920                                    GFP_KERNEL);
2921         if (!its->collections)
2922                 return -ENOMEM;
2923
2924         for (i = 0; i < nr_cpu_ids; i++)
2925                 its->collections[i].target_address = ~0ULL;
2926
2927         return 0;
2928 }
2929
2930 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2931 {
2932         struct page *pend_page;
2933
2934         pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2935                                 get_order(LPI_PENDBASE_SZ));
2936         if (!pend_page)
2937                 return NULL;
2938
2939         /* Make sure the GIC will observe the zero-ed page */
2940         gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2941
2942         return pend_page;
2943 }
2944
2945 static void its_free_pending_table(struct page *pt)
2946 {
2947         free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2948 }
2949
2950 /*
2951  * Booting with kdump and LPIs enabled is generally fine. Any other
2952  * case is wrong in the absence of firmware/EFI support.
2953  */
2954 static bool enabled_lpis_allowed(void)
2955 {
2956         phys_addr_t addr;
2957         u64 val;
2958
2959         /* Check whether the property table is in a reserved region */
2960         val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2961         addr = val & GENMASK_ULL(51, 12);
2962
2963         return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2964 }
2965
2966 static int __init allocate_lpi_tables(void)
2967 {
2968         u64 val;
2969         int err, cpu;
2970
2971         /*
2972          * If LPIs are enabled while we run this from the boot CPU,
2973          * flag the RD tables as pre-allocated if the stars do align.
2974          */
2975         val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2976         if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2977                 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2978                                       RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2979                 pr_info("GICv3: Using preallocated redistributor tables\n");
2980         }
2981
2982         err = its_setup_lpi_prop_table();
2983         if (err)
2984                 return err;
2985
2986         /*
2987          * We allocate all the pending tables anyway, as we may have a
2988          * mix of RDs that have had LPIs enabled, and some that
2989          * don't. We'll free the unused ones as each CPU comes online.
2990          */
2991         for_each_possible_cpu(cpu) {
2992                 struct page *pend_page;
2993
2994                 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2995                 if (!pend_page) {
2996                         pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2997                         return -ENOMEM;
2998                 }
2999
3000                 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3001         }
3002
3003         return 0;
3004 }
3005
3006 static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
3007 {
3008         u32 count = 1000000;    /* 1s! */
3009         bool clean;
3010         u64 val;
3011
3012         val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3013         val &= ~GICR_VPENDBASER_Valid;
3014         val &= ~clr;
3015         val |= set;
3016         gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3017
3018         do {
3019                 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
3020                 clean = !(val & GICR_VPENDBASER_Dirty);
3021                 if (!clean) {
3022                         count--;
3023                         cpu_relax();
3024                         udelay(1);
3025                 }
3026         } while (!clean && count);
3027
3028         if (unlikely(val & GICR_VPENDBASER_Dirty)) {
3029                 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3030                 val |= GICR_VPENDBASER_PendingLast;
3031         }
3032
3033         return val;
3034 }
3035
3036 static void its_cpu_init_lpis(void)
3037 {
3038         void __iomem *rbase = gic_data_rdist_rd_base();
3039         struct page *pend_page;
3040         phys_addr_t paddr;
3041         u64 val, tmp;
3042
3043         if (gic_data_rdist()->lpi_enabled)
3044                 return;
3045
3046         val = readl_relaxed(rbase + GICR_CTLR);
3047         if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3048             (val & GICR_CTLR_ENABLE_LPIS)) {
3049                 /*
3050                  * Check that we get the same property table on all
3051                  * RDs. If we don't, this is hopeless.
3052                  */
3053                 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3054                 paddr &= GENMASK_ULL(51, 12);
3055                 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3056                         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3057
3058                 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3059                 paddr &= GENMASK_ULL(51, 16);
3060
3061                 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
3062                 its_free_pending_table(gic_data_rdist()->pend_page);
3063                 gic_data_rdist()->pend_page = NULL;
3064
3065                 goto out;
3066         }
3067
3068         pend_page = gic_data_rdist()->pend_page;
3069         paddr = page_to_phys(pend_page);
3070         WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
3071
3072         /* set PROPBASE */
3073         val = (gic_rdists->prop_table_pa |
3074                GICR_PROPBASER_InnerShareable |
3075                GICR_PROPBASER_RaWaWb |
3076                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3077
3078         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3079         tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
3080
3081         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
3082                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3083                         /*
3084                          * The HW reports non-shareable, we must
3085                          * remove the cacheability attributes as
3086                          * well.
3087                          */
3088                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3089                                  GICR_PROPBASER_CACHEABILITY_MASK);
3090                         val |= GICR_PROPBASER_nC;
3091                         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3092                 }
3093                 pr_info_once("GIC: using cache flushing for LPI property table\n");
3094                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3095         }
3096
3097         /* set PENDBASE */
3098         val = (page_to_phys(pend_page) |
3099                GICR_PENDBASER_InnerShareable |
3100                GICR_PENDBASER_RaWaWb);
3101
3102         gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3103         tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3104
3105         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3106                 /*
3107                  * The HW reports non-shareable, we must remove the
3108                  * cacheability attributes as well.
3109                  */
3110                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3111                          GICR_PENDBASER_CACHEABILITY_MASK);
3112                 val |= GICR_PENDBASER_nC;
3113                 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3114         }
3115
3116         /* Enable LPIs */
3117         val = readl_relaxed(rbase + GICR_CTLR);
3118         val |= GICR_CTLR_ENABLE_LPIS;
3119         writel_relaxed(val, rbase + GICR_CTLR);
3120
3121         if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
3122                 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3123
3124                 /*
3125                  * It's possible for CPU to receive VLPIs before it is
3126                  * sheduled as a vPE, especially for the first CPU, and the
3127                  * VLPI with INTID larger than 2^(IDbits+1) will be considered
3128                  * as out of range and dropped by GIC.
3129                  * So we initialize IDbits to known value to avoid VLPI drop.
3130                  */
3131                 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3132                 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3133                         smp_processor_id(), val);
3134                 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3135
3136                 /*
3137                  * Also clear Valid bit of GICR_VPENDBASER, in case some
3138                  * ancient programming gets left in and has possibility of
3139                  * corrupting memory.
3140                  */
3141                 val = its_clear_vpend_valid(vlpi_base, 0, 0);
3142         }
3143
3144         if (allocate_vpe_l1_table()) {
3145                 /*
3146                  * If the allocation has failed, we're in massive trouble.
3147                  * Disable direct injection, and pray that no VM was
3148                  * already running...
3149                  */
3150                 gic_rdists->has_rvpeid = false;
3151                 gic_rdists->has_vlpis = false;
3152         }
3153
3154         /* Make sure the GIC has seen the above */
3155         dsb(sy);
3156 out:
3157         gic_data_rdist()->lpi_enabled = true;
3158         pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
3159                 smp_processor_id(),
3160                 gic_data_rdist()->pend_page ? "allocated" : "reserved",
3161                 &paddr);
3162 }
3163
3164 static void its_cpu_init_collection(struct its_node *its)
3165 {
3166         int cpu = smp_processor_id();
3167         u64 target;
3168
3169         /* avoid cross node collections and its mapping */
3170         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3171                 struct device_node *cpu_node;
3172
3173                 cpu_node = of_get_cpu_node(cpu, NULL);
3174                 if (its->numa_node != NUMA_NO_NODE &&
3175                         its->numa_node != of_node_to_nid(cpu_node))
3176                         return;
3177         }
3178
3179         /*
3180          * We now have to bind each collection to its target
3181          * redistributor.
3182          */
3183         if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
3184                 /*
3185                  * This ITS wants the physical address of the
3186                  * redistributor.
3187                  */
3188                 target = gic_data_rdist()->phys_base;
3189         } else {
3190                 /* This ITS wants a linear CPU number. */
3191                 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3192                 target = GICR_TYPER_CPU_NUMBER(target) << 16;
3193         }
3194
3195         /* Perform collection mapping */
3196         its->collections[cpu].target_address = target;
3197         its->collections[cpu].col_id = cpu;
3198
3199         its_send_mapc(its, &its->collections[cpu], 1);
3200         its_send_invall(its, &its->collections[cpu]);
3201 }
3202
3203 static void its_cpu_init_collections(void)
3204 {
3205         struct its_node *its;
3206
3207         raw_spin_lock(&its_lock);
3208
3209         list_for_each_entry(its, &its_nodes, entry)
3210                 its_cpu_init_collection(its);
3211
3212         raw_spin_unlock(&its_lock);
3213 }
3214
3215 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3216 {
3217         struct its_device *its_dev = NULL, *tmp;
3218         unsigned long flags;
3219
3220         raw_spin_lock_irqsave(&its->lock, flags);
3221
3222         list_for_each_entry(tmp, &its->its_device_list, entry) {
3223                 if (tmp->device_id == dev_id) {
3224                         its_dev = tmp;
3225                         break;
3226                 }
3227         }
3228
3229         raw_spin_unlock_irqrestore(&its->lock, flags);
3230
3231         return its_dev;
3232 }
3233
3234 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3235 {
3236         int i;
3237
3238         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3239                 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3240                         return &its->tables[i];
3241         }
3242
3243         return NULL;
3244 }
3245
3246 static bool its_alloc_table_entry(struct its_node *its,
3247                                   struct its_baser *baser, u32 id)
3248 {
3249         struct page *page;
3250         u32 esz, idx;
3251         __le64 *table;
3252
3253         /* Don't allow device id that exceeds single, flat table limit */
3254         esz = GITS_BASER_ENTRY_SIZE(baser->val);
3255         if (!(baser->val & GITS_BASER_INDIRECT))
3256                 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
3257
3258         /* Compute 1st level table index & check if that exceeds table limit */
3259         idx = id >> ilog2(baser->psz / esz);
3260         if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3261                 return false;
3262
3263         table = baser->base;
3264
3265         /* Allocate memory for 2nd level table */
3266         if (!table[idx]) {
3267                 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3268                                         get_order(baser->psz));
3269                 if (!page)
3270                         return false;
3271
3272                 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3273                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3274                         gic_flush_dcache_to_poc(page_address(page), baser->psz);
3275
3276                 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3277
3278                 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3279                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
3280                         gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
3281
3282                 /* Ensure updated table contents are visible to ITS hardware */
3283                 dsb(sy);
3284         }
3285
3286         return true;
3287 }
3288
3289 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3290 {
3291         struct its_baser *baser;
3292
3293         baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3294
3295         /* Don't allow device id that exceeds ITS hardware limit */
3296         if (!baser)
3297                 return (ilog2(dev_id) < device_ids(its));
3298
3299         return its_alloc_table_entry(its, baser, dev_id);
3300 }
3301
3302 static bool its_alloc_vpe_table(u32 vpe_id)
3303 {
3304         struct its_node *its;
3305         int cpu;
3306
3307         /*
3308          * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3309          * could try and only do it on ITSs corresponding to devices
3310          * that have interrupts targeted at this VPE, but the
3311          * complexity becomes crazy (and you have tons of memory
3312          * anyway, right?).
3313          */
3314         list_for_each_entry(its, &its_nodes, entry) {
3315                 struct its_baser *baser;
3316
3317                 if (!is_v4(its))
3318                         continue;
3319
3320                 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3321                 if (!baser)
3322                         return false;
3323
3324                 if (!its_alloc_table_entry(its, baser, vpe_id))
3325                         return false;
3326         }
3327
3328         /* Non v4.1? No need to iterate RDs and go back early. */
3329         if (!gic_rdists->has_rvpeid)
3330                 return true;
3331
3332         /*
3333          * Make sure the L2 tables are allocated for all copies of
3334          * the L1 table on *all* v4.1 RDs.
3335          */
3336         for_each_possible_cpu(cpu) {
3337                 if (!allocate_vpe_l2_table(cpu, vpe_id))
3338                         return false;
3339         }
3340
3341         return true;
3342 }
3343
3344 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
3345                                             int nvecs, bool alloc_lpis)
3346 {
3347         struct its_device *dev;
3348         unsigned long *lpi_map = NULL;
3349         unsigned long flags;
3350         u16 *col_map = NULL;
3351         void *itt;
3352         int lpi_base;
3353         int nr_lpis;
3354         int nr_ites;
3355         int sz;
3356
3357         if (!its_alloc_device_table(its, dev_id))
3358                 return NULL;
3359
3360         if (WARN_ON(!is_power_of_2(nvecs)))
3361                 nvecs = roundup_pow_of_two(nvecs);
3362
3363         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3364         /*
3365          * Even if the device wants a single LPI, the ITT must be
3366          * sized as a power of two (and you need at least one bit...).
3367          */
3368         nr_ites = max(2, nvecs);
3369         sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
3370         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
3371         itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
3372         if (alloc_lpis) {
3373                 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
3374                 if (lpi_map)
3375                         col_map = kcalloc(nr_lpis, sizeof(*col_map),
3376                                           GFP_KERNEL);
3377         } else {
3378                 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
3379                 nr_lpis = 0;
3380                 lpi_base = 0;
3381         }
3382
3383         if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
3384                 kfree(dev);
3385                 kfree(itt);
3386                 kfree(lpi_map);
3387                 kfree(col_map);
3388                 return NULL;
3389         }
3390
3391         gic_flush_dcache_to_poc(itt, sz);
3392
3393         dev->its = its;
3394         dev->itt = itt;
3395         dev->nr_ites = nr_ites;
3396         dev->event_map.lpi_map = lpi_map;
3397         dev->event_map.col_map = col_map;
3398         dev->event_map.lpi_base = lpi_base;
3399         dev->event_map.nr_lpis = nr_lpis;
3400         raw_spin_lock_init(&dev->event_map.vlpi_lock);
3401         dev->device_id = dev_id;
3402         INIT_LIST_HEAD(&dev->entry);
3403
3404         raw_spin_lock_irqsave(&its->lock, flags);
3405         list_add(&dev->entry, &its->its_device_list);
3406         raw_spin_unlock_irqrestore(&its->lock, flags);
3407
3408         /* Map device to its ITT */
3409         its_send_mapd(dev, 1);
3410
3411         return dev;
3412 }
3413
3414 static void its_free_device(struct its_device *its_dev)
3415 {
3416         unsigned long flags;
3417
3418         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
3419         list_del(&its_dev->entry);
3420         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
3421         kfree(its_dev->event_map.col_map);
3422         kfree(its_dev->itt);
3423         kfree(its_dev);
3424 }
3425
3426 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
3427 {
3428         int idx;
3429
3430         /* Find a free LPI region in lpi_map and allocate them. */
3431         idx = bitmap_find_free_region(dev->event_map.lpi_map,
3432                                       dev->event_map.nr_lpis,
3433                                       get_count_order(nvecs));
3434         if (idx < 0)
3435                 return -ENOSPC;
3436
3437         *hwirq = dev->event_map.lpi_base + idx;
3438
3439         return 0;
3440 }
3441
3442 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3443                            int nvec, msi_alloc_info_t *info)
3444 {
3445         struct its_node *its;
3446         struct its_device *its_dev;
3447         struct msi_domain_info *msi_info;
3448         u32 dev_id;
3449         int err = 0;
3450
3451         /*
3452          * We ignore "dev" entirely, and rely on the dev_id that has
3453          * been passed via the scratchpad. This limits this domain's
3454          * usefulness to upper layers that definitely know that they
3455          * are built on top of the ITS.
3456          */
3457         dev_id = info->scratchpad[0].ul;
3458
3459         msi_info = msi_get_domain_info(domain);
3460         its = msi_info->data;
3461
3462         if (!gic_rdists->has_direct_lpi &&
3463             vpe_proxy.dev &&
3464             vpe_proxy.dev->its == its &&
3465             dev_id == vpe_proxy.dev->device_id) {
3466                 /* Bad luck. Get yourself a better implementation */
3467                 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3468                           dev_id);
3469                 return -EINVAL;
3470         }
3471
3472         mutex_lock(&its->dev_alloc_lock);
3473         its_dev = its_find_device(its, dev_id);
3474         if (its_dev) {
3475                 /*
3476                  * We already have seen this ID, probably through
3477                  * another alias (PCI bridge of some sort). No need to
3478                  * create the device.
3479                  */
3480                 its_dev->shared = true;
3481                 pr_debug("Reusing ITT for devID %x\n", dev_id);
3482                 goto out;
3483         }
3484
3485         its_dev = its_create_device(its, dev_id, nvec, true);
3486         if (!its_dev) {
3487                 err = -ENOMEM;
3488                 goto out;
3489         }
3490
3491         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
3492 out:
3493         mutex_unlock(&its->dev_alloc_lock);
3494         info->scratchpad[0].ptr = its_dev;
3495         return err;
3496 }
3497
3498 static struct msi_domain_ops its_msi_domain_ops = {
3499         .msi_prepare    = its_msi_prepare,
3500 };
3501
3502 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3503                                     unsigned int virq,
3504                                     irq_hw_number_t hwirq)
3505 {
3506         struct irq_fwspec fwspec;
3507
3508         if (irq_domain_get_of_node(domain->parent)) {
3509                 fwspec.fwnode = domain->parent->fwnode;
3510                 fwspec.param_count = 3;
3511                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3512                 fwspec.param[1] = hwirq;
3513                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
3514         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3515                 fwspec.fwnode = domain->parent->fwnode;
3516                 fwspec.param_count = 2;
3517                 fwspec.param[0] = hwirq;
3518                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
3519         } else {
3520                 return -EINVAL;
3521         }
3522
3523         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
3524 }
3525
3526 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3527                                 unsigned int nr_irqs, void *args)
3528 {
3529         msi_alloc_info_t *info = args;
3530         struct its_device *its_dev = info->scratchpad[0].ptr;
3531         struct its_node *its = its_dev->its;
3532         struct irq_data *irqd;
3533         irq_hw_number_t hwirq;
3534         int err;
3535         int i;
3536
3537         err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3538         if (err)
3539                 return err;
3540
3541         err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3542         if (err)
3543                 return err;
3544
3545         for (i = 0; i < nr_irqs; i++) {
3546                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
3547                 if (err)
3548                         return err;
3549
3550                 irq_domain_set_hwirq_and_chip(domain, virq + i,
3551                                               hwirq + i, &its_irq_chip, its_dev);
3552                 irqd = irq_get_irq_data(virq + i);
3553                 irqd_set_single_target(irqd);
3554                 irqd_set_affinity_on_activate(irqd);
3555                 pr_debug("ID:%d pID:%d vID:%d\n",
3556                          (int)(hwirq + i - its_dev->event_map.lpi_base),
3557                          (int)(hwirq + i), virq + i);
3558         }
3559
3560         return 0;
3561 }
3562
3563 static int its_irq_domain_activate(struct irq_domain *domain,
3564                                    struct irq_data *d, bool reserve)
3565 {
3566         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3567         u32 event = its_get_event_id(d);
3568         int cpu;
3569
3570         cpu = its_select_cpu(d, cpu_online_mask);
3571         if (cpu < 0 || cpu >= nr_cpu_ids)
3572                 return -EINVAL;
3573
3574         its_inc_lpi_count(d, cpu);
3575         its_dev->event_map.col_map[event] = cpu;
3576         irq_data_update_effective_affinity(d, cpumask_of(cpu));
3577
3578         /* Map the GIC IRQ and event to the device */
3579         its_send_mapti(its_dev, d->hwirq, event);
3580         return 0;
3581 }
3582
3583 static void its_irq_domain_deactivate(struct irq_domain *domain,
3584                                       struct irq_data *d)
3585 {
3586         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3587         u32 event = its_get_event_id(d);
3588
3589         its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
3590         /* Stop the delivery of interrupts */
3591         its_send_discard(its_dev, event);
3592 }
3593
3594 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3595                                 unsigned int nr_irqs)
3596 {
3597         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3598         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3599         struct its_node *its = its_dev->its;
3600         int i;
3601
3602         bitmap_release_region(its_dev->event_map.lpi_map,
3603                               its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3604                               get_count_order(nr_irqs));
3605
3606         for (i = 0; i < nr_irqs; i++) {
3607                 struct irq_data *data = irq_domain_get_irq_data(domain,
3608                                                                 virq + i);
3609                 /* Nuke the entry in the domain */
3610                 irq_domain_reset_irq_data(data);
3611         }
3612
3613         mutex_lock(&its->dev_alloc_lock);
3614
3615         /*
3616          * If all interrupts have been freed, start mopping the
3617          * floor. This is conditionned on the device not being shared.
3618          */
3619         if (!its_dev->shared &&
3620             bitmap_empty(its_dev->event_map.lpi_map,
3621                          its_dev->event_map.nr_lpis)) {
3622                 its_lpi_free(its_dev->event_map.lpi_map,
3623                              its_dev->event_map.lpi_base,
3624                              its_dev->event_map.nr_lpis);
3625
3626                 /* Unmap device/itt */
3627                 its_send_mapd(its_dev, 0);
3628                 its_free_device(its_dev);
3629         }
3630
3631         mutex_unlock(&its->dev_alloc_lock);
3632
3633         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3634 }
3635
3636 static const struct irq_domain_ops its_domain_ops = {
3637         .alloc                  = its_irq_domain_alloc,
3638         .free                   = its_irq_domain_free,
3639         .activate               = its_irq_domain_activate,
3640         .deactivate             = its_irq_domain_deactivate,
3641 };
3642
3643 /*
3644  * This is insane.
3645  *
3646  * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
3647  * likely), the only way to perform an invalidate is to use a fake
3648  * device to issue an INV command, implying that the LPI has first
3649  * been mapped to some event on that device. Since this is not exactly
3650  * cheap, we try to keep that mapping around as long as possible, and
3651  * only issue an UNMAP if we're short on available slots.
3652  *
3653  * Broken by design(tm).
3654  *
3655  * GICv4.1, on the other hand, mandates that we're able to invalidate
3656  * by writing to a MMIO register. It doesn't implement the whole of
3657  * DirectLPI, but that's good enough. And most of the time, we don't
3658  * even have to invalidate anything, as the redistributor can be told
3659  * whether to generate a doorbell or not (we thus leave it enabled,
3660  * always).
3661  */
3662 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3663 {
3664         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3665         if (gic_rdists->has_rvpeid)
3666                 return;
3667
3668         /* Already unmapped? */
3669         if (vpe->vpe_proxy_event == -1)
3670                 return;
3671
3672         its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3673         vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3674
3675         /*
3676          * We don't track empty slots at all, so let's move the
3677          * next_victim pointer if we can quickly reuse that slot
3678          * instead of nuking an existing entry. Not clear that this is
3679          * always a win though, and this might just generate a ripple
3680          * effect... Let's just hope VPEs don't migrate too often.
3681          */
3682         if (vpe_proxy.vpes[vpe_proxy.next_victim])
3683                 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3684
3685         vpe->vpe_proxy_event = -1;
3686 }
3687
3688 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3689 {
3690         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3691         if (gic_rdists->has_rvpeid)
3692                 return;
3693
3694         if (!gic_rdists->has_direct_lpi) {
3695                 unsigned long flags;
3696
3697                 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3698                 its_vpe_db_proxy_unmap_locked(vpe);
3699                 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3700         }
3701 }
3702
3703 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3704 {
3705         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3706         if (gic_rdists->has_rvpeid)
3707                 return;
3708
3709         /* Already mapped? */
3710         if (vpe->vpe_proxy_event != -1)
3711                 return;
3712
3713         /* This slot was already allocated. Kick the other VPE out. */
3714         if (vpe_proxy.vpes[vpe_proxy.next_victim])
3715                 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3716
3717         /* Map the new VPE instead */
3718         vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3719         vpe->vpe_proxy_event = vpe_proxy.next_victim;
3720         vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3721
3722         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3723         its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3724 }
3725
3726 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3727 {
3728         unsigned long flags;
3729         struct its_collection *target_col;
3730
3731         /* GICv4.1 doesn't use a proxy, so nothing to do here */
3732         if (gic_rdists->has_rvpeid)
3733                 return;
3734
3735         if (gic_rdists->has_direct_lpi) {
3736                 void __iomem *rdbase;
3737
3738                 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3739                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3740                 wait_for_syncr(rdbase);
3741
3742                 return;
3743         }
3744
3745         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3746
3747         its_vpe_db_proxy_map_locked(vpe);
3748
3749         target_col = &vpe_proxy.dev->its->collections[to];
3750         its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3751         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3752
3753         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3754 }
3755
3756 static int its_vpe_set_affinity(struct irq_data *d,
3757                                 const struct cpumask *mask_val,
3758                                 bool force)
3759 {
3760         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3761         int from, cpu = cpumask_first(mask_val);
3762         unsigned long flags;
3763
3764         /*
3765          * Changing affinity is mega expensive, so let's be as lazy as
3766          * we can and only do it if we really have to. Also, if mapped
3767          * into the proxy device, we need to move the doorbell
3768          * interrupt to its new location.
3769          *
3770          * Another thing is that changing the affinity of a vPE affects
3771          * *other interrupts* such as all the vLPIs that are routed to
3772          * this vPE. This means that the irq_desc lock is not enough to
3773          * protect us, and that we must ensure nobody samples vpe->col_idx
3774          * during the update, hence the lock below which must also be
3775          * taken on any vLPI handling path that evaluates vpe->col_idx.
3776          */
3777         from = vpe_to_cpuid_lock(vpe, &flags);
3778         if (from == cpu)
3779                 goto out;
3780
3781         vpe->col_idx = cpu;
3782
3783         /*
3784          * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3785          * is sharing its VPE table with the current one.
3786          */
3787         if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3788             cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3789                 goto out;
3790
3791         its_send_vmovp(vpe);
3792         its_vpe_db_proxy_move(vpe, from, cpu);
3793
3794 out:
3795         irq_data_update_effective_affinity(d, cpumask_of(cpu));
3796         vpe_to_cpuid_unlock(vpe, flags);
3797
3798         return IRQ_SET_MASK_OK_DONE;
3799 }
3800
3801 static void its_wait_vpt_parse_complete(void)
3802 {
3803         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3804         u64 val;
3805
3806         if (!gic_rdists->has_vpend_valid_dirty)
3807                 return;
3808
3809         WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3810                                                        val,
3811                                                        !(val & GICR_VPENDBASER_Dirty),
3812                                                        10, 500));
3813 }
3814
3815 static void its_vpe_schedule(struct its_vpe *vpe)
3816 {
3817         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3818         u64 val;
3819
3820         /* Schedule the VPE */
3821         val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3822                 GENMASK_ULL(51, 12);
3823         val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3824         val |= GICR_VPROPBASER_RaWb;
3825         val |= GICR_VPROPBASER_InnerShareable;
3826         gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
3827
3828         val  = virt_to_phys(page_address(vpe->vpt_page)) &
3829                 GENMASK_ULL(51, 16);
3830         val |= GICR_VPENDBASER_RaWaWb;
3831         val |= GICR_VPENDBASER_InnerShareable;
3832         /*
3833          * There is no good way of finding out if the pending table is
3834          * empty as we can race against the doorbell interrupt very
3835          * easily. So in the end, vpe->pending_last is only an
3836          * indication that the vcpu has something pending, not one
3837          * that the pending table is empty. A good implementation
3838          * would be able to read its coarse map pretty quickly anyway,
3839          * making this a tolerable issue.
3840          */
3841         val |= GICR_VPENDBASER_PendingLast;
3842         val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3843         val |= GICR_VPENDBASER_Valid;
3844         gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
3845
3846         its_wait_vpt_parse_complete();
3847 }
3848
3849 static void its_vpe_deschedule(struct its_vpe *vpe)
3850 {
3851         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3852         u64 val;
3853
3854         val = its_clear_vpend_valid(vlpi_base, 0, 0);
3855
3856         vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3857         vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
3858 }
3859
3860 static void its_vpe_invall(struct its_vpe *vpe)
3861 {
3862         struct its_node *its;
3863
3864         list_for_each_entry(its, &its_nodes, entry) {
3865                 if (!is_v4(its))
3866                         continue;
3867
3868                 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3869                         continue;
3870
3871                 /*
3872                  * Sending a VINVALL to a single ITS is enough, as all
3873                  * we need is to reach the redistributors.
3874                  */
3875                 its_send_vinvall(its, vpe);
3876                 return;
3877         }
3878 }
3879
3880 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3881 {
3882         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3883         struct its_cmd_info *info = vcpu_info;
3884
3885         switch (info->cmd_type) {
3886         case SCHEDULE_VPE:
3887                 its_vpe_schedule(vpe);
3888                 return 0;
3889
3890         case DESCHEDULE_VPE:
3891                 its_vpe_deschedule(vpe);
3892                 return 0;
3893
3894         case INVALL_VPE:
3895                 its_vpe_invall(vpe);
3896                 return 0;
3897
3898         default:
3899                 return -EINVAL;
3900         }
3901 }
3902
3903 static void its_vpe_send_cmd(struct its_vpe *vpe,
3904                              void (*cmd)(struct its_device *, u32))
3905 {
3906         unsigned long flags;
3907
3908         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3909
3910         its_vpe_db_proxy_map_locked(vpe);
3911         cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3912
3913         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3914 }
3915
3916 static void its_vpe_send_inv(struct irq_data *d)
3917 {
3918         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3919
3920         if (gic_rdists->has_direct_lpi) {
3921                 void __iomem *rdbase;
3922
3923                 /* Target the redistributor this VPE is currently known on */
3924                 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3925                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3926                 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
3927                 wait_for_syncr(rdbase);
3928                 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
3929         } else {
3930                 its_vpe_send_cmd(vpe, its_send_inv);
3931         }
3932 }
3933
3934 static void its_vpe_mask_irq(struct irq_data *d)
3935 {
3936         /*
3937          * We need to unmask the LPI, which is described by the parent
3938          * irq_data. Instead of calling into the parent (which won't
3939          * exactly do the right thing, let's simply use the
3940          * parent_data pointer. Yes, I'm naughty.
3941          */
3942         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3943         its_vpe_send_inv(d);
3944 }
3945
3946 static void its_vpe_unmask_irq(struct irq_data *d)
3947 {
3948         /* Same hack as above... */
3949         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3950         its_vpe_send_inv(d);
3951 }
3952
3953 static int its_vpe_set_irqchip_state(struct irq_data *d,
3954                                      enum irqchip_irq_state which,
3955                                      bool state)
3956 {
3957         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3958
3959         if (which != IRQCHIP_STATE_PENDING)
3960                 return -EINVAL;
3961
3962         if (gic_rdists->has_direct_lpi) {
3963                 void __iomem *rdbase;
3964
3965                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3966                 if (state) {
3967                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3968                 } else {
3969                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
3970                         wait_for_syncr(rdbase);
3971                 }
3972         } else {
3973                 if (state)
3974                         its_vpe_send_cmd(vpe, its_send_int);
3975                 else
3976                         its_vpe_send_cmd(vpe, its_send_clear);
3977         }
3978
3979         return 0;
3980 }
3981
3982 static int its_vpe_retrigger(struct irq_data *d)
3983 {
3984         return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
3985 }
3986
3987 static struct irq_chip its_vpe_irq_chip = {
3988         .name                   = "GICv4-vpe",
3989         .irq_mask               = its_vpe_mask_irq,
3990         .irq_unmask             = its_vpe_unmask_irq,
3991         .irq_eoi                = irq_chip_eoi_parent,
3992         .irq_set_affinity       = its_vpe_set_affinity,
3993         .irq_retrigger          = its_vpe_retrigger,
3994         .irq_set_irqchip_state  = its_vpe_set_irqchip_state,
3995         .irq_set_vcpu_affinity  = its_vpe_set_vcpu_affinity,
3996 };
3997
3998 static struct its_node *find_4_1_its(void)
3999 {
4000         static struct its_node *its = NULL;
4001
4002         if (!its) {
4003                 list_for_each_entry(its, &its_nodes, entry) {
4004                         if (is_v4_1(its))
4005                                 return its;
4006                 }
4007
4008                 /* Oops? */
4009                 its = NULL;
4010         }
4011
4012         return its;
4013 }
4014
4015 static void its_vpe_4_1_send_inv(struct irq_data *d)
4016 {
4017         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4018         struct its_node *its;
4019
4020         /*
4021          * GICv4.1 wants doorbells to be invalidated using the
4022          * INVDB command in order to be broadcast to all RDs. Send
4023          * it to the first valid ITS, and let the HW do its magic.
4024          */
4025         its = find_4_1_its();
4026         if (its)
4027                 its_send_invdb(its, vpe);
4028 }
4029
4030 static void its_vpe_4_1_mask_irq(struct irq_data *d)
4031 {
4032         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4033         its_vpe_4_1_send_inv(d);
4034 }
4035
4036 static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4037 {
4038         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4039         its_vpe_4_1_send_inv(d);
4040 }
4041
4042 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4043                                  struct its_cmd_info *info)
4044 {
4045         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4046         u64 val = 0;
4047
4048         /* Schedule the VPE */
4049         val |= GICR_VPENDBASER_Valid;
4050         val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4051         val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4052         val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4053
4054         gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
4055
4056         its_wait_vpt_parse_complete();
4057 }
4058
4059 static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4060                                    struct its_cmd_info *info)
4061 {
4062         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4063         u64 val;
4064
4065         if (info->req_db) {
4066                 unsigned long flags;
4067
4068                 /*
4069                  * vPE is going to block: make the vPE non-resident with
4070                  * PendingLast clear and DB set. The GIC guarantees that if
4071                  * we read-back PendingLast clear, then a doorbell will be
4072                  * delivered when an interrupt comes.
4073                  *
4074                  * Note the locking to deal with the concurrent update of
4075                  * pending_last from the doorbell interrupt handler that can
4076                  * run concurrently.
4077                  */
4078                 raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
4079                 val = its_clear_vpend_valid(vlpi_base,
4080                                             GICR_VPENDBASER_PendingLast,
4081                                             GICR_VPENDBASER_4_1_DB);
4082                 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
4083                 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
4084         } else {
4085                 /*
4086                  * We're not blocking, so just make the vPE non-resident
4087                  * with PendingLast set, indicating that we'll be back.
4088                  */
4089                 val = its_clear_vpend_valid(vlpi_base,
4090                                             0,
4091                                             GICR_VPENDBASER_PendingLast);
4092                 vpe->pending_last = true;
4093         }
4094 }
4095
4096 static void its_vpe_4_1_invall(struct its_vpe *vpe)
4097 {
4098         void __iomem *rdbase;
4099         unsigned long flags;
4100         u64 val;
4101         int cpu;
4102
4103         val  = GICR_INVALLR_V;
4104         val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4105
4106         /* Target the redistributor this vPE is currently known on */
4107         cpu = vpe_to_cpuid_lock(vpe, &flags);
4108         raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4109         rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
4110         gic_write_lpir(val, rdbase + GICR_INVALLR);
4111
4112         wait_for_syncr(rdbase);
4113         raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4114         vpe_to_cpuid_unlock(vpe, flags);
4115 }
4116
4117 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4118 {
4119         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4120         struct its_cmd_info *info = vcpu_info;
4121
4122         switch (info->cmd_type) {
4123         case SCHEDULE_VPE:
4124                 its_vpe_4_1_schedule(vpe, info);
4125                 return 0;
4126
4127         case DESCHEDULE_VPE:
4128                 its_vpe_4_1_deschedule(vpe, info);
4129                 return 0;
4130
4131         case INVALL_VPE:
4132                 its_vpe_4_1_invall(vpe);
4133                 return 0;
4134
4135         default:
4136                 return -EINVAL;
4137         }
4138 }
4139
4140 static struct irq_chip its_vpe_4_1_irq_chip = {
4141         .name                   = "GICv4.1-vpe",
4142         .irq_mask               = its_vpe_4_1_mask_irq,
4143         .irq_unmask             = its_vpe_4_1_unmask_irq,
4144         .irq_eoi                = irq_chip_eoi_parent,
4145         .irq_set_affinity       = its_vpe_set_affinity,
4146         .irq_set_vcpu_affinity  = its_vpe_4_1_set_vcpu_affinity,
4147 };
4148
4149 static void its_configure_sgi(struct irq_data *d, bool clear)
4150 {
4151         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4152         struct its_cmd_desc desc;
4153
4154         desc.its_vsgi_cmd.vpe = vpe;
4155         desc.its_vsgi_cmd.sgi = d->hwirq;
4156         desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4157         desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4158         desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4159         desc.its_vsgi_cmd.clear = clear;
4160
4161         /*
4162          * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4163          * destination VPE is mapped there. Since we map them eagerly at
4164          * activation time, we're pretty sure the first GICv4.1 ITS will do.
4165          */
4166         its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4167 }
4168
4169 static void its_sgi_mask_irq(struct irq_data *d)
4170 {
4171         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4172
4173         vpe->sgi_config[d->hwirq].enabled = false;
4174         its_configure_sgi(d, false);
4175 }
4176
4177 static void its_sgi_unmask_irq(struct irq_data *d)
4178 {
4179         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4180
4181         vpe->sgi_config[d->hwirq].enabled = true;
4182         its_configure_sgi(d, false);
4183 }
4184
4185 static int its_sgi_set_affinity(struct irq_data *d,
4186                                 const struct cpumask *mask_val,
4187                                 bool force)
4188 {
4189         /*
4190          * There is no notion of affinity for virtual SGIs, at least
4191          * not on the host (since they can only be targetting a vPE).
4192          * Tell the kernel we've done whatever it asked for.
4193          */
4194         irq_data_update_effective_affinity(d, mask_val);
4195         return IRQ_SET_MASK_OK;
4196 }
4197
4198 static int its_sgi_set_irqchip_state(struct irq_data *d,
4199                                      enum irqchip_irq_state which,
4200                                      bool state)
4201 {
4202         if (which != IRQCHIP_STATE_PENDING)
4203                 return -EINVAL;
4204
4205         if (state) {
4206                 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4207                 struct its_node *its = find_4_1_its();
4208                 u64 val;
4209
4210                 val  = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4211                 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4212                 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4213         } else {
4214                 its_configure_sgi(d, true);
4215         }
4216
4217         return 0;
4218 }
4219
4220 static int its_sgi_get_irqchip_state(struct irq_data *d,
4221                                      enum irqchip_irq_state which, bool *val)
4222 {
4223         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4224         void __iomem *base;
4225         unsigned long flags;
4226         u32 count = 1000000;    /* 1s! */
4227         u32 status;
4228         int cpu;
4229
4230         if (which != IRQCHIP_STATE_PENDING)
4231                 return -EINVAL;
4232
4233         /*
4234          * Locking galore! We can race against two different events:
4235          *
4236          * - Concurent vPE affinity change: we must make sure it cannot
4237          *   happen, or we'll talk to the wrong redistributor. This is
4238          *   identical to what happens with vLPIs.
4239          *
4240          * - Concurrent VSGIPENDR access: As it involves accessing two
4241          *   MMIO registers, this must be made atomic one way or another.
4242          */
4243         cpu = vpe_to_cpuid_lock(vpe, &flags);
4244         raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4245         base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4246         writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4247         do {
4248                 status = readl_relaxed(base + GICR_VSGIPENDR);
4249                 if (!(status & GICR_VSGIPENDR_BUSY))
4250                         goto out;
4251
4252                 count--;
4253                 if (!count) {
4254                         pr_err_ratelimited("Unable to get SGI status\n");
4255                         goto out;
4256                 }
4257                 cpu_relax();
4258                 udelay(1);
4259         } while (count);
4260
4261 out:
4262         raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4263         vpe_to_cpuid_unlock(vpe, flags);
4264
4265         if (!count)
4266                 return -ENXIO;
4267
4268         *val = !!(status & (1 << d->hwirq));
4269
4270         return 0;
4271 }
4272
4273 static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4274 {
4275         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4276         struct its_cmd_info *info = vcpu_info;
4277
4278         switch (info->cmd_type) {
4279         case PROP_UPDATE_VSGI:
4280                 vpe->sgi_config[d->hwirq].priority = info->priority;
4281                 vpe->sgi_config[d->hwirq].group = info->group;
4282                 its_configure_sgi(d, false);
4283                 return 0;
4284
4285         default:
4286                 return -EINVAL;
4287         }
4288 }
4289
4290 static struct irq_chip its_sgi_irq_chip = {
4291         .name                   = "GICv4.1-sgi",
4292         .irq_mask               = its_sgi_mask_irq,
4293         .irq_unmask             = its_sgi_unmask_irq,
4294         .irq_set_affinity       = its_sgi_set_affinity,
4295         .irq_set_irqchip_state  = its_sgi_set_irqchip_state,
4296         .irq_get_irqchip_state  = its_sgi_get_irqchip_state,
4297         .irq_set_vcpu_affinity  = its_sgi_set_vcpu_affinity,
4298 };
4299
4300 static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4301                                     unsigned int virq, unsigned int nr_irqs,
4302                                     void *args)
4303 {
4304         struct its_vpe *vpe = args;
4305         int i;
4306
4307         /* Yes, we do want 16 SGIs */
4308         WARN_ON(nr_irqs != 16);
4309
4310         for (i = 0; i < 16; i++) {
4311                 vpe->sgi_config[i].priority = 0;
4312                 vpe->sgi_config[i].enabled = false;
4313                 vpe->sgi_config[i].group = false;
4314
4315                 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4316                                               &its_sgi_irq_chip, vpe);
4317                 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4318         }
4319
4320         return 0;
4321 }
4322
4323 static void its_sgi_irq_domain_free(struct irq_domain *domain,
4324                                     unsigned int virq,
4325                                     unsigned int nr_irqs)
4326 {
4327         /* Nothing to do */
4328 }
4329
4330 static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4331                                        struct irq_data *d, bool reserve)
4332 {
4333         /* Write out the initial SGI configuration */
4334         its_configure_sgi(d, false);
4335         return 0;
4336 }
4337
4338 static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4339                                           struct irq_data *d)
4340 {
4341         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4342
4343         /*
4344          * The VSGI command is awkward:
4345          *
4346          * - To change the configuration, CLEAR must be set to false,
4347          *   leaving the pending bit unchanged.
4348          * - To clear the pending bit, CLEAR must be set to true, leaving
4349          *   the configuration unchanged.
4350          *
4351          * You just can't do both at once, hence the two commands below.
4352          */
4353         vpe->sgi_config[d->hwirq].enabled = false;
4354         its_configure_sgi(d, false);
4355         its_configure_sgi(d, true);
4356 }
4357
4358 static const struct irq_domain_ops its_sgi_domain_ops = {
4359         .alloc          = its_sgi_irq_domain_alloc,
4360         .free           = its_sgi_irq_domain_free,
4361         .activate       = its_sgi_irq_domain_activate,
4362         .deactivate     = its_sgi_irq_domain_deactivate,
4363 };
4364
4365 static int its_vpe_id_alloc(void)
4366 {
4367         return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
4368 }
4369
4370 static void its_vpe_id_free(u16 id)
4371 {
4372         ida_simple_remove(&its_vpeid_ida, id);
4373 }
4374
4375 static int its_vpe_init(struct its_vpe *vpe)
4376 {
4377         struct page *vpt_page;
4378         int vpe_id;
4379
4380         /* Allocate vpe_id */
4381         vpe_id = its_vpe_id_alloc();
4382         if (vpe_id < 0)
4383                 return vpe_id;
4384
4385         /* Allocate VPT */
4386         vpt_page = its_allocate_pending_table(GFP_KERNEL);
4387         if (!vpt_page) {
4388                 its_vpe_id_free(vpe_id);
4389                 return -ENOMEM;
4390         }
4391
4392         if (!its_alloc_vpe_table(vpe_id)) {
4393                 its_vpe_id_free(vpe_id);
4394                 its_free_pending_table(vpt_page);
4395                 return -ENOMEM;
4396         }
4397
4398         raw_spin_lock_init(&vpe->vpe_lock);
4399         vpe->vpe_id = vpe_id;
4400         vpe->vpt_page = vpt_page;
4401         if (gic_rdists->has_rvpeid)
4402                 atomic_set(&vpe->vmapp_count, 0);
4403         else
4404                 vpe->vpe_proxy_event = -1;
4405
4406         return 0;
4407 }
4408
4409 static void its_vpe_teardown(struct its_vpe *vpe)
4410 {
4411         its_vpe_db_proxy_unmap(vpe);
4412         its_vpe_id_free(vpe->vpe_id);
4413         its_free_pending_table(vpe->vpt_page);
4414 }
4415
4416 static void its_vpe_irq_domain_free(struct irq_domain *domain,
4417                                     unsigned int virq,
4418                                     unsigned int nr_irqs)
4419 {
4420         struct its_vm *vm = domain->host_data;
4421         int i;
4422
4423         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4424
4425         for (i = 0; i < nr_irqs; i++) {
4426                 struct irq_data *data = irq_domain_get_irq_data(domain,
4427                                                                 virq + i);
4428                 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4429
4430                 BUG_ON(vm != vpe->its_vm);
4431
4432                 clear_bit(data->hwirq, vm->db_bitmap);
4433                 its_vpe_teardown(vpe);
4434                 irq_domain_reset_irq_data(data);
4435         }
4436
4437         if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
4438                 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
4439                 its_free_prop_table(vm->vprop_page);
4440         }
4441 }
4442
4443 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4444                                     unsigned int nr_irqs, void *args)
4445 {
4446         struct irq_chip *irqchip = &its_vpe_irq_chip;
4447         struct its_vm *vm = args;
4448         unsigned long *bitmap;
4449         struct page *vprop_page;
4450         int base, nr_ids, i, err = 0;
4451
4452         BUG_ON(!vm);
4453
4454         bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
4455         if (!bitmap)
4456                 return -ENOMEM;
4457
4458         if (nr_ids < nr_irqs) {
4459                 its_lpi_free(bitmap, base, nr_ids);
4460                 return -ENOMEM;
4461         }
4462
4463         vprop_page = its_allocate_prop_table(GFP_KERNEL);
4464         if (!vprop_page) {
4465                 its_lpi_free(bitmap, base, nr_ids);
4466                 return -ENOMEM;
4467         }
4468
4469         vm->db_bitmap = bitmap;
4470         vm->db_lpi_base = base;
4471         vm->nr_db_lpis = nr_ids;
4472         vm->vprop_page = vprop_page;
4473
4474         if (gic_rdists->has_rvpeid)
4475                 irqchip = &its_vpe_4_1_irq_chip;
4476
4477         for (i = 0; i < nr_irqs; i++) {
4478                 vm->vpes[i]->vpe_db_lpi = base + i;
4479                 err = its_vpe_init(vm->vpes[i]);
4480                 if (err)
4481                         break;
4482                 err = its_irq_gic_domain_alloc(domain, virq + i,
4483                                                vm->vpes[i]->vpe_db_lpi);
4484                 if (err)
4485                         break;
4486                 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4487                                               irqchip, vm->vpes[i]);
4488                 set_bit(i, bitmap);
4489         }
4490
4491         if (err) {
4492                 if (i > 0)
4493                         its_vpe_irq_domain_free(domain, virq, i - 1);
4494
4495                 its_lpi_free(bitmap, base, nr_ids);
4496                 its_free_prop_table(vprop_page);
4497         }
4498
4499         return err;
4500 }
4501
4502 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
4503                                        struct irq_data *d, bool reserve)
4504 {
4505         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4506         struct its_node *its;
4507
4508         /*
4509          * If we use the list map, we issue VMAPP on demand... Unless
4510          * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4511          * so that VSGIs can work.
4512          */
4513         if (!gic_requires_eager_mapping())
4514                 return 0;
4515
4516         /* Map the VPE to the first possible CPU */
4517         vpe->col_idx = cpumask_first(cpu_online_mask);
4518
4519         list_for_each_entry(its, &its_nodes, entry) {
4520                 if (!is_v4(its))
4521                         continue;
4522
4523                 its_send_vmapp(its, vpe, true);
4524                 its_send_vinvall(its, vpe);
4525         }
4526
4527         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4528
4529         return 0;
4530 }
4531
4532 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4533                                           struct irq_data *d)
4534 {
4535         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4536         struct its_node *its;
4537
4538         /*
4539          * If we use the list map on GICv4.0, we unmap the VPE once no
4540          * VLPIs are associated with the VM.
4541          */
4542         if (!gic_requires_eager_mapping())
4543                 return;
4544
4545         list_for_each_entry(its, &its_nodes, entry) {
4546                 if (!is_v4(its))
4547                         continue;
4548
4549                 its_send_vmapp(its, vpe, false);
4550         }
4551 }
4552
4553 static const struct irq_domain_ops its_vpe_domain_ops = {
4554         .alloc                  = its_vpe_irq_domain_alloc,
4555         .free                   = its_vpe_irq_domain_free,
4556         .activate               = its_vpe_irq_domain_activate,
4557         .deactivate             = its_vpe_irq_domain_deactivate,
4558 };
4559
4560 static int its_force_quiescent(void __iomem *base)
4561 {
4562         u32 count = 1000000;    /* 1s */
4563         u32 val;
4564
4565         val = readl_relaxed(base + GITS_CTLR);
4566         /*
4567          * GIC architecture specification requires the ITS to be both
4568          * disabled and quiescent for writes to GITS_BASER<n> or
4569          * GITS_CBASER to not have UNPREDICTABLE results.
4570          */
4571         if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
4572                 return 0;
4573
4574         /* Disable the generation of all interrupts to this ITS */
4575         val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
4576         writel_relaxed(val, base + GITS_CTLR);
4577
4578         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4579         while (1) {
4580                 val = readl_relaxed(base + GITS_CTLR);
4581                 if (val & GITS_CTLR_QUIESCENT)
4582                         return 0;
4583
4584                 count--;
4585                 if (!count)
4586                         return -EBUSY;
4587
4588                 cpu_relax();
4589                 udelay(1);
4590         }
4591 }
4592
4593 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
4594 {
4595         struct its_node *its = data;
4596
4597         /* erratum 22375: only alloc 8MB table size (20 bits) */
4598         its->typer &= ~GITS_TYPER_DEVBITS;
4599         its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
4600         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
4601
4602         return true;
4603 }
4604
4605 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
4606 {
4607         struct its_node *its = data;
4608
4609         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
4610
4611         return true;
4612 }
4613
4614 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
4615 {
4616         struct its_node *its = data;
4617
4618         /* On QDF2400, the size of the ITE is 16Bytes */
4619         its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4620         its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
4621
4622         return true;
4623 }
4624
4625 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4626 {
4627         struct its_node *its = its_dev->its;
4628
4629         /*
4630          * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4631          * which maps 32-bit writes targeted at a separate window of
4632          * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4633          * with device ID taken from bits [device_id_bits + 1:2] of
4634          * the window offset.
4635          */
4636         return its->pre_its_base + (its_dev->device_id << 2);
4637 }
4638
4639 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4640 {
4641         struct its_node *its = data;
4642         u32 pre_its_window[2];
4643         u32 ids;
4644
4645         if (!fwnode_property_read_u32_array(its->fwnode_handle,
4646                                            "socionext,synquacer-pre-its",
4647                                            pre_its_window,
4648                                            ARRAY_SIZE(pre_its_window))) {
4649
4650                 its->pre_its_base = pre_its_window[0];
4651                 its->get_msi_base = its_irq_get_msi_base_pre_its;
4652
4653                 ids = ilog2(pre_its_window[1]) - 2;
4654                 if (device_ids(its) > ids) {
4655                         its->typer &= ~GITS_TYPER_DEVBITS;
4656                         its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4657                 }
4658
4659                 /* the pre-ITS breaks isolation, so disable MSI remapping */
4660                 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
4661                 return true;
4662         }
4663         return false;
4664 }
4665
4666 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4667 {
4668         struct its_node *its = data;
4669
4670         /*
4671          * Hip07 insists on using the wrong address for the VLPI
4672          * page. Trick it into doing the right thing...
4673          */
4674         its->vlpi_redist_offset = SZ_128K;
4675         return true;
4676 }
4677
4678 static const struct gic_quirk its_quirks[] = {
4679 #ifdef CONFIG_CAVIUM_ERRATUM_22375
4680         {
4681                 .desc   = "ITS: Cavium errata 22375, 24313",
4682                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
4683                 .mask   = 0xffff0fff,
4684                 .init   = its_enable_quirk_cavium_22375,
4685         },
4686 #endif
4687 #ifdef CONFIG_CAVIUM_ERRATUM_23144
4688         {
4689                 .desc   = "ITS: Cavium erratum 23144",
4690                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
4691                 .mask   = 0xffff0fff,
4692                 .init   = its_enable_quirk_cavium_23144,
4693         },
4694 #endif
4695 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4696         {
4697                 .desc   = "ITS: QDF2400 erratum 0065",
4698                 .iidr   = 0x00001070, /* QDF2400 ITS rev 1.x */
4699                 .mask   = 0xffffffff,
4700                 .init   = its_enable_quirk_qdf2400_e0065,
4701         },
4702 #endif
4703 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4704         {
4705                 /*
4706                  * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4707                  * implementation, but with a 'pre-ITS' added that requires
4708                  * special handling in software.
4709                  */
4710                 .desc   = "ITS: Socionext Synquacer pre-ITS",
4711                 .iidr   = 0x0001143b,
4712                 .mask   = 0xffffffff,
4713                 .init   = its_enable_quirk_socionext_synquacer,
4714         },
4715 #endif
4716 #ifdef CONFIG_HISILICON_ERRATUM_161600802
4717         {
4718                 .desc   = "ITS: Hip07 erratum 161600802",
4719                 .iidr   = 0x00000004,
4720                 .mask   = 0xffffffff,
4721                 .init   = its_enable_quirk_hip07_161600802,
4722         },
4723 #endif
4724         {
4725         }
4726 };
4727
4728 static void its_enable_quirks(struct its_node *its)
4729 {
4730         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4731
4732         gic_enable_quirks(iidr, its_quirks, its);
4733 }
4734
4735 static int its_save_disable(void)
4736 {
4737         struct its_node *its;
4738         int err = 0;
4739
4740         raw_spin_lock(&its_lock);
4741         list_for_each_entry(its, &its_nodes, entry) {
4742                 void __iomem *base;
4743
4744                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4745                         continue;
4746
4747                 base = its->base;
4748                 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4749                 err = its_force_quiescent(base);
4750                 if (err) {
4751                         pr_err("ITS@%pa: failed to quiesce: %d\n",
4752                                &its->phys_base, err);
4753                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4754                         goto err;
4755                 }
4756
4757                 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4758         }
4759
4760 err:
4761         if (err) {
4762                 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4763                         void __iomem *base;
4764
4765                         if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4766                                 continue;
4767
4768                         base = its->base;
4769                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4770                 }
4771         }
4772         raw_spin_unlock(&its_lock);
4773
4774         return err;
4775 }
4776
4777 static void its_restore_enable(void)
4778 {
4779         struct its_node *its;
4780         int ret;
4781
4782         raw_spin_lock(&its_lock);
4783         list_for_each_entry(its, &its_nodes, entry) {
4784                 void __iomem *base;
4785                 int i;
4786
4787                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
4788                         continue;
4789
4790                 base = its->base;
4791
4792                 /*
4793                  * Make sure that the ITS is disabled. If it fails to quiesce,
4794                  * don't restore it since writing to CBASER or BASER<n>
4795                  * registers is undefined according to the GIC v3 ITS
4796                  * Specification.
4797                  */
4798                 ret = its_force_quiescent(base);
4799                 if (ret) {
4800                         pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4801                                &its->phys_base, ret);
4802                         continue;
4803                 }
4804
4805                 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4806
4807                 /*
4808                  * Writing CBASER resets CREADR to 0, so make CWRITER and
4809                  * cmd_write line up with it.
4810                  */
4811                 its->cmd_write = its->cmd_base;
4812                 gits_write_cwriter(0, base + GITS_CWRITER);
4813
4814                 /* Restore GITS_BASER from the value cache. */
4815                 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4816                         struct its_baser *baser = &its->tables[i];
4817
4818                         if (!(baser->val & GITS_BASER_VALID))
4819                                 continue;
4820
4821                         its_write_baser(its, baser, baser->val);
4822                 }
4823                 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4824
4825                 /*
4826                  * Reinit the collection if it's stored in the ITS. This is
4827                  * indicated by the col_id being less than the HCC field.
4828                  * CID < HCC as specified in the GIC v3 Documentation.
4829                  */
4830                 if (its->collections[smp_processor_id()].col_id <
4831                     GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4832                         its_cpu_init_collection(its);
4833         }
4834         raw_spin_unlock(&its_lock);
4835 }
4836
4837 static struct syscore_ops its_syscore_ops = {
4838         .suspend = its_save_disable,
4839         .resume = its_restore_enable,
4840 };
4841
4842 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
4843 {
4844         struct irq_domain *inner_domain;
4845         struct msi_domain_info *info;
4846
4847         info = kzalloc(sizeof(*info), GFP_KERNEL);
4848         if (!info)
4849                 return -ENOMEM;
4850
4851         inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
4852         if (!inner_domain) {
4853                 kfree(info);
4854                 return -ENOMEM;
4855         }
4856
4857         inner_domain->parent = its_parent;
4858         irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
4859         inner_domain->flags |= its->msi_domain_flags;
4860         info->ops = &its_msi_domain_ops;
4861         info->data = its;
4862         inner_domain->host_data = info;
4863
4864         return 0;
4865 }
4866
4867 static int its_init_vpe_domain(void)
4868 {
4869         struct its_node *its;
4870         u32 devid;
4871         int entries;
4872
4873         if (gic_rdists->has_direct_lpi) {
4874                 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
4875                 return 0;
4876         }
4877
4878         /* Any ITS will do, even if not v4 */
4879         its = list_first_entry(&its_nodes, struct its_node, entry);
4880
4881         entries = roundup_pow_of_two(nr_cpu_ids);
4882         vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
4883                                  GFP_KERNEL);
4884         if (!vpe_proxy.vpes) {
4885                 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
4886                 return -ENOMEM;
4887         }
4888
4889         /* Use the last possible DevID */
4890         devid = GENMASK(device_ids(its) - 1, 0);
4891         vpe_proxy.dev = its_create_device(its, devid, entries, false);
4892         if (!vpe_proxy.dev) {
4893                 kfree(vpe_proxy.vpes);
4894                 pr_err("ITS: Can't allocate GICv4 proxy device\n");
4895                 return -ENOMEM;
4896         }
4897
4898         BUG_ON(entries > vpe_proxy.dev->nr_ites);
4899
4900         raw_spin_lock_init(&vpe_proxy.lock);
4901         vpe_proxy.next_victim = 0;
4902         pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
4903                 devid, vpe_proxy.dev->nr_ites);
4904
4905         return 0;
4906 }
4907
4908 static int __init its_compute_its_list_map(struct resource *res,
4909                                            void __iomem *its_base)
4910 {
4911         int its_number;
4912         u32 ctlr;
4913
4914         /*
4915          * This is assumed to be done early enough that we're
4916          * guaranteed to be single-threaded, hence no
4917          * locking. Should this change, we should address
4918          * this.
4919          */
4920         its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
4921         if (its_number >= GICv4_ITS_LIST_MAX) {
4922                 pr_err("ITS@%pa: No ITSList entry available!\n",
4923                        &res->start);
4924                 return -EINVAL;
4925         }
4926
4927         ctlr = readl_relaxed(its_base + GITS_CTLR);
4928         ctlr &= ~GITS_CTLR_ITS_NUMBER;
4929         ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
4930         writel_relaxed(ctlr, its_base + GITS_CTLR);
4931         ctlr = readl_relaxed(its_base + GITS_CTLR);
4932         if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
4933                 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
4934                 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
4935         }
4936
4937         if (test_and_set_bit(its_number, &its_list_map)) {
4938                 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
4939                        &res->start, its_number);
4940                 return -EINVAL;
4941         }
4942
4943         return its_number;
4944 }
4945
4946 static int __init its_probe_one(struct resource *res,
4947                                 struct fwnode_handle *handle, int numa_node)
4948 {
4949         struct its_node *its;
4950         void __iomem *its_base;
4951         u32 val, ctlr;
4952         u64 baser, tmp, typer;
4953         struct page *page;
4954         int err;
4955
4956         its_base = ioremap(res->start, SZ_64K);
4957         if (!its_base) {
4958                 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4959                 return -ENOMEM;
4960         }
4961
4962         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4963         if (val != 0x30 && val != 0x40) {
4964                 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4965                 err = -ENODEV;
4966                 goto out_unmap;
4967         }
4968
4969         err = its_force_quiescent(its_base);
4970         if (err) {
4971                 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4972                 goto out_unmap;
4973         }
4974
4975         pr_info("ITS %pR\n", res);
4976
4977         its = kzalloc(sizeof(*its), GFP_KERNEL);
4978         if (!its) {
4979                 err = -ENOMEM;
4980                 goto out_unmap;
4981         }
4982
4983         raw_spin_lock_init(&its->lock);
4984         mutex_init(&its->dev_alloc_lock);
4985         INIT_LIST_HEAD(&its->entry);
4986         INIT_LIST_HEAD(&its->its_device_list);
4987         typer = gic_read_typer(its_base + GITS_TYPER);
4988         its->typer = typer;
4989         its->base = its_base;
4990         its->phys_base = res->start;
4991         if (is_v4(its)) {
4992                 if (!(typer & GITS_TYPER_VMOVP)) {
4993                         err = its_compute_its_list_map(res, its_base);
4994                         if (err < 0)
4995                                 goto out_free_its;
4996
4997                         its->list_nr = err;
4998
4999                         pr_info("ITS@%pa: Using ITS number %d\n",
5000                                 &res->start, err);
5001                 } else {
5002                         pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
5003                 }
5004
5005                 if (is_v4_1(its)) {
5006                         u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer);
5007
5008                         its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K);
5009                         if (!its->sgir_base) {
5010                                 err = -ENOMEM;
5011                                 goto out_free_its;
5012                         }
5013
5014                         its->mpidr = readl_relaxed(its_base + GITS_MPIDR);
5015
5016                         pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5017                                 &res->start, its->mpidr, svpet);
5018                 }
5019         }
5020
5021         its->numa_node = numa_node;
5022
5023         page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5024                                 get_order(ITS_CMD_QUEUE_SZ));
5025         if (!page) {
5026                 err = -ENOMEM;
5027                 goto out_unmap_sgir;
5028         }
5029         its->cmd_base = (void *)page_address(page);
5030         its->cmd_write = its->cmd_base;
5031         its->fwnode_handle = handle;
5032         its->get_msi_base = its_irq_get_msi_base;
5033         its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
5034
5035         its_enable_quirks(its);
5036
5037         err = its_alloc_tables(its);
5038         if (err)
5039                 goto out_free_cmd;
5040
5041         err = its_alloc_collections(its);
5042         if (err)
5043                 goto out_free_tables;
5044
5045         baser = (virt_to_phys(its->cmd_base)    |
5046                  GITS_CBASER_RaWaWb             |
5047                  GITS_CBASER_InnerShareable     |
5048                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5049                  GITS_CBASER_VALID);
5050
5051         gits_write_cbaser(baser, its->base + GITS_CBASER);
5052         tmp = gits_read_cbaser(its->base + GITS_CBASER);
5053
5054         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
5055                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5056                         /*
5057                          * The HW reports non-shareable, we must
5058                          * remove the cacheability attributes as
5059                          * well.
5060                          */
5061                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5062                                    GITS_CBASER_CACHEABILITY_MASK);
5063                         baser |= GITS_CBASER_nC;
5064                         gits_write_cbaser(baser, its->base + GITS_CBASER);
5065                 }
5066                 pr_info("ITS: using cache flushing for cmd queue\n");
5067                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5068         }
5069
5070         gits_write_cwriter(0, its->base + GITS_CWRITER);
5071         ctlr = readl_relaxed(its->base + GITS_CTLR);
5072         ctlr |= GITS_CTLR_ENABLE;
5073         if (is_v4(its))
5074                 ctlr |= GITS_CTLR_ImDe;
5075         writel_relaxed(ctlr, its->base + GITS_CTLR);
5076
5077         if (GITS_TYPER_HCC(typer))
5078                 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
5079
5080         err = its_init_domain(handle, its);
5081         if (err)
5082                 goto out_free_tables;
5083
5084         raw_spin_lock(&its_lock);
5085         list_add(&its->entry, &its_nodes);
5086         raw_spin_unlock(&its_lock);
5087
5088         return 0;
5089
5090 out_free_tables:
5091         its_free_tables(its);
5092 out_free_cmd:
5093         free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
5094 out_unmap_sgir:
5095         if (its->sgir_base)
5096                 iounmap(its->sgir_base);
5097 out_free_its:
5098         kfree(its);
5099 out_unmap:
5100         iounmap(its_base);
5101         pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
5102         return err;
5103 }
5104
5105 static bool gic_rdists_supports_plpis(void)
5106 {
5107         return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
5108 }
5109
5110 static int redist_disable_lpis(void)
5111 {
5112         void __iomem *rbase = gic_data_rdist_rd_base();
5113         u64 timeout = USEC_PER_SEC;
5114         u64 val;
5115
5116         if (!gic_rdists_supports_plpis()) {
5117                 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5118                 return -ENXIO;
5119         }
5120
5121         val = readl_relaxed(rbase + GICR_CTLR);
5122         if (!(val & GICR_CTLR_ENABLE_LPIS))
5123                 return 0;
5124
5125         /*
5126          * If coming via a CPU hotplug event, we don't need to disable
5127          * LPIs before trying to re-enable them. They are already
5128          * configured and all is well in the world.
5129          *
5130          * If running with preallocated tables, there is nothing to do.
5131          */
5132         if (gic_data_rdist()->lpi_enabled ||
5133             (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
5134                 return 0;
5135
5136         /*
5137          * From that point on, we only try to do some damage control.
5138          */
5139         pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
5140                 smp_processor_id());
5141         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5142
5143         /* Disable LPIs */
5144         val &= ~GICR_CTLR_ENABLE_LPIS;
5145         writel_relaxed(val, rbase + GICR_CTLR);
5146
5147         /* Make sure any change to GICR_CTLR is observable by the GIC */
5148         dsb(sy);
5149
5150         /*
5151          * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5152          * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5153          * Error out if we time out waiting for RWP to clear.
5154          */
5155         while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5156                 if (!timeout) {
5157                         pr_err("CPU%d: Timeout while disabling LPIs\n",
5158                                smp_processor_id());
5159                         return -ETIMEDOUT;
5160                 }
5161                 udelay(1);
5162                 timeout--;
5163         }
5164
5165         /*
5166          * After it has been written to 1, it is IMPLEMENTATION
5167          * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5168          * cleared to 0. Error out if clearing the bit failed.
5169          */
5170         if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5171                 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5172                 return -EBUSY;
5173         }
5174
5175         return 0;
5176 }
5177
5178 int its_cpu_init(void)
5179 {
5180         if (!list_empty(&its_nodes)) {
5181                 int ret;
5182
5183                 ret = redist_disable_lpis();
5184                 if (ret)
5185                         return ret;
5186
5187                 its_cpu_init_lpis();
5188                 its_cpu_init_collections();
5189         }
5190
5191         return 0;
5192 }
5193
5194 static const struct of_device_id its_device_id[] = {
5195         {       .compatible     = "arm,gic-v3-its",     },
5196         {},
5197 };
5198
5199 static int __init its_of_probe(struct device_node *node)
5200 {
5201         struct device_node *np;
5202         struct resource res;
5203
5204         for (np = of_find_matching_node(node, its_device_id); np;
5205              np = of_find_matching_node(np, its_device_id)) {
5206                 if (!of_device_is_available(np))
5207                         continue;
5208                 if (!of_property_read_bool(np, "msi-controller")) {
5209                         pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5210                                 np);
5211                         continue;
5212                 }
5213
5214                 if (of_address_to_resource(np, 0, &res)) {
5215                         pr_warn("%pOF: no regs?\n", np);
5216                         continue;
5217                 }
5218
5219                 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
5220         }
5221         return 0;
5222 }
5223
5224 #ifdef CONFIG_ACPI
5225
5226 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5227
5228 #ifdef CONFIG_ACPI_NUMA
5229 struct its_srat_map {
5230         /* numa node id */
5231         u32     numa_node;
5232         /* GIC ITS ID */
5233         u32     its_id;
5234 };
5235
5236 static struct its_srat_map *its_srat_maps __initdata;
5237 static int its_in_srat __initdata;
5238
5239 static int __init acpi_get_its_numa_node(u32 its_id)
5240 {
5241         int i;
5242
5243         for (i = 0; i < its_in_srat; i++) {
5244                 if (its_id == its_srat_maps[i].its_id)
5245                         return its_srat_maps[i].numa_node;
5246         }
5247         return NUMA_NO_NODE;
5248 }
5249
5250 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
5251                                           const unsigned long end)
5252 {
5253         return 0;
5254 }
5255
5256 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
5257                          const unsigned long end)
5258 {
5259         int node;
5260         struct acpi_srat_gic_its_affinity *its_affinity;
5261
5262         its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5263         if (!its_affinity)
5264                 return -EINVAL;
5265
5266         if (its_affinity->header.length < sizeof(*its_affinity)) {
5267                 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5268                         its_affinity->header.length);
5269                 return -EINVAL;
5270         }
5271
5272         /*
5273          * Note that in theory a new proximity node could be created by this
5274          * entry as it is an SRAT resource allocation structure.
5275          * We do not currently support doing so.
5276          */
5277         node = pxm_to_node(its_affinity->proximity_domain);
5278
5279         if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5280                 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5281                 return 0;
5282         }
5283
5284         its_srat_maps[its_in_srat].numa_node = node;
5285         its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5286         its_in_srat++;
5287         pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5288                 its_affinity->proximity_domain, its_affinity->its_id, node);
5289
5290         return 0;
5291 }
5292
5293 static void __init acpi_table_parse_srat_its(void)
5294 {
5295         int count;
5296
5297         count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5298                         sizeof(struct acpi_table_srat),
5299                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5300                         gic_acpi_match_srat_its, 0);
5301         if (count <= 0)
5302                 return;
5303
5304         its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5305                                       GFP_KERNEL);
5306         if (!its_srat_maps) {
5307                 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
5308                 return;
5309         }
5310
5311         acpi_table_parse_entries(ACPI_SIG_SRAT,
5312                         sizeof(struct acpi_table_srat),
5313                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5314                         gic_acpi_parse_srat_its, 0);
5315 }
5316
5317 /* free the its_srat_maps after ITS probing */
5318 static void __init acpi_its_srat_maps_free(void)
5319 {
5320         kfree(its_srat_maps);
5321 }
5322 #else
5323 static void __init acpi_table_parse_srat_its(void)      { }
5324 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
5325 static void __init acpi_its_srat_maps_free(void) { }
5326 #endif
5327
5328 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
5329                                           const unsigned long end)
5330 {
5331         struct acpi_madt_generic_translator *its_entry;
5332         struct fwnode_handle *dom_handle;
5333         struct resource res;
5334         int err;
5335
5336         its_entry = (struct acpi_madt_generic_translator *)header;
5337         memset(&res, 0, sizeof(res));
5338         res.start = its_entry->base_address;
5339         res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5340         res.flags = IORESOURCE_MEM;
5341
5342         dom_handle = irq_domain_alloc_fwnode(&res.start);
5343         if (!dom_handle) {
5344                 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5345                        &res.start);
5346                 return -ENOMEM;
5347         }
5348
5349         err = iort_register_domain_token(its_entry->translation_id, res.start,
5350                                          dom_handle);
5351         if (err) {
5352                 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5353                        &res.start, its_entry->translation_id);
5354                 goto dom_err;
5355         }
5356
5357         err = its_probe_one(&res, dom_handle,
5358                         acpi_get_its_numa_node(its_entry->translation_id));
5359         if (!err)
5360                 return 0;
5361
5362         iort_deregister_domain_token(its_entry->translation_id);
5363 dom_err:
5364         irq_domain_free_fwnode(dom_handle);
5365         return err;
5366 }
5367
5368 static void __init its_acpi_probe(void)
5369 {
5370         acpi_table_parse_srat_its();
5371         acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5372                               gic_acpi_parse_madt_its, 0);
5373         acpi_its_srat_maps_free();
5374 }
5375 #else
5376 static void __init its_acpi_probe(void) { }
5377 #endif
5378
5379 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5380                     struct irq_domain *parent_domain)
5381 {
5382         struct device_node *of_node;
5383         struct its_node *its;
5384         bool has_v4 = false;
5385         bool has_v4_1 = false;
5386         int err;
5387
5388         gic_rdists = rdists;
5389
5390         its_parent = parent_domain;
5391         of_node = to_of_node(handle);
5392         if (of_node)
5393                 its_of_probe(of_node);
5394         else
5395                 its_acpi_probe();
5396
5397         if (list_empty(&its_nodes)) {
5398                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5399                 return -ENXIO;
5400         }
5401
5402         err = allocate_lpi_tables();
5403         if (err)
5404                 return err;
5405
5406         list_for_each_entry(its, &its_nodes, entry) {
5407                 has_v4 |= is_v4(its);
5408                 has_v4_1 |= is_v4_1(its);
5409         }
5410
5411         /* Don't bother with inconsistent systems */
5412         if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5413                 rdists->has_rvpeid = false;
5414
5415         if (has_v4 & rdists->has_vlpis) {
5416                 const struct irq_domain_ops *sgi_ops;
5417
5418                 if (has_v4_1)
5419                         sgi_ops = &its_sgi_domain_ops;
5420                 else
5421                         sgi_ops = NULL;
5422
5423                 if (its_init_vpe_domain() ||
5424                     its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
5425                         rdists->has_vlpis = false;
5426                         pr_err("ITS: Disabling GICv4 support\n");
5427                 }
5428         }
5429
5430         register_syscore_ops(&its_syscore_ops);
5431
5432         return 0;
5433 }