1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
4 * Support for Message Signaled Interrupts for systems that
5 * implement ARM Generic Interrupt Controller: GICv2m.
7 * Copyright (C) 2014 Advanced Micro Devices, Inc.
8 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
9 * Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
10 * Brandon Anderson <brandon.anderson@amd.com>
13 #define pr_fmt(fmt) "GICv2m: " fmt
15 #include <linux/acpi.h>
16 #include <linux/dma-iommu.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/kernel.h>
20 #include <linux/msi.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/irqchip/arm-gic.h>
30 * [25:16] lowest SPI assigned to MSI
32 * [9:0] Numer of SPIs assigned to MSI
34 #define V2M_MSI_TYPER 0x008
35 #define V2M_MSI_TYPER_BASE_SHIFT 16
36 #define V2M_MSI_TYPER_BASE_MASK 0x3FF
37 #define V2M_MSI_TYPER_NUM_MASK 0x3FF
38 #define V2M_MSI_SETSPI_NS 0x040
39 #define V2M_MIN_SPI 32
40 #define V2M_MAX_SPI 1019
41 #define V2M_MSI_IIDR 0xFCC
43 #define V2M_MSI_TYPER_BASE_SPI(x) \
44 (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
46 #define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
48 /* APM X-Gene with GICv2m MSI_IIDR register value */
49 #define XGENE_GICV2M_MSI_IIDR 0x06000170
51 /* Broadcom NS2 GICv2m MSI_IIDR register value */
52 #define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f
54 /* List of flags for specific v2m implementation */
55 #define GICV2M_NEEDS_SPI_OFFSET 0x00000001
57 static LIST_HEAD(v2m_nodes);
58 static DEFINE_SPINLOCK(v2m_lock);
61 struct list_head entry;
62 struct fwnode_handle *fwnode;
63 struct resource res; /* GICv2m resource */
64 void __iomem *base; /* GICv2m virt address */
65 u32 spi_start; /* The SPI number that MSIs start */
66 u32 nr_spis; /* The number of SPIs for MSIs */
67 u32 spi_offset; /* offset to be subtracted from SPI number */
68 unsigned long *bm; /* MSI vector bitmap */
69 u32 flags; /* v2m flags for specific implementation */
72 static void gicv2m_mask_msi_irq(struct irq_data *d)
75 irq_chip_mask_parent(d);
78 static void gicv2m_unmask_msi_irq(struct irq_data *d)
80 pci_msi_unmask_irq(d);
81 irq_chip_unmask_parent(d);
84 static struct irq_chip gicv2m_msi_irq_chip = {
86 .irq_mask = gicv2m_mask_msi_irq,
87 .irq_unmask = gicv2m_unmask_msi_irq,
88 .irq_eoi = irq_chip_eoi_parent,
89 .irq_write_msi_msg = pci_msi_domain_write_msg,
92 static struct msi_domain_info gicv2m_msi_domain_info = {
93 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
94 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
95 .chip = &gicv2m_msi_irq_chip,
98 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
100 struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
101 phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
103 msg->address_hi = upper_32_bits(addr);
104 msg->address_lo = lower_32_bits(addr);
105 msg->data = data->hwirq;
107 if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
108 msg->data -= v2m->spi_offset;
110 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
113 static struct irq_chip gicv2m_irq_chip = {
115 .irq_mask = irq_chip_mask_parent,
116 .irq_unmask = irq_chip_unmask_parent,
117 .irq_eoi = irq_chip_eoi_parent,
118 .irq_set_affinity = irq_chip_set_affinity_parent,
119 .irq_compose_msi_msg = gicv2m_compose_msi_msg,
122 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
124 irq_hw_number_t hwirq)
126 struct irq_fwspec fwspec;
130 if (is_of_node(domain->parent->fwnode)) {
131 fwspec.fwnode = domain->parent->fwnode;
132 fwspec.param_count = 3;
134 fwspec.param[1] = hwirq - 32;
135 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
136 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
137 fwspec.fwnode = domain->parent->fwnode;
138 fwspec.param_count = 2;
139 fwspec.param[0] = hwirq;
140 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
145 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
149 /* Configure the interrupt line to be edge */
150 d = irq_domain_get_irq_data(domain->parent, virq);
151 d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
155 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
158 spin_lock(&v2m_lock);
159 bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
160 get_count_order(nr_irqs));
161 spin_unlock(&v2m_lock);
164 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
165 unsigned int nr_irqs, void *args)
167 msi_alloc_info_t *info = args;
168 struct v2m_data *v2m = NULL, *tmp;
169 int hwirq, offset, i, err = 0;
171 spin_lock(&v2m_lock);
172 list_for_each_entry(tmp, &v2m_nodes, entry) {
173 offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
174 get_count_order(nr_irqs));
180 spin_unlock(&v2m_lock);
185 hwirq = v2m->spi_start + offset;
187 err = iommu_dma_prepare_msi(info->desc,
188 v2m->res.start + V2M_MSI_SETSPI_NS);
192 for (i = 0; i < nr_irqs; i++) {
193 err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
197 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
198 &gicv2m_irq_chip, v2m);
204 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
205 gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
209 static void gicv2m_irq_domain_free(struct irq_domain *domain,
210 unsigned int virq, unsigned int nr_irqs)
212 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
213 struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
215 gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
216 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
219 static const struct irq_domain_ops gicv2m_domain_ops = {
220 .alloc = gicv2m_irq_domain_alloc,
221 .free = gicv2m_irq_domain_free,
224 static bool is_msi_spi_valid(u32 base, u32 num)
226 if (base < V2M_MIN_SPI) {
227 pr_err("Invalid MSI base SPI (base:%u)\n", base);
231 if ((num == 0) || (base + num > V2M_MAX_SPI)) {
232 pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
233 num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
240 static struct irq_chip gicv2m_pmsi_irq_chip = {
244 static struct msi_domain_ops gicv2m_pmsi_ops = {
247 static struct msi_domain_info gicv2m_pmsi_domain_info = {
248 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
249 .ops = &gicv2m_pmsi_ops,
250 .chip = &gicv2m_pmsi_irq_chip,
253 static void gicv2m_teardown(void)
255 struct v2m_data *v2m, *tmp;
257 list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
258 list_del(&v2m->entry);
261 of_node_put(to_of_node(v2m->fwnode));
262 if (is_fwnode_irqchip(v2m->fwnode))
263 irq_domain_free_fwnode(v2m->fwnode);
268 static int gicv2m_allocate_domains(struct irq_domain *parent)
270 struct irq_domain *inner_domain, *pci_domain, *plat_domain;
271 struct v2m_data *v2m;
273 v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
277 inner_domain = irq_domain_create_tree(v2m->fwnode,
278 &gicv2m_domain_ops, v2m);
280 pr_err("Failed to create GICv2m domain\n");
284 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
285 inner_domain->parent = parent;
286 pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
287 &gicv2m_msi_domain_info,
289 plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
290 &gicv2m_pmsi_domain_info,
292 if (!pci_domain || !plat_domain) {
293 pr_err("Failed to create MSI domains\n");
295 irq_domain_remove(plat_domain);
297 irq_domain_remove(pci_domain);
298 irq_domain_remove(inner_domain);
305 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
306 u32 spi_start, u32 nr_spis,
307 struct resource *res)
310 struct v2m_data *v2m;
312 v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
314 pr_err("Failed to allocate struct v2m_data.\n");
318 INIT_LIST_HEAD(&v2m->entry);
319 v2m->fwnode = fwnode;
321 memcpy(&v2m->res, res, sizeof(struct resource));
323 v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
325 pr_err("Failed to map GICv2m resource\n");
330 if (spi_start && nr_spis) {
331 v2m->spi_start = spi_start;
332 v2m->nr_spis = nr_spis;
334 u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
336 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
337 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
340 if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
346 * APM X-Gene GICv2m implementation has an erratum where
347 * the MSI data needs to be the offset from the spi_start
348 * in order to trigger the correct MSI interrupt. This is
349 * different from the standard GICv2m implementation where
350 * the MSI data is the absolute value within the range from
351 * spi_start to (spi_start + num_spis).
353 * Broadom NS2 GICv2m implementation has an erratum where the MSI data
354 * is 'spi_number - 32'
356 switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
357 case XGENE_GICV2M_MSI_IIDR:
358 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
359 v2m->spi_offset = v2m->spi_start;
361 case BCM_NS2_GICV2M_MSI_IIDR:
362 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
363 v2m->spi_offset = 32;
367 v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long),
374 list_add_tail(&v2m->entry, &v2m_nodes);
376 pr_info("range%pR, SPI[%d:%d]\n", res,
377 v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
387 static struct of_device_id gicv2m_device_id[] = {
388 { .compatible = "arm,gic-v2m-frame", },
392 static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
393 struct irq_domain *parent)
396 struct device_node *node = to_of_node(parent_handle);
397 struct device_node *child;
399 for (child = of_find_matching_node(node, gicv2m_device_id); child;
400 child = of_find_matching_node(child, gicv2m_device_id)) {
401 u32 spi_start = 0, nr_spis = 0;
404 if (!of_find_property(child, "msi-controller", NULL))
407 ret = of_address_to_resource(child, 0, &res);
409 pr_err("Failed to allocate v2m resource.\n");
413 if (!of_property_read_u32(child, "arm,msi-base-spi",
415 !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
416 pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
419 ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
427 ret = gicv2m_allocate_domains(parent);
434 static int acpi_num_msi;
436 static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
438 struct v2m_data *data;
440 if (WARN_ON(acpi_num_msi <= 0))
443 /* We only return the fwnode of the first MSI frame. */
444 data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
452 acpi_parse_madt_msi(union acpi_subtable_headers *header,
453 const unsigned long end)
457 u32 spi_start = 0, nr_spis = 0;
458 struct acpi_madt_generic_msi_frame *m;
459 struct fwnode_handle *fwnode;
461 m = (struct acpi_madt_generic_msi_frame *)header;
462 if (BAD_MADT_ENTRY(m, end))
465 res.start = m->base_address;
466 res.end = m->base_address + SZ_4K - 1;
467 res.flags = IORESOURCE_MEM;
469 if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
470 spi_start = m->spi_base;
471 nr_spis = m->spi_count;
473 pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
477 fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
479 pr_err("Unable to allocate GICv2m domain token\n");
483 ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
485 irq_domain_free_fwnode(fwnode);
490 static int __init gicv2m_acpi_init(struct irq_domain *parent)
494 if (acpi_num_msi > 0)
497 acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
498 acpi_parse_madt_msi, 0);
500 if (acpi_num_msi <= 0)
503 ret = gicv2m_allocate_domains(parent);
507 pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
515 #else /* CONFIG_ACPI */
516 static int __init gicv2m_acpi_init(struct irq_domain *parent)
520 #endif /* CONFIG_ACPI */
522 int __init gicv2m_init(struct fwnode_handle *parent_handle,
523 struct irq_domain *parent)
525 if (is_of_node(parent_handle))
526 return gicv2m_of_init(parent_handle, parent);
528 return gicv2m_acpi_init(parent);