1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #include <linux/kernel.h>
5 #include <linux/init.h>
7 #include <linux/of_address.h>
8 #include <linux/module.h>
9 #include <linux/irqdomain.h>
10 #include <linux/irqchip.h>
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/smp.h>
16 #include <asm/traps.h>
17 #include <asm/reg_ops.h>
19 static struct irq_domain *root_domain;
20 static void __iomem *INTCG_base;
21 static void __iomem *INTCL_base;
25 #define COMM_IRQ_BASE 32
27 #define INTCG_SIZE 0x8000
28 #define INTCL_SIZE 0x1000
30 #define INTCG_ICTLR 0x0
31 #define INTCG_CICFGR 0x100
32 #define INTCG_CIDSTR 0x1000
34 #define INTCL_PICTLR 0x0
35 #define INTCL_CFGR 0x14
36 #define INTCL_SIGR 0x60
37 #define INTCL_RDYIR 0x6c
38 #define INTCL_SENR 0xa0
39 #define INTCL_CENR 0xa4
40 #define INTCL_CACR 0xb4
42 static DEFINE_PER_CPU(void __iomem *, intcl_reg);
44 static unsigned long *__trigger;
46 #define IRQ_OFFSET(irq) ((irq < COMM_IRQ_BASE) ? irq : (irq - COMM_IRQ_BASE))
48 #define TRIG_BYTE_OFFSET(i) ((((i) * 2) / 32) * 4)
49 #define TRIG_BIT_OFFSET(i) (((i) * 2) % 32)
51 #define TRIG_VAL(trigger, irq) (trigger << TRIG_BIT_OFFSET(IRQ_OFFSET(irq)))
52 #define TRIG_VAL_MSK(irq) (~(3 << TRIG_BIT_OFFSET(IRQ_OFFSET(irq))))
54 #define TRIG_BASE(irq) \
55 (TRIG_BYTE_OFFSET(IRQ_OFFSET(irq)) + ((irq < COMM_IRQ_BASE) ? \
56 (this_cpu_read(intcl_reg) + INTCL_CFGR) : (INTCG_base + INTCG_CICFGR)))
58 static DEFINE_SPINLOCK(setup_lock);
59 static void setup_trigger(unsigned long irq, unsigned long trigger)
63 spin_lock(&setup_lock);
66 tmp = readl_relaxed(TRIG_BASE(irq)) & TRIG_VAL_MSK(irq);
68 writel_relaxed(tmp | TRIG_VAL(trigger, irq), TRIG_BASE(irq));
70 spin_unlock(&setup_lock);
73 static void csky_mpintc_handler(struct pt_regs *regs)
75 void __iomem *reg_base = this_cpu_read(intcl_reg);
77 handle_domain_irq(root_domain,
78 readl_relaxed(reg_base + INTCL_RDYIR), regs);
81 static void csky_mpintc_enable(struct irq_data *d)
83 void __iomem *reg_base = this_cpu_read(intcl_reg);
85 setup_trigger(d->hwirq, __trigger[d->hwirq]);
87 writel_relaxed(d->hwirq, reg_base + INTCL_SENR);
90 static void csky_mpintc_disable(struct irq_data *d)
92 void __iomem *reg_base = this_cpu_read(intcl_reg);
94 writel_relaxed(d->hwirq, reg_base + INTCL_CENR);
97 static void csky_mpintc_eoi(struct irq_data *d)
99 void __iomem *reg_base = this_cpu_read(intcl_reg);
101 writel_relaxed(d->hwirq, reg_base + INTCL_CACR);
104 static int csky_mpintc_set_type(struct irq_data *d, unsigned int type)
106 switch (type & IRQ_TYPE_SENSE_MASK) {
107 case IRQ_TYPE_LEVEL_HIGH:
108 __trigger[d->hwirq] = 0;
110 case IRQ_TYPE_LEVEL_LOW:
111 __trigger[d->hwirq] = 1;
113 case IRQ_TYPE_EDGE_RISING:
114 __trigger[d->hwirq] = 2;
116 case IRQ_TYPE_EDGE_FALLING:
117 __trigger[d->hwirq] = 3;
127 static int csky_irq_set_affinity(struct irq_data *d,
128 const struct cpumask *mask_val,
132 unsigned int offset = 4 * (d->hwirq - COMM_IRQ_BASE);
135 cpu = cpumask_any_and(mask_val, cpu_online_mask);
137 cpu = cpumask_first(mask_val);
139 if (cpu >= nr_cpu_ids)
143 * The csky,mpintc could support auto irq deliver, but it only
144 * could deliver external irq to one cpu or all cpus. So it
145 * doesn't support deliver external irq to a group of cpus
147 * SO we only use auto deliver mode when affinity mask_val is
148 * equal to cpu_present_mask.
151 if (cpumask_equal(mask_val, cpu_present_mask))
156 writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset);
158 irq_data_update_effective_affinity(d, cpumask_of(cpu));
160 return IRQ_SET_MASK_OK_DONE;
164 static struct irq_chip csky_irq_chip = {
165 .name = "C-SKY SMP Intc",
166 .irq_eoi = csky_mpintc_eoi,
167 .irq_enable = csky_mpintc_enable,
168 .irq_disable = csky_mpintc_disable,
169 .irq_set_type = csky_mpintc_set_type,
171 .irq_set_affinity = csky_irq_set_affinity,
175 static int csky_irqdomain_map(struct irq_domain *d, unsigned int irq,
176 irq_hw_number_t hwirq)
178 if (hwirq < COMM_IRQ_BASE) {
179 irq_set_percpu_devid(irq);
180 irq_set_chip_and_handler(irq, &csky_irq_chip,
183 irq_set_chip_and_handler(irq, &csky_irq_chip,
190 static int csky_irq_domain_xlate_cells(struct irq_domain *d,
191 struct device_node *ctrlr, const u32 *intspec,
192 unsigned int intsize, unsigned long *out_hwirq,
193 unsigned int *out_type)
195 if (WARN_ON(intsize < 1))
198 *out_hwirq = intspec[0];
200 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
202 *out_type = IRQ_TYPE_LEVEL_HIGH;
207 static const struct irq_domain_ops csky_irqdomain_ops = {
208 .map = csky_irqdomain_map,
209 .xlate = csky_irq_domain_xlate_cells,
213 static void csky_mpintc_send_ipi(const struct cpumask *mask)
215 void __iomem *reg_base = this_cpu_read(intcl_reg);
218 * INTCL_SIGR[3:0] INTID
219 * INTCL_SIGR[8:15] CPUMASK
221 writel_relaxed((*cpumask_bits(mask)) << 8 | IPI_IRQ,
222 reg_base + INTCL_SIGR);
226 /* C-SKY multi processor interrupt controller */
228 csky_mpintc_init(struct device_node *node, struct device_node *parent)
231 unsigned int cpu, nr_irq;
233 unsigned int ipi_irq;
239 ret = of_property_read_u32(node, "csky,num-irqs", &nr_irq);
243 __trigger = kcalloc(nr_irq, sizeof(unsigned long), GFP_KERNEL);
244 if (__trigger == NULL)
247 if (INTCG_base == NULL) {
248 INTCG_base = ioremap(mfcr("cr<31, 14>"),
249 INTCL_SIZE*nr_cpu_ids + INTCG_SIZE);
250 if (INTCG_base == NULL)
253 INTCL_base = INTCG_base + INTCG_SIZE;
255 writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
258 root_domain = irq_domain_add_linear(node, nr_irq, &csky_irqdomain_ops,
264 for_each_present_cpu(cpu) {
265 per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu);
266 writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
269 set_handle_irq(&csky_mpintc_handler);
272 ipi_irq = irq_create_mapping(root_domain, IPI_IRQ);
276 set_send_ipi(&csky_mpintc_send_ipi, ipi_irq);
281 IRQCHIP_DECLARE(csky_mpintc, "csky,mpintc", csky_mpintc_init);