drivers/irqchip/irq-csky-mpintc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
   3
   4 #include <linux/kernel.h>
   5 #include <linux/init.h>
   6 #include <linux/of.h>
   7 #include <linux/of_address.h>
   8 #include <linux/module.h>
   9 #include <linux/irqdomain.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/smp.h>
  14 #include <linux/io.h>
  15 #include <asm/irq.h>
  16 #include <asm/traps.h>
  17 #include <asm/reg_ops.h>
  18
  19 static struct irq_domain *root_domain;
  20 static void __iomem *INTCG_base;
  21 static void __iomem *INTCL_base;
  22
  23 #define IPI_IRQ         15
  24 #define INTC_IRQS       256
  25 #define COMM_IRQ_BASE   32
  26
  27 #define INTCG_SIZE      0x8000
  28 #define INTCL_SIZE      0x1000
  29
  30 #define INTCG_ICTLR     0x0
  31 #define INTCG_CICFGR    0x100
  32 #define INTCG_CIDSTR    0x1000
  33
  34 #define INTCL_PICTLR    0x0
  35 #define INTCL_SIGR      0x60
  36 #define INTCL_HPPIR     0x68
  37 #define INTCL_RDYIR     0x6c
  38 #define INTCL_SENR      0xa0
  39 #define INTCL_CENR      0xa4
  40 #define INTCL_CACR      0xb4
  41
  42 static DEFINE_PER_CPU(void __iomem *, intcl_reg);
  43
  44 static void csky_mpintc_handler(struct pt_regs *regs)
  45 {
  46         void __iomem *reg_base = this_cpu_read(intcl_reg);
  47
  48         do {
  49                 handle_domain_irq(root_domain,
  50                                   readl_relaxed(reg_base + INTCL_RDYIR),
  51                                   regs);
  52         } while (readl_relaxed(reg_base + INTCL_HPPIR) & BIT(31));
  53 }
  54
  55 static void csky_mpintc_enable(struct irq_data *d)
  56 {
  57         void __iomem *reg_base = this_cpu_read(intcl_reg);
  58
  59         writel_relaxed(d->hwirq, reg_base + INTCL_SENR);
  60 }
  61
  62 static void csky_mpintc_disable(struct irq_data *d)
  63 {
  64         void __iomem *reg_base = this_cpu_read(intcl_reg);
  65
  66         writel_relaxed(d->hwirq, reg_base + INTCL_CENR);
  67 }
  68
  69 static void csky_mpintc_eoi(struct irq_data *d)
  70 {
  71         void __iomem *reg_base = this_cpu_read(intcl_reg);
  72
  73         writel_relaxed(d->hwirq, reg_base + INTCL_CACR);
  74 }
  75
  76 #ifdef CONFIG_SMP
  77 static int csky_irq_set_affinity(struct irq_data *d,
  78                                  const struct cpumask *mask_val,
  79                                  bool force)
  80 {
  81         unsigned int cpu;
  82         unsigned int offset = 4 * (d->hwirq - COMM_IRQ_BASE);
  83
  84         if (!force)
  85                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
  86         else
  87                 cpu = cpumask_first(mask_val);
  88
  89         if (cpu >= nr_cpu_ids)
  90                 return -EINVAL;
  91
  92         /*
  93          * The csky,mpintc could support auto irq deliver, but it only
  94          * could deliver external irq to one cpu or all cpus. So it
  95          * doesn't support deliver external irq to a group of cpus
  96          * with cpu_mask.
  97          * SO we only use auto deliver mode when affinity mask_val is
  98          * equal to cpu_present_mask.
  99          *
 100          */
 101         if (cpumask_equal(mask_val, cpu_present_mask))
 102                 cpu = 0;
 103         else
 104                 cpu |= BIT(31);
 105
 106         writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset);
 107
 108         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 109
 110         return IRQ_SET_MASK_OK_DONE;
 111 }
 112 #endif
 113
 114 static struct irq_chip csky_irq_chip = {
 115         .name           = "C-SKY SMP Intc",
 116         .irq_eoi        = csky_mpintc_eoi,
 117         .irq_enable     = csky_mpintc_enable,
 118         .irq_disable    = csky_mpintc_disable,
 119 #ifdef CONFIG_SMP
 120         .irq_set_affinity = csky_irq_set_affinity,
 121 #endif
 122 };
 123
 124 static int csky_irqdomain_map(struct irq_domain *d, unsigned int irq,
 125                               irq_hw_number_t hwirq)
 126 {
 127         if (hwirq < COMM_IRQ_BASE) {
 128                 irq_set_percpu_devid(irq);
 129                 irq_set_chip_and_handler(irq, &csky_irq_chip,
 130                                          handle_percpu_irq);
 131         } else {
 132                 irq_set_chip_and_handler(irq, &csky_irq_chip,
 133                                          handle_fasteoi_irq);
 134         }
 135
 136         return 0;
 137 }
 138
 139 static const struct irq_domain_ops csky_irqdomain_ops = {
 140         .map    = csky_irqdomain_map,
 141         .xlate  = irq_domain_xlate_onecell,
 142 };
 143
 144 #ifdef CONFIG_SMP
 145 static void csky_mpintc_send_ipi(const struct cpumask *mask)
 146 {
 147         void __iomem *reg_base = this_cpu_read(intcl_reg);
 148
 149         /*
 150          * INTCL_SIGR[3:0] INTID
 151          * INTCL_SIGR[8:15] CPUMASK
 152          */
 153         writel_relaxed((*cpumask_bits(mask)) << 8 | IPI_IRQ,
 154                                         reg_base + INTCL_SIGR);
 155 }
 156 #endif
 157
 158 /* C-SKY multi processor interrupt controller */
 159 static int __init
 160 csky_mpintc_init(struct device_node *node, struct device_node *parent)
 161 {
 162         int ret;
 163         unsigned int cpu, nr_irq;
 164 #ifdef CONFIG_SMP
 165         unsigned int ipi_irq;
 166 #endif
 167
 168         if (parent)
 169                 return 0;
 170
 171         ret = of_property_read_u32(node, "csky,num-irqs", &nr_irq);
 172         if (ret < 0)
 173                 nr_irq = INTC_IRQS;
 174
 175         if (INTCG_base == NULL) {
 176                 INTCG_base = ioremap(mfcr("cr<31, 14>"),
 177                                      INTCL_SIZE*nr_cpu_ids + INTCG_SIZE);
 178                 if (INTCG_base == NULL)
 179                         return -EIO;
 180
 181                 INTCL_base = INTCG_base + INTCG_SIZE;
 182
 183                 writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
 184         }
 185
 186         root_domain = irq_domain_add_linear(node, nr_irq, &csky_irqdomain_ops,
 187                                             NULL);
 188         if (!root_domain)
 189                 return -ENXIO;
 190
 191         /* for every cpu */
 192         for_each_present_cpu(cpu) {
 193                 per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu);
 194                 writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
 195         }
 196
 197         set_handle_irq(&csky_mpintc_handler);
 198
 199 #ifdef CONFIG_SMP
 200         ipi_irq = irq_create_mapping(root_domain, IPI_IRQ);
 201         if (!ipi_irq)
 202                 return -EIO;
 203
 204         set_send_ipi(&csky_mpintc_send_ipi, ipi_irq);
 205 #endif
 206
 207         return 0;
 208 }
 209 IRQCHIP_DECLARE(csky_mpintc, "csky,mpintc", csky_mpintc_init);