drivers/irqchip/irq-ativic32.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2005-2017 Andes Technology Corporation
   3
   4 #include <linux/irq.h>
   5 #include <linux/of.h>
   6 #include <linux/of_irq.h>
   7 #include <linux/of_address.h>
   8 #include <linux/hardirq.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/irqdomain.h>
  11 #include <linux/irqchip.h>
  12 #include <nds32_intrinsic.h>
  13
  14 #include <asm/irq_regs.h>
  15
  16 unsigned long wake_mask;
  17
  18 static void ativic32_ack_irq(struct irq_data *data)
  19 {
  20         __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
  21 }
  22
  23 static void ativic32_mask_irq(struct irq_data *data)
  24 {
  25         unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
  26         __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), NDS32_SR_INT_MASK2);
  27 }
  28
  29 static void ativic32_unmask_irq(struct irq_data *data)
  30 {
  31         unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
  32         __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
  33 }
  34
  35 static int nointc_set_wake(struct irq_data *data, unsigned int on)
  36 {
  37         unsigned long int_mask = __nds32__mfsr(NDS32_SR_INT_MASK);
  38         static unsigned long irq_orig_bit;
  39         u32 bit = 1 << data->hwirq;
  40
  41         if (on) {
  42                 if (int_mask & bit)
  43                         __assign_bit(data->hwirq, &irq_orig_bit, true);
  44                 else
  45                         __assign_bit(data->hwirq, &irq_orig_bit, false);
  46
  47                 __assign_bit(data->hwirq, &int_mask, true);
  48                 __assign_bit(data->hwirq, &wake_mask, true);
  49
  50         } else {
  51                 if (!(irq_orig_bit & bit))
  52                         __assign_bit(data->hwirq, &int_mask, false);
  53
  54                 __assign_bit(data->hwirq, &wake_mask, false);
  55                 __assign_bit(data->hwirq, &irq_orig_bit, false);
  56         }
  57
  58         __nds32__mtsr_dsb(int_mask, NDS32_SR_INT_MASK);
  59
  60         return 0;
  61 }
  62
  63 static struct irq_chip ativic32_chip = {
  64         .name = "ativic32",
  65         .irq_ack = ativic32_ack_irq,
  66         .irq_mask = ativic32_mask_irq,
  67         .irq_unmask = ativic32_unmask_irq,
  68         .irq_set_wake = nointc_set_wake,
  69 };
  70
  71 static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
  72
  73 static struct irq_domain *root_domain;
  74 static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
  75                                   irq_hw_number_t hw)
  76 {
  77
  78         unsigned long int_trigger_type;
  79         u32 type;
  80         struct irq_data *irq_data;
  81         int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER);
  82         irq_data = irq_get_irq_data(virq);
  83         if (!irq_data)
  84                 return -EINVAL;
  85
  86         if (int_trigger_type & (BIT(hw))) {
  87                 irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq);
  88                 type = IRQ_TYPE_EDGE_RISING;
  89         } else {
  90                 irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);
  91                 type = IRQ_TYPE_LEVEL_HIGH;
  92         }
  93
  94         irqd_set_trigger_type(irq_data, type);
  95         return 0;
  96 }
  97
  98 static const struct irq_domain_ops ativic32_ops = {
  99         .map = ativic32_irq_domain_map,
 100         .xlate = irq_domain_xlate_onecell
 101 };
 102
 103 static irq_hw_number_t get_intr_src(void)
 104 {
 105         return ((__nds32__mfsr(NDS32_SR_ITYPE) & ITYPE_mskVECTOR) >> ITYPE_offVECTOR)
 106                 - NDS32_VECTOR_offINTERRUPT;
 107 }
 108
 109 static void ativic32_handle_irq(struct pt_regs *regs)
 110 {
 111         irq_hw_number_t hwirq = get_intr_src();
 112         generic_handle_domain_irq(root_domain, hwirq);
 113 }
 114
 115 /*
 116  * TODO: convert nds32 to GENERIC_IRQ_MULTI_HANDLER so that this entry logic
 117  * can live in arch code.
 118  */
 119 asmlinkage void asm_do_IRQ(struct pt_regs *regs)
 120 {
 121         struct pt_regs *old_regs;
 122
 123         irq_enter();
 124         old_regs = set_irq_regs(regs);
 125         ativic32_handle_irq(regs);
 126         set_irq_regs(old_regs);
 127         irq_exit();
 128 }
 129
 130 int __init ativic32_init_irq(struct device_node *node, struct device_node *parent)
 131 {
 132         unsigned long int_vec_base, nivic, nr_ints;
 133
 134         if (WARN(parent, "non-root ativic32 are not supported"))
 135                 return -EINVAL;
 136
 137         int_vec_base = __nds32__mfsr(NDS32_SR_IVB);
 138
 139         if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0)
 140                 panic("Unable to use atcivic32 for this cpu.\n");
 141
 142         nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC;
 143         if (nivic >= ARRAY_SIZE(nivic_map))
 144                 panic("The number of input for ativic32 is not supported.\n");
 145
 146         nr_ints = nivic_map[nivic];
 147
 148         root_domain = irq_domain_add_linear(node, nr_ints,
 149                         &ativic32_ops, NULL);
 150
 151         if (!root_domain)
 152                 panic("%s: unable to create IRQ domain\n", node->full_name);
 153
 154         return 0;
 155 }
 156 IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq);