1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_MULTI_HANDLER
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
22 default 2 if ARCH_REALVIEW
36 select GENERIC_IRQ_MULTI_HANDLER
37 select IRQ_DOMAIN_HIERARCHY
38 select PARTITION_PERCPU
39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
43 select GENERIC_MSI_IRQ_DOMAIN
46 config ARM_GIC_V3_ITS_PCI
48 depends on ARM_GIC_V3_ITS
51 default ARM_GIC_V3_ITS
53 config ARM_GIC_V3_ITS_FSL_MC
55 depends on ARM_GIC_V3_ITS
57 default ARM_GIC_V3_ITS
61 select IRQ_DOMAIN_HIERARCHY
62 select GENERIC_IRQ_CHIP
67 select GENERIC_IRQ_MULTI_HANDLER
71 default 4 if ARCH_S5PV210
75 The maximum number of VICs available in the system, for
78 config ARMADA_370_XP_IRQ
80 select GENERIC_IRQ_CHIP
82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
88 select GENERIC_IRQ_CHIP
91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
92 depends on OF || COMPILE_TEST
93 select GENERIC_IRQ_CHIP
96 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
100 select GENERIC_IRQ_CHIP
102 select GENERIC_IRQ_MULTI_HANDLER
105 config ATMEL_AIC5_IRQ
107 select GENERIC_IRQ_CHIP
109 select GENERIC_IRQ_MULTI_HANDLER
116 config BCM6345_L1_IRQ
118 select GENERIC_IRQ_CHIP
120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
122 config BCM7038_L1_IRQ
124 select GENERIC_IRQ_CHIP
126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
128 config BCM7120_L2_IRQ
130 select GENERIC_IRQ_CHIP
133 config BRCMSTB_L2_IRQ
135 select GENERIC_IRQ_CHIP
140 select GENERIC_IRQ_CHIP
143 config DAVINCI_CP_INTC
145 select GENERIC_IRQ_CHIP
150 select GENERIC_IRQ_CHIP
153 config FARADAY_FTINTC010
156 select GENERIC_IRQ_MULTI_HANDLER
159 config HISILICON_IRQ_MBIGEN
162 select ARM_GIC_V3_ITS
166 select GENERIC_IRQ_CHIP
172 select GENERIC_IRQ_MULTI_HANDLER
180 select GENERIC_IRQ_CHIP
181 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
183 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
184 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
186 config CLPS711X_IRQCHIP
188 depends on ARCH_CLPS711X
190 select GENERIC_IRQ_MULTI_HANDLER
203 select GENERIC_IRQ_CHIP
209 select GENERIC_IRQ_MULTI_HANDLER
213 select GENERIC_IRQ_CHIP
217 bool "J-Core integrated AIC" if COMPILE_TEST
221 Support for the J-Core integrated AIC.
227 config RENESAS_INTC_IRQPIN
228 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
231 Enable support for the Renesas Interrupt Controller for external
232 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
235 bool "Renesas R-Mobile APE6 and R-Car IRQC support" if COMPILE_TEST
236 select GENERIC_IRQ_CHIP
239 Enable support for the Renesas Interrupt Controller for external
240 devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs.
242 config RENESAS_RZA1_IRQC
243 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
244 select IRQ_DOMAIN_HIERARCHY
246 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
247 to 8 external interrupts with configurable sense select.
254 Enables SysCfg Controlled IRQs on STi based platforms.
259 select GENERIC_IRQ_CHIP
264 select GENERIC_IRQ_CHIP
267 tristate "TS-4800 IRQ controller"
270 depends on SOC_IMX51 || COMPILE_TEST
272 Support for the TS-4800 FPGA IRQ controller
274 config VERSATILE_FPGA_IRQ
278 config VERSATILE_FPGA_IRQ_NR
281 depends on VERSATILE_FPGA_IRQ
286 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
295 Support for a CROSSBAR ip that precedes the main interrupt controller.
296 The primary irqchip invokes the crossbar's callback which inturn allocates
297 a free irq and configures the IP. Thus the peripheral interrupts are
298 routed to one of the free irqchip interrupt lines.
301 tristate "Keystone 2 IRQ controller IP"
302 depends on ARCH_KEYSTONE
304 Support for Texas Instruments Keystone 2 IRQ controller IP which
305 is part of the Keystone 2 IPC mechanism
309 select GENERIC_IRQ_IPI
310 select IRQ_DOMAIN_HIERARCHY
315 depends on MACH_INGENIC
318 config INGENIC_TCU_IRQ
319 bool "Ingenic JZ47xx TCU interrupt controller"
321 depends on MIPS || COMPILE_TEST
323 select GENERIC_IRQ_CHIP
325 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
330 config RENESAS_H8300H_INTC
334 config RENESAS_H8S_INTC
335 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
338 Enable support for the Renesas H8/300 Interrupt Controller, as found
345 Enables the wakeup IRQs for IMX platforms with GPCv2 block
348 def_bool y if MACH_ASM9260 || ARCH_MXS
352 config MSCC_OCELOT_IRQ
355 select GENERIC_IRQ_CHIP
365 select GENERIC_MSI_IRQ_DOMAIN
374 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
378 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
379 depends on PCI && PCI_MSI
381 config PARTITION_PERCPU
385 bool "NPS400 Global Interrupt Manager (GIM)"
386 depends on ARC || (COMPILE_TEST && !64BIT)
389 Support the EZchip NPS400 global interrupt controller
394 select GENERIC_IRQ_CHIP
396 config QCOM_IRQ_COMBINER
397 bool "QCOM IRQ combiner support"
398 depends on ARCH_QCOM && ACPI
399 select IRQ_DOMAIN_HIERARCHY
401 Say yes here to add support for the IRQ combiner devices embedded
402 in Qualcomm Technologies chips.
404 config IRQ_UNIPHIER_AIDET
405 bool "UniPhier AIDET support" if COMPILE_TEST
406 depends on ARCH_UNIPHIER || COMPILE_TEST
407 default ARCH_UNIPHIER
408 select IRQ_DOMAIN_HIERARCHY
410 Support for the UniPhier AIDET (ARM Interrupt Detector).
412 config MESON_IRQ_GPIO
413 bool "Meson GPIO Interrupt Multiplexer"
414 depends on ARCH_MESON
415 select IRQ_DOMAIN_HIERARCHY
417 Support Meson SoC Family GPIO Interrupt Multiplexer
420 bool "Goldfish programmable interrupt controller"
421 depends on MIPS && (GOLDFISH || COMPILE_TEST)
424 Say yes here to enable Goldfish interrupt controller driver used
425 for Goldfish based virtual platforms.
430 select IRQ_DOMAIN_HIERARCHY
432 Power Domain Controller driver to manage and configure wakeup
433 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
436 bool "C-SKY Multi Processor Interrupt Controller"
439 Say yes here to enable C-SKY SMP interrupt controller driver used
440 for C-SKY SMP system.
441 In fact it's not mmio map in hardware and it uses ld/st to visit the
442 controller's register inside CPU.
445 bool "C-SKY APB Interrupt Controller"
448 Say yes here to enable C-SKY APB interrupt controller driver used
449 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
450 the controller's register.
453 bool "i.MX IRQSTEER support"
454 depends on ARCH_MXC || COMPILE_TEST
458 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
461 def_bool y if ARCH_MXC || COMPILE_TEST
464 Support for the i.MX INTMUX interrupt multiplexer.
467 bool "Loongson-1 Interrupt Controller"
468 depends on MACH_LOONGSON32
471 select GENERIC_IRQ_CHIP
473 Support for the Loongson-1 platform Interrupt Controller.
475 config TI_SCI_INTR_IRQCHIP
477 depends on TI_SCI_PROTOCOL
478 select IRQ_DOMAIN_HIERARCHY
480 This enables the irqchip driver support for K3 Interrupt router
481 over TI System Control Interface available on some new TI's SoCs.
482 If you wish to use interrupt router irq resources managed by the
483 TI System Controller, say Y here. Otherwise, say N.
485 config TI_SCI_INTA_IRQCHIP
487 depends on TI_SCI_PROTOCOL
488 select IRQ_DOMAIN_HIERARCHY
489 select TI_SCI_INTA_MSI_DOMAIN
491 This enables the irqchip driver support for K3 Interrupt aggregator
492 over TI System Control Interface available on some new TI's SoCs.
493 If you wish to use interrupt aggregator irq resources managed by the
494 TI System Controller, say Y here. Otherwise, say N.
497 bool "RISC-V Local Interrupt Controller"
501 This enables support for the per-HART local interrupt controller
502 found in standard RISC-V systems. The per-HART local interrupt
503 controller handles timer interrupts, software interrupts, and
504 hardware interrupts. Without a per-HART local interrupt controller,
505 a RISC-V system will be unable to handle any interrupts.
507 If you don't know what to do here, say Y.
510 bool "SiFive Platform-Level Interrupt Controller"
512 select IRQ_DOMAIN_HIERARCHY
514 This enables support for the PLIC chip found in SiFive (and
515 potentially other) RISC-V systems. The PLIC controls devices
516 interrupts and connects them to each core's local interrupt
517 controller. Aside from timer and software interrupts, all other
518 interrupt sources are subordinate to the PLIC.
520 If you don't know what to do here, say Y.
522 config EXYNOS_IRQ_COMBINER
523 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
524 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
526 Say yes here to add support for the IRQ combiner devices embedded
527 in Samsung Exynos chips.
529 config LOONGSON_LIOINTC
530 bool "Loongson Local I/O Interrupt Controller"
531 depends on MACH_LOONGSON64
534 select GENERIC_IRQ_CHIP
536 Support for the Loongson Local I/O Interrupt Controller.
538 config LOONGSON_HTPIC
539 bool "Loongson3 HyperTransport PIC Controller"
540 depends on MACH_LOONGSON64
543 select GENERIC_IRQ_CHIP
546 Support for the Loongson-3 HyperTransport PIC Controller.
548 config LOONGSON_HTVEC
549 bool "Loongson3 HyperTransport Interrupt Vector Controller"
550 depends on MACH_LOONGSON64
551 default MACH_LOONGSON64
552 select IRQ_DOMAIN_HIERARCHY
554 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
556 config LOONGSON_PCH_PIC
557 bool "Loongson PCH PIC Controller"
558 depends on MACH_LOONGSON64 || COMPILE_TEST
559 default MACH_LOONGSON64
560 select IRQ_DOMAIN_HIERARCHY
561 select IRQ_FASTEOI_HIERARCHY_HANDLERS
563 Support for the Loongson PCH PIC Controller.
565 config LOONGSON_PCH_MSI
566 bool "Loongson PCH PIC Controller"
567 depends on MACH_LOONGSON64 || COMPILE_TEST
569 default MACH_LOONGSON64
570 select IRQ_DOMAIN_HIERARCHY
573 Support for the Loongson PCH MSI Controller.