1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
6 depends on (OF_IRQ || ACPI_GENERIC_GSI)
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
21 default 2 if ARCH_REALVIEW
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
41 select GENERIC_MSI_IRQ
44 config ARM_GIC_V3_ITS_PCI
46 depends on ARM_GIC_V3_ITS
49 default ARM_GIC_V3_ITS
51 config ARM_GIC_V3_ITS_FSL_MC
53 depends on ARM_GIC_V3_ITS
55 default ARM_GIC_V3_ITS
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
68 default 4 if ARCH_S5PV210
72 The maximum number of VICs available in the system, for
75 config ARMADA_370_XP_IRQ
77 select GENERIC_IRQ_CHIP
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
85 select GENERIC_IRQ_CHIP
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
90 select GENERIC_IRQ_CHIP
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97 select GENERIC_IRQ_CHIP
101 config ATMEL_AIC5_IRQ
103 select GENERIC_IRQ_CHIP
111 config BCM6345_L1_IRQ
113 select GENERIC_IRQ_CHIP
115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
117 config BCM7038_L1_IRQ
118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
119 depends on ARCH_BRCMSTB || BMIPS_GENERIC
120 default ARCH_BRCMSTB || BMIPS_GENERIC
121 select GENERIC_IRQ_CHIP
123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
125 config BCM7120_L2_IRQ
126 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
127 depends on ARCH_BRCMSTB || BMIPS_GENERIC
128 default ARCH_BRCMSTB || BMIPS_GENERIC
129 select GENERIC_IRQ_CHIP
132 config BRCMSTB_L2_IRQ
133 tristate "Broadcom STB generic L2 interrupt controller driver"
134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
136 select GENERIC_IRQ_CHIP
139 config DAVINCI_CP_INTC
141 select GENERIC_IRQ_CHIP
146 select GENERIC_IRQ_CHIP
147 select IRQ_DOMAIN_HIERARCHY
149 config FARADAY_FTINTC010
154 config HISILICON_IRQ_MBIGEN
157 select ARM_GIC_V3_ITS
161 select GENERIC_IRQ_CHIP
174 select GENERIC_IRQ_CHIP
175 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
177 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
179 config CLPS711X_IRQCHIP
181 depends on ARCH_CLPS711X
195 select GENERIC_IRQ_CHIP
204 select GENERIC_IRQ_CHIP
208 bool "J-Core integrated AIC" if COMPILE_TEST
212 Support for the J-Core integrated AIC.
218 config RENESAS_INTC_IRQPIN
219 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
222 Enable support for the Renesas Interrupt Controller for external
223 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
226 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
227 select GENERIC_IRQ_CHIP
230 Enable support for the Renesas Interrupt Controller for external
231 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
233 config RENESAS_RZA1_IRQC
234 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
235 select IRQ_DOMAIN_HIERARCHY
237 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
238 to 8 external interrupts with configurable sense select.
240 config RENESAS_RZG2L_IRQC
241 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
242 select GENERIC_IRQ_CHIP
243 select IRQ_DOMAIN_HIERARCHY
245 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
246 for external devices.
249 bool "Kontron sl28cpld IRQ controller"
250 depends on MFD_SL28CPLD=y || COMPILE_TEST
253 Interrupt controller driver for the board management controller
254 found on the Kontron sl28 CPLD.
261 Enables SysCfg Controlled IRQs on STi based platforms.
268 select IRQ_DOMAIN_HIERARCHY
269 select IRQ_FASTEOI_HIERARCHY_HANDLERS
271 config SUNXI_NMI_INTC
273 select GENERIC_IRQ_CHIP
278 select GENERIC_IRQ_CHIP
281 tristate "TS-4800 IRQ controller"
284 depends on SOC_IMX51 || COMPILE_TEST
286 Support for the TS-4800 FPGA IRQ controller
288 config VERSATILE_FPGA_IRQ
292 config VERSATILE_FPGA_IRQ_NR
295 depends on VERSATILE_FPGA_IRQ
300 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
303 bool "Xilinx Interrupt Controller IP"
304 depends on OF_ADDRESS
307 Support for the Xilinx Interrupt Controller IP core.
308 This is used as a primary controller with MicroBlaze and can also
309 be used as a secondary chained controller on other platforms.
314 Support for a CROSSBAR ip that precedes the main interrupt controller.
315 The primary irqchip invokes the crossbar's callback which inturn allocates
316 a free irq and configures the IP. Thus the peripheral interrupts are
317 routed to one of the free irqchip interrupt lines.
320 tristate "Keystone 2 IRQ controller IP"
321 depends on ARCH_KEYSTONE
323 Support for Texas Instruments Keystone 2 IRQ controller IP which
324 is part of the Keystone 2 IPC mechanism
328 select GENERIC_IRQ_IPI if SMP
329 select IRQ_DOMAIN_HIERARCHY
334 depends on MACH_INGENIC
337 config INGENIC_TCU_IRQ
338 bool "Ingenic JZ47xx TCU interrupt controller"
340 depends on MIPS || COMPILE_TEST
342 select GENERIC_IRQ_CHIP
344 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
353 Enables the wakeup IRQs for IMX platforms with GPCv2 block
356 def_bool y if MACH_ASM9260 || ARCH_MXS
360 config MSCC_OCELOT_IRQ
363 select GENERIC_IRQ_CHIP
373 select GENERIC_MSI_IRQ
382 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
386 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
389 config PARTITION_PERCPU
395 select GENERIC_IRQ_CHIP
397 config QCOM_IRQ_COMBINER
398 bool "QCOM IRQ combiner support"
399 depends on ARCH_QCOM && ACPI
400 select IRQ_DOMAIN_HIERARCHY
402 Say yes here to add support for the IRQ combiner devices embedded
403 in Qualcomm Technologies chips.
405 config IRQ_UNIPHIER_AIDET
406 bool "UniPhier AIDET support" if COMPILE_TEST
407 depends on ARCH_UNIPHIER || COMPILE_TEST
408 default ARCH_UNIPHIER
409 select IRQ_DOMAIN_HIERARCHY
411 Support for the UniPhier AIDET (ARM Interrupt Detector).
413 config MESON_IRQ_GPIO
414 tristate "Meson GPIO Interrupt Multiplexer"
415 depends on ARCH_MESON || COMPILE_TEST
417 select IRQ_DOMAIN_HIERARCHY
419 Support Meson SoC Family GPIO Interrupt Multiplexer
422 bool "Goldfish programmable interrupt controller"
423 depends on MIPS && (GOLDFISH || COMPILE_TEST)
424 select GENERIC_IRQ_CHIP
427 Say yes here to enable Goldfish interrupt controller driver used
428 for Goldfish based virtual platforms.
433 select IRQ_DOMAIN_HIERARCHY
435 Power Domain Controller driver to manage and configure wakeup
436 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
442 select IRQ_DOMAIN_HIERARCHY
444 MSM Power Manager driver to manage and configure wakeup
445 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
451 Say yes here to enable C-SKY SMP interrupt controller driver used
452 for C-SKY SMP system.
453 In fact it's not mmio map in hardware and it uses ld/st to visit the
454 controller's register inside CPU.
457 bool "C-SKY APB Interrupt Controller"
460 Say yes here to enable C-SKY APB interrupt controller driver used
461 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
462 the controller's register.
465 bool "i.MX IRQSTEER support"
466 depends on ARCH_MXC || COMPILE_TEST
470 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
473 bool "i.MX INTMUX support" if COMPILE_TEST
474 default y if ARCH_MXC
477 Support for the i.MX INTMUX interrupt multiplexer.
480 tristate "i.MX MU used as MSI controller"
481 depends on OF && HAS_IOMEM
482 depends on ARCH_MXC || COMPILE_TEST
483 default m if ARCH_MXC
485 select IRQ_DOMAIN_HIERARCHY
486 select GENERIC_MSI_IRQ
488 Provide a driver for the i.MX Messaging Unit block used as a
489 CPU-to-CPU MSI controller. This requires a specially crafted DT
490 to make use of this driver.
495 bool "Loongson-1 Interrupt Controller"
496 depends on MACH_LOONGSON32
499 select GENERIC_IRQ_CHIP
501 Support for the Loongson-1 platform Interrupt Controller.
503 config TI_SCI_INTR_IRQCHIP
505 depends on TI_SCI_PROTOCOL
506 select IRQ_DOMAIN_HIERARCHY
508 This enables the irqchip driver support for K3 Interrupt router
509 over TI System Control Interface available on some new TI's SoCs.
510 If you wish to use interrupt router irq resources managed by the
511 TI System Controller, say Y here. Otherwise, say N.
513 config TI_SCI_INTA_IRQCHIP
515 depends on TI_SCI_PROTOCOL
516 select IRQ_DOMAIN_HIERARCHY
517 select TI_SCI_INTA_MSI_DOMAIN
519 This enables the irqchip driver support for K3 Interrupt aggregator
520 over TI System Control Interface available on some new TI's SoCs.
521 If you wish to use interrupt aggregator irq resources managed by the
522 TI System Controller, say Y here. Otherwise, say N.
530 This enables support for the PRU-ICSS Local Interrupt Controller
531 present within a PRU-ICSS subsystem present on various TI SoCs.
532 The PRUSS INTC enables various interrupts to be routed to multiple
533 different processors within the SoC.
542 select IRQ_DOMAIN_HIERARCHY
543 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
545 config EXYNOS_IRQ_COMBINER
546 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
547 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
549 Say yes here to add support for the IRQ combiner devices embedded
550 in Samsung Exynos chips.
552 config IRQ_LOONGARCH_CPU
554 select GENERIC_IRQ_CHIP
556 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
557 select LOONGSON_HTVEC
558 select LOONGSON_LIOINTC
559 select LOONGSON_EIOINTC
560 select LOONGSON_PCH_PIC
561 select LOONGSON_PCH_MSI
562 select LOONGSON_PCH_LPC
564 Support for the LoongArch CPU Interrupt Controller. For details of
565 irq chip hierarchy on LoongArch platforms please read the document
566 Documentation/loongarch/irq-chip-model.rst.
568 config LOONGSON_LIOINTC
569 bool "Loongson Local I/O Interrupt Controller"
570 depends on MACH_LOONGSON64
573 select GENERIC_IRQ_CHIP
575 Support for the Loongson Local I/O Interrupt Controller.
577 config LOONGSON_EIOINTC
578 bool "Loongson Extend I/O Interrupt Controller"
580 depends on MACH_LOONGSON64
581 default MACH_LOONGSON64
582 select IRQ_DOMAIN_HIERARCHY
583 select GENERIC_IRQ_CHIP
585 Support for the Loongson3 Extend I/O Interrupt Vector Controller.
587 config LOONGSON_HTPIC
588 bool "Loongson3 HyperTransport PIC Controller"
589 depends on MACH_LOONGSON64 && MIPS
592 select GENERIC_IRQ_CHIP
594 Support for the Loongson-3 HyperTransport PIC Controller.
596 config LOONGSON_HTVEC
597 bool "Loongson HyperTransport Interrupt Vector Controller"
598 depends on MACH_LOONGSON64
599 default MACH_LOONGSON64
600 select IRQ_DOMAIN_HIERARCHY
602 Support for the Loongson HyperTransport Interrupt Vector Controller.
604 config LOONGSON_PCH_PIC
605 bool "Loongson PCH PIC Controller"
606 depends on MACH_LOONGSON64
607 default MACH_LOONGSON64
608 select IRQ_DOMAIN_HIERARCHY
609 select IRQ_FASTEOI_HIERARCHY_HANDLERS
611 Support for the Loongson PCH PIC Controller.
613 config LOONGSON_PCH_MSI
614 bool "Loongson PCH MSI Controller"
615 depends on MACH_LOONGSON64
617 default MACH_LOONGSON64
618 select IRQ_DOMAIN_HIERARCHY
621 Support for the Loongson PCH MSI Controller.
623 config LOONGSON_PCH_LPC
624 bool "Loongson PCH LPC Controller"
626 depends on MACH_LOONGSON64
627 default MACH_LOONGSON64
628 select IRQ_DOMAIN_HIERARCHY
630 Support for the Loongson PCH LPC Controller.
633 bool "MStar Interrupt Controller"
634 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
635 default ARCH_MEDIATEK
637 select IRQ_DOMAIN_HIERARCHY
639 Support MStar Interrupt Controller.
642 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
643 depends on ARCH_WPCM450
645 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
649 select GENERIC_IRQ_CHIP
653 bool "Apple Interrupt Controller (AIC)"
655 depends on ARCH_APPLE || COMPILE_TEST
656 select GENERIC_IRQ_IPI_MUX
658 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
662 bool "Microchip External Interrupt Controller"
663 depends on ARCH_AT91 || COMPILE_TEST
665 select IRQ_DOMAIN_HIERARCHY
667 Support for Microchip External Interrupt Controller.
669 config SUNPLUS_SP7021_INTC
670 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
673 Support for the Sunplus SP7021 Interrupt Controller IP core.
674 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
675 chained controller, routing all interrupt source in P-Chip to
676 the primary controller on C-Chip.