1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
21 default 2 if ARCH_REALVIEW
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
41 select GENERIC_MSI_IRQ_DOMAIN
44 config ARM_GIC_V3_ITS_PCI
46 depends on ARM_GIC_V3_ITS
49 default ARM_GIC_V3_ITS
51 config ARM_GIC_V3_ITS_FSL_MC
53 depends on ARM_GIC_V3_ITS
55 default ARM_GIC_V3_ITS
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
68 default 4 if ARCH_S5PV210
72 The maximum number of VICs available in the system, for
75 config ARMADA_370_XP_IRQ
77 select GENERIC_IRQ_CHIP
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
85 select GENERIC_IRQ_CHIP
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF || COMPILE_TEST
90 select GENERIC_IRQ_CHIP
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97 select GENERIC_IRQ_CHIP
101 config ATMEL_AIC5_IRQ
103 select GENERIC_IRQ_CHIP
111 config BCM6345_L1_IRQ
113 select GENERIC_IRQ_CHIP
115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
117 config BCM7038_L1_IRQ
118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
119 depends on ARCH_BRCMSTB || BMIPS_GENERIC
120 default ARCH_BRCMSTB || BMIPS_GENERIC
121 select GENERIC_IRQ_CHIP
123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
125 config BCM7120_L2_IRQ
126 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
127 depends on ARCH_BRCMSTB || BMIPS_GENERIC
128 default ARCH_BRCMSTB || BMIPS_GENERIC
129 select GENERIC_IRQ_CHIP
132 config BRCMSTB_L2_IRQ
133 tristate "Broadcom STB generic L2 interrupt controller driver"
134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
136 select GENERIC_IRQ_CHIP
141 select GENERIC_IRQ_CHIP
144 config DAVINCI_CP_INTC
146 select GENERIC_IRQ_CHIP
151 select GENERIC_IRQ_CHIP
152 select IRQ_DOMAIN_HIERARCHY
154 config FARADAY_FTINTC010
159 config HISILICON_IRQ_MBIGEN
162 select ARM_GIC_V3_ITS
166 select GENERIC_IRQ_CHIP
179 select GENERIC_IRQ_CHIP
180 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
182 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
184 config CLPS711X_IRQCHIP
186 depends on ARCH_CLPS711X
200 select GENERIC_IRQ_CHIP
209 select GENERIC_IRQ_CHIP
213 bool "J-Core integrated AIC" if COMPILE_TEST
217 Support for the J-Core integrated AIC.
223 config RENESAS_INTC_IRQPIN
224 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
227 Enable support for the Renesas Interrupt Controller for external
228 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
231 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
232 select GENERIC_IRQ_CHIP
235 Enable support for the Renesas Interrupt Controller for external
236 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
238 config RENESAS_RZA1_IRQC
239 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
240 select IRQ_DOMAIN_HIERARCHY
242 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
243 to 8 external interrupts with configurable sense select.
246 bool "Kontron sl28cpld IRQ controller"
247 depends on MFD_SL28CPLD=y || COMPILE_TEST
250 Interrupt controller driver for the board management controller
251 found on the Kontron sl28 CPLD.
258 Enables SysCfg Controlled IRQs on STi based platforms.
263 select GENERIC_IRQ_CHIP
266 tristate "TS-4800 IRQ controller"
269 depends on SOC_IMX51 || COMPILE_TEST
271 Support for the TS-4800 FPGA IRQ controller
273 config VERSATILE_FPGA_IRQ
277 config VERSATILE_FPGA_IRQ_NR
280 depends on VERSATILE_FPGA_IRQ
285 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
288 bool "Xilinx Interrupt Controller IP"
289 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
292 Support for the Xilinx Interrupt Controller IP core.
293 This is used as a primary controller with MicroBlaze and can also
294 be used as a secondary chained controller on other platforms.
299 Support for a CROSSBAR ip that precedes the main interrupt controller.
300 The primary irqchip invokes the crossbar's callback which inturn allocates
301 a free irq and configures the IP. Thus the peripheral interrupts are
302 routed to one of the free irqchip interrupt lines.
305 tristate "Keystone 2 IRQ controller IP"
306 depends on ARCH_KEYSTONE
308 Support for Texas Instruments Keystone 2 IRQ controller IP which
309 is part of the Keystone 2 IPC mechanism
313 select GENERIC_IRQ_IPI
318 depends on MACH_INGENIC
321 config INGENIC_TCU_IRQ
322 bool "Ingenic JZ47xx TCU interrupt controller"
324 depends on MIPS || COMPILE_TEST
326 select GENERIC_IRQ_CHIP
328 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
333 config RENESAS_H8300H_INTC
337 config RENESAS_H8S_INTC
338 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
341 Enable support for the Renesas H8/300 Interrupt Controller, as found
348 Enables the wakeup IRQs for IMX platforms with GPCv2 block
351 def_bool y if MACH_ASM9260 || ARCH_MXS
355 config MSCC_OCELOT_IRQ
358 select GENERIC_IRQ_CHIP
368 select GENERIC_MSI_IRQ_DOMAIN
377 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
381 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
382 depends on PCI && PCI_MSI
384 config PARTITION_PERCPU
390 select GENERIC_IRQ_CHIP
392 config QCOM_IRQ_COMBINER
393 bool "QCOM IRQ combiner support"
394 depends on ARCH_QCOM && ACPI
395 select IRQ_DOMAIN_HIERARCHY
397 Say yes here to add support for the IRQ combiner devices embedded
398 in Qualcomm Technologies chips.
400 config IRQ_UNIPHIER_AIDET
401 bool "UniPhier AIDET support" if COMPILE_TEST
402 depends on ARCH_UNIPHIER || COMPILE_TEST
403 default ARCH_UNIPHIER
404 select IRQ_DOMAIN_HIERARCHY
406 Support for the UniPhier AIDET (ARM Interrupt Detector).
408 config MESON_IRQ_GPIO
409 tristate "Meson GPIO Interrupt Multiplexer"
410 depends on ARCH_MESON || COMPILE_TEST
412 select IRQ_DOMAIN_HIERARCHY
414 Support Meson SoC Family GPIO Interrupt Multiplexer
417 bool "Goldfish programmable interrupt controller"
418 depends on MIPS && (GOLDFISH || COMPILE_TEST)
419 select GENERIC_IRQ_CHIP
422 Say yes here to enable Goldfish interrupt controller driver used
423 for Goldfish based virtual platforms.
428 select IRQ_DOMAIN_HIERARCHY
430 Power Domain Controller driver to manage and configure wakeup
431 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
437 Say yes here to enable C-SKY SMP interrupt controller driver used
438 for C-SKY SMP system.
439 In fact it's not mmio map in hardware and it uses ld/st to visit the
440 controller's register inside CPU.
443 bool "C-SKY APB Interrupt Controller"
446 Say yes here to enable C-SKY APB interrupt controller driver used
447 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
448 the controller's register.
451 bool "i.MX IRQSTEER support"
452 depends on ARCH_MXC || COMPILE_TEST
456 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
459 bool "i.MX INTMUX support" if COMPILE_TEST
460 default y if ARCH_MXC
463 Support for the i.MX INTMUX interrupt multiplexer.
466 bool "Loongson-1 Interrupt Controller"
467 depends on MACH_LOONGSON32
470 select GENERIC_IRQ_CHIP
472 Support for the Loongson-1 platform Interrupt Controller.
474 config TI_SCI_INTR_IRQCHIP
476 depends on TI_SCI_PROTOCOL
477 select IRQ_DOMAIN_HIERARCHY
479 This enables the irqchip driver support for K3 Interrupt router
480 over TI System Control Interface available on some new TI's SoCs.
481 If you wish to use interrupt router irq resources managed by the
482 TI System Controller, say Y here. Otherwise, say N.
484 config TI_SCI_INTA_IRQCHIP
486 depends on TI_SCI_PROTOCOL
487 select IRQ_DOMAIN_HIERARCHY
488 select TI_SCI_INTA_MSI_DOMAIN
490 This enables the irqchip driver support for K3 Interrupt aggregator
491 over TI System Control Interface available on some new TI's SoCs.
492 If you wish to use interrupt aggregator irq resources managed by the
493 TI System Controller, say Y here. Otherwise, say N.
501 This enables support for the PRU-ICSS Local Interrupt Controller
502 present within a PRU-ICSS subsystem present on various TI SoCs.
503 The PRUSS INTC enables various interrupts to be routed to multiple
504 different processors within the SoC.
507 bool "RISC-V Local Interrupt Controller"
511 This enables support for the per-HART local interrupt controller
512 found in standard RISC-V systems. The per-HART local interrupt
513 controller handles timer interrupts, software interrupts, and
514 hardware interrupts. Without a per-HART local interrupt controller,
515 a RISC-V system will be unable to handle any interrupts.
517 If you don't know what to do here, say Y.
520 bool "SiFive Platform-Level Interrupt Controller"
522 select IRQ_DOMAIN_HIERARCHY
524 This enables support for the PLIC chip found in SiFive (and
525 potentially other) RISC-V systems. The PLIC controls devices
526 interrupts and connects them to each core's local interrupt
527 controller. Aside from timer and software interrupts, all other
528 interrupt sources are subordinate to the PLIC.
530 If you don't know what to do here, say Y.
532 config EXYNOS_IRQ_COMBINER
533 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
534 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
536 Say yes here to add support for the IRQ combiner devices embedded
537 in Samsung Exynos chips.
539 config LOONGSON_LIOINTC
540 bool "Loongson Local I/O Interrupt Controller"
541 depends on MACH_LOONGSON64
544 select GENERIC_IRQ_CHIP
546 Support for the Loongson Local I/O Interrupt Controller.
548 config LOONGSON_HTPIC
549 bool "Loongson3 HyperTransport PIC Controller"
550 depends on MACH_LOONGSON64
553 select GENERIC_IRQ_CHIP
555 Support for the Loongson-3 HyperTransport PIC Controller.
557 config LOONGSON_HTVEC
558 bool "Loongson3 HyperTransport Interrupt Vector Controller"
559 depends on MACH_LOONGSON64
560 default MACH_LOONGSON64
561 select IRQ_DOMAIN_HIERARCHY
563 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
565 config LOONGSON_PCH_PIC
566 bool "Loongson PCH PIC Controller"
567 depends on MACH_LOONGSON64 || COMPILE_TEST
568 default MACH_LOONGSON64
569 select IRQ_DOMAIN_HIERARCHY
570 select IRQ_FASTEOI_HIERARCHY_HANDLERS
572 Support for the Loongson PCH PIC Controller.
574 config LOONGSON_PCH_MSI
575 bool "Loongson PCH MSI Controller"
576 depends on MACH_LOONGSON64 || COMPILE_TEST
578 default MACH_LOONGSON64
579 select IRQ_DOMAIN_HIERARCHY
582 Support for the Loongson PCH MSI Controller.
585 bool "MStar Interrupt Controller"
586 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
587 default ARCH_MEDIATEK
589 select IRQ_DOMAIN_HIERARCHY
591 Support MStar Interrupt Controller.
594 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
595 depends on ARCH_WPCM450
597 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
601 select GENERIC_IRQ_CHIP
605 bool "Apple Interrupt Controller (AIC)"
607 depends on ARCH_APPLE || COMPILE_TEST
609 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
613 bool "Microchip External Interrupt Controller"
614 depends on ARCH_AT91 || COMPILE_TEST
616 select IRQ_DOMAIN_HIERARCHY
618 Support for Microchip External Interrupt Controller.