1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
21 default 2 if ARCH_REALVIEW
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
41 select GENERIC_MSI_IRQ_DOMAIN
44 config ARM_GIC_V3_ITS_PCI
46 depends on ARM_GIC_V3_ITS
49 default ARM_GIC_V3_ITS
51 config ARM_GIC_V3_ITS_FSL_MC
53 depends on ARM_GIC_V3_ITS
55 default ARM_GIC_V3_ITS
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
68 default 4 if ARCH_S5PV210
72 The maximum number of VICs available in the system, for
75 config ARMADA_370_XP_IRQ
77 select GENERIC_IRQ_CHIP
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
85 select GENERIC_IRQ_CHIP
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF || COMPILE_TEST
90 select GENERIC_IRQ_CHIP
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97 select GENERIC_IRQ_CHIP
101 config ATMEL_AIC5_IRQ
103 select GENERIC_IRQ_CHIP
111 config BCM6345_L1_IRQ
113 select GENERIC_IRQ_CHIP
115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
117 config BCM7038_L1_IRQ
119 select GENERIC_IRQ_CHIP
121 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
123 config BCM7120_L2_IRQ
125 select GENERIC_IRQ_CHIP
128 config BRCMSTB_L2_IRQ
130 select GENERIC_IRQ_CHIP
135 select GENERIC_IRQ_CHIP
138 config DAVINCI_CP_INTC
140 select GENERIC_IRQ_CHIP
145 select GENERIC_IRQ_CHIP
146 select IRQ_DOMAIN_HIERARCHY
148 config FARADAY_FTINTC010
153 config HISILICON_IRQ_MBIGEN
156 select ARM_GIC_V3_ITS
160 select GENERIC_IRQ_CHIP
173 select GENERIC_IRQ_CHIP
174 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
178 config CLPS711X_IRQCHIP
180 depends on ARCH_CLPS711X
194 select GENERIC_IRQ_CHIP
203 select GENERIC_IRQ_CHIP
207 bool "J-Core integrated AIC" if COMPILE_TEST
211 Support for the J-Core integrated AIC.
217 config RENESAS_INTC_IRQPIN
218 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
221 Enable support for the Renesas Interrupt Controller for external
222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
226 select GENERIC_IRQ_CHIP
229 Enable support for the Renesas Interrupt Controller for external
230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
232 config RENESAS_RZA1_IRQC
233 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
234 select IRQ_DOMAIN_HIERARCHY
236 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
237 to 8 external interrupts with configurable sense select.
240 bool "Kontron sl28cpld IRQ controller"
241 depends on MFD_SL28CPLD=y || COMPILE_TEST
244 Interrupt controller driver for the board management controller
245 found on the Kontron sl28 CPLD.
252 Enables SysCfg Controlled IRQs on STi based platforms.
257 select GENERIC_IRQ_CHIP
260 tristate "TS-4800 IRQ controller"
263 depends on SOC_IMX51 || COMPILE_TEST
265 Support for the TS-4800 FPGA IRQ controller
267 config VERSATILE_FPGA_IRQ
271 config VERSATILE_FPGA_IRQ_NR
274 depends on VERSATILE_FPGA_IRQ
279 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
288 Support for a CROSSBAR ip that precedes the main interrupt controller.
289 The primary irqchip invokes the crossbar's callback which inturn allocates
290 a free irq and configures the IP. Thus the peripheral interrupts are
291 routed to one of the free irqchip interrupt lines.
294 tristate "Keystone 2 IRQ controller IP"
295 depends on ARCH_KEYSTONE
297 Support for Texas Instruments Keystone 2 IRQ controller IP which
298 is part of the Keystone 2 IPC mechanism
302 select GENERIC_IRQ_IPI
307 depends on MACH_INGENIC
310 config INGENIC_TCU_IRQ
311 bool "Ingenic JZ47xx TCU interrupt controller"
313 depends on MIPS || COMPILE_TEST
315 select GENERIC_IRQ_CHIP
317 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
322 config RENESAS_H8300H_INTC
326 config RENESAS_H8S_INTC
327 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
330 Enable support for the Renesas H8/300 Interrupt Controller, as found
337 Enables the wakeup IRQs for IMX platforms with GPCv2 block
340 def_bool y if MACH_ASM9260 || ARCH_MXS
344 config MSCC_OCELOT_IRQ
347 select GENERIC_IRQ_CHIP
357 select GENERIC_MSI_IRQ_DOMAIN
366 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
370 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
371 depends on PCI && PCI_MSI
373 config PARTITION_PERCPU
379 select GENERIC_IRQ_CHIP
381 config QCOM_IRQ_COMBINER
382 bool "QCOM IRQ combiner support"
383 depends on ARCH_QCOM && ACPI
384 select IRQ_DOMAIN_HIERARCHY
386 Say yes here to add support for the IRQ combiner devices embedded
387 in Qualcomm Technologies chips.
389 config IRQ_UNIPHIER_AIDET
390 bool "UniPhier AIDET support" if COMPILE_TEST
391 depends on ARCH_UNIPHIER || COMPILE_TEST
392 default ARCH_UNIPHIER
393 select IRQ_DOMAIN_HIERARCHY
395 Support for the UniPhier AIDET (ARM Interrupt Detector).
397 config MESON_IRQ_GPIO
398 bool "Meson GPIO Interrupt Multiplexer"
399 depends on ARCH_MESON
400 select IRQ_DOMAIN_HIERARCHY
402 Support Meson SoC Family GPIO Interrupt Multiplexer
405 bool "Goldfish programmable interrupt controller"
406 depends on MIPS && (GOLDFISH || COMPILE_TEST)
409 Say yes here to enable Goldfish interrupt controller driver used
410 for Goldfish based virtual platforms.
415 select IRQ_DOMAIN_HIERARCHY
417 Power Domain Controller driver to manage and configure wakeup
418 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
424 Say yes here to enable C-SKY SMP interrupt controller driver used
425 for C-SKY SMP system.
426 In fact it's not mmio map in hardware and it uses ld/st to visit the
427 controller's register inside CPU.
430 bool "C-SKY APB Interrupt Controller"
433 Say yes here to enable C-SKY APB interrupt controller driver used
434 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
435 the controller's register.
438 bool "i.MX IRQSTEER support"
439 depends on ARCH_MXC || COMPILE_TEST
443 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
446 bool "i.MX INTMUX support" if COMPILE_TEST
447 default y if ARCH_MXC
450 Support for the i.MX INTMUX interrupt multiplexer.
453 bool "Loongson-1 Interrupt Controller"
454 depends on MACH_LOONGSON32
457 select GENERIC_IRQ_CHIP
459 Support for the Loongson-1 platform Interrupt Controller.
461 config TI_SCI_INTR_IRQCHIP
463 depends on TI_SCI_PROTOCOL
464 select IRQ_DOMAIN_HIERARCHY
466 This enables the irqchip driver support for K3 Interrupt router
467 over TI System Control Interface available on some new TI's SoCs.
468 If you wish to use interrupt router irq resources managed by the
469 TI System Controller, say Y here. Otherwise, say N.
471 config TI_SCI_INTA_IRQCHIP
473 depends on TI_SCI_PROTOCOL
474 select IRQ_DOMAIN_HIERARCHY
475 select TI_SCI_INTA_MSI_DOMAIN
477 This enables the irqchip driver support for K3 Interrupt aggregator
478 over TI System Control Interface available on some new TI's SoCs.
479 If you wish to use interrupt aggregator irq resources managed by the
480 TI System Controller, say Y here. Otherwise, say N.
488 This enables support for the PRU-ICSS Local Interrupt Controller
489 present within a PRU-ICSS subsystem present on various TI SoCs.
490 The PRUSS INTC enables various interrupts to be routed to multiple
491 different processors within the SoC.
494 bool "RISC-V Local Interrupt Controller"
498 This enables support for the per-HART local interrupt controller
499 found in standard RISC-V systems. The per-HART local interrupt
500 controller handles timer interrupts, software interrupts, and
501 hardware interrupts. Without a per-HART local interrupt controller,
502 a RISC-V system will be unable to handle any interrupts.
504 If you don't know what to do here, say Y.
507 bool "SiFive Platform-Level Interrupt Controller"
509 select IRQ_DOMAIN_HIERARCHY
511 This enables support for the PLIC chip found in SiFive (and
512 potentially other) RISC-V systems. The PLIC controls devices
513 interrupts and connects them to each core's local interrupt
514 controller. Aside from timer and software interrupts, all other
515 interrupt sources are subordinate to the PLIC.
517 If you don't know what to do here, say Y.
519 config EXYNOS_IRQ_COMBINER
520 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
521 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
523 Say yes here to add support for the IRQ combiner devices embedded
524 in Samsung Exynos chips.
526 config LOONGSON_LIOINTC
527 bool "Loongson Local I/O Interrupt Controller"
528 depends on MACH_LOONGSON64
531 select GENERIC_IRQ_CHIP
533 Support for the Loongson Local I/O Interrupt Controller.
535 config LOONGSON_HTPIC
536 bool "Loongson3 HyperTransport PIC Controller"
537 depends on MACH_LOONGSON64
540 select GENERIC_IRQ_CHIP
542 Support for the Loongson-3 HyperTransport PIC Controller.
544 config LOONGSON_HTVEC
545 bool "Loongson3 HyperTransport Interrupt Vector Controller"
546 depends on MACH_LOONGSON64
547 default MACH_LOONGSON64
548 select IRQ_DOMAIN_HIERARCHY
550 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
552 config LOONGSON_PCH_PIC
553 bool "Loongson PCH PIC Controller"
554 depends on MACH_LOONGSON64 || COMPILE_TEST
555 default MACH_LOONGSON64
556 select IRQ_DOMAIN_HIERARCHY
557 select IRQ_FASTEOI_HIERARCHY_HANDLERS
559 Support for the Loongson PCH PIC Controller.
561 config LOONGSON_PCH_MSI
562 bool "Loongson PCH MSI Controller"
563 depends on MACH_LOONGSON64 || COMPILE_TEST
565 default MACH_LOONGSON64
566 select IRQ_DOMAIN_HIERARCHY
569 Support for the Loongson PCH MSI Controller.
572 bool "MStar Interrupt Controller"
573 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
574 default ARCH_MEDIATEK
576 select IRQ_DOMAIN_HIERARCHY
578 Support MStar Interrupt Controller.