1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
6 #include <linux/bitops.h>
7 #include <linux/debugfs.h>
9 #include <linux/iommu.h>
10 #include <linux/kernel.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/dma-mapping.h>
17 #include <soc/tegra/ahb.h>
18 #include <soc/tegra/mc.h>
20 struct tegra_smmu_group {
21 struct list_head list;
22 struct tegra_smmu *smmu;
23 const struct tegra_smmu_group_soc *soc;
24 struct iommu_group *group;
32 const struct tegra_smmu_soc *soc;
34 struct list_head groups;
36 unsigned long pfn_mask;
37 unsigned long tlb_mask;
42 struct list_head list;
44 struct dentry *debugfs;
46 struct iommu_device iommu; /* IOMMU Core code handle */
49 struct tegra_smmu_as {
50 struct iommu_domain domain;
51 struct tegra_smmu *smmu;
52 unsigned int use_count;
61 static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
63 return container_of(dom, struct tegra_smmu_as, domain);
66 static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
69 writel(value, smmu->regs + offset);
72 static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
74 return readl(smmu->regs + offset);
77 #define SMMU_CONFIG 0x010
78 #define SMMU_CONFIG_ENABLE (1 << 0)
80 #define SMMU_TLB_CONFIG 0x14
81 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
82 #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
83 #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \
84 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
86 #define SMMU_PTC_CONFIG 0x18
87 #define SMMU_PTC_CONFIG_ENABLE (1 << 29)
88 #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
89 #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
91 #define SMMU_PTB_ASID 0x01c
92 #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
94 #define SMMU_PTB_DATA 0x020
95 #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr))
97 #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr))
99 #define SMMU_TLB_FLUSH 0x030
100 #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
101 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
102 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
103 #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
104 SMMU_TLB_FLUSH_VA_MATCH_SECTION)
105 #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
106 SMMU_TLB_FLUSH_VA_MATCH_GROUP)
107 #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31)
109 #define SMMU_PTC_FLUSH 0x034
110 #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0)
111 #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0)
113 #define SMMU_PTC_FLUSH_HI 0x9b8
114 #define SMMU_PTC_FLUSH_HI_MASK 0x3
116 /* per-SWGROUP SMMU_*_ASID register */
117 #define SMMU_ASID_ENABLE (1 << 31)
118 #define SMMU_ASID_MASK 0x7f
119 #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK)
121 /* page table definitions */
122 #define SMMU_NUM_PDE 1024
123 #define SMMU_NUM_PTE 1024
125 #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4)
126 #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4)
128 #define SMMU_PDE_SHIFT 22
129 #define SMMU_PTE_SHIFT 12
131 #define SMMU_PD_READABLE (1 << 31)
132 #define SMMU_PD_WRITABLE (1 << 30)
133 #define SMMU_PD_NONSECURE (1 << 29)
135 #define SMMU_PDE_READABLE (1 << 31)
136 #define SMMU_PDE_WRITABLE (1 << 30)
137 #define SMMU_PDE_NONSECURE (1 << 29)
138 #define SMMU_PDE_NEXT (1 << 28)
140 #define SMMU_PTE_READABLE (1 << 31)
141 #define SMMU_PTE_WRITABLE (1 << 30)
142 #define SMMU_PTE_NONSECURE (1 << 29)
144 #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
147 static unsigned int iova_pd_index(unsigned long iova)
149 return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1);
152 static unsigned int iova_pt_index(unsigned long iova)
154 return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1);
157 static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr)
160 return (addr & smmu->pfn_mask) == addr;
163 static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde)
165 return (dma_addr_t)(pde & smmu->pfn_mask) << 12;
168 static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
170 smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
173 static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma,
174 unsigned long offset)
178 offset &= ~(smmu->mc->soc->atom_size - 1);
180 if (smmu->mc->soc->num_address_bits > 32) {
181 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
182 value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;
186 smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
189 value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
190 smmu_writel(smmu, value, SMMU_PTC_FLUSH);
193 static inline void smmu_flush_tlb(struct tegra_smmu *smmu)
195 smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH);
198 static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
203 if (smmu->soc->num_asids == 4)
204 value = (asid & 0x3) << 29;
206 value = (asid & 0x7f) << 24;
208 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
209 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
212 static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
218 if (smmu->soc->num_asids == 4)
219 value = (asid & 0x3) << 29;
221 value = (asid & 0x7f) << 24;
223 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
224 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
227 static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
233 if (smmu->soc->num_asids == 4)
234 value = (asid & 0x3) << 29;
236 value = (asid & 0x7f) << 24;
238 value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
239 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
242 static inline void smmu_flush(struct tegra_smmu *smmu)
244 smmu_readl(smmu, SMMU_PTB_ASID);
247 static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp)
251 mutex_lock(&smmu->lock);
253 id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids);
254 if (id >= smmu->soc->num_asids) {
255 mutex_unlock(&smmu->lock);
259 set_bit(id, smmu->asids);
262 mutex_unlock(&smmu->lock);
266 static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id)
268 mutex_lock(&smmu->lock);
269 clear_bit(id, smmu->asids);
270 mutex_unlock(&smmu->lock);
273 static bool tegra_smmu_capable(enum iommu_cap cap)
278 static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type)
280 struct tegra_smmu_as *as;
282 if (type != IOMMU_DOMAIN_UNMANAGED)
285 as = kzalloc(sizeof(*as), GFP_KERNEL);
289 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
291 as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
297 as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL);
304 as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL);
313 as->domain.geometry.aperture_start = 0;
314 as->domain.geometry.aperture_end = 0xffffffff;
315 as->domain.geometry.force_aperture = true;
320 static void tegra_smmu_domain_free(struct iommu_domain *domain)
322 struct tegra_smmu_as *as = to_smmu_as(domain);
324 /* TODO: free page directory and page tables */
326 WARN_ON_ONCE(as->use_count);
332 static const struct tegra_smmu_swgroup *
333 tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup)
335 const struct tegra_smmu_swgroup *group = NULL;
338 for (i = 0; i < smmu->soc->num_swgroups; i++) {
339 if (smmu->soc->swgroups[i].swgroup == swgroup) {
340 group = &smmu->soc->swgroups[i];
348 static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
351 const struct tegra_smmu_swgroup *group;
355 group = tegra_smmu_find_swgroup(smmu, swgroup);
357 value = smmu_readl(smmu, group->reg);
358 value &= ~SMMU_ASID_MASK;
359 value |= SMMU_ASID_VALUE(asid);
360 value |= SMMU_ASID_ENABLE;
361 smmu_writel(smmu, value, group->reg);
363 pr_warn("%s group from swgroup %u not found\n", __func__,
365 /* No point moving ahead if group was not found */
369 for (i = 0; i < smmu->soc->num_clients; i++) {
370 const struct tegra_mc_client *client = &smmu->soc->clients[i];
372 if (client->swgroup != swgroup)
375 value = smmu_readl(smmu, client->smmu.reg);
376 value |= BIT(client->smmu.bit);
377 smmu_writel(smmu, value, client->smmu.reg);
381 static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
384 const struct tegra_smmu_swgroup *group;
388 group = tegra_smmu_find_swgroup(smmu, swgroup);
390 value = smmu_readl(smmu, group->reg);
391 value &= ~SMMU_ASID_MASK;
392 value |= SMMU_ASID_VALUE(asid);
393 value &= ~SMMU_ASID_ENABLE;
394 smmu_writel(smmu, value, group->reg);
397 for (i = 0; i < smmu->soc->num_clients; i++) {
398 const struct tegra_mc_client *client = &smmu->soc->clients[i];
400 if (client->swgroup != swgroup)
403 value = smmu_readl(smmu, client->smmu.reg);
404 value &= ~BIT(client->smmu.bit);
405 smmu_writel(smmu, value, client->smmu.reg);
409 static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
410 struct tegra_smmu_as *as)
415 if (as->use_count > 0) {
420 as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD,
422 if (dma_mapping_error(smmu->dev, as->pd_dma))
425 /* We can't handle 64-bit DMA addresses */
426 if (!smmu_dma_addr_valid(smmu, as->pd_dma)) {
431 err = tegra_smmu_alloc_asid(smmu, &as->id);
435 smmu_flush_ptc(smmu, as->pd_dma, 0);
436 smmu_flush_tlb_asid(smmu, as->id);
438 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
439 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
440 smmu_writel(smmu, value, SMMU_PTB_DATA);
449 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
453 static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
454 struct tegra_smmu_as *as)
456 if (--as->use_count > 0)
459 tegra_smmu_free_asid(smmu, as->id);
461 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
466 static int tegra_smmu_attach_dev(struct iommu_domain *domain,
469 struct tegra_smmu *smmu = dev_iommu_priv_get(dev);
470 struct tegra_smmu_as *as = to_smmu_as(domain);
471 struct device_node *np = dev->of_node;
472 struct of_phandle_args args;
473 unsigned int index = 0;
476 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
478 unsigned int swgroup = args.args[0];
480 if (args.np != smmu->dev->of_node) {
481 of_node_put(args.np);
485 of_node_put(args.np);
487 err = tegra_smmu_as_prepare(smmu, as);
491 tegra_smmu_enable(smmu, swgroup, as->id);
501 static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
503 struct tegra_smmu_as *as = to_smmu_as(domain);
504 struct device_node *np = dev->of_node;
505 struct tegra_smmu *smmu = as->smmu;
506 struct of_phandle_args args;
507 unsigned int index = 0;
509 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
511 unsigned int swgroup = args.args[0];
513 if (args.np != smmu->dev->of_node) {
514 of_node_put(args.np);
518 of_node_put(args.np);
520 tegra_smmu_disable(smmu, swgroup, as->id);
521 tegra_smmu_as_unprepare(smmu, as);
526 static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova,
529 unsigned int pd_index = iova_pd_index(iova);
530 struct tegra_smmu *smmu = as->smmu;
531 u32 *pd = page_address(as->pd);
532 unsigned long offset = pd_index * sizeof(*pd);
534 /* Set the page directory entry first */
535 pd[pd_index] = value;
537 /* The flush the page directory entry from caches */
538 dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset,
539 sizeof(*pd), DMA_TO_DEVICE);
541 /* And flush the iommu */
542 smmu_flush_ptc(smmu, as->pd_dma, offset);
543 smmu_flush_tlb_section(smmu, as->id, iova);
547 static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova)
549 u32 *pt = page_address(pt_page);
551 return pt + iova_pt_index(iova);
554 static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
557 unsigned int pd_index = iova_pd_index(iova);
558 struct tegra_smmu *smmu = as->smmu;
559 struct page *pt_page;
562 pt_page = as->pts[pd_index];
566 pd = page_address(as->pd);
567 *dmap = smmu_pde_to_dma(smmu, pd[pd_index]);
569 return tegra_smmu_pte_offset(pt_page, iova);
572 static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
575 unsigned int pde = iova_pd_index(iova);
576 struct tegra_smmu *smmu = as->smmu;
582 page = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
586 dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT,
588 if (dma_mapping_error(smmu->dev, dma)) {
593 if (!smmu_dma_addr_valid(smmu, dma)) {
594 dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT,
602 tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR |
607 u32 *pd = page_address(as->pd);
609 *dmap = smmu_pde_to_dma(smmu, pd[pde]);
612 return tegra_smmu_pte_offset(as->pts[pde], iova);
615 static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova)
617 unsigned int pd_index = iova_pd_index(iova);
619 as->count[pd_index]++;
622 static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
624 unsigned int pde = iova_pd_index(iova);
625 struct page *page = as->pts[pde];
628 * When no entries in this page table are used anymore, return the
629 * memory page to the system.
631 if (--as->count[pde] == 0) {
632 struct tegra_smmu *smmu = as->smmu;
633 u32 *pd = page_address(as->pd);
634 dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]);
636 tegra_smmu_set_pde(as, iova, 0);
638 dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE);
644 static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
645 u32 *pte, dma_addr_t pte_dma, u32 val)
647 struct tegra_smmu *smmu = as->smmu;
648 unsigned long offset = offset_in_page(pte);
652 dma_sync_single_range_for_device(smmu->dev, pte_dma, offset,
654 smmu_flush_ptc(smmu, pte_dma, offset);
655 smmu_flush_tlb_group(smmu, as->id, iova);
659 static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
660 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
662 struct tegra_smmu_as *as = to_smmu_as(domain);
667 pte = as_get_pte(as, iova, &pte_dma);
671 /* If we aren't overwriting a pre-existing entry, increment use */
673 tegra_smmu_pte_get_use(as, iova);
675 pte_attrs = SMMU_PTE_NONSECURE;
677 if (prot & IOMMU_READ)
678 pte_attrs |= SMMU_PTE_READABLE;
680 if (prot & IOMMU_WRITE)
681 pte_attrs |= SMMU_PTE_WRITABLE;
683 tegra_smmu_set_pte(as, iova, pte, pte_dma,
684 __phys_to_pfn(paddr) | pte_attrs);
689 static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
690 size_t size, struct iommu_iotlb_gather *gather)
692 struct tegra_smmu_as *as = to_smmu_as(domain);
696 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
700 tegra_smmu_set_pte(as, iova, pte, pte_dma, 0);
701 tegra_smmu_pte_put_use(as, iova);
706 static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
709 struct tegra_smmu_as *as = to_smmu_as(domain);
714 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
718 pfn = *pte & as->smmu->pfn_mask;
720 return PFN_PHYS(pfn);
723 static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
725 struct platform_device *pdev;
728 pdev = of_find_device_by_node(np);
732 mc = platform_get_drvdata(pdev);
739 static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev,
740 struct of_phandle_args *args)
742 const struct iommu_ops *ops = smmu->iommu.ops;
745 err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops);
747 dev_err(dev, "failed to initialize fwspec: %d\n", err);
751 err = ops->of_xlate(dev, args);
753 dev_err(dev, "failed to parse SW group ID: %d\n", err);
754 iommu_fwspec_free(dev);
761 static struct iommu_device *tegra_smmu_probe_device(struct device *dev)
763 struct device_node *np = dev->of_node;
764 struct tegra_smmu *smmu = NULL;
765 struct of_phandle_args args;
766 unsigned int index = 0;
769 while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
771 smmu = tegra_smmu_find(args.np);
773 err = tegra_smmu_configure(smmu, dev, &args);
774 of_node_put(args.np);
780 * Only a single IOMMU master interface is currently
781 * supported by the Linux kernel, so abort after the
784 dev_iommu_priv_set(dev, smmu);
789 of_node_put(args.np);
794 return ERR_PTR(-ENODEV);
799 static void tegra_smmu_release_device(struct device *dev)
801 dev_iommu_priv_set(dev, NULL);
804 static const struct tegra_smmu_group_soc *
805 tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup)
809 for (i = 0; i < smmu->soc->num_groups; i++)
810 for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++)
811 if (smmu->soc->groups[i].swgroups[j] == swgroup)
812 return &smmu->soc->groups[i];
817 static void tegra_smmu_group_release(void *iommu_data)
819 struct tegra_smmu_group *group = iommu_data;
820 struct tegra_smmu *smmu = group->smmu;
822 mutex_lock(&smmu->lock);
823 list_del(&group->list);
824 mutex_unlock(&smmu->lock);
827 static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu,
828 unsigned int swgroup)
830 const struct tegra_smmu_group_soc *soc;
831 struct tegra_smmu_group *group;
832 struct iommu_group *grp;
834 soc = tegra_smmu_find_group(smmu, swgroup);
838 mutex_lock(&smmu->lock);
840 list_for_each_entry(group, &smmu->groups, list)
841 if (group->soc == soc) {
842 grp = iommu_group_ref_get(group->group);
843 mutex_unlock(&smmu->lock);
847 group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL);
849 mutex_unlock(&smmu->lock);
853 INIT_LIST_HEAD(&group->list);
857 group->group = iommu_group_alloc();
858 if (IS_ERR(group->group)) {
859 devm_kfree(smmu->dev, group);
860 mutex_unlock(&smmu->lock);
864 iommu_group_set_iommudata(group->group, group, tegra_smmu_group_release);
865 iommu_group_set_name(group->group, soc->name);
866 list_add_tail(&group->list, &smmu->groups);
867 mutex_unlock(&smmu->lock);
872 static struct iommu_group *tegra_smmu_device_group(struct device *dev)
874 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
875 struct tegra_smmu *smmu = dev_iommu_priv_get(dev);
876 struct iommu_group *group;
878 group = tegra_smmu_group_get(smmu, fwspec->ids[0]);
880 group = generic_device_group(dev);
885 static int tegra_smmu_of_xlate(struct device *dev,
886 struct of_phandle_args *args)
888 u32 id = args->args[0];
890 return iommu_fwspec_add_ids(dev, &id, 1);
893 static const struct iommu_ops tegra_smmu_ops = {
894 .capable = tegra_smmu_capable,
895 .domain_alloc = tegra_smmu_domain_alloc,
896 .domain_free = tegra_smmu_domain_free,
897 .attach_dev = tegra_smmu_attach_dev,
898 .detach_dev = tegra_smmu_detach_dev,
899 .probe_device = tegra_smmu_probe_device,
900 .release_device = tegra_smmu_release_device,
901 .device_group = tegra_smmu_device_group,
902 .map = tegra_smmu_map,
903 .unmap = tegra_smmu_unmap,
904 .iova_to_phys = tegra_smmu_iova_to_phys,
905 .of_xlate = tegra_smmu_of_xlate,
906 .pgsize_bitmap = SZ_4K,
909 static void tegra_smmu_ahb_enable(void)
911 static const struct of_device_id ahb_match[] = {
912 { .compatible = "nvidia,tegra30-ahb", },
915 struct device_node *ahb;
917 ahb = of_find_matching_node(NULL, ahb_match);
919 tegra_ahb_enable_smmu(ahb);
924 static int tegra_smmu_swgroups_show(struct seq_file *s, void *data)
926 struct tegra_smmu *smmu = s->private;
930 seq_printf(s, "swgroup enabled ASID\n");
931 seq_printf(s, "------------------------\n");
933 for (i = 0; i < smmu->soc->num_swgroups; i++) {
934 const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i];
938 value = smmu_readl(smmu, group->reg);
940 if (value & SMMU_ASID_ENABLE)
945 asid = value & SMMU_ASID_MASK;
947 seq_printf(s, "%-9s %-7s %#04x\n", group->name, status,
954 DEFINE_SHOW_ATTRIBUTE(tegra_smmu_swgroups);
956 static int tegra_smmu_clients_show(struct seq_file *s, void *data)
958 struct tegra_smmu *smmu = s->private;
962 seq_printf(s, "client enabled\n");
963 seq_printf(s, "--------------------\n");
965 for (i = 0; i < smmu->soc->num_clients; i++) {
966 const struct tegra_mc_client *client = &smmu->soc->clients[i];
969 value = smmu_readl(smmu, client->smmu.reg);
971 if (value & BIT(client->smmu.bit))
976 seq_printf(s, "%-12s %s\n", client->name, status);
982 DEFINE_SHOW_ATTRIBUTE(tegra_smmu_clients);
984 static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu)
986 smmu->debugfs = debugfs_create_dir("smmu", NULL);
990 debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu,
991 &tegra_smmu_swgroups_fops);
992 debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu,
993 &tegra_smmu_clients_fops);
996 static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)
998 debugfs_remove_recursive(smmu->debugfs);
1001 struct tegra_smmu *tegra_smmu_probe(struct device *dev,
1002 const struct tegra_smmu_soc *soc,
1003 struct tegra_mc *mc)
1005 struct tegra_smmu *smmu;
1010 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1012 return ERR_PTR(-ENOMEM);
1015 * This is a bit of a hack. Ideally we'd want to simply return this
1016 * value. However the IOMMU registration process will attempt to add
1017 * all devices to the IOMMU when bus_set_iommu() is called. In order
1018 * not to rely on global variables to track the IOMMU instance, we
1019 * set it here so that it can be looked up from the .probe_device()
1020 * callback via the IOMMU device's .drvdata field.
1024 size = BITS_TO_LONGS(soc->num_asids) * sizeof(long);
1026 smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL);
1028 return ERR_PTR(-ENOMEM);
1030 INIT_LIST_HEAD(&smmu->groups);
1031 mutex_init(&smmu->lock);
1033 smmu->regs = mc->regs;
1038 smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
1039 dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
1040 mc->soc->num_address_bits, smmu->pfn_mask);
1041 smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1;
1042 dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines,
1045 value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
1047 if (soc->supports_request_limit)
1048 value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
1050 smmu_writel(smmu, value, SMMU_PTC_CONFIG);
1052 value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
1053 SMMU_TLB_CONFIG_ACTIVE_LINES(smmu);
1055 if (soc->supports_round_robin_arbitration)
1056 value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
1058 smmu_writel(smmu, value, SMMU_TLB_CONFIG);
1060 smmu_flush_ptc_all(smmu);
1061 smmu_flush_tlb(smmu);
1062 smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
1065 tegra_smmu_ahb_enable();
1067 err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev));
1069 return ERR_PTR(err);
1071 iommu_device_set_ops(&smmu->iommu, &tegra_smmu_ops);
1072 iommu_device_set_fwnode(&smmu->iommu, dev->fwnode);
1074 err = iommu_device_register(&smmu->iommu);
1076 iommu_device_sysfs_remove(&smmu->iommu);
1077 return ERR_PTR(err);
1080 err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops);
1082 iommu_device_unregister(&smmu->iommu);
1083 iommu_device_sysfs_remove(&smmu->iommu);
1084 return ERR_PTR(err);
1087 if (IS_ENABLED(CONFIG_DEBUG_FS))
1088 tegra_smmu_debugfs_init(smmu);
1093 void tegra_smmu_remove(struct tegra_smmu *smmu)
1095 iommu_device_unregister(&smmu->iommu);
1096 iommu_device_sysfs_remove(&smmu->iommu);
1098 if (IS_ENABLED(CONFIG_DEBUG_FS))
1099 tegra_smmu_debugfs_exit(smmu);