drivers/iommu/mtk_iommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015-2016 MediaTek Inc.
   4  * Author: Yong Wu <yong.wu@mediatek.com>
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/bug.h>
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-direct.h>
  12 #include <linux/err.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iommu.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/list.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regmap.h>
  27 #include <linux/slab.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/soc/mediatek/infracfg.h>
  30 #include <asm/barrier.h>
  31 #include <soc/mediatek/smi.h>
  32
  33 #include "mtk_iommu.h"
  34
  35 #define REG_MMU_PT_BASE_ADDR                    0x000
  36 #define MMU_PT_ADDR_MASK                        GENMASK(31, 7)
  37
  38 #define REG_MMU_INVALIDATE                      0x020
  39 #define F_ALL_INVLD                             0x2
  40 #define F_MMU_INV_RANGE                         0x1
  41
  42 #define REG_MMU_INVLD_START_A                   0x024
  43 #define REG_MMU_INVLD_END_A                     0x028
  44
  45 #define REG_MMU_INV_SEL_GEN2                    0x02c
  46 #define REG_MMU_INV_SEL_GEN1                    0x038
  47 #define F_INVLD_EN0                             BIT(0)
  48 #define F_INVLD_EN1                             BIT(1)
  49
  50 #define REG_MMU_MISC_CTRL                       0x048
  51 #define F_MMU_IN_ORDER_WR_EN_MASK               (BIT(1) | BIT(17))
  52 #define F_MMU_STANDARD_AXI_MODE_MASK            (BIT(3) | BIT(19))
  53
  54 #define REG_MMU_DCM_DIS                         0x050
  55 #define F_MMU_DCM                               BIT(8)
  56
  57 #define REG_MMU_WR_LEN_CTRL                     0x054
  58 #define F_MMU_WR_THROT_DIS_MASK                 (BIT(5) | BIT(21))
  59
  60 #define REG_MMU_CTRL_REG                        0x110
  61 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR           (2 << 4)
  62 #define F_MMU_PREFETCH_RT_REPLACE_MOD           BIT(4)
  63 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173    (2 << 5)
  64
  65 #define REG_MMU_IVRP_PADDR                      0x114
  66
  67 #define REG_MMU_VLD_PA_RNG                      0x118
  68 #define F_MMU_VLD_PA_RNG(EA, SA)                (((EA) << 8) | (SA))
  69
  70 #define REG_MMU_INT_CONTROL0                    0x120
  71 #define F_L2_MULIT_HIT_EN                       BIT(0)
  72 #define F_TABLE_WALK_FAULT_INT_EN               BIT(1)
  73 #define F_PREETCH_FIFO_OVERFLOW_INT_EN          BIT(2)
  74 #define F_MISS_FIFO_OVERFLOW_INT_EN             BIT(3)
  75 #define F_PREFETCH_FIFO_ERR_INT_EN              BIT(5)
  76 #define F_MISS_FIFO_ERR_INT_EN                  BIT(6)
  77 #define F_INT_CLR_BIT                           BIT(12)
  78
  79 #define REG_MMU_INT_MAIN_CONTROL                0x124
  80                                                 /* mmu0 | mmu1 */
  81 #define F_INT_TRANSLATION_FAULT                 (BIT(0) | BIT(7))
  82 #define F_INT_MAIN_MULTI_HIT_FAULT              (BIT(1) | BIT(8))
  83 #define F_INT_INVALID_PA_FAULT                  (BIT(2) | BIT(9))
  84 #define F_INT_ENTRY_REPLACEMENT_FAULT           (BIT(3) | BIT(10))
  85 #define F_INT_TLB_MISS_FAULT                    (BIT(4) | BIT(11))
  86 #define F_INT_MISS_TRANSACTION_FIFO_FAULT       (BIT(5) | BIT(12))
  87 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    (BIT(6) | BIT(13))
  88
  89 #define REG_MMU_CPE_DONE                        0x12C
  90
  91 #define REG_MMU_FAULT_ST1                       0x134
  92 #define F_REG_MMU0_FAULT_MASK                   GENMASK(6, 0)
  93 #define F_REG_MMU1_FAULT_MASK                   GENMASK(13, 7)
  94
  95 #define REG_MMU0_FAULT_VA                       0x13c
  96 #define F_MMU_INVAL_VA_31_12_MASK               GENMASK(31, 12)
  97 #define F_MMU_INVAL_VA_34_32_MASK               GENMASK(11, 9)
  98 #define F_MMU_INVAL_PA_34_32_MASK               GENMASK(8, 6)
  99 #define F_MMU_FAULT_VA_WRITE_BIT                BIT(1)
 100 #define F_MMU_FAULT_VA_LAYER_BIT                BIT(0)
 101
 102 #define REG_MMU0_INVLD_PA                       0x140
 103 #define REG_MMU1_FAULT_VA                       0x144
 104 #define REG_MMU1_INVLD_PA                       0x148
 105 #define REG_MMU0_INT_ID                         0x150
 106 #define REG_MMU1_INT_ID                         0x154
 107 #define F_MMU_INT_ID_COMM_ID(a)                 (((a) >> 9) & 0x7)
 108 #define F_MMU_INT_ID_SUB_COMM_ID(a)             (((a) >> 7) & 0x3)
 109 #define F_MMU_INT_ID_COMM_ID_EXT(a)             (((a) >> 10) & 0x7)
 110 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a)         (((a) >> 7) & 0x7)
 111 #define F_MMU_INT_ID_LARB_ID(a)                 (((a) >> 7) & 0x7)
 112 #define F_MMU_INT_ID_PORT_ID(a)                 (((a) >> 2) & 0x1f)
 113
 114 #define MTK_PROTECT_PA_ALIGN                    256
 115
 116 #define PERICFG_IOMMU_1                         0x714
 117
 118 #define HAS_4GB_MODE                    BIT(0)
 119 /* HW will use the EMI clock if there isn't the "bclk". */
 120 #define HAS_BCLK                        BIT(1)
 121 #define HAS_VLD_PA_RNG                  BIT(2)
 122 #define RESET_AXI                       BIT(3)
 123 #define OUT_ORDER_WR_EN                 BIT(4)
 124 #define HAS_SUB_COMM_2BITS              BIT(5)
 125 #define HAS_SUB_COMM_3BITS              BIT(6)
 126 #define WR_THROT_EN                     BIT(7)
 127 #define HAS_LEGACY_IVRP_PADDR           BIT(8)
 128 #define IOVA_34_EN                      BIT(9)
 129 #define SHARE_PGTABLE                   BIT(10) /* 2 HW share pgtable */
 130 #define DCM_DISABLE                     BIT(11)
 131 #define STD_AXI_MODE                    BIT(12) /* For non MM iommu */
 132 /* 2 bits: iommu type */
 133 #define MTK_IOMMU_TYPE_MM               (0x0 << 13)
 134 #define MTK_IOMMU_TYPE_INFRA            (0x1 << 13)
 135 #define MTK_IOMMU_TYPE_MASK             (0x3 << 13)
 136 /* PM and clock always on. e.g. infra iommu */
 137 #define PM_CLK_AO                       BIT(15)
 138 #define IFA_IOMMU_PCIE_SUPPORT          BIT(16)
 139
 140 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)        \
 141                                 ((((pdata)->flags) & (mask)) == (_x))
 142
 143 #define MTK_IOMMU_HAS_FLAG(pdata, _x)   MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
 144 #define MTK_IOMMU_IS_TYPE(pdata, _x)    MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
 145                                                         MTK_IOMMU_TYPE_MASK)
 146
 147 #define MTK_INVALID_LARBID              MTK_LARB_NR_MAX
 148
 149 struct mtk_iommu_domain {
 150         struct io_pgtable_cfg           cfg;
 151         struct io_pgtable_ops           *iop;
 152
 153         struct mtk_iommu_data           *data;
 154         struct iommu_domain             domain;
 155
 156         struct mutex                    mutex; /* Protect "data" in this structure */
 157 };
 158
 159 static const struct iommu_ops mtk_iommu_ops;
 160
 161 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
 162
 163 #define MTK_IOMMU_TLB_ADDR(iova) ({                                     \
 164         dma_addr_t _addr = iova;                                        \
 165         ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
 166 })
 167
 168 /*
 169  * In M4U 4GB mode, the physical address is remapped as below:
 170  *
 171  * CPU Physical address:
 172  * ====================
 173  *
 174  * 0      1G       2G     3G       4G     5G
 175  * |---A---|---B---|---C---|---D---|---E---|
 176  * +--I/O--+------------Memory-------------+
 177  *
 178  * IOMMU output physical address:
 179  *  =============================
 180  *
 181  *                                 4G      5G     6G      7G      8G
 182  *                                 |---E---|---B---|---C---|---D---|
 183  *                                 +------------Memory-------------+
 184  *
 185  * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
 186  * bit32 of the CPU physical address always is needed to set, and for Region
 187  * 'E', the CPU physical address keep as is.
 188  * Additionally, The iommu consumers always use the CPU phyiscal address.
 189  */
 190 #define MTK_IOMMU_4GB_MODE_REMAP_BASE    0x140000000UL
 191
 192 static LIST_HEAD(m4ulist);      /* List all the M4U HWs */
 193
 194 #define for_each_m4u(data, head)  list_for_each_entry(data, head, list)
 195
 196 struct mtk_iommu_iova_region {
 197         dma_addr_t              iova_base;
 198         unsigned long long      size;
 199 };
 200
 201 static const struct mtk_iommu_iova_region single_domain[] = {
 202         {.iova_base = 0,                .size = SZ_4G},
 203 };
 204
 205 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
 206         { .iova_base = 0x0,             .size = SZ_4G},         /* 0 ~ 4G */
 207         #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
 208         { .iova_base = SZ_4G,           .size = SZ_4G},         /* 4G ~ 8G */
 209         { .iova_base = SZ_4G * 2,       .size = SZ_4G},         /* 8G ~ 12G */
 210         { .iova_base = SZ_4G * 3,       .size = SZ_4G},         /* 12G ~ 16G */
 211
 212         { .iova_base = 0x240000000ULL,  .size = 0x4000000},     /* CCU0 */
 213         { .iova_base = 0x244000000ULL,  .size = 0x4000000},     /* CCU1 */
 214         #endif
 215 };
 216
 217 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
 218 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
 219 {
 220         return list_first_entry(hwlist, struct mtk_iommu_data, list);
 221 }
 222
 223 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 224 {
 225         return container_of(dom, struct mtk_iommu_domain, domain);
 226 }
 227
 228 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 229 {
 230         void __iomem *base = data->base;
 231         unsigned long flags;
 232
 233         spin_lock_irqsave(&data->tlb_lock, flags);
 234         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
 235         writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
 236         wmb(); /* Make sure the tlb flush all done */
 237         spin_unlock_irqrestore(&data->tlb_lock, flags);
 238 }
 239
 240 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 241                                            struct mtk_iommu_data *data)
 242 {
 243         struct list_head *head = data->hw_list;
 244         bool check_pm_status;
 245         unsigned long flags;
 246         void __iomem *base;
 247         int ret;
 248         u32 tmp;
 249
 250         for_each_m4u(data, head) {
 251                 /*
 252                  * To avoid resume the iommu device frequently when the iommu device
 253                  * is not active, it doesn't always call pm_runtime_get here, then tlb
 254                  * flush depends on the tlb flush all in the runtime resume.
 255                  *
 256                  * There are 2 special cases:
 257                  *
 258                  * Case1: The iommu dev doesn't have power domain but has bclk. This case
 259                  * should also avoid the tlb flush while the dev is not active to mute
 260                  * the tlb timeout log. like mt8173.
 261                  *
 262                  * Case2: The power/clock of infra iommu is always on, and it doesn't
 263                  * have the device link with the master devices. This case should avoid
 264                  * the PM status check.
 265                  */
 266                 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
 267
 268                 if (check_pm_status) {
 269                         if (pm_runtime_get_if_in_use(data->dev) <= 0)
 270                                 continue;
 271                 }
 272
 273                 base = data->base;
 274
 275                 spin_lock_irqsave(&data->tlb_lock, flags);
 276                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 277                                base + data->plat_data->inv_sel_reg);
 278
 279                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
 280                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
 281                                base + REG_MMU_INVLD_END_A);
 282                 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
 283
 284                 /* tlb sync */
 285                 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
 286                                                 tmp, tmp != 0, 10, 1000);
 287
 288                 /* Clear the CPE status */
 289                 writel_relaxed(0, base + REG_MMU_CPE_DONE);
 290                 spin_unlock_irqrestore(&data->tlb_lock, flags);
 291
 292                 if (ret) {
 293                         dev_warn(data->dev,
 294                                  "Partial TLB flush timed out, falling back to full flush\n");
 295                         mtk_iommu_tlb_flush_all(data);
 296                 }
 297
 298                 if (check_pm_status)
 299                         pm_runtime_put(data->dev);
 300         }
 301 }
 302
 303 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 304 {
 305         struct mtk_iommu_data *data = dev_id;
 306         struct mtk_iommu_domain *dom = data->m4u_dom;
 307         unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
 308         u32 int_state, regval, va34_32, pa34_32;
 309         const struct mtk_iommu_plat_data *plat_data = data->plat_data;
 310         void __iomem *base = data->base;
 311         u64 fault_iova, fault_pa;
 312         bool layer, write;
 313
 314         /* Read error info from registers */
 315         int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
 316         if (int_state & F_REG_MMU0_FAULT_MASK) {
 317                 regval = readl_relaxed(base + REG_MMU0_INT_ID);
 318                 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
 319                 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
 320         } else {
 321                 regval = readl_relaxed(base + REG_MMU1_INT_ID);
 322                 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
 323                 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
 324         }
 325         layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 326         write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
 327         if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
 328                 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
 329                 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
 330                 fault_iova |= (u64)va34_32 << 32;
 331         }
 332         pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
 333         fault_pa |= (u64)pa34_32 << 32;
 334
 335         if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
 336                 fault_port = F_MMU_INT_ID_PORT_ID(regval);
 337                 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
 338                         fault_larb = F_MMU_INT_ID_COMM_ID(regval);
 339                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
 340                 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
 341                         fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
 342                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
 343                 } else {
 344                         fault_larb = F_MMU_INT_ID_LARB_ID(regval);
 345                 }
 346                 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
 347         }
 348
 349         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
 350                                write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 351                 dev_err_ratelimited(
 352                         data->dev,
 353                         "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
 354                         int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
 355                         layer, write ? "write" : "read");
 356         }
 357
 358         /* Interrupt clear */
 359         regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
 360         regval |= F_INT_CLR_BIT;
 361         writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
 362
 363         mtk_iommu_tlb_flush_all(data);
 364
 365         return IRQ_HANDLED;
 366 }
 367
 368 static int mtk_iommu_get_domain_id(struct device *dev,
 369                                    const struct mtk_iommu_plat_data *plat_data)
 370 {
 371         const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;
 372         const struct bus_dma_region *dma_rgn = dev->dma_range_map;
 373         int i, candidate = -1;
 374         dma_addr_t dma_end;
 375
 376         if (!dma_rgn || plat_data->iova_region_nr == 1)
 377                 return 0;
 378
 379         dma_end = dma_rgn->dma_start + dma_rgn->size - 1;
 380         for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) {
 381                 /* Best fit. */
 382                 if (dma_rgn->dma_start == rgn->iova_base &&
 383                     dma_end == rgn->iova_base + rgn->size - 1)
 384                         return i;
 385                 /* ok if it is inside this region. */
 386                 if (dma_rgn->dma_start >= rgn->iova_base &&
 387                     dma_end < rgn->iova_base + rgn->size)
 388                         candidate = i;
 389         }
 390
 391         if (candidate >= 0)
 392                 return candidate;
 393         dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n",
 394                 &dma_rgn->dma_start, dma_rgn->size);
 395         return -EINVAL;
 396 }
 397
 398 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
 399                             bool enable, unsigned int domid)
 400 {
 401         struct mtk_smi_larb_iommu    *larb_mmu;
 402         unsigned int                 larbid, portid;
 403         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 404         const struct mtk_iommu_iova_region *region;
 405         u32 peri_mmuen, peri_mmuen_msk;
 406         int i, ret = 0;
 407
 408         for (i = 0; i < fwspec->num_ids; ++i) {
 409                 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
 410                 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
 411
 412                 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 413                         larb_mmu = &data->larb_imu[larbid];
 414
 415                         region = data->plat_data->iova_region + domid;
 416                         larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
 417
 418                         dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",
 419                                 enable ? "enable" : "disable", dev_name(larb_mmu->dev),
 420                                 portid, domid, larb_mmu->bank[portid]);
 421
 422                         if (enable)
 423                                 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 424                         else
 425                                 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 426                 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
 427                         peri_mmuen_msk = BIT(portid);
 428                         /* PCI dev has only one output id, enable the next writing bit for PCIe */
 429                         if (dev_is_pci(dev))
 430                                 peri_mmuen_msk |= BIT(portid + 1);
 431
 432                         peri_mmuen = enable ? peri_mmuen_msk : 0;
 433                         ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
 434                                                  peri_mmuen_msk, peri_mmuen);
 435                         if (ret)
 436                                 dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",
 437                                         enable ? "enable" : "disable",
 438                                         dev_name(data->dev), peri_mmuen_msk, ret);
 439                 }
 440         }
 441         return ret;
 442 }
 443
 444 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
 445                                      struct mtk_iommu_data *data,
 446                                      unsigned int domid)
 447 {
 448         const struct mtk_iommu_iova_region *region;
 449
 450         /* Use the exist domain as there is only one pgtable here. */
 451         if (data->m4u_dom) {
 452                 dom->iop = data->m4u_dom->iop;
 453                 dom->cfg = data->m4u_dom->cfg;
 454                 dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap;
 455                 goto update_iova_region;
 456         }
 457
 458         dom->cfg = (struct io_pgtable_cfg) {
 459                 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
 460                         IO_PGTABLE_QUIRK_NO_PERMS |
 461                         IO_PGTABLE_QUIRK_ARM_MTK_EXT,
 462                 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
 463                 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
 464                 .iommu_dev = data->dev,
 465         };
 466
 467         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
 468                 dom->cfg.oas = data->enable_4GB ? 33 : 32;
 469         else
 470                 dom->cfg.oas = 35;
 471
 472         dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
 473         if (!dom->iop) {
 474                 dev_err(data->dev, "Failed to alloc io pgtable\n");
 475                 return -EINVAL;
 476         }
 477
 478         /* Update our support page sizes bitmap */
 479         dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
 480
 481 update_iova_region:
 482         /* Update the iova region for this domain */
 483         region = data->plat_data->iova_region + domid;
 484         dom->domain.geometry.aperture_start = region->iova_base;
 485         dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
 486         dom->domain.geometry.force_aperture = true;
 487         return 0;
 488 }
 489
 490 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 491 {
 492         struct mtk_iommu_domain *dom;
 493
 494         if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED)
 495                 return NULL;
 496
 497         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 498         if (!dom)
 499                 return NULL;
 500         mutex_init(&dom->mutex);
 501
 502         return &dom->domain;
 503 }
 504
 505 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 506 {
 507         kfree(to_mtk_domain(domain));
 508 }
 509
 510 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 511                                    struct device *dev)
 512 {
 513         struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
 514         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 515         struct list_head *hw_list = data->hw_list;
 516         struct device *m4udev = data->dev;
 517         int ret, domid;
 518
 519         domid = mtk_iommu_get_domain_id(dev, data->plat_data);
 520         if (domid < 0)
 521                 return domid;
 522
 523         mutex_lock(&dom->mutex);
 524         if (!dom->data) {
 525                 /* Data is in the frstdata in sharing pgtable case. */
 526                 frstdata = mtk_iommu_get_frst_data(hw_list);
 527
 528                 ret = mtk_iommu_domain_finalise(dom, frstdata, domid);
 529                 if (ret) {
 530                         mutex_unlock(&dom->mutex);
 531                         return -ENODEV;
 532                 }
 533                 dom->data = data;
 534         }
 535         mutex_unlock(&dom->mutex);
 536
 537         mutex_lock(&data->mutex);
 538         if (!data->m4u_dom) { /* Initialize the M4U HW */
 539                 ret = pm_runtime_resume_and_get(m4udev);
 540                 if (ret < 0)
 541                         goto err_unlock;
 542
 543                 ret = mtk_iommu_hw_init(data);
 544                 if (ret) {
 545                         pm_runtime_put(m4udev);
 546                         goto err_unlock;
 547                 }
 548                 data->m4u_dom = dom;
 549                 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
 550                        data->base + REG_MMU_PT_BASE_ADDR);
 551
 552                 pm_runtime_put(m4udev);
 553         }
 554         mutex_unlock(&data->mutex);
 555
 556         return mtk_iommu_config(data, dev, true, domid);
 557
 558 err_unlock:
 559         mutex_unlock(&data->mutex);
 560         return ret;
 561 }
 562
 563 static void mtk_iommu_detach_device(struct iommu_domain *domain,
 564                                     struct device *dev)
 565 {
 566         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 567
 568         mtk_iommu_config(data, dev, false, 0);
 569 }
 570
 571 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 572                          phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
 573 {
 574         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 575
 576         /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
 577         if (dom->data->enable_4GB)
 578                 paddr |= BIT_ULL(32);
 579
 580         /* Synchronize with the tlb_lock */
 581         return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp);
 582 }
 583
 584 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 585                               unsigned long iova, size_t size,
 586                               struct iommu_iotlb_gather *gather)
 587 {
 588         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 589
 590         iommu_iotlb_gather_add_range(gather, iova, size);
 591         return dom->iop->unmap(dom->iop, iova, size, gather);
 592 }
 593
 594 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
 595 {
 596         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 597
 598         mtk_iommu_tlb_flush_all(dom->data);
 599 }
 600
 601 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
 602                                  struct iommu_iotlb_gather *gather)
 603 {
 604         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 605         size_t length = gather->end - gather->start + 1;
 606
 607         mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->data);
 608 }
 609
 610 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
 611                                size_t size)
 612 {
 613         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 614
 615         mtk_iommu_tlb_flush_range_sync(iova, size, dom->data);
 616 }
 617
 618 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 619                                           dma_addr_t iova)
 620 {
 621         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 622         phys_addr_t pa;
 623
 624         pa = dom->iop->iova_to_phys(dom->iop, iova);
 625         if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
 626             dom->data->enable_4GB &&
 627             pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
 628                 pa &= ~BIT_ULL(32);
 629
 630         return pa;
 631 }
 632
 633 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
 634 {
 635         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 636         struct mtk_iommu_data *data;
 637         struct device_link *link;
 638         struct device *larbdev;
 639         unsigned int larbid, larbidx, i;
 640
 641         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 642                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 643
 644         data = dev_iommu_priv_get(dev);
 645
 646         if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
 647                 return &data->iommu;
 648
 649         /*
 650          * Link the consumer device with the smi-larb device(supplier).
 651          * The device that connects with each a larb is a independent HW.
 652          * All the ports in each a device should be in the same larbs.
 653          */
 654         larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 655         for (i = 1; i < fwspec->num_ids; i++) {
 656                 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
 657                 if (larbid != larbidx) {
 658                         dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
 659                                 larbid, larbidx);
 660                         return ERR_PTR(-EINVAL);
 661                 }
 662         }
 663         larbdev = data->larb_imu[larbid].dev;
 664         link = device_link_add(dev, larbdev,
 665                                DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
 666         if (!link)
 667                 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
 668         return &data->iommu;
 669 }
 670
 671 static void mtk_iommu_release_device(struct device *dev)
 672 {
 673         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 674         struct mtk_iommu_data *data;
 675         struct device *larbdev;
 676         unsigned int larbid;
 677
 678         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 679                 return;
 680
 681         data = dev_iommu_priv_get(dev);
 682         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 683                 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 684                 larbdev = data->larb_imu[larbid].dev;
 685                 device_link_remove(dev, larbdev);
 686         }
 687
 688         iommu_fwspec_free(dev);
 689 }
 690
 691 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 692 {
 693         struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
 694         struct list_head *hw_list = c_data->hw_list;
 695         struct iommu_group *group;
 696         int domid;
 697
 698         data = mtk_iommu_get_frst_data(hw_list);
 699         if (!data)
 700                 return ERR_PTR(-ENODEV);
 701
 702         domid = mtk_iommu_get_domain_id(dev, data->plat_data);
 703         if (domid < 0)
 704                 return ERR_PTR(domid);
 705
 706         mutex_lock(&data->mutex);
 707         group = data->m4u_group[domid];
 708         if (!group) {
 709                 group = iommu_group_alloc();
 710                 if (!IS_ERR(group))
 711                         data->m4u_group[domid] = group;
 712         } else {
 713                 iommu_group_ref_get(group);
 714         }
 715         mutex_unlock(&data->mutex);
 716         return group;
 717 }
 718
 719 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 720 {
 721         struct platform_device *m4updev;
 722
 723         if (args->args_count != 1) {
 724                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 725                         args->args_count);
 726                 return -EINVAL;
 727         }
 728
 729         if (!dev_iommu_priv_get(dev)) {
 730                 /* Get the m4u device */
 731                 m4updev = of_find_device_by_node(args->np);
 732                 if (WARN_ON(!m4updev))
 733                         return -EINVAL;
 734
 735                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 736         }
 737
 738         return iommu_fwspec_add_ids(dev, args->args, 1);
 739 }
 740
 741 static void mtk_iommu_get_resv_regions(struct device *dev,
 742                                        struct list_head *head)
 743 {
 744         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 745         unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i;
 746         const struct mtk_iommu_iova_region *resv, *curdom;
 747         struct iommu_resv_region *region;
 748         int prot = IOMMU_WRITE | IOMMU_READ;
 749
 750         if ((int)domid < 0)
 751                 return;
 752         curdom = data->plat_data->iova_region + domid;
 753         for (i = 0; i < data->plat_data->iova_region_nr; i++) {
 754                 resv = data->plat_data->iova_region + i;
 755
 756                 /* Only reserve when the region is inside the current domain */
 757                 if (resv->iova_base <= curdom->iova_base ||
 758                     resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
 759                         continue;
 760
 761                 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
 762                                                  prot, IOMMU_RESV_RESERVED);
 763                 if (!region)
 764                         return;
 765
 766                 list_add_tail(&region->list, head);
 767         }
 768 }
 769
 770 static const struct iommu_ops mtk_iommu_ops = {
 771         .domain_alloc   = mtk_iommu_domain_alloc,
 772         .probe_device   = mtk_iommu_probe_device,
 773         .release_device = mtk_iommu_release_device,
 774         .device_group   = mtk_iommu_device_group,
 775         .of_xlate       = mtk_iommu_of_xlate,
 776         .get_resv_regions = mtk_iommu_get_resv_regions,
 777         .put_resv_regions = generic_iommu_put_resv_regions,
 778         .pgsize_bitmap  = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
 779         .owner          = THIS_MODULE,
 780         .default_domain_ops = &(const struct iommu_domain_ops) {
 781                 .attach_dev     = mtk_iommu_attach_device,
 782                 .detach_dev     = mtk_iommu_detach_device,
 783                 .map            = mtk_iommu_map,
 784                 .unmap          = mtk_iommu_unmap,
 785                 .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
 786                 .iotlb_sync     = mtk_iommu_iotlb_sync,
 787                 .iotlb_sync_map = mtk_iommu_sync_map,
 788                 .iova_to_phys   = mtk_iommu_iova_to_phys,
 789                 .free           = mtk_iommu_domain_free,
 790         }
 791 };
 792
 793 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 794 {
 795         u32 regval;
 796
 797         if (data->plat_data->m4u_plat == M4U_MT8173) {
 798                 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
 799                          F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
 800         } else {
 801                 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
 802                 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
 803         }
 804         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 805
 806         if (data->enable_4GB &&
 807             MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
 808                 /*
 809                  * If 4GB mode is enabled, the validate PA range is from
 810                  * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
 811                  */
 812                 regval = F_MMU_VLD_PA_RNG(7, 4);
 813                 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
 814         }
 815         if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
 816                 writel_relaxed(F_MMU_DCM, data->base + REG_MMU_DCM_DIS);
 817         else
 818                 writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 819
 820         if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
 821                 /* write command throttling mode */
 822                 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);
 823                 regval &= ~F_MMU_WR_THROT_DIS_MASK;
 824                 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);
 825         }
 826
 827         if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
 828                 /* The register is called STANDARD_AXI_MODE in this case */
 829                 regval = 0;
 830         } else {
 831                 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
 832                 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
 833                         regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
 834                 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
 835                         regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
 836         }
 837         writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
 838
 839         regval = F_L2_MULIT_HIT_EN |
 840                 F_TABLE_WALK_FAULT_INT_EN |
 841                 F_PREETCH_FIFO_OVERFLOW_INT_EN |
 842                 F_MISS_FIFO_OVERFLOW_INT_EN |
 843                 F_PREFETCH_FIFO_ERR_INT_EN |
 844                 F_MISS_FIFO_ERR_INT_EN;
 845         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
 846
 847         regval = F_INT_TRANSLATION_FAULT |
 848                 F_INT_MAIN_MULTI_HIT_FAULT |
 849                 F_INT_INVALID_PA_FAULT |
 850                 F_INT_ENTRY_REPLACEMENT_FAULT |
 851                 F_INT_TLB_MISS_FAULT |
 852                 F_INT_MISS_TRANSACTION_FIFO_FAULT |
 853                 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
 854         writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
 855
 856         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
 857                 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
 858         else
 859                 regval = lower_32_bits(data->protect_base) |
 860                          upper_32_bits(data->protect_base);
 861         writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
 862
 863         if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
 864                              dev_name(data->dev), (void *)data)) {
 865                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 866                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
 867                 return -ENODEV;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static const struct component_master_ops mtk_iommu_com_ops = {
 874         .bind           = mtk_iommu_bind,
 875         .unbind         = mtk_iommu_unbind,
 876 };
 877
 878 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
 879                                   struct mtk_iommu_data *data)
 880 {
 881         struct device_node *larbnode, *smicomm_node, *smi_subcomm_node;
 882         struct platform_device *plarbdev;
 883         struct device_link *link;
 884         int i, larb_nr, ret;
 885
 886         larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
 887         if (larb_nr < 0)
 888                 return larb_nr;
 889
 890         for (i = 0; i < larb_nr; i++) {
 891                 u32 id;
 892
 893                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
 894                 if (!larbnode)
 895                         return -EINVAL;
 896
 897                 if (!of_device_is_available(larbnode)) {
 898                         of_node_put(larbnode);
 899                         continue;
 900                 }
 901
 902                 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
 903                 if (ret)/* The id is consecutive if there is no this property */
 904                         id = i;
 905
 906                 plarbdev = of_find_device_by_node(larbnode);
 907                 if (!plarbdev) {
 908                         of_node_put(larbnode);
 909                         return -ENODEV;
 910                 }
 911                 if (!plarbdev->dev.driver) {
 912                         of_node_put(larbnode);
 913                         return -EPROBE_DEFER;
 914                 }
 915                 data->larb_imu[id].dev = &plarbdev->dev;
 916
 917                 component_match_add_release(dev, match, component_release_of,
 918                                             component_compare_of, larbnode);
 919         }
 920
 921         /* Get smi-(sub)-common dev from the last larb. */
 922         smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
 923         if (!smi_subcomm_node)
 924                 return -EINVAL;
 925
 926         /*
 927          * It may have two level smi-common. the node is smi-sub-common if it
 928          * has a new mediatek,smi property. otherwise it is smi-commmon.
 929          */
 930         smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
 931         if (smicomm_node)
 932                 of_node_put(smi_subcomm_node);
 933         else
 934                 smicomm_node = smi_subcomm_node;
 935
 936         plarbdev = of_find_device_by_node(smicomm_node);
 937         of_node_put(smicomm_node);
 938         data->smicomm_dev = &plarbdev->dev;
 939
 940         link = device_link_add(data->smicomm_dev, dev,
 941                                DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
 942         if (!link) {
 943                 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
 944                 return -EINVAL;
 945         }
 946         return 0;
 947 }
 948
 949 static int mtk_iommu_probe(struct platform_device *pdev)
 950 {
 951         struct mtk_iommu_data   *data;
 952         struct device           *dev = &pdev->dev;
 953         struct resource         *res;
 954         resource_size_t         ioaddr;
 955         struct component_match  *match = NULL;
 956         struct regmap           *infracfg;
 957         void                    *protect;
 958         int                     ret;
 959         u32                     val;
 960         char                    *p;
 961
 962         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 963         if (!data)
 964                 return -ENOMEM;
 965         data->dev = dev;
 966         data->plat_data = of_device_get_match_data(dev);
 967
 968         /* Protect memory. HW will access here while translation fault.*/
 969         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
 970         if (!protect)
 971                 return -ENOMEM;
 972         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
 973
 974         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
 975                 switch (data->plat_data->m4u_plat) {
 976                 case M4U_MT2712:
 977                         p = "mediatek,mt2712-infracfg";
 978                         break;
 979                 case M4U_MT8173:
 980                         p = "mediatek,mt8173-infracfg";
 981                         break;
 982                 default:
 983                         p = NULL;
 984                 }
 985
 986                 infracfg = syscon_regmap_lookup_by_compatible(p);
 987
 988                 if (IS_ERR(infracfg))
 989                         return PTR_ERR(infracfg);
 990
 991                 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
 992                 if (ret)
 993                         return ret;
 994                 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
 995         }
 996
 997         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 998         data->base = devm_ioremap_resource(dev, res);
 999         if (IS_ERR(data->base))
1000                 return PTR_ERR(data->base);
1001         ioaddr = res->start;
1002
1003         data->irq = platform_get_irq(pdev, 0);
1004         if (data->irq < 0)
1005                 return data->irq;
1006
1007         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
1008                 data->bclk = devm_clk_get(dev, "bclk");
1009                 if (IS_ERR(data->bclk))
1010                         return PTR_ERR(data->bclk);
1011         }
1012
1013         pm_runtime_enable(dev);
1014
1015         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1016                 ret = mtk_iommu_mm_dts_parse(dev, &match, data);
1017                 if (ret) {
1018                         dev_err(dev, "mm dts parse fail(%d).", ret);
1019                         goto out_runtime_disable;
1020                 }
1021         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
1022                    data->plat_data->pericfg_comp_str) {
1023                 infracfg = syscon_regmap_lookup_by_compatible(data->plat_data->pericfg_comp_str);
1024                 if (IS_ERR(infracfg)) {
1025                         ret = PTR_ERR(infracfg);
1026                         goto out_runtime_disable;
1027                 }
1028
1029                 data->pericfg = infracfg;
1030         }
1031
1032         platform_set_drvdata(pdev, data);
1033         mutex_init(&data->mutex);
1034
1035         ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
1036                                      "mtk-iommu.%pa", &ioaddr);
1037         if (ret)
1038                 goto out_link_remove;
1039
1040         ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
1041         if (ret)
1042                 goto out_sysfs_remove;
1043
1044         spin_lock_init(&data->tlb_lock);
1045
1046         if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
1047                 list_add_tail(&data->list, data->plat_data->hw_list);
1048                 data->hw_list = data->plat_data->hw_list;
1049         } else {
1050                 INIT_LIST_HEAD(&data->hw_list_head);
1051                 list_add_tail(&data->list, &data->hw_list_head);
1052                 data->hw_list = &data->hw_list_head;
1053         }
1054
1055         if (!iommu_present(&platform_bus_type)) {
1056                 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
1057                 if (ret)
1058                         goto out_list_del;
1059         }
1060
1061         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1062                 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
1063                 if (ret)
1064                         goto out_bus_set_null;
1065         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
1066                    MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
1067 #ifdef CONFIG_PCI
1068                 if (!iommu_present(&pci_bus_type)) {
1069                         ret = bus_set_iommu(&pci_bus_type, &mtk_iommu_ops);
1070                         if (ret) /* PCIe fail don't affect platform_bus. */
1071                                 goto out_list_del;
1072                 }
1073 #endif
1074         }
1075         return ret;
1076
1077 out_bus_set_null:
1078         bus_set_iommu(&platform_bus_type, NULL);
1079 out_list_del:
1080         list_del(&data->list);
1081         iommu_device_unregister(&data->iommu);
1082 out_sysfs_remove:
1083         iommu_device_sysfs_remove(&data->iommu);
1084 out_link_remove:
1085         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
1086                 device_link_remove(data->smicomm_dev, dev);
1087 out_runtime_disable:
1088         pm_runtime_disable(dev);
1089         return ret;
1090 }
1091
1092 static int mtk_iommu_remove(struct platform_device *pdev)
1093 {
1094         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
1095
1096         iommu_device_sysfs_remove(&data->iommu);
1097         iommu_device_unregister(&data->iommu);
1098
1099         list_del(&data->list);
1100
1101         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1102                 device_link_remove(data->smicomm_dev, &pdev->dev);
1103                 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
1104         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
1105                    MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
1106 #ifdef CONFIG_PCI
1107                 bus_set_iommu(&pci_bus_type, NULL);
1108 #endif
1109         }
1110         pm_runtime_disable(&pdev->dev);
1111         devm_free_irq(&pdev->dev, data->irq, data);
1112         return 0;
1113 }
1114
1115 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
1116 {
1117         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1118         struct mtk_iommu_suspend_reg *reg = &data->reg;
1119         void __iomem *base = data->base;
1120
1121         reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
1122         reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
1123         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
1124         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1125         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1126         reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1127         reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1128         reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1129         clk_disable_unprepare(data->bclk);
1130         return 0;
1131 }
1132
1133 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
1134 {
1135         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1136         struct mtk_iommu_suspend_reg *reg = &data->reg;
1137         struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
1138         void __iomem *base = data->base;
1139         int ret;
1140
1141         ret = clk_prepare_enable(data->bclk);
1142         if (ret) {
1143                 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
1144                 return ret;
1145         }
1146
1147         /*
1148          * Uppon first resume, only enable the clk and return, since the values of the
1149          * registers are not yet set.
1150          */
1151         if (!m4u_dom)
1152                 return 0;
1153
1154         writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1155         writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1156         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1157         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1158         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
1159         writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
1160         writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
1161         writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1162         writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);
1163
1164         /*
1165          * Users may allocate dma buffer before they call pm_runtime_get,
1166          * in which case it will lack the necessary tlb flush.
1167          * Thus, make sure to update the tlb after each PM resume.
1168          */
1169         mtk_iommu_tlb_flush_all(data);
1170         return 0;
1171 }
1172
1173 static const struct dev_pm_ops mtk_iommu_pm_ops = {
1174         SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
1175         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1176                                      pm_runtime_force_resume)
1177 };
1178
1179 static const struct mtk_iommu_plat_data mt2712_data = {
1180         .m4u_plat     = M4U_MT2712,
1181         .flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
1182                         MTK_IOMMU_TYPE_MM,
1183         .hw_list      = &m4ulist,
1184         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1185         .iova_region  = single_domain,
1186         .iova_region_nr = ARRAY_SIZE(single_domain),
1187         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1188 };
1189
1190 static const struct mtk_iommu_plat_data mt6779_data = {
1191         .m4u_plat      = M4U_MT6779,
1192         .flags         = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
1193                          MTK_IOMMU_TYPE_MM,
1194         .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
1195         .iova_region   = single_domain,
1196         .iova_region_nr = ARRAY_SIZE(single_domain),
1197         .larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1198 };
1199
1200 static const struct mtk_iommu_plat_data mt8167_data = {
1201         .m4u_plat     = M4U_MT8167,
1202         .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1203         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1204         .iova_region  = single_domain,
1205         .iova_region_nr = ARRAY_SIZE(single_domain),
1206         .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1207 };
1208
1209 static const struct mtk_iommu_plat_data mt8173_data = {
1210         .m4u_plat     = M4U_MT8173,
1211         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1212                         HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1213         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1214         .iova_region  = single_domain,
1215         .iova_region_nr = ARRAY_SIZE(single_domain),
1216         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1217 };
1218
1219 static const struct mtk_iommu_plat_data mt8183_data = {
1220         .m4u_plat     = M4U_MT8183,
1221         .flags        = RESET_AXI | MTK_IOMMU_TYPE_MM,
1222         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1223         .iova_region  = single_domain,
1224         .iova_region_nr = ARRAY_SIZE(single_domain),
1225         .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1226 };
1227
1228 static const struct mtk_iommu_plat_data mt8192_data = {
1229         .m4u_plat       = M4U_MT8192,
1230         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1231                           WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1232         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1233         .iova_region    = mt8192_multi_dom,
1234         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1235         .larbid_remap   = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1236                            {0, 14, 16}, {0, 13, 18, 17}},
1237 };
1238
1239 static const struct mtk_iommu_plat_data mt8195_data_infra = {
1240         .m4u_plat         = M4U_MT8195,
1241         .flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1242                             MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
1243         .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1244         .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
1245         .iova_region      = single_domain,
1246         .iova_region_nr   = ARRAY_SIZE(single_domain),
1247 };
1248
1249 static const struct mtk_iommu_plat_data mt8195_data_vdo = {
1250         .m4u_plat       = M4U_MT8195,
1251         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1252                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1253         .hw_list        = &m4ulist,
1254         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1255         .iova_region    = mt8192_multi_dom,
1256         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1257         .larbid_remap   = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
1258                            {13, 17, 15/* 17b */, 25}, {5}},
1259 };
1260
1261 static const struct mtk_iommu_plat_data mt8195_data_vpp = {
1262         .m4u_plat       = M4U_MT8195,
1263         .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1264                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1265         .hw_list        = &m4ulist,
1266         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1267         .iova_region    = mt8192_multi_dom,
1268         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1269         .larbid_remap   = {{1}, {3},
1270                            {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
1271                            {8}, {20}, {12},
1272                            /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
1273                            {14, 16, 29, 26, 30, 31, 18},
1274                            {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
1275 };
1276
1277 static const struct of_device_id mtk_iommu_of_ids[] = {
1278         { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1279         { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1280         { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1281         { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1282         { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1283         { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1284         { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1285         { .compatible = "mediatek,mt8195-iommu-vdo",   .data = &mt8195_data_vdo},
1286         { .compatible = "mediatek,mt8195-iommu-vpp",   .data = &mt8195_data_vpp},
1287         {}
1288 };
1289
1290 static struct platform_driver mtk_iommu_driver = {
1291         .probe  = mtk_iommu_probe,
1292         .remove = mtk_iommu_remove,
1293         .driver = {
1294                 .name = "mtk-iommu",
1295                 .of_match_table = mtk_iommu_of_ids,
1296                 .pm = &mtk_iommu_pm_ops,
1297         }
1298 };
1299 module_platform_driver(mtk_iommu_driver);
1300
1301 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1302 MODULE_LICENSE("GPL v2");