1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
6 #include <linux/bitfield.h>
9 #include <linux/component.h>
10 #include <linux/device.h>
11 #include <linux/dma-direct.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
15 #include <linux/iommu.h>
16 #include <linux/iopoll.h>
17 #include <linux/io-pgtable.h>
18 #include <linux/list.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regmap.h>
28 #include <linux/slab.h>
29 #include <linux/spinlock.h>
30 #include <linux/soc/mediatek/infracfg.h>
31 #include <asm/barrier.h>
32 #include <soc/mediatek/smi.h>
34 #include <dt-bindings/memory/mtk-memory-port.h>
36 #define REG_MMU_PT_BASE_ADDR 0x000
38 #define REG_MMU_INVALIDATE 0x020
39 #define F_ALL_INVLD 0x2
40 #define F_MMU_INV_RANGE 0x1
42 #define REG_MMU_INVLD_START_A 0x024
43 #define REG_MMU_INVLD_END_A 0x028
45 #define REG_MMU_INV_SEL_GEN2 0x02c
46 #define REG_MMU_INV_SEL_GEN1 0x038
47 #define F_INVLD_EN0 BIT(0)
48 #define F_INVLD_EN1 BIT(1)
50 #define REG_MMU_MISC_CTRL 0x048
51 #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
52 #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
54 #define REG_MMU_DCM_DIS 0x050
55 #define F_MMU_DCM BIT(8)
57 #define REG_MMU_WR_LEN_CTRL 0x054
58 #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21))
60 #define REG_MMU_CTRL_REG 0x110
61 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
62 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
63 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5)
65 #define REG_MMU_IVRP_PADDR 0x114
67 #define REG_MMU_VLD_PA_RNG 0x118
68 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))
70 #define REG_MMU_INT_CONTROL0 0x120
71 #define F_L2_MULIT_HIT_EN BIT(0)
72 #define F_TABLE_WALK_FAULT_INT_EN BIT(1)
73 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
74 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
75 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
76 #define F_MISS_FIFO_ERR_INT_EN BIT(6)
77 #define F_INT_CLR_BIT BIT(12)
79 #define REG_MMU_INT_MAIN_CONTROL 0x124
81 #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
82 #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
83 #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
84 #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
85 #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
86 #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
87 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
89 #define REG_MMU_CPE_DONE 0x12C
91 #define REG_MMU_FAULT_ST1 0x134
92 #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
93 #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
95 #define REG_MMU0_FAULT_VA 0x13c
96 #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
97 #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
98 #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
99 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
100 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
102 #define REG_MMU0_INVLD_PA 0x140
103 #define REG_MMU1_FAULT_VA 0x144
104 #define REG_MMU1_INVLD_PA 0x148
105 #define REG_MMU0_INT_ID 0x150
106 #define REG_MMU1_INT_ID 0x154
107 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
108 #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
109 #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
110 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
111 /* Macro for 5 bits length port ID field (default) */
112 #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
113 #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
114 /* Macro for 6 bits length port ID field */
115 #define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7)
116 #define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f)
118 #define MTK_PROTECT_PA_ALIGN 256
119 #define MTK_IOMMU_BANK_SZ 0x1000
121 #define PERICFG_IOMMU_1 0x714
123 #define HAS_4GB_MODE BIT(0)
124 /* HW will use the EMI clock if there isn't the "bclk". */
125 #define HAS_BCLK BIT(1)
126 #define HAS_VLD_PA_RNG BIT(2)
127 #define RESET_AXI BIT(3)
128 #define OUT_ORDER_WR_EN BIT(4)
129 #define HAS_SUB_COMM_2BITS BIT(5)
130 #define HAS_SUB_COMM_3BITS BIT(6)
131 #define WR_THROT_EN BIT(7)
132 #define HAS_LEGACY_IVRP_PADDR BIT(8)
133 #define IOVA_34_EN BIT(9)
134 #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */
135 #define DCM_DISABLE BIT(11)
136 #define STD_AXI_MODE BIT(12) /* For non MM iommu */
137 /* 2 bits: iommu type */
138 #define MTK_IOMMU_TYPE_MM (0x0 << 13)
139 #define MTK_IOMMU_TYPE_INFRA (0x1 << 13)
140 #define MTK_IOMMU_TYPE_MASK (0x3 << 13)
141 /* PM and clock always on. e.g. infra iommu */
142 #define PM_CLK_AO BIT(15)
143 #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
144 #define PGTABLE_PA_35_EN BIT(17)
145 #define TF_PORT_TO_ADDR_MT8173 BIT(18)
146 #define INT_ID_PORT_WIDTH_6 BIT(19)
148 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
149 ((((pdata)->flags) & (mask)) == (_x))
151 #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
152 #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
155 #define MTK_INVALID_LARBID MTK_LARB_NR_MAX
157 #define MTK_LARB_COM_MAX 8
158 #define MTK_LARB_SUBCOM_MAX 8
160 #define MTK_IOMMU_GROUP_MAX 8
161 #define MTK_IOMMU_BANK_MAX 5
163 enum mtk_iommu_plat {
176 struct mtk_iommu_iova_region {
177 dma_addr_t iova_base;
178 unsigned long long size;
181 struct mtk_iommu_suspend_reg {
188 u32 int_control[MTK_IOMMU_BANK_MAX];
189 u32 int_main_control[MTK_IOMMU_BANK_MAX];
190 u32 ivrp_paddr[MTK_IOMMU_BANK_MAX];
193 struct mtk_iommu_plat_data {
194 enum mtk_iommu_plat m4u_plat;
198 char *pericfg_comp_str;
199 struct list_head *hw_list;
200 unsigned int iova_region_nr;
201 const struct mtk_iommu_iova_region *iova_region;
204 bool banks_enable[MTK_IOMMU_BANK_MAX];
205 unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
206 unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
209 struct mtk_iommu_bank_data {
213 struct device *parent_dev;
214 struct mtk_iommu_data *parent_data;
215 spinlock_t tlb_lock; /* lock for tlb range flush */
216 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */
219 struct mtk_iommu_data {
222 phys_addr_t protect_base; /* protect memory base */
223 struct mtk_iommu_suspend_reg reg;
224 struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
227 struct iommu_device iommu;
228 const struct mtk_iommu_plat_data *plat_data;
229 struct device *smicomm_dev;
231 struct mtk_iommu_bank_data *bank;
232 struct regmap *pericfg;
233 struct mutex mutex; /* Protect m4u_group/m4u_dom above */
236 * In the sharing pgtable case, list data->list to the global list like m4ulist.
237 * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
239 struct list_head *hw_list;
240 struct list_head hw_list_head;
241 struct list_head list;
242 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
245 struct mtk_iommu_domain {
246 struct io_pgtable_cfg cfg;
247 struct io_pgtable_ops *iop;
249 struct mtk_iommu_bank_data *bank;
250 struct iommu_domain domain;
252 struct mutex mutex; /* Protect "data" in this structure */
255 static int mtk_iommu_bind(struct device *dev)
257 struct mtk_iommu_data *data = dev_get_drvdata(dev);
259 return component_bind_all(dev, &data->larb_imu);
262 static void mtk_iommu_unbind(struct device *dev)
264 struct mtk_iommu_data *data = dev_get_drvdata(dev);
266 component_unbind_all(dev, &data->larb_imu);
269 static const struct iommu_ops mtk_iommu_ops;
271 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);
273 #define MTK_IOMMU_TLB_ADDR(iova) ({ \
274 dma_addr_t _addr = iova; \
275 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
279 * In M4U 4GB mode, the physical address is remapped as below:
281 * CPU Physical address:
282 * ====================
285 * |---A---|---B---|---C---|---D---|---E---|
286 * +--I/O--+------------Memory-------------+
288 * IOMMU output physical address:
289 * =============================
292 * |---E---|---B---|---C---|---D---|
293 * +------------Memory-------------+
295 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
296 * bit32 of the CPU physical address always is needed to set, and for Region
297 * 'E', the CPU physical address keep as is.
298 * Additionally, The iommu consumers always use the CPU phyiscal address.
300 #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL
302 static LIST_HEAD(m4ulist); /* List all the M4U HWs */
304 #define for_each_m4u(data, head) list_for_each_entry(data, head, list)
306 static const struct mtk_iommu_iova_region single_domain[] = {
307 {.iova_base = 0, .size = SZ_4G},
310 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
311 { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */
312 #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
313 { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */
314 { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */
315 { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */
317 { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
318 { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
322 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
323 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
325 return list_first_entry(hwlist, struct mtk_iommu_data, list);
328 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
330 return container_of(dom, struct mtk_iommu_domain, domain);
333 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
335 /* Tlb flush all always is in bank0. */
336 struct mtk_iommu_bank_data *bank = &data->bank[0];
337 void __iomem *base = bank->base;
340 spin_lock_irqsave(&bank->tlb_lock, flags);
341 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
342 writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
343 wmb(); /* Make sure the tlb flush all done */
344 spin_unlock_irqrestore(&bank->tlb_lock, flags);
347 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
348 struct mtk_iommu_bank_data *bank)
350 struct list_head *head = bank->parent_data->hw_list;
351 struct mtk_iommu_bank_data *curbank;
352 struct mtk_iommu_data *data;
353 bool check_pm_status;
359 for_each_m4u(data, head) {
361 * To avoid resume the iommu device frequently when the iommu device
362 * is not active, it doesn't always call pm_runtime_get here, then tlb
363 * flush depends on the tlb flush all in the runtime resume.
365 * There are 2 special cases:
367 * Case1: The iommu dev doesn't have power domain but has bclk. This case
368 * should also avoid the tlb flush while the dev is not active to mute
369 * the tlb timeout log. like mt8173.
371 * Case2: The power/clock of infra iommu is always on, and it doesn't
372 * have the device link with the master devices. This case should avoid
373 * the PM status check.
375 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
377 if (check_pm_status) {
378 if (pm_runtime_get_if_in_use(data->dev) <= 0)
382 curbank = &data->bank[bank->id];
383 base = curbank->base;
385 spin_lock_irqsave(&curbank->tlb_lock, flags);
386 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
387 base + data->plat_data->inv_sel_reg);
389 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
390 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
391 base + REG_MMU_INVLD_END_A);
392 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
395 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
396 tmp, tmp != 0, 10, 1000);
398 /* Clear the CPE status */
399 writel_relaxed(0, base + REG_MMU_CPE_DONE);
400 spin_unlock_irqrestore(&curbank->tlb_lock, flags);
404 "Partial TLB flush timed out, falling back to full flush\n");
405 mtk_iommu_tlb_flush_all(data);
409 pm_runtime_put(data->dev);
413 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
415 struct mtk_iommu_bank_data *bank = dev_id;
416 struct mtk_iommu_data *data = bank->parent_data;
417 struct mtk_iommu_domain *dom = bank->m4u_dom;
418 unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
419 u32 int_state, regval, va34_32, pa34_32;
420 const struct mtk_iommu_plat_data *plat_data = data->plat_data;
421 void __iomem *base = bank->base;
422 u64 fault_iova, fault_pa;
425 /* Read error info from registers */
426 int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
427 if (int_state & F_REG_MMU0_FAULT_MASK) {
428 regval = readl_relaxed(base + REG_MMU0_INT_ID);
429 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
430 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
432 regval = readl_relaxed(base + REG_MMU1_INT_ID);
433 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
434 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
436 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
437 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
438 if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
439 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
440 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
441 fault_iova |= (u64)va34_32 << 32;
443 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
444 fault_pa |= (u64)pa34_32 << 32;
446 if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
447 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
448 fault_larb = F_MMU_INT_ID_COMM_ID(regval);
449 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
450 fault_port = F_MMU_INT_ID_PORT_ID(regval);
451 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
452 fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
453 sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
454 fault_port = F_MMU_INT_ID_PORT_ID(regval);
455 } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
456 fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
457 fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
459 fault_port = F_MMU_INT_ID_PORT_ID(regval);
460 fault_larb = F_MMU_INT_ID_LARB_ID(regval);
462 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
465 if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,
466 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
469 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
470 int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
471 layer, write ? "write" : "read");
474 /* Interrupt clear */
475 regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
476 regval |= F_INT_CLR_BIT;
477 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
479 mtk_iommu_tlb_flush_all(data);
484 static unsigned int mtk_iommu_get_bank_id(struct device *dev,
485 const struct mtk_iommu_plat_data *plat_data)
487 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
488 unsigned int i, portmsk = 0, bankid = 0;
490 if (plat_data->banks_num == 1)
493 for (i = 0; i < fwspec->num_ids; i++)
494 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
496 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) {
497 if (!plat_data->banks_enable[i])
500 if (portmsk & plat_data->banks_portmsk[i]) {
505 return bankid; /* default is 0 */
508 static int mtk_iommu_get_iova_region_id(struct device *dev,
509 const struct mtk_iommu_plat_data *plat_data)
511 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;
512 const struct bus_dma_region *dma_rgn = dev->dma_range_map;
513 int i, candidate = -1;
516 if (!dma_rgn || plat_data->iova_region_nr == 1)
519 dma_end = dma_rgn->dma_start + dma_rgn->size - 1;
520 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) {
522 if (dma_rgn->dma_start == rgn->iova_base &&
523 dma_end == rgn->iova_base + rgn->size - 1)
525 /* ok if it is inside this region. */
526 if (dma_rgn->dma_start >= rgn->iova_base &&
527 dma_end < rgn->iova_base + rgn->size)
533 dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n",
534 &dma_rgn->dma_start, dma_rgn->size);
538 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
539 bool enable, unsigned int regionid)
541 struct mtk_smi_larb_iommu *larb_mmu;
542 unsigned int larbid, portid;
543 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
544 const struct mtk_iommu_iova_region *region;
545 u32 peri_mmuen, peri_mmuen_msk;
548 for (i = 0; i < fwspec->num_ids; ++i) {
549 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
550 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
552 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
553 larb_mmu = &data->larb_imu[larbid];
555 region = data->plat_data->iova_region + regionid;
556 larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
558 dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n",
559 enable ? "enable" : "disable", dev_name(larb_mmu->dev),
560 portid, regionid, larb_mmu->bank[portid]);
563 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
565 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
566 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
567 peri_mmuen_msk = BIT(portid);
568 /* PCI dev has only one output id, enable the next writing bit for PCIe */
570 peri_mmuen_msk |= BIT(portid + 1);
572 peri_mmuen = enable ? peri_mmuen_msk : 0;
573 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
574 peri_mmuen_msk, peri_mmuen);
576 dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",
577 enable ? "enable" : "disable",
578 dev_name(data->dev), peri_mmuen_msk, ret);
584 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
585 struct mtk_iommu_data *data,
586 unsigned int region_id)
588 const struct mtk_iommu_iova_region *region;
589 struct mtk_iommu_domain *m4u_dom;
591 /* Always use bank0 in sharing pgtable case */
592 m4u_dom = data->bank[0].m4u_dom;
594 dom->iop = m4u_dom->iop;
595 dom->cfg = m4u_dom->cfg;
596 dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap;
597 goto update_iova_region;
600 dom->cfg = (struct io_pgtable_cfg) {
601 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
602 IO_PGTABLE_QUIRK_NO_PERMS |
603 IO_PGTABLE_QUIRK_ARM_MTK_EXT,
604 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
605 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
606 .iommu_dev = data->dev,
609 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
610 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
612 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
613 dom->cfg.oas = data->enable_4GB ? 33 : 32;
617 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
619 dev_err(data->dev, "Failed to alloc io pgtable\n");
623 /* Update our support page sizes bitmap */
624 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
627 /* Update the iova region for this domain */
628 region = data->plat_data->iova_region + region_id;
629 dom->domain.geometry.aperture_start = region->iova_base;
630 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
631 dom->domain.geometry.force_aperture = true;
635 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
637 struct mtk_iommu_domain *dom;
639 if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED)
642 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
645 mutex_init(&dom->mutex);
650 static void mtk_iommu_domain_free(struct iommu_domain *domain)
652 kfree(to_mtk_domain(domain));
655 static int mtk_iommu_attach_device(struct iommu_domain *domain,
658 struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
659 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
660 struct list_head *hw_list = data->hw_list;
661 struct device *m4udev = data->dev;
662 struct mtk_iommu_bank_data *bank;
666 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data);
670 bankid = mtk_iommu_get_bank_id(dev, data->plat_data);
671 mutex_lock(&dom->mutex);
673 /* Data is in the frstdata in sharing pgtable case. */
674 frstdata = mtk_iommu_get_frst_data(hw_list);
676 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
678 mutex_unlock(&dom->mutex);
681 dom->bank = &data->bank[bankid];
683 mutex_unlock(&dom->mutex);
685 mutex_lock(&data->mutex);
686 bank = &data->bank[bankid];
687 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */
688 ret = pm_runtime_resume_and_get(m4udev);
690 dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);
694 ret = mtk_iommu_hw_init(data, bankid);
696 pm_runtime_put(m4udev);
700 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
702 pm_runtime_put(m4udev);
704 mutex_unlock(&data->mutex);
706 return mtk_iommu_config(data, dev, true, region_id);
709 mutex_unlock(&data->mutex);
713 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
714 phys_addr_t paddr, size_t pgsize, size_t pgcount,
715 int prot, gfp_t gfp, size_t *mapped)
717 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
719 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
720 if (dom->bank->parent_data->enable_4GB)
721 paddr |= BIT_ULL(32);
723 /* Synchronize with the tlb_lock */
724 return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped);
727 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
728 unsigned long iova, size_t pgsize, size_t pgcount,
729 struct iommu_iotlb_gather *gather)
731 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
733 iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount);
734 return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather);
737 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
739 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
741 mtk_iommu_tlb_flush_all(dom->bank->parent_data);
744 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
745 struct iommu_iotlb_gather *gather)
747 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
748 size_t length = gather->end - gather->start + 1;
750 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);
753 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
756 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
758 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
761 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
764 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
767 pa = dom->iop->iova_to_phys(dom->iop, iova);
768 if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
769 dom->bank->parent_data->enable_4GB &&
770 pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
776 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
778 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
779 struct mtk_iommu_data *data;
780 struct device_link *link;
781 struct device *larbdev;
782 unsigned int larbid, larbidx, i;
784 if (!fwspec || fwspec->ops != &mtk_iommu_ops)
785 return ERR_PTR(-ENODEV); /* Not a iommu client device */
787 data = dev_iommu_priv_get(dev);
789 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
793 * Link the consumer device with the smi-larb device(supplier).
794 * The device that connects with each a larb is a independent HW.
795 * All the ports in each a device should be in the same larbs.
797 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
798 if (larbid >= MTK_LARB_NR_MAX)
799 return ERR_PTR(-EINVAL);
801 for (i = 1; i < fwspec->num_ids; i++) {
802 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
803 if (larbid != larbidx) {
804 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
806 return ERR_PTR(-EINVAL);
809 larbdev = data->larb_imu[larbid].dev;
811 return ERR_PTR(-EINVAL);
813 link = device_link_add(dev, larbdev,
814 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
816 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
820 static void mtk_iommu_release_device(struct device *dev)
822 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
823 struct mtk_iommu_data *data;
824 struct device *larbdev;
827 data = dev_iommu_priv_get(dev);
828 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
829 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
830 larbdev = data->larb_imu[larbid].dev;
831 device_link_remove(dev, larbdev);
835 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data)
840 * If the bank function is enabled, each bank is a iommu group/domain.
841 * Otherwise, each iova region is a iommu group/domain.
843 bankid = mtk_iommu_get_bank_id(dev, plat_data);
847 return mtk_iommu_get_iova_region_id(dev, plat_data);
850 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
852 struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
853 struct list_head *hw_list = c_data->hw_list;
854 struct iommu_group *group;
857 data = mtk_iommu_get_frst_data(hw_list);
859 return ERR_PTR(-ENODEV);
861 groupid = mtk_iommu_get_group_id(dev, data->plat_data);
863 return ERR_PTR(groupid);
865 mutex_lock(&data->mutex);
866 group = data->m4u_group[groupid];
868 group = iommu_group_alloc();
870 data->m4u_group[groupid] = group;
872 iommu_group_ref_get(group);
874 mutex_unlock(&data->mutex);
878 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
880 struct platform_device *m4updev;
882 if (args->args_count != 1) {
883 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
888 if (!dev_iommu_priv_get(dev)) {
889 /* Get the m4u device */
890 m4updev = of_find_device_by_node(args->np);
891 if (WARN_ON(!m4updev))
894 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
897 return iommu_fwspec_add_ids(dev, args->args, 1);
900 static void mtk_iommu_get_resv_regions(struct device *dev,
901 struct list_head *head)
903 struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
904 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i;
905 const struct mtk_iommu_iova_region *resv, *curdom;
906 struct iommu_resv_region *region;
907 int prot = IOMMU_WRITE | IOMMU_READ;
909 if ((int)regionid < 0)
911 curdom = data->plat_data->iova_region + regionid;
912 for (i = 0; i < data->plat_data->iova_region_nr; i++) {
913 resv = data->plat_data->iova_region + i;
915 /* Only reserve when the region is inside the current domain */
916 if (resv->iova_base <= curdom->iova_base ||
917 resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
920 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
921 prot, IOMMU_RESV_RESERVED,
926 list_add_tail(®ion->list, head);
930 static const struct iommu_ops mtk_iommu_ops = {
931 .domain_alloc = mtk_iommu_domain_alloc,
932 .probe_device = mtk_iommu_probe_device,
933 .release_device = mtk_iommu_release_device,
934 .device_group = mtk_iommu_device_group,
935 .of_xlate = mtk_iommu_of_xlate,
936 .get_resv_regions = mtk_iommu_get_resv_regions,
937 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
938 .owner = THIS_MODULE,
939 .default_domain_ops = &(const struct iommu_domain_ops) {
940 .attach_dev = mtk_iommu_attach_device,
941 .map_pages = mtk_iommu_map,
942 .unmap_pages = mtk_iommu_unmap,
943 .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
944 .iotlb_sync = mtk_iommu_iotlb_sync,
945 .iotlb_sync_map = mtk_iommu_sync_map,
946 .iova_to_phys = mtk_iommu_iova_to_phys,
947 .free = mtk_iommu_domain_free,
951 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)
953 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];
954 const struct mtk_iommu_bank_data *bank0 = &data->bank[0];
958 * Global control settings are in bank0. May re-init these global registers
959 * since no sure if there is bank0 consumers.
961 if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) {
962 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
963 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
965 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
966 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
968 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
970 if (data->enable_4GB &&
971 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
973 * If 4GB mode is enabled, the validate PA range is from
974 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
976 regval = F_MMU_VLD_PA_RNG(7, 4);
977 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
979 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
980 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
982 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
984 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
985 /* write command throttling mode */
986 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
987 regval &= ~F_MMU_WR_THROT_DIS_MASK;
988 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
991 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
992 /* The register is called STANDARD_AXI_MODE in this case */
995 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
996 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
997 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
998 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
999 regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
1001 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
1003 /* Independent settings for each bank */
1004 regval = F_L2_MULIT_HIT_EN |
1005 F_TABLE_WALK_FAULT_INT_EN |
1006 F_PREETCH_FIFO_OVERFLOW_INT_EN |
1007 F_MISS_FIFO_OVERFLOW_INT_EN |
1008 F_PREFETCH_FIFO_ERR_INT_EN |
1009 F_MISS_FIFO_ERR_INT_EN;
1010 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
1012 regval = F_INT_TRANSLATION_FAULT |
1013 F_INT_MAIN_MULTI_HIT_FAULT |
1014 F_INT_INVALID_PA_FAULT |
1015 F_INT_ENTRY_REPLACEMENT_FAULT |
1016 F_INT_TLB_MISS_FAULT |
1017 F_INT_MISS_TRANSACTION_FIFO_FAULT |
1018 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
1019 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
1021 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
1022 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
1024 regval = lower_32_bits(data->protect_base) |
1025 upper_32_bits(data->protect_base);
1026 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
1028 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,
1029 dev_name(bankx->parent_dev), (void *)bankx)) {
1030 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
1031 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);
1038 static const struct component_master_ops mtk_iommu_com_ops = {
1039 .bind = mtk_iommu_bind,
1040 .unbind = mtk_iommu_unbind,
1043 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
1044 struct mtk_iommu_data *data)
1046 struct device_node *larbnode, *frst_avail_smicomm_node = NULL;
1047 struct platform_device *plarbdev, *pcommdev;
1048 struct device_link *link;
1049 int i, larb_nr, ret;
1051 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
1054 if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX)
1057 for (i = 0; i < larb_nr; i++) {
1058 struct device_node *smicomm_node, *smi_subcomm_node;
1061 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
1064 goto err_larbdev_put;
1067 if (!of_device_is_available(larbnode)) {
1068 of_node_put(larbnode);
1072 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
1073 if (ret)/* The id is consecutive if there is no this property */
1075 if (id >= MTK_LARB_NR_MAX) {
1076 of_node_put(larbnode);
1078 goto err_larbdev_put;
1081 plarbdev = of_find_device_by_node(larbnode);
1082 of_node_put(larbnode);
1085 goto err_larbdev_put;
1087 if (data->larb_imu[id].dev) {
1088 platform_device_put(plarbdev);
1090 goto err_larbdev_put;
1092 data->larb_imu[id].dev = &plarbdev->dev;
1094 if (!plarbdev->dev.driver) {
1095 ret = -EPROBE_DEFER;
1096 goto err_larbdev_put;
1099 /* Get smi-(sub)-common dev from the last larb. */
1100 smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
1101 if (!smi_subcomm_node) {
1103 goto err_larbdev_put;
1107 * It may have two level smi-common. the node is smi-sub-common if it
1108 * has a new mediatek,smi property. otherwise it is smi-commmon.
1110 smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
1112 of_node_put(smi_subcomm_node);
1114 smicomm_node = smi_subcomm_node;
1117 * All the larbs that connect to one IOMMU must connect with the same
1120 if (!frst_avail_smicomm_node) {
1121 frst_avail_smicomm_node = smicomm_node;
1122 } else if (frst_avail_smicomm_node != smicomm_node) {
1123 dev_err(dev, "mediatek,smi property is not right @larb%d.", id);
1124 of_node_put(smicomm_node);
1126 goto err_larbdev_put;
1128 of_node_put(smicomm_node);
1131 component_match_add(dev, match, component_compare_dev, &plarbdev->dev);
1132 platform_device_put(plarbdev);
1135 if (!frst_avail_smicomm_node)
1138 pcommdev = of_find_device_by_node(frst_avail_smicomm_node);
1139 of_node_put(frst_avail_smicomm_node);
1142 data->smicomm_dev = &pcommdev->dev;
1144 link = device_link_add(data->smicomm_dev, dev,
1145 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1146 platform_device_put(pcommdev);
1148 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
1154 for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) {
1155 if (!data->larb_imu[i].dev)
1157 put_device(data->larb_imu[i].dev);
1162 static int mtk_iommu_probe(struct platform_device *pdev)
1164 struct mtk_iommu_data *data;
1165 struct device *dev = &pdev->dev;
1166 struct resource *res;
1167 resource_size_t ioaddr;
1168 struct component_match *match = NULL;
1169 struct regmap *infracfg;
1171 int ret, banks_num, i = 0;
1174 struct mtk_iommu_bank_data *bank;
1177 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1181 data->plat_data = of_device_get_match_data(dev);
1183 /* Protect memory. HW will access here while translation fault.*/
1184 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
1187 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
1189 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
1190 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg");
1191 if (IS_ERR(infracfg)) {
1193 * Legacy devicetrees will not specify a phandle to
1194 * mediatek,infracfg: in that case, we use the older
1195 * way to retrieve a syscon to infra.
1197 * This is for retrocompatibility purposes only, hence
1198 * no more compatibles shall be added to this.
1200 switch (data->plat_data->m4u_plat) {
1202 p = "mediatek,mt2712-infracfg";
1205 p = "mediatek,mt8173-infracfg";
1211 infracfg = syscon_regmap_lookup_by_compatible(p);
1212 if (IS_ERR(infracfg))
1213 return PTR_ERR(infracfg);
1216 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
1219 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
1222 banks_num = data->plat_data->banks_num;
1223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1226 if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) {
1227 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res);
1230 base = devm_ioremap_resource(dev, res);
1232 return PTR_ERR(base);
1233 ioaddr = res->start;
1235 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);
1240 if (!data->plat_data->banks_enable[i])
1242 bank = &data->bank[i];
1244 bank->base = base + i * MTK_IOMMU_BANK_SZ;
1245 bank->m4u_dom = NULL;
1247 bank->irq = platform_get_irq(pdev, i);
1250 bank->parent_dev = dev;
1251 bank->parent_data = data;
1252 spin_lock_init(&bank->tlb_lock);
1253 } while (++i < banks_num);
1255 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
1256 data->bclk = devm_clk_get(dev, "bclk");
1257 if (IS_ERR(data->bclk))
1258 return PTR_ERR(data->bclk);
1261 pm_runtime_enable(dev);
1263 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1264 ret = mtk_iommu_mm_dts_parse(dev, &match, data);
1266 dev_err_probe(dev, ret, "mm dts parse fail\n");
1267 goto out_runtime_disable;
1269 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
1270 p = data->plat_data->pericfg_comp_str;
1271 data->pericfg = syscon_regmap_lookup_by_compatible(p);
1272 if (IS_ERR(data->pericfg)) {
1273 ret = PTR_ERR(data->pericfg);
1274 goto out_runtime_disable;
1278 platform_set_drvdata(pdev, data);
1279 mutex_init(&data->mutex);
1281 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
1282 "mtk-iommu.%pa", &ioaddr);
1284 goto out_link_remove;
1286 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
1288 goto out_sysfs_remove;
1290 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
1291 list_add_tail(&data->list, data->plat_data->hw_list);
1292 data->hw_list = data->plat_data->hw_list;
1294 INIT_LIST_HEAD(&data->hw_list_head);
1295 list_add_tail(&data->list, &data->hw_list_head);
1296 data->hw_list = &data->hw_list_head;
1299 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1300 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
1307 list_del(&data->list);
1308 iommu_device_unregister(&data->iommu);
1310 iommu_device_sysfs_remove(&data->iommu);
1312 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
1313 device_link_remove(data->smicomm_dev, dev);
1314 out_runtime_disable:
1315 pm_runtime_disable(dev);
1319 static int mtk_iommu_remove(struct platform_device *pdev)
1321 struct mtk_iommu_data *data = platform_get_drvdata(pdev);
1322 struct mtk_iommu_bank_data *bank;
1325 iommu_device_sysfs_remove(&data->iommu);
1326 iommu_device_unregister(&data->iommu);
1328 list_del(&data->list);
1330 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1331 device_link_remove(data->smicomm_dev, &pdev->dev);
1332 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
1334 pm_runtime_disable(&pdev->dev);
1335 for (i = 0; i < data->plat_data->banks_num; i++) {
1336 bank = &data->bank[i];
1339 devm_free_irq(&pdev->dev, bank->irq, bank);
1344 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
1346 struct mtk_iommu_data *data = dev_get_drvdata(dev);
1347 struct mtk_iommu_suspend_reg *reg = &data->reg;
1351 base = data->bank[i].base;
1352 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
1353 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
1354 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
1355 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1356 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1358 if (!data->plat_data->banks_enable[i])
1360 base = data->bank[i].base;
1361 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1362 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1363 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1364 } while (++i < data->plat_data->banks_num);
1365 clk_disable_unprepare(data->bclk);
1369 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
1371 struct mtk_iommu_data *data = dev_get_drvdata(dev);
1372 struct mtk_iommu_suspend_reg *reg = &data->reg;
1373 struct mtk_iommu_domain *m4u_dom;
1377 ret = clk_prepare_enable(data->bclk);
1379 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
1384 * Uppon first resume, only enable the clk and return, since the values of the
1385 * registers are not yet set.
1387 if (!reg->wr_len_ctrl)
1390 base = data->bank[i].base;
1391 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1392 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1393 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1394 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1395 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1397 m4u_dom = data->bank[i].m4u_dom;
1398 if (!data->plat_data->banks_enable[i] || !m4u_dom)
1400 base = data->bank[i].base;
1401 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
1402 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
1403 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
1404 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
1405 } while (++i < data->plat_data->banks_num);
1408 * Users may allocate dma buffer before they call pm_runtime_get,
1409 * in which case it will lack the necessary tlb flush.
1410 * Thus, make sure to update the tlb after each PM resume.
1412 mtk_iommu_tlb_flush_all(data);
1416 static const struct dev_pm_ops mtk_iommu_pm_ops = {
1417 SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
1418 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1419 pm_runtime_force_resume)
1422 static const struct mtk_iommu_plat_data mt2712_data = {
1423 .m4u_plat = M4U_MT2712,
1424 .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
1426 .hw_list = &m4ulist,
1427 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1428 .iova_region = single_domain,
1430 .banks_enable = {true},
1431 .iova_region_nr = ARRAY_SIZE(single_domain),
1432 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1435 static const struct mtk_iommu_plat_data mt6779_data = {
1436 .m4u_plat = M4U_MT6779,
1437 .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
1438 MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
1439 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1441 .banks_enable = {true},
1442 .iova_region = single_domain,
1443 .iova_region_nr = ARRAY_SIZE(single_domain),
1444 .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1447 static const struct mtk_iommu_plat_data mt6795_data = {
1448 .m4u_plat = M4U_MT6795,
1449 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1450 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1451 TF_PORT_TO_ADDR_MT8173,
1452 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1454 .banks_enable = {true},
1455 .iova_region = single_domain,
1456 .iova_region_nr = ARRAY_SIZE(single_domain),
1457 .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
1460 static const struct mtk_iommu_plat_data mt8167_data = {
1461 .m4u_plat = M4U_MT8167,
1462 .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1463 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1465 .banks_enable = {true},
1466 .iova_region = single_domain,
1467 .iova_region_nr = ARRAY_SIZE(single_domain),
1468 .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1471 static const struct mtk_iommu_plat_data mt8173_data = {
1472 .m4u_plat = M4U_MT8173,
1473 .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1474 HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1475 TF_PORT_TO_ADDR_MT8173,
1476 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1478 .banks_enable = {true},
1479 .iova_region = single_domain,
1480 .iova_region_nr = ARRAY_SIZE(single_domain),
1481 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1484 static const struct mtk_iommu_plat_data mt8183_data = {
1485 .m4u_plat = M4U_MT8183,
1486 .flags = RESET_AXI | MTK_IOMMU_TYPE_MM,
1487 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1489 .banks_enable = {true},
1490 .iova_region = single_domain,
1491 .iova_region_nr = ARRAY_SIZE(single_domain),
1492 .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1495 static const struct mtk_iommu_plat_data mt8186_data_mm = {
1496 .m4u_plat = M4U_MT8186,
1497 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1498 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1499 .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20},
1500 {MTK_INVALID_LARBID, 14, 16},
1501 {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}},
1502 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1504 .banks_enable = {true},
1505 .iova_region = mt8192_multi_dom,
1506 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1509 static const struct mtk_iommu_plat_data mt8192_data = {
1510 .m4u_plat = M4U_MT8192,
1511 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1512 WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1513 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1515 .banks_enable = {true},
1516 .iova_region = mt8192_multi_dom,
1517 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1518 .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1519 {0, 14, 16}, {0, 13, 18, 17}},
1522 static const struct mtk_iommu_plat_data mt8195_data_infra = {
1523 .m4u_plat = M4U_MT8195,
1524 .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1525 MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
1526 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1527 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1529 .banks_enable = {true, false, false, false, true},
1530 .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */
1531 [4] = GENMASK(31, 20), /* USB */
1533 .iova_region = single_domain,
1534 .iova_region_nr = ARRAY_SIZE(single_domain),
1537 static const struct mtk_iommu_plat_data mt8195_data_vdo = {
1538 .m4u_plat = M4U_MT8195,
1539 .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1540 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1541 .hw_list = &m4ulist,
1542 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1544 .banks_enable = {true},
1545 .iova_region = mt8192_multi_dom,
1546 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1547 .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
1548 {13, 17, 15/* 17b */, 25}, {5}},
1551 static const struct mtk_iommu_plat_data mt8195_data_vpp = {
1552 .m4u_plat = M4U_MT8195,
1553 .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1554 WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1555 .hw_list = &m4ulist,
1556 .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1558 .banks_enable = {true},
1559 .iova_region = mt8192_multi_dom,
1560 .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1561 .larbid_remap = {{1}, {3},
1562 {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
1564 /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
1565 {14, 16, 29, 26, 30, 31, 18},
1566 {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
1569 static const struct mtk_iommu_plat_data mt8365_data = {
1570 .m4u_plat = M4U_MT8365,
1571 .flags = RESET_AXI | INT_ID_PORT_WIDTH_6,
1572 .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1574 .banks_enable = {true},
1575 .iova_region = single_domain,
1576 .iova_region_nr = ARRAY_SIZE(single_domain),
1577 .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1580 static const struct of_device_id mtk_iommu_of_ids[] = {
1581 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1582 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1583 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
1584 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1585 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1586 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1587 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
1588 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1589 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1590 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
1591 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
1592 { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
1596 static struct platform_driver mtk_iommu_driver = {
1597 .probe = mtk_iommu_probe,
1598 .remove = mtk_iommu_remove,
1600 .name = "mtk-iommu",
1601 .of_match_table = mtk_iommu_of_ids,
1602 .pm = &mtk_iommu_pm_ops,
1605 module_platform_driver(mtk_iommu_driver);
1607 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1608 MODULE_LICENSE("GPL v2");