1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
9 #include <linux/bitmap.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/export.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
17 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
20 #include <linux/of_device.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/sizes.h>
24 #include <linux/slab.h>
25 #include <linux/sys_soc.h>
27 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
28 #include <asm/dma-iommu.h>
30 #define arm_iommu_create_mapping(...) NULL
31 #define arm_iommu_attach_device(...) -ENODEV
32 #define arm_iommu_release_mapping(...) do {} while (0)
33 #define arm_iommu_detach_device(...) do {} while (0)
36 #define IPMMU_CTX_MAX 16U
37 #define IPMMU_CTX_INVALID -1
39 #define IPMMU_UTLB_MAX 64U
41 struct ipmmu_features {
42 bool use_ns_alias_offset;
43 bool has_cache_leaf_nodes;
44 unsigned int number_of_contexts;
45 unsigned int num_utlbs;
47 bool twobit_imttbcr_sl0;
48 bool reserved_context;
50 unsigned int ctx_offset_base;
51 unsigned int ctx_offset_stride;
52 unsigned int utlb_offset_base;
55 struct ipmmu_vmsa_device {
58 struct iommu_device iommu;
59 struct ipmmu_vmsa_device *root;
60 const struct ipmmu_features *features;
62 spinlock_t lock; /* Protects ctx and domains[] */
63 DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
64 struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
65 s8 utlb_ctx[IPMMU_UTLB_MAX];
67 struct iommu_group *group;
68 struct dma_iommu_mapping *mapping;
71 struct ipmmu_vmsa_domain {
72 struct ipmmu_vmsa_device *mmu;
73 struct iommu_domain io_domain;
75 struct io_pgtable_cfg cfg;
76 struct io_pgtable_ops *iop;
78 unsigned int context_id;
79 struct mutex mutex; /* Protects mappings */
82 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
84 return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
87 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
89 return dev_iommu_priv_get(dev);
92 #define TLB_LOOP_TIMEOUT 100 /* 100us */
94 /* -----------------------------------------------------------------------------
95 * Registers Definition
98 #define IM_NS_ALIAS_OFFSET 0x800
100 /* MMU "context" registers */
101 #define IMCTR 0x0000 /* R-Car Gen2/3 */
102 #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */
103 #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
104 #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
106 #define IMTTBCR 0x0008 /* R-Car Gen2/3 */
107 #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */
108 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */
109 #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */
110 #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */
111 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */
112 #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */
114 #define IMBUSCR 0x000c /* R-Car Gen2 only */
115 #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */
116 #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */
118 #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */
119 #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */
121 #define IMSTR 0x0020 /* R-Car Gen2/3 */
122 #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */
123 #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */
124 #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */
125 #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */
127 #define IMMAIR0 0x0028 /* R-Car Gen2/3 */
129 #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */
130 #define IMEUAR 0x0034 /* R-Car Gen3 only */
133 #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n))
134 #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */
135 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */
136 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */
137 #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
138 #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
140 #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n))
141 #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */
142 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */
144 /* -----------------------------------------------------------------------------
145 * Root device handling
148 static struct platform_driver ipmmu_driver;
150 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu)
152 return mmu->root == mmu;
155 static int __ipmmu_check_device(struct device *dev, void *data)
157 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
158 struct ipmmu_vmsa_device **rootp = data;
160 if (ipmmu_is_root(mmu))
166 static struct ipmmu_vmsa_device *ipmmu_find_root(void)
168 struct ipmmu_vmsa_device *root = NULL;
170 return driver_for_each_device(&ipmmu_driver.driver, NULL, &root,
171 __ipmmu_check_device) == 0 ? root : NULL;
174 /* -----------------------------------------------------------------------------
178 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
180 return ioread32(mmu->base + offset);
183 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
186 iowrite32(data, mmu->base + offset);
189 static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu,
190 unsigned int context_id, unsigned int reg)
192 unsigned int base = mmu->features->ctx_offset_base;
195 base += 0x800 - 8 * 0x40;
197 return base + context_id * mmu->features->ctx_offset_stride + reg;
200 static u32 ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu,
201 unsigned int context_id, unsigned int reg)
203 return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg));
206 static void ipmmu_ctx_write(struct ipmmu_vmsa_device *mmu,
207 unsigned int context_id, unsigned int reg, u32 data)
209 ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data);
212 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain,
215 return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg);
218 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain,
219 unsigned int reg, u32 data)
221 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data);
224 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
225 unsigned int reg, u32 data)
227 if (domain->mmu != domain->mmu->root)
228 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data);
230 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data);
233 static u32 ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, unsigned int reg)
235 return mmu->features->utlb_offset_base + reg;
238 static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu,
239 unsigned int utlb, u32 data)
241 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)), data);
244 static void ipmmu_imuctr_write(struct ipmmu_vmsa_device *mmu,
245 unsigned int utlb, u32 data)
247 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb)), data);
250 /* -----------------------------------------------------------------------------
251 * TLB and microTLB Management
254 /* Wait for any pending TLB invalidations to complete */
255 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
257 unsigned int count = 0;
259 while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) {
261 if (++count == TLB_LOOP_TIMEOUT) {
262 dev_err_ratelimited(domain->mmu->dev,
263 "TLB sync timed out -- MMU may be deadlocked\n");
270 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
274 reg = ipmmu_ctx_read_root(domain, IMCTR);
276 ipmmu_ctx_write_all(domain, IMCTR, reg);
278 ipmmu_tlb_sync(domain);
282 * Enable MMU translation for the microTLB.
284 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
287 struct ipmmu_vmsa_device *mmu = domain->mmu;
290 * TODO: Reference-count the microTLB as several bus masters can be
291 * connected to the same microTLB.
294 /* TODO: What should we set the ASID to ? */
295 ipmmu_imuasid_write(mmu, utlb, 0);
296 /* TODO: Do we need to flush the microTLB ? */
297 ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) |
298 IMUCTR_FLUSH | IMUCTR_MMUEN);
299 mmu->utlb_ctx[utlb] = domain->context_id;
302 static void ipmmu_tlb_flush_all(void *cookie)
304 struct ipmmu_vmsa_domain *domain = cookie;
306 ipmmu_tlb_invalidate(domain);
309 static void ipmmu_tlb_flush(unsigned long iova, size_t size,
310 size_t granule, void *cookie)
312 ipmmu_tlb_flush_all(cookie);
315 static const struct iommu_flush_ops ipmmu_flush_ops = {
316 .tlb_flush_all = ipmmu_tlb_flush_all,
317 .tlb_flush_walk = ipmmu_tlb_flush,
320 /* -----------------------------------------------------------------------------
321 * Domain/Context Management
324 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu,
325 struct ipmmu_vmsa_domain *domain)
330 spin_lock_irqsave(&mmu->lock, flags);
332 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx);
333 if (ret != mmu->num_ctx) {
334 mmu->domains[ret] = domain;
335 set_bit(ret, mmu->ctx);
339 spin_unlock_irqrestore(&mmu->lock, flags);
344 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
345 unsigned int context_id)
349 spin_lock_irqsave(&mmu->lock, flags);
351 clear_bit(context_id, mmu->ctx);
352 mmu->domains[context_id] = NULL;
354 spin_unlock_irqrestore(&mmu->lock, flags);
357 static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
363 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr;
364 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
365 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
369 * We use long descriptors and allocate the whole 32-bit VA space to
372 if (domain->mmu->features->twobit_imttbcr_sl0)
373 tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
375 tmp = IMTTBCR_SL0_LVL_1;
377 if (domain->mmu->features->cache_snoop)
378 tmp |= IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
381 ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | tmp);
384 ipmmu_ctx_write_root(domain, IMMAIR0,
385 domain->cfg.arm_lpae_s1_cfg.mair);
388 if (domain->mmu->features->setup_imbuscr)
389 ipmmu_ctx_write_root(domain, IMBUSCR,
390 ipmmu_ctx_read_root(domain, IMBUSCR) &
391 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
395 * Clear all interrupt flags.
397 ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR));
401 * Enable the MMU and interrupt generation. The long-descriptor
402 * translation table format doesn't use TEX remapping. Don't enable AF
403 * software management as we have no use for it. Flush the TLB as
404 * required when modifying the context registers.
406 ipmmu_ctx_write_all(domain, IMCTR,
407 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
410 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
415 * Allocate the page table operations.
417 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
418 * access, Long-descriptor format" that the NStable bit being set in a
419 * table descriptor will result in the NStable and NS bits of all child
420 * entries being ignored and considered as being set. The IPMMU seems
421 * not to comply with this, as it generates a secure access page fault
422 * if any of the NStable and NS bits isn't set when running in
425 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
426 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
427 domain->cfg.ias = 32;
428 domain->cfg.oas = 40;
429 domain->cfg.tlb = &ipmmu_flush_ops;
430 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
431 domain->io_domain.geometry.force_aperture = true;
433 * TODO: Add support for coherent walk through CCI with DVM and remove
434 * cache handling. For now, delegate it to the io-pgtable code.
436 domain->cfg.coherent_walk = false;
437 domain->cfg.iommu_dev = domain->mmu->root->dev;
440 * Find an unused context.
442 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
446 domain->context_id = ret;
448 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
451 ipmmu_domain_free_context(domain->mmu->root,
456 ipmmu_domain_setup_context(domain);
460 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
466 * Disable the context. Flush the TLB as required when modifying the
469 * TODO: Is TLB flush really needed ?
471 ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH);
472 ipmmu_tlb_sync(domain);
473 ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
476 /* -----------------------------------------------------------------------------
480 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
482 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
483 struct ipmmu_vmsa_device *mmu = domain->mmu;
487 status = ipmmu_ctx_read_root(domain, IMSTR);
488 if (!(status & err_mask))
491 iova = ipmmu_ctx_read_root(domain, IMELAR);
492 if (IS_ENABLED(CONFIG_64BIT))
493 iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32;
496 * Clear the error status flags. Unlike traditional interrupt flag
497 * registers that must be cleared by writing 1, this status register
498 * seems to require 0. The error address register must be read before,
499 * otherwise its value will be 0.
501 ipmmu_ctx_write_root(domain, IMSTR, 0);
503 /* Log fatal errors. */
504 if (status & IMSTR_MHIT)
505 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n",
507 if (status & IMSTR_ABORT)
508 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n",
511 if (!(status & (IMSTR_PF | IMSTR_TF)))
515 * Try to handle page faults and translation faults.
517 * TODO: We need to look up the faulty device based on the I/O VA. Use
518 * the IOMMU device for now.
520 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
523 dev_err_ratelimited(mmu->dev,
524 "Unhandled fault: status 0x%08x iova 0x%lx\n",
530 static irqreturn_t ipmmu_irq(int irq, void *dev)
532 struct ipmmu_vmsa_device *mmu = dev;
533 irqreturn_t status = IRQ_NONE;
537 spin_lock_irqsave(&mmu->lock, flags);
540 * Check interrupts for all active contexts.
542 for (i = 0; i < mmu->num_ctx; i++) {
543 if (!mmu->domains[i])
545 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED)
546 status = IRQ_HANDLED;
549 spin_unlock_irqrestore(&mmu->lock, flags);
554 /* -----------------------------------------------------------------------------
558 static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
560 struct ipmmu_vmsa_domain *domain;
562 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
565 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
569 mutex_init(&domain->mutex);
571 return &domain->io_domain;
574 static void ipmmu_domain_free(struct iommu_domain *io_domain)
576 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
579 * Free the domain resources. We assume that all devices have already
582 ipmmu_domain_destroy_context(domain);
583 free_io_pgtable_ops(domain->iop);
587 static int ipmmu_attach_device(struct iommu_domain *io_domain,
590 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
591 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
592 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
597 dev_err(dev, "Cannot attach to IPMMU\n");
601 mutex_lock(&domain->mutex);
604 /* The domain hasn't been used yet, initialize it. */
606 ret = ipmmu_domain_init_context(domain);
608 dev_err(dev, "Unable to initialize IPMMU context\n");
611 dev_info(dev, "Using IPMMU context %u\n",
614 } else if (domain->mmu != mmu) {
616 * Something is wrong, we can't attach two devices using
617 * different IOMMUs to the same domain.
621 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id);
623 mutex_unlock(&domain->mutex);
628 for (i = 0; i < fwspec->num_ids; ++i)
629 ipmmu_utlb_enable(domain, fwspec->ids[i]);
634 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
635 phys_addr_t paddr, size_t pgsize, size_t pgcount,
636 int prot, gfp_t gfp, size_t *mapped)
638 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
640 return domain->iop->map_pages(domain->iop, iova, paddr, pgsize, pgcount,
644 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
645 size_t pgsize, size_t pgcount,
646 struct iommu_iotlb_gather *gather)
648 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
650 return domain->iop->unmap_pages(domain->iop, iova, pgsize, pgcount, gather);
653 static void ipmmu_flush_iotlb_all(struct iommu_domain *io_domain)
655 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
658 ipmmu_tlb_flush_all(domain);
661 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain,
662 struct iommu_iotlb_gather *gather)
664 ipmmu_flush_iotlb_all(io_domain);
667 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
670 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
672 /* TODO: Is locking needed ? */
674 return domain->iop->iova_to_phys(domain->iop, iova);
677 static int ipmmu_init_platform_device(struct device *dev,
678 struct of_phandle_args *args)
680 struct platform_device *ipmmu_pdev;
682 ipmmu_pdev = of_find_device_by_node(args->np);
686 dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev));
691 static const struct soc_device_attribute soc_needs_opt_in[] = {
692 { .family = "R-Car Gen3", },
693 { .family = "R-Car Gen4", },
694 { .family = "RZ/G2", },
698 static const struct soc_device_attribute soc_denylist[] = {
699 { .soc_id = "r8a774a1", },
700 { .soc_id = "r8a7795", .revision = "ES1.*" },
701 { .soc_id = "r8a7795", .revision = "ES2.*" },
702 { .soc_id = "r8a7796", },
706 static const char * const devices_allowlist[] = {
713 static bool ipmmu_device_is_allowed(struct device *dev)
718 * R-Car Gen3/4 and RZ/G2 use the allow list to opt-in devices.
719 * For Other SoCs, this returns true anyway.
721 if (!soc_device_match(soc_needs_opt_in))
724 /* Check whether this SoC can use the IPMMU correctly or not */
725 if (soc_device_match(soc_denylist))
728 /* Check whether this device can work with the IPMMU */
729 for (i = 0; i < ARRAY_SIZE(devices_allowlist); i++) {
730 if (!strcmp(dev_name(dev), devices_allowlist[i]))
734 /* Otherwise, do not allow use of IPMMU */
738 static int ipmmu_of_xlate(struct device *dev,
739 struct of_phandle_args *spec)
741 if (!ipmmu_device_is_allowed(dev))
744 iommu_fwspec_add_ids(dev, spec->args, 1);
746 /* Initialize once - xlate() will call multiple times */
750 return ipmmu_init_platform_device(dev, spec);
753 static int ipmmu_init_arm_mapping(struct device *dev)
755 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
759 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
760 * VAs. This will allocate a corresponding IOMMU domain.
763 * - Create one mapping per context (TLB).
764 * - Make the mapping size configurable ? We currently use a 2GB mapping
765 * at a 1GB offset to ensure that NULL VAs will fault.
768 struct dma_iommu_mapping *mapping;
770 mapping = arm_iommu_create_mapping(&platform_bus_type,
772 if (IS_ERR(mapping)) {
773 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
774 ret = PTR_ERR(mapping);
778 mmu->mapping = mapping;
781 /* Attach the ARM VA mapping to the device. */
782 ret = arm_iommu_attach_device(dev, mmu->mapping);
784 dev_err(dev, "Failed to attach device to VA mapping\n");
792 arm_iommu_release_mapping(mmu->mapping);
797 static struct iommu_device *ipmmu_probe_device(struct device *dev)
799 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
802 * Only let through devices that have been verified in xlate()
805 return ERR_PTR(-ENODEV);
810 static void ipmmu_probe_finalize(struct device *dev)
814 if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA))
815 ret = ipmmu_init_arm_mapping(dev);
818 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
821 static void ipmmu_release_device(struct device *dev)
823 arm_iommu_detach_device(dev);
826 static struct iommu_group *ipmmu_find_group(struct device *dev)
828 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
829 struct iommu_group *group;
832 return iommu_group_ref_get(mmu->group);
834 group = iommu_group_alloc();
841 static const struct iommu_ops ipmmu_ops = {
842 .domain_alloc = ipmmu_domain_alloc,
843 .probe_device = ipmmu_probe_device,
844 .release_device = ipmmu_release_device,
845 .probe_finalize = ipmmu_probe_finalize,
846 .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)
847 ? generic_device_group : ipmmu_find_group,
848 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
849 .of_xlate = ipmmu_of_xlate,
850 .default_domain_ops = &(const struct iommu_domain_ops) {
851 .attach_dev = ipmmu_attach_device,
852 .map_pages = ipmmu_map,
853 .unmap_pages = ipmmu_unmap,
854 .flush_iotlb_all = ipmmu_flush_iotlb_all,
855 .iotlb_sync = ipmmu_iotlb_sync,
856 .iova_to_phys = ipmmu_iova_to_phys,
857 .free = ipmmu_domain_free,
861 /* -----------------------------------------------------------------------------
862 * Probe/remove and init
865 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
869 /* Disable all contexts. */
870 for (i = 0; i < mmu->num_ctx; ++i)
871 ipmmu_ctx_write(mmu, i, IMCTR, 0);
874 static const struct ipmmu_features ipmmu_features_default = {
875 .use_ns_alias_offset = true,
876 .has_cache_leaf_nodes = false,
877 .number_of_contexts = 1, /* software only tested with one context */
879 .setup_imbuscr = true,
880 .twobit_imttbcr_sl0 = false,
881 .reserved_context = false,
883 .ctx_offset_base = 0,
884 .ctx_offset_stride = 0x40,
885 .utlb_offset_base = 0,
888 static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
889 .use_ns_alias_offset = false,
890 .has_cache_leaf_nodes = true,
891 .number_of_contexts = 8,
893 .setup_imbuscr = false,
894 .twobit_imttbcr_sl0 = true,
895 .reserved_context = true,
896 .cache_snoop = false,
897 .ctx_offset_base = 0,
898 .ctx_offset_stride = 0x40,
899 .utlb_offset_base = 0,
902 static const struct ipmmu_features ipmmu_features_rcar_gen4 = {
903 .use_ns_alias_offset = false,
904 .has_cache_leaf_nodes = true,
905 .number_of_contexts = 16,
907 .setup_imbuscr = false,
908 .twobit_imttbcr_sl0 = true,
909 .reserved_context = true,
910 .cache_snoop = false,
911 .ctx_offset_base = 0x10000,
912 .ctx_offset_stride = 0x1040,
913 .utlb_offset_base = 0x3000,
916 static const struct of_device_id ipmmu_of_ids[] = {
918 .compatible = "renesas,ipmmu-vmsa",
919 .data = &ipmmu_features_default,
921 .compatible = "renesas,ipmmu-r8a774a1",
922 .data = &ipmmu_features_rcar_gen3,
924 .compatible = "renesas,ipmmu-r8a774b1",
925 .data = &ipmmu_features_rcar_gen3,
927 .compatible = "renesas,ipmmu-r8a774c0",
928 .data = &ipmmu_features_rcar_gen3,
930 .compatible = "renesas,ipmmu-r8a774e1",
931 .data = &ipmmu_features_rcar_gen3,
933 .compatible = "renesas,ipmmu-r8a7795",
934 .data = &ipmmu_features_rcar_gen3,
936 .compatible = "renesas,ipmmu-r8a7796",
937 .data = &ipmmu_features_rcar_gen3,
939 .compatible = "renesas,ipmmu-r8a77961",
940 .data = &ipmmu_features_rcar_gen3,
942 .compatible = "renesas,ipmmu-r8a77965",
943 .data = &ipmmu_features_rcar_gen3,
945 .compatible = "renesas,ipmmu-r8a77970",
946 .data = &ipmmu_features_rcar_gen3,
948 .compatible = "renesas,ipmmu-r8a77980",
949 .data = &ipmmu_features_rcar_gen3,
951 .compatible = "renesas,ipmmu-r8a77990",
952 .data = &ipmmu_features_rcar_gen3,
954 .compatible = "renesas,ipmmu-r8a77995",
955 .data = &ipmmu_features_rcar_gen3,
957 .compatible = "renesas,ipmmu-r8a779a0",
958 .data = &ipmmu_features_rcar_gen4,
960 .compatible = "renesas,rcar-gen4-ipmmu-vmsa",
961 .data = &ipmmu_features_rcar_gen4,
967 static int ipmmu_probe(struct platform_device *pdev)
969 struct ipmmu_vmsa_device *mmu;
970 struct resource *res;
974 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
976 dev_err(&pdev->dev, "cannot allocate device data\n");
980 mmu->dev = &pdev->dev;
981 spin_lock_init(&mmu->lock);
982 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
983 mmu->features = of_device_get_match_data(&pdev->dev);
984 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs);
985 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
989 /* Map I/O memory and request IRQ. */
990 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
991 mmu->base = devm_ioremap_resource(&pdev->dev, res);
992 if (IS_ERR(mmu->base))
993 return PTR_ERR(mmu->base);
996 * The IPMMU has two register banks, for secure and non-secure modes.
997 * The bank mapped at the beginning of the IPMMU address space
998 * corresponds to the running mode of the CPU. When running in secure
999 * mode the non-secure register bank is also available at an offset.
1001 * Secure mode operation isn't clearly documented and is thus currently
1002 * not implemented in the driver. Furthermore, preliminary tests of
1003 * non-secure operation with the main register bank were not successful.
1004 * Offset the registers base unconditionally to point to the non-secure
1005 * alias space for now.
1007 if (mmu->features->use_ns_alias_offset)
1008 mmu->base += IM_NS_ALIAS_OFFSET;
1010 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts);
1013 * Determine if this IPMMU instance is a root device by checking for
1014 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
1016 if (!mmu->features->has_cache_leaf_nodes ||
1017 !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL))
1020 mmu->root = ipmmu_find_root();
1023 * Wait until the root device has been registered for sure.
1026 return -EPROBE_DEFER;
1028 /* Root devices have mandatory IRQs */
1029 if (ipmmu_is_root(mmu)) {
1030 irq = platform_get_irq(pdev, 0);
1034 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
1035 dev_name(&pdev->dev), mmu);
1037 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
1041 ipmmu_device_reset(mmu);
1043 if (mmu->features->reserved_context) {
1044 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n");
1045 set_bit(0, mmu->ctx);
1050 * Register the IPMMU to the IOMMU subsystem in the following cases:
1051 * - R-Car Gen2 IPMMU (all devices registered)
1052 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
1054 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) {
1055 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
1056 dev_name(&pdev->dev));
1060 ret = iommu_device_register(&mmu->iommu, &ipmmu_ops, &pdev->dev);
1066 * We can't create the ARM mapping here as it requires the bus to have
1067 * an IOMMU, which only happens when bus_set_iommu() is called in
1068 * ipmmu_init() after the probe function returns.
1071 platform_set_drvdata(pdev, mmu);
1076 static int ipmmu_remove(struct platform_device *pdev)
1078 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
1080 iommu_device_sysfs_remove(&mmu->iommu);
1081 iommu_device_unregister(&mmu->iommu);
1083 arm_iommu_release_mapping(mmu->mapping);
1085 ipmmu_device_reset(mmu);
1090 #ifdef CONFIG_PM_SLEEP
1091 static int ipmmu_resume_noirq(struct device *dev)
1093 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
1096 /* Reset root MMU and restore contexts */
1097 if (ipmmu_is_root(mmu)) {
1098 ipmmu_device_reset(mmu);
1100 for (i = 0; i < mmu->num_ctx; i++) {
1101 if (!mmu->domains[i])
1104 ipmmu_domain_setup_context(mmu->domains[i]);
1108 /* Re-enable active micro-TLBs */
1109 for (i = 0; i < mmu->features->num_utlbs; i++) {
1110 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID)
1113 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i);
1119 static const struct dev_pm_ops ipmmu_pm = {
1120 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq)
1122 #define DEV_PM_OPS &ipmmu_pm
1124 #define DEV_PM_OPS NULL
1125 #endif /* CONFIG_PM_SLEEP */
1127 static struct platform_driver ipmmu_driver = {
1129 .name = "ipmmu-vmsa",
1130 .of_match_table = of_match_ptr(ipmmu_of_ids),
1133 .probe = ipmmu_probe,
1134 .remove = ipmmu_remove,
1136 builtin_platform_driver(ipmmu_driver);