1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU-agnostic ARM page table allocator.
5 * Copyright (C) 2014 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
10 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
12 #include <linux/atomic.h>
13 #include <linux/bitops.h>
14 #include <linux/io-pgtable.h>
15 #include <linux/kernel.h>
16 #include <linux/sizes.h>
17 #include <linux/slab.h>
18 #include <linux/types.h>
19 #include <linux/dma-mapping.h>
21 #include <asm/barrier.h>
23 #define ARM_LPAE_MAX_ADDR_BITS 52
24 #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
25 #define ARM_LPAE_MAX_LEVELS 4
27 /* Struct accessors */
28 #define io_pgtable_to_data(x) \
29 container_of((x), struct arm_lpae_io_pgtable, iop)
31 #define io_pgtable_ops_to_data(x) \
32 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
35 * Calculate the right shift amount to get to the portion describing level l
36 * in a virtual address mapped by the pagetable in d.
38 #define ARM_LPAE_LVL_SHIFT(l,d) \
39 (((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level) + \
40 ilog2(sizeof(arm_lpae_iopte)))
42 #define ARM_LPAE_GRANULE(d) \
43 (sizeof(arm_lpae_iopte) << (d)->bits_per_level)
44 #define ARM_LPAE_PGD_SIZE(d) \
45 (sizeof(arm_lpae_iopte) << (d)->pgd_bits)
48 * Calculate the index at level l used to map virtual address a using the
51 #define ARM_LPAE_PGD_IDX(l,d) \
52 ((l) == (d)->start_level ? (d)->pgd_bits - (d)->bits_per_level : 0)
54 #define ARM_LPAE_LVL_IDX(a,l,d) \
55 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
56 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
58 /* Calculate the block/page mapping size at level l for pagetable in d. */
59 #define ARM_LPAE_BLOCK_SIZE(l,d) (1ULL << ARM_LPAE_LVL_SHIFT(l,d))
62 #define ARM_LPAE_PTE_TYPE_SHIFT 0
63 #define ARM_LPAE_PTE_TYPE_MASK 0x3
65 #define ARM_LPAE_PTE_TYPE_BLOCK 1
66 #define ARM_LPAE_PTE_TYPE_TABLE 3
67 #define ARM_LPAE_PTE_TYPE_PAGE 3
69 #define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
71 #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
72 #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
73 #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
74 #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
75 #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
76 #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
77 #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
78 #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
80 #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
81 /* Ignore the contiguous bit for block splitting */
82 #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
83 #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
84 ARM_LPAE_PTE_ATTR_HI_MASK)
85 /* Software bit for solving coherency races */
86 #define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
89 #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
90 #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
91 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
92 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
95 #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
96 #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
97 #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
98 #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
99 #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
100 #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
103 #define ARM_LPAE_TCR_TG0_4K 0
104 #define ARM_LPAE_TCR_TG0_64K 1
105 #define ARM_LPAE_TCR_TG0_16K 2
107 #define ARM_LPAE_TCR_TG1_16K 1
108 #define ARM_LPAE_TCR_TG1_4K 2
109 #define ARM_LPAE_TCR_TG1_64K 3
111 #define ARM_LPAE_TCR_SH_NS 0
112 #define ARM_LPAE_TCR_SH_OS 2
113 #define ARM_LPAE_TCR_SH_IS 3
115 #define ARM_LPAE_TCR_RGN_NC 0
116 #define ARM_LPAE_TCR_RGN_WBWA 1
117 #define ARM_LPAE_TCR_RGN_WT 2
118 #define ARM_LPAE_TCR_RGN_WB 3
120 #define ARM_LPAE_VTCR_SL0_MASK 0x3
122 #define ARM_LPAE_TCR_T0SZ_SHIFT 0
124 #define ARM_LPAE_VTCR_PS_SHIFT 16
125 #define ARM_LPAE_VTCR_PS_MASK 0x7
127 #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
128 #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
129 #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
130 #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
131 #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
132 #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
133 #define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
135 #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
136 #define ARM_LPAE_MAIR_ATTR_MASK 0xff
137 #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
138 #define ARM_LPAE_MAIR_ATTR_NC 0x44
139 #define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4
140 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
141 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
142 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
143 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
144 #define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3
146 #define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
147 #define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
148 #define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4)
150 #define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL
151 #define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
153 /* IOPTE accessors */
154 #define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
156 #define iopte_type(pte,l) \
157 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
159 #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
161 struct arm_lpae_io_pgtable {
162 struct io_pgtable iop;
171 typedef u64 arm_lpae_iopte;
173 static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl,
174 enum io_pgtable_fmt fmt)
176 if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE)
177 return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_PAGE;
179 return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_BLOCK;
182 static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
183 struct arm_lpae_io_pgtable *data)
185 arm_lpae_iopte pte = paddr;
187 /* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
188 return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
191 static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
192 struct arm_lpae_io_pgtable *data)
194 u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
196 if (ARM_LPAE_GRANULE(data) < SZ_64K)
199 /* Rotate the packed high-order bits back to the top */
200 return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
203 static bool selftest_running = false;
205 static dma_addr_t __arm_lpae_dma_addr(void *pages)
207 return (dma_addr_t)virt_to_phys(pages);
210 static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
211 struct io_pgtable_cfg *cfg)
213 struct device *dev = cfg->iommu_dev;
214 int order = get_order(size);
219 VM_BUG_ON((gfp & __GFP_HIGHMEM));
220 p = alloc_pages_node(dev ? dev_to_node(dev) : NUMA_NO_NODE,
221 gfp | __GFP_ZERO, order);
225 pages = page_address(p);
226 if (!cfg->coherent_walk) {
227 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
228 if (dma_mapping_error(dev, dma))
231 * We depend on the IOMMU being able to work with any physical
232 * address directly, so if the DMA layer suggests otherwise by
233 * translating or truncating them, that bodes very badly...
235 if (dma != virt_to_phys(pages))
242 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
243 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
245 __free_pages(p, order);
249 static void __arm_lpae_free_pages(void *pages, size_t size,
250 struct io_pgtable_cfg *cfg)
252 if (!cfg->coherent_walk)
253 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
254 size, DMA_TO_DEVICE);
255 free_pages((unsigned long)pages, get_order(size));
258 static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep,
259 struct io_pgtable_cfg *cfg)
261 dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
262 sizeof(*ptep), DMA_TO_DEVICE);
265 static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
266 struct io_pgtable_cfg *cfg)
270 if (!cfg->coherent_walk)
271 __arm_lpae_sync_pte(ptep, cfg);
274 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
275 struct iommu_iotlb_gather *gather,
276 unsigned long iova, size_t size, int lvl,
277 arm_lpae_iopte *ptep);
279 static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
280 phys_addr_t paddr, arm_lpae_iopte prot,
281 int lvl, arm_lpae_iopte *ptep)
283 arm_lpae_iopte pte = prot;
285 if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1)
286 pte |= ARM_LPAE_PTE_TYPE_PAGE;
288 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
290 pte |= paddr_to_iopte(paddr, data);
292 __arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
295 static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
296 unsigned long iova, phys_addr_t paddr,
297 arm_lpae_iopte prot, int lvl,
298 arm_lpae_iopte *ptep)
300 arm_lpae_iopte pte = *ptep;
302 if (iopte_leaf(pte, lvl, data->iop.fmt)) {
303 /* We require an unmap first */
304 WARN_ON(!selftest_running);
306 } else if (iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_TABLE) {
308 * We need to unmap and free the old table before
309 * overwriting it with a block entry.
311 arm_lpae_iopte *tblp;
312 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
314 tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
315 if (__arm_lpae_unmap(data, NULL, iova, sz, lvl, tblp) != sz) {
321 __arm_lpae_init_pte(data, paddr, prot, lvl, ptep);
325 static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
326 arm_lpae_iopte *ptep,
328 struct io_pgtable_cfg *cfg)
330 arm_lpae_iopte old, new;
332 new = __pa(table) | ARM_LPAE_PTE_TYPE_TABLE;
333 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
334 new |= ARM_LPAE_PTE_NSTABLE;
337 * Ensure the table itself is visible before its PTE can be.
338 * Whilst we could get away with cmpxchg64_release below, this
339 * doesn't have any ordering semantics when !CONFIG_SMP.
343 old = cmpxchg64_relaxed(ptep, curr, new);
345 if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC))
348 /* Even if it's not ours, there's no point waiting; just kick it */
349 __arm_lpae_sync_pte(ptep, cfg);
351 WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
356 static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
357 phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
358 int lvl, arm_lpae_iopte *ptep, gfp_t gfp)
360 arm_lpae_iopte *cptep, pte;
361 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
362 size_t tblsz = ARM_LPAE_GRANULE(data);
363 struct io_pgtable_cfg *cfg = &data->iop.cfg;
365 /* Find our entry at the current level */
366 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
368 /* If we can install a leaf entry at this level, then do so */
369 if (size == block_size)
370 return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
372 /* We can't allocate tables at the final level */
373 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
376 /* Grab a pointer to the next level */
377 pte = READ_ONCE(*ptep);
379 cptep = __arm_lpae_alloc_pages(tblsz, gfp, cfg);
383 pte = arm_lpae_install_table(cptep, ptep, 0, cfg);
385 __arm_lpae_free_pages(cptep, tblsz, cfg);
386 } else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) {
387 __arm_lpae_sync_pte(ptep, cfg);
390 if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) {
391 cptep = iopte_deref(pte, data);
393 /* We require an unmap first */
394 WARN_ON(!selftest_running);
399 return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep, gfp);
402 static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
407 if (data->iop.fmt == ARM_64_LPAE_S1 ||
408 data->iop.fmt == ARM_32_LPAE_S1) {
409 pte = ARM_LPAE_PTE_nG;
410 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
411 pte |= ARM_LPAE_PTE_AP_RDONLY;
412 if (!(prot & IOMMU_PRIV))
413 pte |= ARM_LPAE_PTE_AP_UNPRIV;
415 pte = ARM_LPAE_PTE_HAP_FAULT;
416 if (prot & IOMMU_READ)
417 pte |= ARM_LPAE_PTE_HAP_READ;
418 if (prot & IOMMU_WRITE)
419 pte |= ARM_LPAE_PTE_HAP_WRITE;
423 * Note that this logic is structured to accommodate Mali LPAE
424 * having stage-1-like attributes but stage-2-like permissions.
426 if (data->iop.fmt == ARM_64_LPAE_S2 ||
427 data->iop.fmt == ARM_32_LPAE_S2) {
428 if (prot & IOMMU_MMIO)
429 pte |= ARM_LPAE_PTE_MEMATTR_DEV;
430 else if (prot & IOMMU_CACHE)
431 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
433 pte |= ARM_LPAE_PTE_MEMATTR_NC;
435 if (prot & IOMMU_MMIO)
436 pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
437 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
438 else if (prot & IOMMU_CACHE)
439 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
440 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
443 if (prot & IOMMU_CACHE)
444 pte |= ARM_LPAE_PTE_SH_IS;
446 pte |= ARM_LPAE_PTE_SH_OS;
448 if (prot & IOMMU_NOEXEC)
449 pte |= ARM_LPAE_PTE_XN;
451 if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
452 pte |= ARM_LPAE_PTE_NS;
454 if (data->iop.fmt != ARM_MALI_LPAE)
455 pte |= ARM_LPAE_PTE_AF;
460 static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
461 phys_addr_t paddr, size_t size, int iommu_prot, gfp_t gfp)
463 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
464 struct io_pgtable_cfg *cfg = &data->iop.cfg;
465 arm_lpae_iopte *ptep = data->pgd;
466 int ret, lvl = data->start_level;
468 long iaext = (s64)iova >> cfg->ias;
470 /* If no access, then nothing to do */
471 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
474 if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size))
477 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
479 if (WARN_ON(iaext || paddr >> cfg->oas))
482 prot = arm_lpae_prot_to_pte(data, iommu_prot);
483 ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep, gfp);
485 * Synchronise all PTE updates for the new mapping before there's
486 * a chance for anything to kick off a table walk for the new iova.
493 static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
494 arm_lpae_iopte *ptep)
496 arm_lpae_iopte *start, *end;
497 unsigned long table_size;
499 if (lvl == data->start_level)
500 table_size = ARM_LPAE_PGD_SIZE(data);
502 table_size = ARM_LPAE_GRANULE(data);
506 /* Only leaf entries at the last level */
507 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
510 end = (void *)ptep + table_size;
512 while (ptep != end) {
513 arm_lpae_iopte pte = *ptep++;
515 if (!pte || iopte_leaf(pte, lvl, data->iop.fmt))
518 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
521 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
524 static void arm_lpae_free_pgtable(struct io_pgtable *iop)
526 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
528 __arm_lpae_free_pgtable(data, data->start_level, data->pgd);
532 static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
533 struct iommu_iotlb_gather *gather,
534 unsigned long iova, size_t size,
535 arm_lpae_iopte blk_pte, int lvl,
536 arm_lpae_iopte *ptep)
538 struct io_pgtable_cfg *cfg = &data->iop.cfg;
539 arm_lpae_iopte pte, *tablep;
540 phys_addr_t blk_paddr;
541 size_t tablesz = ARM_LPAE_GRANULE(data);
542 size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
543 int i, unmap_idx = -1;
545 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
548 tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg);
550 return 0; /* Bytes unmapped */
552 if (size == split_sz)
553 unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data);
555 blk_paddr = iopte_to_paddr(blk_pte, data);
556 pte = iopte_prot(blk_pte);
558 for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
563 __arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]);
566 pte = arm_lpae_install_table(tablep, ptep, blk_pte, cfg);
567 if (pte != blk_pte) {
568 __arm_lpae_free_pages(tablep, tablesz, cfg);
570 * We may race against someone unmapping another part of this
571 * block, but anything else is invalid. We can't misinterpret
572 * a page entry here since we're never at the last level.
574 if (iopte_type(pte, lvl - 1) != ARM_LPAE_PTE_TYPE_TABLE)
577 tablep = iopte_deref(pte, data);
578 } else if (unmap_idx >= 0) {
579 io_pgtable_tlb_add_page(&data->iop, gather, iova, size);
583 return __arm_lpae_unmap(data, gather, iova, size, lvl, tablep);
586 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
587 struct iommu_iotlb_gather *gather,
588 unsigned long iova, size_t size, int lvl,
589 arm_lpae_iopte *ptep)
592 struct io_pgtable *iop = &data->iop;
594 /* Something went horribly wrong and we ran out of page table */
595 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
598 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
599 pte = READ_ONCE(*ptep);
603 /* If the size matches this level, we're in the right place */
604 if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
605 __arm_lpae_set_pte(ptep, 0, &iop->cfg);
607 if (!iopte_leaf(pte, lvl, iop->fmt)) {
608 /* Also flush any partial walks */
609 io_pgtable_tlb_flush_walk(iop, iova, size,
610 ARM_LPAE_GRANULE(data));
611 ptep = iopte_deref(pte, data);
612 __arm_lpae_free_pgtable(data, lvl + 1, ptep);
613 } else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) {
615 * Order the PTE update against queueing the IOVA, to
616 * guarantee that a flush callback from a different CPU
617 * has observed it before the TLBIALL can be issued.
621 io_pgtable_tlb_add_page(iop, gather, iova, size);
625 } else if (iopte_leaf(pte, lvl, iop->fmt)) {
627 * Insert a table at the next level to map the old region,
628 * minus the part we want to unmap
630 return arm_lpae_split_blk_unmap(data, gather, iova, size, pte,
634 /* Keep on walkin' */
635 ptep = iopte_deref(pte, data);
636 return __arm_lpae_unmap(data, gather, iova, size, lvl + 1, ptep);
639 static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
640 size_t size, struct iommu_iotlb_gather *gather)
642 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
643 struct io_pgtable_cfg *cfg = &data->iop.cfg;
644 arm_lpae_iopte *ptep = data->pgd;
645 long iaext = (s64)iova >> cfg->ias;
647 if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size))
650 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
655 return __arm_lpae_unmap(data, gather, iova, size, data->start_level, ptep);
658 static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
661 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
662 arm_lpae_iopte pte, *ptep = data->pgd;
663 int lvl = data->start_level;
666 /* Valid IOPTE pointer? */
670 /* Grab the IOPTE we're interested in */
671 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
672 pte = READ_ONCE(*ptep);
679 if (iopte_leaf(pte, lvl, data->iop.fmt))
680 goto found_translation;
682 /* Take it to the next level */
683 ptep = iopte_deref(pte, data);
684 } while (++lvl < ARM_LPAE_MAX_LEVELS);
686 /* Ran out of page tables to walk */
690 iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
691 return iopte_to_paddr(pte, data) | iova;
694 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
696 unsigned long granule, page_sizes;
697 unsigned int max_addr_bits = 48;
700 * We need to restrict the supported page sizes to match the
701 * translation regime for a particular granule. Aim to match
702 * the CPU page size if possible, otherwise prefer smaller sizes.
703 * While we're at it, restrict the block sizes to match the
706 if (cfg->pgsize_bitmap & PAGE_SIZE)
708 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
709 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
710 else if (cfg->pgsize_bitmap & PAGE_MASK)
711 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
717 page_sizes = (SZ_4K | SZ_2M | SZ_1G);
720 page_sizes = (SZ_16K | SZ_32M);
724 page_sizes = (SZ_64K | SZ_512M);
726 page_sizes |= 1ULL << 42; /* 4TB */
732 cfg->pgsize_bitmap &= page_sizes;
733 cfg->ias = min(cfg->ias, max_addr_bits);
734 cfg->oas = min(cfg->oas, max_addr_bits);
737 static struct arm_lpae_io_pgtable *
738 arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
740 struct arm_lpae_io_pgtable *data;
741 int levels, va_bits, pg_shift;
743 arm_lpae_restrict_pgsizes(cfg);
745 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
748 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
751 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
754 data = kmalloc(sizeof(*data), GFP_KERNEL);
758 pg_shift = __ffs(cfg->pgsize_bitmap);
759 data->bits_per_level = pg_shift - ilog2(sizeof(arm_lpae_iopte));
761 va_bits = cfg->ias - pg_shift;
762 levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
763 data->start_level = ARM_LPAE_MAX_LEVELS - levels;
765 /* Calculate the actual size of our pgd (without concatenation) */
766 data->pgd_bits = va_bits - (data->bits_per_level * (levels - 1));
768 data->iop.ops = (struct io_pgtable_ops) {
770 .unmap = arm_lpae_unmap,
771 .iova_to_phys = arm_lpae_iova_to_phys,
777 static struct io_pgtable *
778 arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
781 struct arm_lpae_io_pgtable *data;
782 typeof(&cfg->arm_lpae_s1_cfg.tcr) tcr = &cfg->arm_lpae_s1_cfg.tcr;
785 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
786 IO_PGTABLE_QUIRK_NON_STRICT |
787 IO_PGTABLE_QUIRK_ARM_TTBR1))
790 data = arm_lpae_alloc_pgtable(cfg);
795 if (cfg->coherent_walk) {
796 tcr->sh = ARM_LPAE_TCR_SH_IS;
797 tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
798 tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
800 tcr->sh = ARM_LPAE_TCR_SH_OS;
801 tcr->irgn = ARM_LPAE_TCR_RGN_NC;
802 tcr->orgn = ARM_LPAE_TCR_RGN_NC;
805 tg1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1;
806 switch (ARM_LPAE_GRANULE(data)) {
808 tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_4K : ARM_LPAE_TCR_TG0_4K;
811 tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_16K : ARM_LPAE_TCR_TG0_16K;
814 tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_64K : ARM_LPAE_TCR_TG0_64K;
820 tcr->ips = ARM_LPAE_TCR_PS_32_BIT;
823 tcr->ips = ARM_LPAE_TCR_PS_36_BIT;
826 tcr->ips = ARM_LPAE_TCR_PS_40_BIT;
829 tcr->ips = ARM_LPAE_TCR_PS_42_BIT;
832 tcr->ips = ARM_LPAE_TCR_PS_44_BIT;
835 tcr->ips = ARM_LPAE_TCR_PS_48_BIT;
838 tcr->ips = ARM_LPAE_TCR_PS_52_BIT;
844 tcr->tsz = 64ULL - cfg->ias;
847 reg = (ARM_LPAE_MAIR_ATTR_NC
848 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
849 (ARM_LPAE_MAIR_ATTR_WBRWA
850 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
851 (ARM_LPAE_MAIR_ATTR_DEVICE
852 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)) |
853 (ARM_LPAE_MAIR_ATTR_INC_OWBRWA
854 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE));
856 cfg->arm_lpae_s1_cfg.mair = reg;
858 /* Looking good; allocate a pgd */
859 data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),
864 /* Ensure the empty pgd is visible before any actual TTBR write */
868 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd);
876 static struct io_pgtable *
877 arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
880 struct arm_lpae_io_pgtable *data;
881 typeof(&cfg->arm_lpae_s2_cfg.vtcr) vtcr = &cfg->arm_lpae_s2_cfg.vtcr;
883 /* The NS quirk doesn't apply at stage 2 */
884 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NON_STRICT))
887 data = arm_lpae_alloc_pgtable(cfg);
892 * Concatenate PGDs at level 1 if possible in order to reduce
893 * the depth of the stage-2 walk.
895 if (data->start_level == 0) {
896 unsigned long pgd_pages;
898 pgd_pages = ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte);
899 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
900 data->pgd_bits += data->bits_per_level;
906 if (cfg->coherent_walk) {
907 vtcr->sh = ARM_LPAE_TCR_SH_IS;
908 vtcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
909 vtcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
911 vtcr->sh = ARM_LPAE_TCR_SH_OS;
912 vtcr->irgn = ARM_LPAE_TCR_RGN_NC;
913 vtcr->orgn = ARM_LPAE_TCR_RGN_NC;
916 sl = data->start_level;
918 switch (ARM_LPAE_GRANULE(data)) {
920 vtcr->tg = ARM_LPAE_TCR_TG0_4K;
921 sl++; /* SL0 format is different for 4K granule size */
924 vtcr->tg = ARM_LPAE_TCR_TG0_16K;
927 vtcr->tg = ARM_LPAE_TCR_TG0_64K;
933 vtcr->ps = ARM_LPAE_TCR_PS_32_BIT;
936 vtcr->ps = ARM_LPAE_TCR_PS_36_BIT;
939 vtcr->ps = ARM_LPAE_TCR_PS_40_BIT;
942 vtcr->ps = ARM_LPAE_TCR_PS_42_BIT;
945 vtcr->ps = ARM_LPAE_TCR_PS_44_BIT;
948 vtcr->ps = ARM_LPAE_TCR_PS_48_BIT;
951 vtcr->ps = ARM_LPAE_TCR_PS_52_BIT;
957 vtcr->tsz = 64ULL - cfg->ias;
958 vtcr->sl = ~sl & ARM_LPAE_VTCR_SL0_MASK;
960 /* Allocate pgd pages */
961 data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),
966 /* Ensure the empty pgd is visible before any actual TTBR write */
970 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
978 static struct io_pgtable *
979 arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
981 if (cfg->ias > 32 || cfg->oas > 40)
984 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
985 return arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
988 static struct io_pgtable *
989 arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
991 if (cfg->ias > 40 || cfg->oas > 40)
994 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
995 return arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
998 static struct io_pgtable *
999 arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
1001 struct arm_lpae_io_pgtable *data;
1003 /* No quirks for Mali (hopefully) */
1007 if (cfg->ias > 48 || cfg->oas > 40)
1010 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
1012 data = arm_lpae_alloc_pgtable(cfg);
1016 /* Mali seems to need a full 4-level table regardless of IAS */
1017 if (data->start_level > 0) {
1018 data->start_level = 0;
1022 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
1023 * best we can do is mimic the out-of-tree driver and hope that the
1024 * "implementation-defined caching policy" is good enough. Similarly,
1025 * we'll use it for the sake of a valid attribute for our 'device'
1026 * index, although callers should never request that in practice.
1028 cfg->arm_mali_lpae_cfg.memattr =
1029 (ARM_MALI_LPAE_MEMATTR_IMP_DEF
1030 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
1031 (ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC
1032 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
1033 (ARM_MALI_LPAE_MEMATTR_IMP_DEF
1034 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
1036 data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), GFP_KERNEL,
1041 /* Ensure the empty pgd is visible before TRANSTAB can be written */
1044 cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
1045 ARM_MALI_LPAE_TTBR_READ_INNER |
1046 ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
1054 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
1055 .alloc = arm_64_lpae_alloc_pgtable_s1,
1056 .free = arm_lpae_free_pgtable,
1059 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
1060 .alloc = arm_64_lpae_alloc_pgtable_s2,
1061 .free = arm_lpae_free_pgtable,
1064 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
1065 .alloc = arm_32_lpae_alloc_pgtable_s1,
1066 .free = arm_lpae_free_pgtable,
1069 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
1070 .alloc = arm_32_lpae_alloc_pgtable_s2,
1071 .free = arm_lpae_free_pgtable,
1074 struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = {
1075 .alloc = arm_mali_lpae_alloc_pgtable,
1076 .free = arm_lpae_free_pgtable,
1079 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
1081 static struct io_pgtable_cfg *cfg_cookie __initdata;
1083 static void __init dummy_tlb_flush_all(void *cookie)
1085 WARN_ON(cookie != cfg_cookie);
1088 static void __init dummy_tlb_flush(unsigned long iova, size_t size,
1089 size_t granule, void *cookie)
1091 WARN_ON(cookie != cfg_cookie);
1092 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
1095 static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather,
1096 unsigned long iova, size_t granule,
1099 dummy_tlb_flush(iova, granule, granule, cookie);
1102 static const struct iommu_flush_ops dummy_tlb_ops __initconst = {
1103 .tlb_flush_all = dummy_tlb_flush_all,
1104 .tlb_flush_walk = dummy_tlb_flush,
1105 .tlb_flush_leaf = dummy_tlb_flush,
1106 .tlb_add_page = dummy_tlb_add_page,
1109 static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
1111 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
1112 struct io_pgtable_cfg *cfg = &data->iop.cfg;
1114 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
1115 cfg->pgsize_bitmap, cfg->ias);
1116 pr_err("data: %d levels, 0x%zx pgd_size, %u pg_shift, %u bits_per_level, pgd @ %p\n",
1117 ARM_LPAE_MAX_LEVELS - data->start_level, ARM_LPAE_PGD_SIZE(data),
1118 ilog2(ARM_LPAE_GRANULE(data)), data->bits_per_level, data->pgd);
1121 #define __FAIL(ops, i) ({ \
1122 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
1123 arm_lpae_dump_ops(ops); \
1124 selftest_running = false; \
1128 static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
1130 static const enum io_pgtable_fmt fmts[] __initconst = {
1138 struct io_pgtable_ops *ops;
1140 selftest_running = true;
1142 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
1144 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
1146 pr_err("selftest: failed to allocate io pgtable ops\n");
1151 * Initial sanity checks.
1152 * Empty page tables shouldn't provide any translations.
1154 if (ops->iova_to_phys(ops, 42))
1155 return __FAIL(ops, i);
1157 if (ops->iova_to_phys(ops, SZ_1G + 42))
1158 return __FAIL(ops, i);
1160 if (ops->iova_to_phys(ops, SZ_2G + 42))
1161 return __FAIL(ops, i);
1164 * Distinct mappings of different granule sizes.
1167 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1170 if (ops->map(ops, iova, iova, size, IOMMU_READ |
1173 IOMMU_CACHE, GFP_KERNEL))
1174 return __FAIL(ops, i);
1176 /* Overlapping mappings */
1177 if (!ops->map(ops, iova, iova + size, size,
1178 IOMMU_READ | IOMMU_NOEXEC, GFP_KERNEL))
1179 return __FAIL(ops, i);
1181 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1182 return __FAIL(ops, i);
1188 size = 1UL << __ffs(cfg->pgsize_bitmap);
1189 if (ops->unmap(ops, SZ_1G + size, size, NULL) != size)
1190 return __FAIL(ops, i);
1192 /* Remap of partial unmap */
1193 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ, GFP_KERNEL))
1194 return __FAIL(ops, i);
1196 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
1197 return __FAIL(ops, i);
1201 for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
1204 if (ops->unmap(ops, iova, size, NULL) != size)
1205 return __FAIL(ops, i);
1207 if (ops->iova_to_phys(ops, iova + 42))
1208 return __FAIL(ops, i);
1210 /* Remap full block */
1211 if (ops->map(ops, iova, iova, size, IOMMU_WRITE, GFP_KERNEL))
1212 return __FAIL(ops, i);
1214 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1215 return __FAIL(ops, i);
1220 free_io_pgtable_ops(ops);
1223 selftest_running = false;
1227 static int __init arm_lpae_do_selftests(void)
1229 static const unsigned long pgsize[] __initconst = {
1230 SZ_4K | SZ_2M | SZ_1G,
1235 static const unsigned int ias[] __initconst = {
1236 32, 36, 40, 42, 44, 48,
1239 int i, j, pass = 0, fail = 0;
1240 struct io_pgtable_cfg cfg = {
1241 .tlb = &dummy_tlb_ops,
1243 .coherent_walk = true,
1246 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1247 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1248 cfg.pgsize_bitmap = pgsize[i];
1250 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1252 if (arm_lpae_run_tests(&cfg))
1259 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1260 return fail ? -EFAULT : 0;
1262 subsys_initcall(arm_lpae_do_selftests);