1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU-agnostic ARM page table allocator.
5 * ARMv7 Short-descriptor format, supporting
6 * - Basic memory attributes
7 * - Simplified access permissions (AP[2:1] model)
8 * - Backwards-compatible TEX remap
9 * - Large pages/supersections (if indicated by the caller)
12 * - Legacy access permissions (AP[2:0] model)
14 * Almost certainly never supporting:
18 * Copyright (C) 2014-2015 ARM Limited
19 * Copyright (c) 2014-2015 MediaTek Inc.
22 #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
24 #include <linux/atomic.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/gfp.h>
27 #include <linux/io-pgtable.h>
28 #include <linux/iommu.h>
29 #include <linux/kernel.h>
30 #include <linux/kmemleak.h>
31 #include <linux/sizes.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/types.h>
36 #include <asm/barrier.h>
38 /* Struct accessors */
39 #define io_pgtable_to_data(x) \
40 container_of((x), struct arm_v7s_io_pgtable, iop)
42 #define io_pgtable_ops_to_data(x) \
43 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
46 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
47 * and 12 bits in a page.
48 * MediaTek extend 2 bits to reach 34bits, 14 bits at lvl1 and 8 bits at lvl2.
50 #define ARM_V7S_ADDR_BITS 32
51 #define _ARM_V7S_LVL_BITS(lvl, cfg) ((lvl) == 1 ? ((cfg)->ias - 20) : 8)
52 #define ARM_V7S_LVL_SHIFT(lvl) ((lvl) == 1 ? 20 : 12)
53 #define ARM_V7S_TABLE_SHIFT 10
55 #define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl, cfg))
56 #define ARM_V7S_TABLE_SIZE(lvl, cfg) \
57 (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
59 #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
60 #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
61 #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
62 #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
63 #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
65 ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
69 * Large page/supersection entries are effectively a block of 16 page/section
70 * entries, along the lines of the LPAE contiguous hint, but all with the
71 * same output address. For want of a better common name we'll call them
72 * "contiguous" versions of their respective page/section entries here, but
73 * noting the distinction (WRT to TLB maintenance) that they represent *one*
74 * entry repeated 16 times, not 16 separate entries (as in the LPAE case).
76 #define ARM_V7S_CONT_PAGES 16
78 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
79 #define ARM_V7S_PTE_TYPE_TABLE 0x1
80 #define ARM_V7S_PTE_TYPE_PAGE 0x2
81 #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1
83 #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0)
84 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) \
85 ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE))
88 #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl)))
89 #define ARM_V7S_ATTR_B BIT(2)
90 #define ARM_V7S_ATTR_C BIT(3)
91 #define ARM_V7S_ATTR_NS_TABLE BIT(3)
92 #define ARM_V7S_ATTR_NS_SECTION BIT(19)
94 #define ARM_V7S_CONT_SECTION BIT(18)
95 #define ARM_V7S_CONT_PAGE_XN_SHIFT 15
98 * The attribute bits are consistently ordered*, but occupy bits [17:10] of
99 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
100 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
102 #define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6)
104 #define ARM_V7S_ATTR_MASK 0xff
105 #define ARM_V7S_ATTR_AP0 BIT(0)
106 #define ARM_V7S_ATTR_AP1 BIT(1)
107 #define ARM_V7S_ATTR_AP2 BIT(5)
108 #define ARM_V7S_ATTR_S BIT(6)
109 #define ARM_V7S_ATTR_NG BIT(7)
110 #define ARM_V7S_TEX_SHIFT 2
111 #define ARM_V7S_TEX_MASK 0x7
112 #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
114 /* MediaTek extend the bits below for PA 32bit/33bit/34bit */
115 #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
116 #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
117 #define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5)
119 /* *well, except for TEX on level 2 large pages, of course :( */
120 #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
121 #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
123 /* Simplified access permissions */
124 #define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0
125 #define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1
126 #define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2
129 #define ARM_V7S_RGN_NC 0
130 #define ARM_V7S_RGN_WBWA 1
131 #define ARM_V7S_RGN_WT 2
132 #define ARM_V7S_RGN_WB 3
134 #define ARM_V7S_PRRR_TYPE_DEVICE 1
135 #define ARM_V7S_PRRR_TYPE_NORMAL 2
136 #define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2))
137 #define ARM_V7S_PRRR_DS0 BIT(16)
138 #define ARM_V7S_PRRR_DS1 BIT(17)
139 #define ARM_V7S_PRRR_NS0 BIT(18)
140 #define ARM_V7S_PRRR_NS1 BIT(19)
141 #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24)
143 #define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2))
144 #define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16))
146 #define ARM_V7S_TTBR_S BIT(1)
147 #define ARM_V7S_TTBR_NOS BIT(5)
148 #define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3)
149 #define ARM_V7S_TTBR_IRGN_ATTR(attr) \
150 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
152 #ifdef CONFIG_ZONE_DMA32
153 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA32
154 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA32
156 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA
157 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA
160 typedef u32 arm_v7s_iopte;
162 static bool selftest_running;
164 struct arm_v7s_io_pgtable {
165 struct io_pgtable iop;
168 struct kmem_cache *l2_tables;
169 spinlock_t split_lock;
172 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl);
174 static dma_addr_t __arm_v7s_dma_addr(void *pages)
176 return (dma_addr_t)virt_to_phys(pages);
179 static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
181 return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
182 (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
185 static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
186 struct io_pgtable_cfg *cfg)
188 arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
190 if (!arm_v7s_is_mtk_enabled(cfg))
193 if (paddr & BIT_ULL(32))
194 pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
195 if (paddr & BIT_ULL(33))
196 pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
197 if (paddr & BIT_ULL(34))
198 pte |= ARM_V7S_ATTR_MTK_PA_BIT34;
202 static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
203 struct io_pgtable_cfg *cfg)
208 if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
209 mask = ARM_V7S_TABLE_MASK;
210 else if (arm_v7s_pte_is_cont(pte, lvl))
211 mask = ARM_V7S_LVL_MASK(lvl) * ARM_V7S_CONT_PAGES;
213 mask = ARM_V7S_LVL_MASK(lvl);
216 if (!arm_v7s_is_mtk_enabled(cfg))
219 if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
220 paddr |= BIT_ULL(32);
221 if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
222 paddr |= BIT_ULL(33);
223 if (pte & ARM_V7S_ATTR_MTK_PA_BIT34)
224 paddr |= BIT_ULL(34);
228 static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl,
229 struct arm_v7s_io_pgtable *data)
231 return phys_to_virt(iopte_to_paddr(pte, lvl, &data->iop.cfg));
234 static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
235 struct arm_v7s_io_pgtable *data)
237 struct io_pgtable_cfg *cfg = &data->iop.cfg;
238 struct device *dev = cfg->iommu_dev;
241 size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
245 table = (void *)__get_free_pages(
246 __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
248 table = kmem_cache_zalloc(data->l2_tables, gfp);
249 phys = virt_to_phys(table);
250 if (phys != (arm_v7s_iopte)phys) {
251 /* Doesn't fit in PTE */
252 dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
255 if (table && !cfg->coherent_walk) {
256 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
257 if (dma_mapping_error(dev, dma))
260 * We depend on the IOMMU being able to work with any physical
261 * address directly, so if the DMA layer suggests otherwise by
262 * translating or truncating them, that bodes very badly...
268 kmemleak_ignore(table);
272 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
273 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
276 free_pages((unsigned long)table, get_order(size));
278 kmem_cache_free(data->l2_tables, table);
282 static void __arm_v7s_free_table(void *table, int lvl,
283 struct arm_v7s_io_pgtable *data)
285 struct io_pgtable_cfg *cfg = &data->iop.cfg;
286 struct device *dev = cfg->iommu_dev;
287 size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
289 if (!cfg->coherent_walk)
290 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
293 free_pages((unsigned long)table, get_order(size));
295 kmem_cache_free(data->l2_tables, table);
298 static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
299 struct io_pgtable_cfg *cfg)
301 if (cfg->coherent_walk)
304 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
305 num_entries * sizeof(*ptep), DMA_TO_DEVICE);
307 static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
308 int num_entries, struct io_pgtable_cfg *cfg)
312 for (i = 0; i < num_entries; i++)
315 __arm_v7s_pte_sync(ptep, num_entries, cfg);
318 static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
319 struct io_pgtable_cfg *cfg)
321 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
322 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
324 if (!(prot & IOMMU_MMIO))
325 pte |= ARM_V7S_ATTR_TEX(1);
327 pte |= ARM_V7S_PTE_AF;
328 if (!(prot & IOMMU_PRIV))
329 pte |= ARM_V7S_PTE_AP_UNPRIV;
330 if (!(prot & IOMMU_WRITE))
331 pte |= ARM_V7S_PTE_AP_RDONLY;
333 pte <<= ARM_V7S_ATTR_SHIFT(lvl);
335 if ((prot & IOMMU_NOEXEC) && ap)
336 pte |= ARM_V7S_ATTR_XN(lvl);
337 if (prot & IOMMU_MMIO)
338 pte |= ARM_V7S_ATTR_B;
339 else if (prot & IOMMU_CACHE)
340 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C;
342 pte |= ARM_V7S_PTE_TYPE_PAGE;
343 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
344 pte |= ARM_V7S_ATTR_NS_SECTION;
349 static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
351 int prot = IOMMU_READ;
352 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
354 if (!(attr & ARM_V7S_PTE_AP_RDONLY))
356 if (!(attr & ARM_V7S_PTE_AP_UNPRIV))
358 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
360 else if (pte & ARM_V7S_ATTR_C)
362 if (pte & ARM_V7S_ATTR_XN(lvl))
363 prot |= IOMMU_NOEXEC;
368 static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl)
371 pte |= ARM_V7S_CONT_SECTION;
372 } else if (lvl == 2) {
373 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl);
374 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK;
376 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE;
377 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) |
378 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) |
379 ARM_V7S_PTE_TYPE_CONT_PAGE;
384 static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl)
387 pte &= ~ARM_V7S_CONT_SECTION;
388 } else if (lvl == 2) {
389 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT);
390 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK <<
391 ARM_V7S_CONT_PAGE_TEX_SHIFT);
393 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE;
394 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) |
395 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) |
396 ARM_V7S_PTE_TYPE_PAGE;
401 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl)
403 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl))
404 return pte & ARM_V7S_CONT_SECTION;
406 return !(pte & ARM_V7S_PTE_TYPE_PAGE);
410 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *,
411 struct iommu_iotlb_gather *, unsigned long,
412 size_t, int, arm_v7s_iopte *);
414 static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
415 unsigned long iova, phys_addr_t paddr, int prot,
416 int lvl, int num_entries, arm_v7s_iopte *ptep)
418 struct io_pgtable_cfg *cfg = &data->iop.cfg;
422 for (i = 0; i < num_entries; i++)
423 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) {
425 * We need to unmap and free the old table before
426 * overwriting it with a block entry.
429 size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
431 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl, cfg);
432 if (WARN_ON(__arm_v7s_unmap(data, NULL, iova + i * sz,
433 sz, lvl, tblp) != sz))
435 } else if (ptep[i]) {
436 /* We require an unmap first */
437 WARN_ON(!selftest_running);
441 pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
443 pte = arm_v7s_pte_to_cont(pte, lvl);
445 pte |= paddr_to_iopte(paddr, lvl, cfg);
447 __arm_v7s_set_pte(ptep, pte, num_entries, cfg);
451 static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
454 struct io_pgtable_cfg *cfg)
456 arm_v7s_iopte old, new;
458 new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
459 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
460 new |= ARM_V7S_ATTR_NS_TABLE;
463 * Ensure the table itself is visible before its PTE can be.
464 * Whilst we could get away with cmpxchg64_release below, this
465 * doesn't have any ordering semantics when !CONFIG_SMP.
469 old = cmpxchg_relaxed(ptep, curr, new);
470 __arm_v7s_pte_sync(ptep, 1, cfg);
475 static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
476 phys_addr_t paddr, size_t size, int prot,
477 int lvl, arm_v7s_iopte *ptep, gfp_t gfp)
479 struct io_pgtable_cfg *cfg = &data->iop.cfg;
480 arm_v7s_iopte pte, *cptep;
481 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
483 /* Find our entry at the current level */
484 ptep += ARM_V7S_LVL_IDX(iova, lvl, cfg);
486 /* If we can install a leaf entry at this level, then do so */
488 return arm_v7s_init_pte(data, iova, paddr, prot,
489 lvl, num_entries, ptep);
491 /* We can't allocate tables at the final level */
492 if (WARN_ON(lvl == 2))
495 /* Grab a pointer to the next level */
496 pte = READ_ONCE(*ptep);
498 cptep = __arm_v7s_alloc_table(lvl + 1, gfp, data);
502 pte = arm_v7s_install_table(cptep, ptep, 0, cfg);
504 __arm_v7s_free_table(cptep, lvl + 1, data);
506 /* We've no easy way of knowing if it's synced yet, so... */
507 __arm_v7s_pte_sync(ptep, 1, cfg);
510 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
511 cptep = iopte_deref(pte, lvl, data);
513 /* We require an unmap first */
514 WARN_ON(!selftest_running);
519 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep, gfp);
522 static int arm_v7s_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
523 phys_addr_t paddr, size_t pgsize, size_t pgcount,
524 int prot, gfp_t gfp, size_t *mapped)
526 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
529 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
530 paddr >= (1ULL << data->iop.cfg.oas)))
533 /* If no access, then nothing to do */
534 if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
538 ret = __arm_v7s_map(data, iova, paddr, pgsize, prot, 1, data->pgd,
549 * Synchronise all PTE updates for the new mapping before there's
550 * a chance for anything to kick off a table walk for the new iova.
557 static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
558 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
560 return arm_v7s_map_pages(ops, iova, paddr, size, 1, prot, gfp, NULL);
563 static void arm_v7s_free_pgtable(struct io_pgtable *iop)
565 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
568 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1, &data->iop.cfg); i++) {
569 arm_v7s_iopte pte = data->pgd[i];
571 if (ARM_V7S_PTE_IS_TABLE(pte, 1))
572 __arm_v7s_free_table(iopte_deref(pte, 1, data),
575 __arm_v7s_free_table(data->pgd, 1, data);
576 kmem_cache_destroy(data->l2_tables);
580 static arm_v7s_iopte arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
581 unsigned long iova, int idx, int lvl,
584 struct io_pgtable *iop = &data->iop;
586 size_t size = ARM_V7S_BLOCK_SIZE(lvl);
589 /* Check that we didn't lose a race to get the lock */
591 if (!arm_v7s_pte_is_cont(pte, lvl))
594 ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
595 pte = arm_v7s_cont_to_pte(pte, lvl);
596 for (i = 0; i < ARM_V7S_CONT_PAGES; i++)
597 ptep[i] = pte + i * size;
599 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
601 size *= ARM_V7S_CONT_PAGES;
602 io_pgtable_tlb_flush_walk(iop, iova, size, size);
606 static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
607 struct iommu_iotlb_gather *gather,
608 unsigned long iova, size_t size,
609 arm_v7s_iopte blk_pte,
612 struct io_pgtable_cfg *cfg = &data->iop.cfg;
613 arm_v7s_iopte pte, *tablep;
614 int i, unmap_idx, num_entries, num_ptes;
616 tablep = __arm_v7s_alloc_table(2, GFP_ATOMIC, data);
618 return 0; /* Bytes unmapped */
620 num_ptes = ARM_V7S_PTES_PER_LVL(2, cfg);
621 num_entries = size >> ARM_V7S_LVL_SHIFT(2);
622 unmap_idx = ARM_V7S_LVL_IDX(iova, 2, cfg);
624 pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
626 pte = arm_v7s_pte_to_cont(pte, 2);
628 for (i = 0; i < num_ptes; i += num_entries, pte += size) {
633 __arm_v7s_set_pte(&tablep[i], pte, num_entries, cfg);
636 pte = arm_v7s_install_table(tablep, ptep, blk_pte, cfg);
637 if (pte != blk_pte) {
638 __arm_v7s_free_table(tablep, 2, data);
640 if (!ARM_V7S_PTE_IS_TABLE(pte, 1))
643 tablep = iopte_deref(pte, 1, data);
644 return __arm_v7s_unmap(data, gather, iova, size, 2, tablep);
647 io_pgtable_tlb_add_page(&data->iop, gather, iova, size);
651 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
652 struct iommu_iotlb_gather *gather,
653 unsigned long iova, size_t size, int lvl,
656 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES];
657 struct io_pgtable *iop = &data->iop;
658 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
660 /* Something went horribly wrong and we ran out of page table */
661 if (WARN_ON(lvl > 2))
664 idx = ARM_V7S_LVL_IDX(iova, lvl, &iop->cfg);
667 pte[i] = READ_ONCE(ptep[i]);
668 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(pte[i])))
670 } while (++i < num_entries);
673 * If we've hit a contiguous 'large page' entry at this level, it
674 * needs splitting first, unless we're unmapping the whole lot.
676 * For splitting, we can't rewrite 16 PTEs atomically, and since we
677 * can't necessarily assume TEX remap we don't have a software bit to
678 * mark live entries being split. In practice (i.e. DMA API code), we
679 * will never be splitting large pages anyway, so just wrap this edge
680 * case in a lock for the sake of correctness and be done with it.
682 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) {
685 spin_lock_irqsave(&data->split_lock, flags);
686 pte[0] = arm_v7s_split_cont(data, iova, idx, lvl, ptep);
687 spin_unlock_irqrestore(&data->split_lock, flags);
690 /* If the size matches this level, we're in the right place */
692 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl);
694 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg);
696 for (i = 0; i < num_entries; i++) {
697 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) {
698 /* Also flush any partial walks */
699 io_pgtable_tlb_flush_walk(iop, iova, blk_size,
700 ARM_V7S_BLOCK_SIZE(lvl + 1));
701 ptep = iopte_deref(pte[i], lvl, data);
702 __arm_v7s_free_table(ptep, lvl + 1, data);
703 } else if (!iommu_iotlb_gather_queued(gather)) {
704 io_pgtable_tlb_add_page(iop, gather, iova, blk_size);
709 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) {
711 * Insert a table at the next level to map the old region,
712 * minus the part we want to unmap
714 return arm_v7s_split_blk_unmap(data, gather, iova, size, pte[0],
718 /* Keep on walkin' */
719 ptep = iopte_deref(pte[0], lvl, data);
720 return __arm_v7s_unmap(data, gather, iova, size, lvl + 1, ptep);
723 static size_t arm_v7s_unmap_pages(struct io_pgtable_ops *ops, unsigned long iova,
724 size_t pgsize, size_t pgcount,
725 struct iommu_iotlb_gather *gather)
727 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
728 size_t unmapped = 0, ret;
730 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
734 ret = __arm_v7s_unmap(data, gather, iova, pgsize, 1, data->pgd);
745 static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
746 size_t size, struct iommu_iotlb_gather *gather)
748 return arm_v7s_unmap_pages(ops, iova, size, 1, gather);
751 static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
754 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
755 arm_v7s_iopte *ptep = data->pgd, pte;
760 ptep += ARM_V7S_LVL_IDX(iova, ++lvl, &data->iop.cfg);
761 pte = READ_ONCE(*ptep);
762 ptep = iopte_deref(pte, lvl, data);
763 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
765 if (!ARM_V7S_PTE_IS_VALID(pte))
768 mask = ARM_V7S_LVL_MASK(lvl);
769 if (arm_v7s_pte_is_cont(pte, lvl))
770 mask *= ARM_V7S_CONT_PAGES;
771 return iopte_to_paddr(pte, lvl, &data->iop.cfg) | (iova & ~mask);
774 static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
777 struct arm_v7s_io_pgtable *data;
779 if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
782 if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
785 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
786 IO_PGTABLE_QUIRK_NO_PERMS |
787 IO_PGTABLE_QUIRK_ARM_MTK_EXT))
790 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
791 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT &&
792 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
795 data = kmalloc(sizeof(*data), GFP_KERNEL);
799 spin_lock_init(&data->split_lock);
800 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
801 ARM_V7S_TABLE_SIZE(2, cfg),
802 ARM_V7S_TABLE_SIZE(2, cfg),
803 ARM_V7S_TABLE_SLAB_FLAGS, NULL);
804 if (!data->l2_tables)
807 data->iop.ops = (struct io_pgtable_ops) {
809 .map_pages = arm_v7s_map_pages,
810 .unmap = arm_v7s_unmap,
811 .unmap_pages = arm_v7s_unmap_pages,
812 .iova_to_phys = arm_v7s_iova_to_phys,
815 /* We have to do this early for __arm_v7s_alloc_table to work... */
816 data->iop.cfg = *cfg;
819 * Unless the IOMMU driver indicates supersection support by
820 * having SZ_16M set in the initial bitmap, they won't be used.
822 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
824 /* TCR: T0SZ=0, EAE=0 (if applicable) */
825 cfg->arm_v7s_cfg.tcr = 0;
828 * TEX remap: the indices used map to the closest equivalent types
829 * under the non-TEX-remap interpretation of those attribute bits,
830 * excepting various implementation-defined aspects of shareability.
832 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) |
833 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) |
834 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) |
835 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 |
836 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7);
837 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) |
838 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA);
840 /* Looking good; allocate a pgd */
841 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data);
845 /* Ensure the empty pgd is visible before any actual TTBR write */
849 cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S |
850 (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
851 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
852 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
853 (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
854 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
858 kmem_cache_destroy(data->l2_tables);
863 struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
864 .alloc = arm_v7s_alloc_pgtable,
865 .free = arm_v7s_free_pgtable,
868 #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
870 static struct io_pgtable_cfg *cfg_cookie __initdata;
872 static void __init dummy_tlb_flush_all(void *cookie)
874 WARN_ON(cookie != cfg_cookie);
877 static void __init dummy_tlb_flush(unsigned long iova, size_t size,
878 size_t granule, void *cookie)
880 WARN_ON(cookie != cfg_cookie);
881 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
884 static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather,
885 unsigned long iova, size_t granule,
888 dummy_tlb_flush(iova, granule, granule, cookie);
891 static const struct iommu_flush_ops dummy_tlb_ops __initconst = {
892 .tlb_flush_all = dummy_tlb_flush_all,
893 .tlb_flush_walk = dummy_tlb_flush,
894 .tlb_add_page = dummy_tlb_add_page,
897 #define __FAIL(ops) ({ \
898 WARN(1, "selftest: test failed\n"); \
899 selftest_running = false; \
903 static int __init arm_v7s_do_selftests(void)
905 struct io_pgtable_ops *ops;
906 struct io_pgtable_cfg cfg = {
907 .tlb = &dummy_tlb_ops,
910 .coherent_walk = true,
911 .quirks = IO_PGTABLE_QUIRK_ARM_NS,
912 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
914 unsigned int iova, size, iova_start;
915 unsigned int i, loopnr = 0;
917 selftest_running = true;
921 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg);
923 pr_err("selftest: failed to allocate io pgtable ops\n");
928 * Initial sanity checks.
929 * Empty page tables shouldn't provide any translations.
931 if (ops->iova_to_phys(ops, 42))
934 if (ops->iova_to_phys(ops, SZ_1G + 42))
937 if (ops->iova_to_phys(ops, SZ_2G + 42))
941 * Distinct mappings of different granule sizes.
944 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
946 if (ops->map(ops, iova, iova, size, IOMMU_READ |
949 IOMMU_CACHE, GFP_KERNEL))
952 /* Overlapping mappings */
953 if (!ops->map(ops, iova, iova + size, size,
954 IOMMU_READ | IOMMU_NOEXEC, GFP_KERNEL))
957 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
966 size = 1UL << __ffs(cfg.pgsize_bitmap);
968 iova_start = i * SZ_16M;
969 if (ops->unmap(ops, iova_start + size, size, NULL) != size)
972 /* Remap of partial unmap */
973 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ, GFP_KERNEL))
976 if (ops->iova_to_phys(ops, iova_start + size + 42)
984 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
987 if (ops->unmap(ops, iova, size, NULL) != size)
990 if (ops->iova_to_phys(ops, iova + 42))
993 /* Remap full block */
994 if (ops->map(ops, iova, iova, size, IOMMU_WRITE, GFP_KERNEL))
997 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1003 free_io_pgtable_ops(ops);
1005 selftest_running = false;
1007 pr_info("self test ok\n");
1010 subsys_initcall(arm_v7s_do_selftests);